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Sujith394cf0a2009-02-09 13:26:54 +05301/*
Sujithcee075a2009-03-13 09:07:23 +05302 * Copyright (c) 2008-2009 Atheros Communications Inc.
Sujith394cf0a2009-02-09 13:26:54 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef EEPROM_H
18#define EEPROM_H
19
Johannes Bergd3236552009-04-20 14:31:42 +020020#include <net/cfg80211.h>
Bob Copeland3a702e42009-03-30 22:30:29 -040021
Sujith394cf0a2009-02-09 13:26:54 +053022#define AH_USE_EEPROM 0x1
23
24#ifdef __BIG_ENDIAN
25#define AR5416_EEPROM_MAGIC 0x5aa5
26#else
27#define AR5416_EEPROM_MAGIC 0xa55a
28#endif
29
30#define CTRY_DEBUG 0x1ff
31#define CTRY_DEFAULT 0
32
33#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
34#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
35#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
36#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
37#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
38#define AR_EEPROM_EEPCAP_MAXQCU_S 4
39#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
40#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
41#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
42
43#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
44#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
45#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
46#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
47#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
48#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
49
50#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
51#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
52
53#define AR5416_EEPROM_MAGIC_OFFSET 0x0
54#define AR5416_EEPROM_S 2
55#define AR5416_EEPROM_OFFSET 0x2000
56#define AR5416_EEPROM_MAX 0xae0
57
58#define AR5416_EEPROM_START_ADDR \
59 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
60
61#define SD_NO_CTL 0xE0
62#define NO_CTL 0xff
63#define CTL_MODE_M 7
64#define CTL_11A 0
65#define CTL_11B 1
66#define CTL_11G 2
67#define CTL_2GHT20 5
68#define CTL_5GHT20 6
69#define CTL_2GHT40 7
70#define CTL_5GHT40 8
71
72#define EXT_ADDITIVE (0x8000)
73#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
74#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
75#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
76
77#define SUB_NUM_CTL_MODES_AT_5G_40 2
78#define SUB_NUM_CTL_MODES_AT_2G_40 3
79
Sujithe421c7b2009-02-12 10:06:36 +053080#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
81#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
82
Sujithfec0de12009-02-12 10:06:43 +053083/*
84 * For AR9285 and later chipsets, the following bits are not being programmed
85 * in EEPROM and so need to be enabled always.
86 *
87 * Bit 0: en_fcc_mid
88 * Bit 1: en_jap_mid
89 * Bit 2: en_fcc_dfs_ht40
90 * Bit 3: en_jap_ht40
91 * Bit 4: en_jap_dfs_ht40
92 */
93#define AR9285_RDEXT_DEFAULT 0x1F
94
Sujith394cf0a2009-02-09 13:26:54 +053095#define AR_EEPROM_MAC(i) (0x1d+(i))
96#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
97#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
98#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
99
Sujith355363f2009-03-13 08:56:02 +0530100#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
Sujithd9ae96d2009-02-20 15:13:13 +0530101#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
102 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530103#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \
104 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
Sujithd9ae96d2009-02-20 15:13:13 +0530105
Sujith394cf0a2009-02-09 13:26:54 +0530106#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
107#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
108#define AR_EEPROM_RFSILENT_POLARITY 0x0002
109#define AR_EEPROM_RFSILENT_POLARITY_S 1
110
111#define EEP_RFSILENT_ENABLED 0x0001
112#define EEP_RFSILENT_ENABLED_S 0
113#define EEP_RFSILENT_POLARITY 0x0002
114#define EEP_RFSILENT_POLARITY_S 1
115#define EEP_RFSILENT_GPIO_SEL 0x001c
116#define EEP_RFSILENT_GPIO_SEL_S 2
117
118#define AR5416_OPFLAGS_11A 0x01
119#define AR5416_OPFLAGS_11G 0x02
120#define AR5416_OPFLAGS_N_5G_HT40 0x04
121#define AR5416_OPFLAGS_N_2G_HT40 0x08
122#define AR5416_OPFLAGS_N_5G_HT20 0x10
123#define AR5416_OPFLAGS_N_2G_HT20 0x20
124
125#define AR5416_EEP_NO_BACK_VER 0x1
126#define AR5416_EEP_VER 0xE
127#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
128#define AR5416_EEP_MINOR_VER_2 0x2
129#define AR5416_EEP_MINOR_VER_3 0x3
130#define AR5416_EEP_MINOR_VER_7 0x7
131#define AR5416_EEP_MINOR_VER_9 0x9
132#define AR5416_EEP_MINOR_VER_16 0x10
133#define AR5416_EEP_MINOR_VER_17 0x11
134#define AR5416_EEP_MINOR_VER_19 0x13
135#define AR5416_EEP_MINOR_VER_20 0x14
Sujith06d0f062009-02-12 10:06:45 +0530136#define AR5416_EEP_MINOR_VER_22 0x16
Sujith394cf0a2009-02-09 13:26:54 +0530137
138#define AR5416_NUM_5G_CAL_PIERS 8
139#define AR5416_NUM_2G_CAL_PIERS 4
140#define AR5416_NUM_5G_20_TARGET_POWERS 8
141#define AR5416_NUM_5G_40_TARGET_POWERS 8
142#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
143#define AR5416_NUM_2G_20_TARGET_POWERS 4
144#define AR5416_NUM_2G_40_TARGET_POWERS 4
145#define AR5416_NUM_CTLS 24
146#define AR5416_NUM_BAND_EDGES 8
147#define AR5416_NUM_PD_GAINS 4
148#define AR5416_PD_GAINS_IN_MASK 4
149#define AR5416_PD_GAIN_ICEPTS 5
150#define AR5416_EEPROM_MODAL_SPURS 5
151#define AR5416_MAX_RATE_POWER 63
152#define AR5416_NUM_PDADC_VALUES 128
153#define AR5416_BCHAN_UNUSED 0xFF
154#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
155#define AR5416_MAX_CHAINS 3
156#define AR5416_PWR_TABLE_OFFSET -5
157
158/* Rx gain type values */
159#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
160#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
161#define AR5416_EEP_RXGAIN_ORIG 2
162
163/* Tx gain type values */
164#define AR5416_EEP_TXGAIN_ORIGINAL 0
165#define AR5416_EEP_TXGAIN_HIGH_POWER 1
166
167#define AR5416_EEP4K_START_LOC 64
168#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
169#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
170#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
171#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
172#define AR5416_EEP4K_NUM_CTLS 12
173#define AR5416_EEP4K_NUM_BAND_EDGES 4
174#define AR5416_EEP4K_NUM_PD_GAINS 2
175#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
176#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
177#define AR5416_EEP4K_MAX_CHAINS 1
178
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530179#define AR9280_TX_GAIN_TABLE_SIZE 22
180
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530181#define AR9287_EEP_VER 0xE
182#define AR9287_EEP_VER_MINOR_MASK 0xFFF
183#define AR9287_EEP_MINOR_VER_1 0x1
184#define AR9287_EEP_MINOR_VER_2 0x2
185#define AR9287_EEP_MINOR_VER_3 0x3
186#define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3
187#define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER
188#define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1
189
190#define AR9287_EEP_START_LOC 128
191#define AR9287_NUM_2G_CAL_PIERS 3
192#define AR9287_NUM_2G_CCK_TARGET_POWERS 3
193#define AR9287_NUM_2G_20_TARGET_POWERS 3
194#define AR9287_NUM_2G_40_TARGET_POWERS 3
195#define AR9287_NUM_CTLS 12
196#define AR9287_NUM_BAND_EDGES 4
197#define AR9287_NUM_PD_GAINS 4
198#define AR9287_PD_GAINS_IN_MASK 4
199#define AR9287_PD_GAIN_ICEPTS 1
200#define AR9287_EEPROM_MODAL_SPURS 5
201#define AR9287_MAX_RATE_POWER 63
202#define AR9287_NUM_PDADC_VALUES 128
203#define AR9287_NUM_RATES 16
204#define AR9287_BCHAN_UNUSED 0xFF
205#define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
206#define AR9287_OPFLAGS_11A 0x01
207#define AR9287_OPFLAGS_11G 0x02
208#define AR9287_OPFLAGS_2G_HT40 0x08
209#define AR9287_OPFLAGS_2G_HT20 0x20
210#define AR9287_OPFLAGS_5G_HT40 0x04
211#define AR9287_OPFLAGS_5G_HT20 0x10
212#define AR9287_EEPMISC_BIG_ENDIAN 0x01
213#define AR9287_EEPMISC_WOW 0x02
214#define AR9287_MAX_CHAINS 2
215#define AR9287_ANT_16S 32
216#define AR9287_custdatasize 20
217
218#define AR9287_NUM_ANT_CHAIN_FIELDS 6
219#define AR9287_NUM_ANT_COMMON_FIELDS 4
220#define AR9287_SIZE_ANT_CHAIN_FIELD 2
221#define AR9287_SIZE_ANT_COMMON_FIELD 4
222#define AR9287_ANT_CHAIN_MASK 0x3
223#define AR9287_ANT_COMMON_MASK 0xf
224#define AR9287_CHAIN_0_IDX 0
225#define AR9287_CHAIN_1_IDX 1
226#define AR9287_DATA_SZ 32
227
228#define AR9287_PWR_TABLE_OFFSET_DB -5
229
230#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
231
Sujith394cf0a2009-02-09 13:26:54 +0530232enum eeprom_param {
233 EEP_NFTHRESH_5,
234 EEP_NFTHRESH_2,
235 EEP_MAC_MSW,
236 EEP_MAC_MID,
237 EEP_MAC_LSW,
238 EEP_REG_0,
239 EEP_REG_1,
240 EEP_OP_CAP,
241 EEP_OP_MODE,
242 EEP_RF_SILENT,
243 EEP_OB_5,
244 EEP_DB_5,
245 EEP_OB_2,
246 EEP_DB_2,
247 EEP_MINOR_REV,
248 EEP_TX_MASK,
249 EEP_RX_MASK,
250 EEP_RXGAIN_TYPE,
251 EEP_TXGAIN_TYPE,
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530252 EEP_OL_PWRCTRL,
253 EEP_RC_CHAIN_MASK,
Sujith394cf0a2009-02-09 13:26:54 +0530254 EEP_DAC_HPWR_5G,
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530255 EEP_FRAC_N_5G,
256 EEP_DEV_TYPE,
257 EEP_TEMPSENSE_SLOPE,
258 EEP_TEMPSENSE_SLOPE_PAL_ON,
259 EEP_PWR_TABLE_OFFSET
Sujith394cf0a2009-02-09 13:26:54 +0530260};
261
262enum ar5416_rates {
263 rate6mb, rate9mb, rate12mb, rate18mb,
264 rate24mb, rate36mb, rate48mb, rate54mb,
265 rate1l, rate2l, rate2s, rate5_5l,
266 rate5_5s, rate11l, rate11s, rateXr,
267 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
268 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
269 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
270 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
271 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
272 Ar5416RateSize
273};
274
275enum ath9k_hal_freq_band {
276 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
277 ATH9K_HAL_FREQ_BAND_2GHZ = 1
278};
279
280struct base_eep_header {
281 u16 length;
282 u16 checksum;
283 u16 version;
284 u8 opCapFlags;
285 u8 eepMisc;
286 u16 regDmn[2];
287 u8 macAddr[6];
288 u8 rxMask;
289 u8 txMask;
290 u16 rfSilent;
291 u16 blueToothOptions;
292 u16 deviceCap;
293 u32 binBuildNumber;
294 u8 deviceType;
295 u8 pwdclkind;
296 u8 futureBase_1[2];
297 u8 rxGainType;
298 u8 dacHiPwrMode_5G;
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530299 u8 openLoopPwrCntl;
Sujith394cf0a2009-02-09 13:26:54 +0530300 u8 dacLpMode;
301 u8 txGainType;
302 u8 rcChainMask;
303 u8 desiredScaleCCK;
Sujith06d0f062009-02-12 10:06:45 +0530304 u8 power_table_offset;
305 u8 frac_n_5g;
306 u8 futureBase_3[21];
Sujith394cf0a2009-02-09 13:26:54 +0530307} __packed;
308
309struct base_eep_header_4k {
310 u16 length;
311 u16 checksum;
312 u16 version;
313 u8 opCapFlags;
314 u8 eepMisc;
315 u16 regDmn[2];
316 u8 macAddr[6];
317 u8 rxMask;
318 u8 txMask;
319 u16 rfSilent;
320 u16 blueToothOptions;
321 u16 deviceCap;
322 u32 binBuildNumber;
323 u8 deviceType;
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530324 u8 txGainType;
Sujith394cf0a2009-02-09 13:26:54 +0530325} __packed;
326
327
328struct spur_chan {
329 u16 spurChan;
330 u8 spurRangeLow;
331 u8 spurRangeHigh;
332} __packed;
333
334struct modal_eep_header {
335 u32 antCtrlChain[AR5416_MAX_CHAINS];
336 u32 antCtrlCommon;
337 u8 antennaGainCh[AR5416_MAX_CHAINS];
338 u8 switchSettling;
339 u8 txRxAttenCh[AR5416_MAX_CHAINS];
340 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
341 u8 adcDesiredSize;
342 u8 pgaDesiredSize;
343 u8 xlnaGainCh[AR5416_MAX_CHAINS];
344 u8 txEndToXpaOff;
345 u8 txEndToRxOn;
346 u8 txFrameToXpaOn;
347 u8 thresh62;
348 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
349 u8 xpdGain;
350 u8 xpd;
351 u8 iqCalICh[AR5416_MAX_CHAINS];
352 u8 iqCalQCh[AR5416_MAX_CHAINS];
353 u8 pdGainOverlap;
354 u8 ob;
355 u8 db;
356 u8 xpaBiasLvl;
357 u8 pwrDecreaseFor2Chain;
358 u8 pwrDecreaseFor3Chain;
359 u8 txFrameToDataStart;
360 u8 txFrameToPaOn;
361 u8 ht40PowerIncForPdadc;
362 u8 bswAtten[AR5416_MAX_CHAINS];
363 u8 bswMargin[AR5416_MAX_CHAINS];
364 u8 swSettleHt40;
365 u8 xatten2Db[AR5416_MAX_CHAINS];
366 u8 xatten2Margin[AR5416_MAX_CHAINS];
367 u8 ob_ch1;
368 u8 db_ch1;
369 u8 useAnt1:1,
370 force_xpaon:1,
371 local_bias:1,
372 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
373 u8 miscBits;
374 u16 xpaBiasLvlFreq[3];
375 u8 futureModal[6];
376
377 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
378} __packed;
379
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530380struct calDataPerFreqOpLoop {
381 u8 pwrPdg[2][5];
382 u8 vpdPdg[2][5];
383 u8 pcdac[2][5];
384 u8 empty[2][5];
385} __packed;
386
Sujith394cf0a2009-02-09 13:26:54 +0530387struct modal_eep_4k_header {
Sujithc16c9d02009-08-07 09:45:11 +0530388 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
389 u32 antCtrlCommon;
390 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
391 u8 switchSettling;
392 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
393 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
394 u8 adcDesiredSize;
395 u8 pgaDesiredSize;
396 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
397 u8 txEndToXpaOff;
398 u8 txEndToRxOn;
399 u8 txFrameToXpaOn;
400 u8 thresh62;
401 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
402 u8 xpdGain;
403 u8 xpd;
404 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
405 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
406 u8 pdGainOverlap;
407 u8 ob_01;
408 u8 db1_01;
409 u8 xpaBiasLvl;
410 u8 txFrameToDataStart;
411 u8 txFrameToPaOn;
412 u8 ht40PowerIncForPdadc;
413 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
414 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
415 u8 swSettleHt40;
416 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
417 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
418 u8 db2_01;
419 u8 version;
420 u16 ob_234;
421 u16 db1_234;
422 u16 db2_234;
423 u8 futureModal[4];
Sujith394cf0a2009-02-09 13:26:54 +0530424 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
425} __packed;
426
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530427struct base_eep_ar9287_header {
Sujithc16c9d02009-08-07 09:45:11 +0530428 u16 length;
429 u16 checksum;
430 u16 version;
431 u8 opCapFlags;
432 u8 eepMisc;
433 u16 regDmn[2];
434 u8 macAddr[6];
435 u8 rxMask;
436 u8 txMask;
437 u16 rfSilent;
438 u16 blueToothOptions;
439 u16 deviceCap;
440 u32 binBuildNumber;
441 u8 deviceType;
442 u8 openLoopPwrCntl;
443 int8_t pwrTableOffset;
444 int8_t tempSensSlope;
445 int8_t tempSensSlopePalOn;
446 u8 futureBase[29];
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530447} __packed;
448
449struct modal_eep_ar9287_header {
Sujithc16c9d02009-08-07 09:45:11 +0530450 u32 antCtrlChain[AR9287_MAX_CHAINS];
451 u32 antCtrlCommon;
452 int8_t antennaGainCh[AR9287_MAX_CHAINS];
453 u8 switchSettling;
454 u8 txRxAttenCh[AR9287_MAX_CHAINS];
455 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
456 int8_t adcDesiredSize;
457 u8 txEndToXpaOff;
458 u8 txEndToRxOn;
459 u8 txFrameToXpaOn;
460 u8 thresh62;
461 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
462 u8 xpdGain;
463 u8 xpd;
464 int8_t iqCalICh[AR9287_MAX_CHAINS];
465 int8_t iqCalQCh[AR9287_MAX_CHAINS];
466 u8 pdGainOverlap;
467 u8 xpaBiasLvl;
468 u8 txFrameToDataStart;
469 u8 txFrameToPaOn;
470 u8 ht40PowerIncForPdadc;
471 u8 bswAtten[AR9287_MAX_CHAINS];
472 u8 bswMargin[AR9287_MAX_CHAINS];
473 u8 swSettleHt40;
474 u8 version;
475 u8 db1;
476 u8 db2;
477 u8 ob_cck;
478 u8 ob_psk;
479 u8 ob_qam;
480 u8 ob_pal_off;
481 u8 futureModal[30];
482 struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530483} __packed;
484
Sujith394cf0a2009-02-09 13:26:54 +0530485struct cal_data_per_freq {
486 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
487 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
488} __packed;
489
490struct cal_data_per_freq_4k {
491 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
492 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
493} __packed;
494
495struct cal_target_power_leg {
496 u8 bChannel;
497 u8 tPow2x[4];
498} __packed;
499
500struct cal_target_power_ht {
501 u8 bChannel;
502 u8 tPow2x[8];
503} __packed;
504
505
506#ifdef __BIG_ENDIAN_BITFIELD
507struct cal_ctl_edges {
508 u8 bChannel;
509 u8 flag:2, tPower:6;
510} __packed;
511#else
512struct cal_ctl_edges {
513 u8 bChannel;
514 u8 tPower:6, flag:2;
515} __packed;
516#endif
517
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530518struct cal_data_op_loop_ar9287 {
519 u8 pwrPdg[2][5];
520 u8 vpdPdg[2][5];
521 u8 pcdac[2][5];
522 u8 empty[2][5];
523} __packed;
524
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530525struct cal_data_per_freq_ar9287 {
526 u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
527 u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
528} __packed;
529
530union cal_data_per_freq_ar9287_u {
531 struct cal_data_op_loop_ar9287 calDataOpen;
532 struct cal_data_per_freq_ar9287 calDataClose;
533} __packed;
534
535struct cal_ctl_data_ar9287 {
536 struct cal_ctl_edges
537 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
538} __packed;
539
Sujith394cf0a2009-02-09 13:26:54 +0530540struct cal_ctl_data {
541 struct cal_ctl_edges
542 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
543} __packed;
544
545struct cal_ctl_data_4k {
546 struct cal_ctl_edges
547 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
548} __packed;
549
550struct ar5416_eeprom_def {
551 struct base_eep_header baseEepHeader;
552 u8 custData[64];
553 struct modal_eep_header modalHeader[2];
554 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
555 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
556 struct cal_data_per_freq
557 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
558 struct cal_data_per_freq
559 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
560 struct cal_target_power_leg
561 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
562 struct cal_target_power_ht
563 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
564 struct cal_target_power_ht
565 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
566 struct cal_target_power_leg
567 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
568 struct cal_target_power_leg
569 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
570 struct cal_target_power_ht
571 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
572 struct cal_target_power_ht
573 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
574 u8 ctlIndex[AR5416_NUM_CTLS];
575 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
576 u8 padding;
577} __packed;
578
579struct ar5416_eeprom_4k {
580 struct base_eep_header_4k baseEepHeader;
581 u8 custData[20];
582 struct modal_eep_4k_header modalHeader;
583 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
584 struct cal_data_per_freq_4k
585 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
586 struct cal_target_power_leg
587 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
588 struct cal_target_power_leg
589 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
590 struct cal_target_power_ht
591 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
592 struct cal_target_power_ht
593 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
594 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
595 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
596 u8 padding;
597} __packed;
598
Luis R. Rodriguez475f5982009-08-03 17:31:25 -0400599struct ar9287_eeprom {
Sujithc16c9d02009-08-07 09:45:11 +0530600 struct base_eep_ar9287_header baseEepHeader;
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530601 u8 custData[AR9287_DATA_SZ];
602 struct modal_eep_ar9287_header modalHeader;
603 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
604 union cal_data_per_freq_ar9287_u
Sujithc16c9d02009-08-07 09:45:11 +0530605 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530606 struct cal_target_power_leg
Sujithc16c9d02009-08-07 09:45:11 +0530607 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530608 struct cal_target_power_leg
Sujithc16c9d02009-08-07 09:45:11 +0530609 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530610 struct cal_target_power_ht
Sujithc16c9d02009-08-07 09:45:11 +0530611 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530612 struct cal_target_power_ht
Sujithc16c9d02009-08-07 09:45:11 +0530613 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530614 u8 ctlIndex[AR9287_NUM_CTLS];
615 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
616 u8 padding;
617} __packed;
618
Sujith394cf0a2009-02-09 13:26:54 +0530619enum reg_ext_bitmap {
620 REG_EXT_JAPAN_MIDBAND = 1,
621 REG_EXT_FCC_DFS_HT40 = 2,
622 REG_EXT_JAPAN_NONDFS_HT40 = 3,
623 REG_EXT_JAPAN_DFS_HT40 = 4
624};
625
626struct ath9k_country_entry {
627 u16 countryCode;
628 u16 regDmnEnum;
629 u16 regDmn5G;
630 u16 regDmn2G;
631 u8 isMultidomain;
632 u8 iso[3];
633};
634
Sujith2660b812009-02-09 13:27:26 +0530635enum ath9k_eep_map {
Sujith394cf0a2009-02-09 13:26:54 +0530636 EEP_MAP_DEFAULT = 0x0,
637 EEP_MAP_4KBITS,
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530638 EEP_MAP_AR9287,
Sujith394cf0a2009-02-09 13:26:54 +0530639 EEP_MAP_MAX
640};
641
Sujithe1537892009-02-09 13:27:15 +0530642struct eeprom_ops {
643 int (*check_eeprom)(struct ath_hw *hw);
644 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
645 bool (*fill_eeprom)(struct ath_hw *hw);
646 int (*get_eeprom_ver)(struct ath_hw *hw);
647 int (*get_eeprom_rev)(struct ath_hw *hw);
648 u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
649 u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
650 struct ath9k_channel *chan);
Sujithd6509152009-03-13 08:56:05 +0530651 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
Sujithe1537892009-02-09 13:27:15 +0530652 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -0700653 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
Sujithe1537892009-02-09 13:27:15 +0530654 u16 cfgCtl, u8 twiceAntennaReduction,
655 u8 twiceMaxRegulatoryPower, u8 powerLimit);
656 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
657};
658
Sujithb5aec952009-08-07 09:45:15 +0530659void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
660 u32 shift, u32 val);
661int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
662 int16_t targetLeft,
663 int16_t targetRight);
664bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
665 u16 *indexL, u16 *indexR);
666bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data);
667void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
668 u8 *pVpdList, u16 numIntercepts,
669 u8 *pRetVpdList);
670void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
671 struct ath9k_channel *chan,
672 struct cal_target_power_leg *powInfo,
673 u16 numChannels,
674 struct cal_target_power_leg *pNewPower,
675 u16 numRates, bool isExtTarget);
676void ath9k_hw_get_target_powers(struct ath_hw *ah,
677 struct ath9k_channel *chan,
678 struct cal_target_power_ht *powInfo,
679 u16 numChannels,
680 struct cal_target_power_ht *pNewPower,
681 u16 numRates, bool isHt40Target);
682u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
683 bool is2GHz, int num_band_edges);
684int ath9k_hw_eeprom_init(struct ath_hw *ah);
685
Sujith394cf0a2009-02-09 13:26:54 +0530686#define ar5416_get_ntxchains(_txchainmask) \
Sujithf74df6f2009-02-09 13:27:24 +0530687 (((_txchainmask >> 2) & 1) + \
Sujith394cf0a2009-02-09 13:26:54 +0530688 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
689
Sujithb5aec952009-08-07 09:45:15 +0530690extern const struct eeprom_ops eep_def_ops;
691extern const struct eeprom_ops eep_4k_ops;
692extern const struct eeprom_ops eep_AR9287_ops;
Sujith394cf0a2009-02-09 13:26:54 +0530693
694#endif /* EEPROM_H */