blob: 1620b83cd13eea594b091cc1f19dc655a0eb2e8d [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Setting up the clock on the MIPS boards.
19 */
20
21#include <linux/types.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/init.h>
23#include <linux/kernel_stat.h>
24#include <linux/sched.h>
25#include <linux/spinlock.h>
26#include <linux/interrupt.h>
27#include <linux/time.h>
28#include <linux/timex.h>
29#include <linux/mc146818rtc.h>
30
31#include <asm/mipsregs.h>
Ralf Baechle41c594a2006-04-05 09:45:45 +010032#include <asm/mipsmtregs.h>
Ralf Baechlee01402b2005-07-14 15:57:16 +000033#include <asm/hardirq.h>
Ralf Baechled865bea2007-10-11 23:46:10 +010034#include <asm/i8253.h>
Ralf Baechlee01402b2005-07-14 15:57:16 +000035#include <asm/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <asm/div64.h>
37#include <asm/cpu.h>
38#include <asm/time.h>
39#include <asm/mc146818-time.h>
Ralf Baechlee01402b2005-07-14 15:57:16 +000040#include <asm/msc01_ic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
42#include <asm/mips-boards/generic.h>
43#include <asm/mips-boards/prom.h>
Maciej W. Rozyckifc095a92006-09-12 19:12:18 +010044
Ralf Baechlee01402b2005-07-14 15:57:16 +000045#include <asm/mips-boards/maltaint.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046
47unsigned long cpu_khz;
48
Ralf Baechlee01402b2005-07-14 15:57:16 +000049static int mips_cpu_timer_irq;
Ralf Baechle39b8d522008-04-28 17:14:26 +010050static int mips_cpu_perf_irq;
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +010051extern int cp0_perfcount_irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Ralf Baechle937a8012006-10-07 19:44:33 +010053static void mips_timer_dispatch(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070054{
Ralf Baechle937a8012006-10-07 19:44:33 +010055 do_IRQ(mips_cpu_timer_irq);
Ralf Baechlee01402b2005-07-14 15:57:16 +000056}
57
Chris Dearmanffe9ee42007-05-24 22:24:20 +010058static void mips_perf_dispatch(void)
59{
Ralf Baechle39b8d522008-04-28 17:14:26 +010060 do_IRQ(mips_cpu_perf_irq);
Chris Dearmanffe9ee42007-05-24 22:24:20 +010061}
62
Ralf Baechle41c594a2006-04-05 09:45:45 +010063/*
Ralf Baechle224dc502006-10-21 02:05:20 +010064 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
Linus Torvalds1da177e2005-04-16 15:20:36 -070065 */
66static unsigned int __init estimate_cpu_frequency(void)
67{
68 unsigned int prid = read_c0_prid() & 0xffff00;
69 unsigned int count;
70
Ralf Baechlee79f55a2006-10-31 19:53:15 +000071 unsigned long flags;
Ralf Baechle70e46f42006-10-31 18:33:09 +000072 unsigned int start;
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
74 local_irq_save(flags);
75
76 /* Start counter exactly on falling edge of update flag */
77 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
78 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
79
80 /* Start r4k counter. */
Ralf Baechle70e46f42006-10-31 18:33:09 +000081 start = read_c0_count();
Linus Torvalds1da177e2005-04-16 15:20:36 -070082
83 /* Read counter exactly on falling edge of update flag */
84 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
85 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
86
Ralf Baechle70e46f42006-10-31 18:33:09 +000087 count = read_c0_count() - start;
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
89 /* restore interrupts */
90 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -070091
92 mips_hpt_frequency = count;
93 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
94 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
95 count *= 2;
96
97 count += 5000; /* round */
98 count -= count%10000;
99
100 return count;
101}
102
Martin Schwidefskyd4f587c2009-08-14 15:47:31 +0200103void read_persistent_clock(struct timespec *ts)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104{
Martin Schwidefskyd4f587c2009-08-14 15:47:31 +0200105 ts->tv_sec = mc146818_get_cmos_time();
106 ts->tv_nsec = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107}
108
Dmitri Vorobievb31dc3c2008-04-01 02:03:23 +0400109static void __init plat_perf_setup(void)
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100110{
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100111#ifdef MSC01E_INT_BASE
112 if (cpu_has_veic) {
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100113 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100114 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100115 } else
116#endif
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +0100117 if (cp0_perfcount_irq >= 0) {
118 if (cpu_has_vint)
119 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100120 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100121#ifdef CONFIG_SMP
Thomas Gleixnere4ec7982011-03-27 15:19:28 +0200122 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100123#endif
124 }
125}
126
Ralf Baechle234fcd12008-03-08 09:56:28 +0000127unsigned int __cpuinit get_c0_compare_int(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128{
Chris Dearman7b4f4ec2007-05-24 22:46:25 +0100129#ifdef MSC01E_INT_BASE
Ralf Baechlee01402b2005-07-14 15:57:16 +0000130 if (cpu_has_veic) {
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100131 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
Ralf Baechlee01402b2005-07-14 15:57:16 +0000132 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
Ralf Baechle38760d42007-10-29 14:23:43 +0000133 } else
Chris Dearman7b4f4ec2007-05-24 22:46:25 +0100134#endif
135 {
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100136 if (cpu_has_vint)
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +0100137 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
138 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100139 }
Ralf Baechlee01402b2005-07-14 15:57:16 +0000140
Ralf Baechle38760d42007-10-29 14:23:43 +0000141 return mips_cpu_timer_irq;
142}
143
144void __init plat_time_init(void)
145{
146 unsigned int est_freq;
147
148 /* Set Data mode - binary. */
149 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
150
151 est_freq = estimate_cpu_frequency();
152
153 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
154 (est_freq%1000000)*100/1000000);
155
156 cpu_khz = est_freq / 1000;
157
158 mips_scroll_message();
159#ifdef CONFIG_I8253 /* Only Malta has a PIT */
160 setup_pit_timer();
Ralf Baechle340ee4b2005-08-17 17:44:08 +0000161#endif
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100162
Ralf Baechle91a2fcc2007-10-11 23:46:09 +0100163 plat_perf_setup();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164}