Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | comment "Processor Type" |
| 2 | |
| 3 | config CPU_32 |
| 4 | bool |
| 5 | default y |
| 6 | |
| 7 | # Select CPU types depending on the architecture selected. This selects |
| 8 | # which CPUs we support in the kernel image, and the compiler instruction |
| 9 | # optimiser behaviour. |
| 10 | |
| 11 | # ARM610 |
| 12 | config CPU_ARM610 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 13 | bool "Support ARM610 processor" if ARCH_RPC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | select CPU_32v3 |
| 15 | select CPU_CACHE_V3 |
| 16 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 17 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 18 | select CPU_COPY_V3 if MMU |
| 19 | select CPU_TLB_V3 if MMU |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 20 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | help |
| 22 | The ARM610 is the successor to the ARM3 processor |
| 23 | and was produced by VLSI Technology Inc. |
| 24 | |
| 25 | Say Y if you want support for the ARM610 processor. |
| 26 | Otherwise, say N. |
| 27 | |
Hyok S. Choi | 07e0da7 | 2006-09-26 17:37:36 +0900 | [diff] [blame] | 28 | # ARM7TDMI |
| 29 | config CPU_ARM7TDMI |
| 30 | bool "Support ARM7TDMI processor" |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 31 | depends on !MMU |
Hyok S. Choi | 07e0da7 | 2006-09-26 17:37:36 +0900 | [diff] [blame] | 32 | select CPU_32v4T |
| 33 | select CPU_ABRT_LV4T |
Catalin Marinas | 4a1fd55 | 2008-04-21 18:42:04 +0100 | [diff] [blame] | 34 | select CPU_PABRT_NOIFAR |
Hyok S. Choi | 07e0da7 | 2006-09-26 17:37:36 +0900 | [diff] [blame] | 35 | select CPU_CACHE_V4 |
| 36 | help |
| 37 | A 32-bit RISC microprocessor based on the ARM7 processor core |
| 38 | which has no memory control unit and cache. |
| 39 | |
| 40 | Say Y if you want support for the ARM7TDMI processor. |
| 41 | Otherwise, say N. |
| 42 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | # ARM710 |
| 44 | config CPU_ARM710 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 45 | bool "Support ARM710 processor" if ARCH_RPC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | select CPU_32v3 |
| 47 | select CPU_CACHE_V3 |
| 48 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 49 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 50 | select CPU_COPY_V3 if MMU |
| 51 | select CPU_TLB_V3 if MMU |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 52 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | help |
| 54 | A 32-bit RISC microprocessor based on the ARM7 processor core |
| 55 | designed by Advanced RISC Machines Ltd. The ARM710 is the |
| 56 | successor to the ARM610 processor. It was released in |
| 57 | July 1994 by VLSI Technology Inc. |
| 58 | |
| 59 | Say Y if you want support for the ARM710 processor. |
| 60 | Otherwise, say N. |
| 61 | |
| 62 | # ARM720T |
| 63 | config CPU_ARM720T |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 64 | bool "Support ARM720T processor" if ARCH_INTEGRATOR |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 65 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | select CPU_ABRT_LV4T |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 67 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | select CPU_CACHE_V4 |
| 69 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 70 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 71 | select CPU_COPY_V4WT if MMU |
| 72 | select CPU_TLB_V4WT if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | help |
| 74 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and |
| 75 | MMU built around an ARM7TDMI core. |
| 76 | |
| 77 | Say Y if you want support for the ARM720T processor. |
| 78 | Otherwise, say N. |
| 79 | |
Hyok S. Choi | b731c31 | 2006-09-26 17:37:50 +0900 | [diff] [blame] | 80 | # ARM740T |
| 81 | config CPU_ARM740T |
| 82 | bool "Support ARM740T processor" if ARCH_INTEGRATOR |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 83 | depends on !MMU |
Hyok S. Choi | b731c31 | 2006-09-26 17:37:50 +0900 | [diff] [blame] | 84 | select CPU_32v4T |
| 85 | select CPU_ABRT_LV4T |
Catalin Marinas | 4a1fd55 | 2008-04-21 18:42:04 +0100 | [diff] [blame] | 86 | select CPU_PABRT_NOIFAR |
Hyok S. Choi | b731c31 | 2006-09-26 17:37:50 +0900 | [diff] [blame] | 87 | select CPU_CACHE_V3 # although the core is v4t |
| 88 | select CPU_CP15_MPU |
| 89 | help |
| 90 | A 32-bit RISC processor with 8KB cache or 4KB variants, |
| 91 | write buffer and MPU(Protection Unit) built around |
| 92 | an ARM7TDMI core. |
| 93 | |
| 94 | Say Y if you want support for the ARM740T processor. |
| 95 | Otherwise, say N. |
| 96 | |
Hyok S. Choi | 43f5f01 | 2006-09-26 17:38:05 +0900 | [diff] [blame] | 97 | # ARM9TDMI |
| 98 | config CPU_ARM9TDMI |
| 99 | bool "Support ARM9TDMI processor" |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 100 | depends on !MMU |
Hyok S. Choi | 43f5f01 | 2006-09-26 17:38:05 +0900 | [diff] [blame] | 101 | select CPU_32v4T |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 102 | select CPU_ABRT_NOMMU |
Catalin Marinas | 4a1fd55 | 2008-04-21 18:42:04 +0100 | [diff] [blame] | 103 | select CPU_PABRT_NOIFAR |
Hyok S. Choi | 43f5f01 | 2006-09-26 17:38:05 +0900 | [diff] [blame] | 104 | select CPU_CACHE_V4 |
| 105 | help |
| 106 | A 32-bit RISC microprocessor based on the ARM9 processor core |
| 107 | which has no memory control unit and cache. |
| 108 | |
| 109 | Say Y if you want support for the ARM9TDMI processor. |
| 110 | Otherwise, say N. |
| 111 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | # ARM920T |
| 113 | config CPU_ARM920T |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 114 | bool "Support ARM920T processor" if ARCH_INTEGRATOR |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 115 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | select CPU_ABRT_EV4T |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 117 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | select CPU_CACHE_V4WT |
| 119 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 120 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 121 | select CPU_COPY_V4WB if MMU |
| 122 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | help |
| 124 | The ARM920T is licensed to be produced by numerous vendors, |
| 125 | and is used in the Maverick EP9312 and the Samsung S3C2410. |
| 126 | |
| 127 | More information on the Maverick EP9312 at |
| 128 | <http://linuxdevices.com/products/PD2382866068.html>. |
| 129 | |
| 130 | Say Y if you want support for the ARM920T processor. |
| 131 | Otherwise, say N. |
| 132 | |
| 133 | # ARM922T |
| 134 | config CPU_ARM922T |
| 135 | bool "Support ARM922T processor" if ARCH_INTEGRATOR |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 136 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | select CPU_ABRT_EV4T |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 138 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | select CPU_CACHE_V4WT |
| 140 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 141 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 142 | select CPU_COPY_V4WB if MMU |
| 143 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | help |
| 145 | The ARM922T is a version of the ARM920T, but with smaller |
| 146 | instruction and data caches. It is used in Altera's |
Andrew Victor | c53c9cf | 2007-05-11 21:01:28 +0100 | [diff] [blame] | 147 | Excalibur XA device family and Micrel's KS8695 Centaur. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 148 | |
| 149 | Say Y if you want support for the ARM922T processor. |
| 150 | Otherwise, say N. |
| 151 | |
| 152 | # ARM925T |
| 153 | config CPU_ARM925T |
Tony Lindgren | b288f75 | 2005-07-10 19:58:08 +0100 | [diff] [blame] | 154 | bool "Support ARM925T processor" if ARCH_OMAP1 |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 155 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | select CPU_ABRT_EV4T |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 157 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | select CPU_CACHE_V4WT |
| 159 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 160 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 161 | select CPU_COPY_V4WB if MMU |
| 162 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | help |
| 164 | The ARM925T is a mix between the ARM920T and ARM926T, but with |
| 165 | different instruction and data caches. It is used in TI's OMAP |
| 166 | device family. |
| 167 | |
| 168 | Say Y if you want support for the ARM925T processor. |
| 169 | Otherwise, say N. |
| 170 | |
| 171 | # ARM926T |
| 172 | config CPU_ARM926T |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 173 | bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | select CPU_32v5 |
| 175 | select CPU_ABRT_EV5TJ |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 176 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 178 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 179 | select CPU_COPY_V4WB if MMU |
| 180 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | help |
| 182 | This is a variant of the ARM920. It has slightly different |
| 183 | instruction sequences for cache and TLB operations. Curiously, |
| 184 | there is no documentation on it at the ARM corporate website. |
| 185 | |
| 186 | Say Y if you want support for the ARM926T processor. |
| 187 | Otherwise, say N. |
| 188 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 189 | # FA526 |
| 190 | config CPU_FA526 |
| 191 | bool |
| 192 | select CPU_32v4 |
| 193 | select CPU_ABRT_EV4 |
| 194 | select CPU_PABRT_NOIFAR |
| 195 | select CPU_CACHE_VIVT |
| 196 | select CPU_CP15_MMU |
| 197 | select CPU_CACHE_FA |
| 198 | select CPU_COPY_FA if MMU |
| 199 | select CPU_TLB_FA if MMU |
| 200 | help |
| 201 | The FA526 is a version of the ARMv4 compatible processor with |
| 202 | Branch Target Buffer, Unified TLB and cache line size 16. |
| 203 | |
| 204 | Say Y if you want support for the FA526 processor. |
| 205 | Otherwise, say N. |
| 206 | |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 207 | # ARM940T |
| 208 | config CPU_ARM940T |
| 209 | bool "Support ARM940T processor" if ARCH_INTEGRATOR |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 210 | depends on !MMU |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 211 | select CPU_32v4T |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 212 | select CPU_ABRT_NOMMU |
Catalin Marinas | 4a1fd55 | 2008-04-21 18:42:04 +0100 | [diff] [blame] | 213 | select CPU_PABRT_NOIFAR |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 214 | select CPU_CACHE_VIVT |
| 215 | select CPU_CP15_MPU |
| 216 | help |
| 217 | ARM940T is a member of the ARM9TDMI family of general- |
Matt LaPlante | 3cb2fcc | 2006-11-30 05:22:59 +0100 | [diff] [blame] | 218 | purpose microprocessors with MPU and separate 4KB |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 219 | instruction and 4KB data cases, each with a 4-word line |
| 220 | length. |
| 221 | |
| 222 | Say Y if you want support for the ARM940T processor. |
| 223 | Otherwise, say N. |
| 224 | |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 225 | # ARM946E-S |
| 226 | config CPU_ARM946E |
| 227 | bool "Support ARM946E-S processor" if ARCH_INTEGRATOR |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 228 | depends on !MMU |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 229 | select CPU_32v5 |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 230 | select CPU_ABRT_NOMMU |
Catalin Marinas | 4a1fd55 | 2008-04-21 18:42:04 +0100 | [diff] [blame] | 231 | select CPU_PABRT_NOIFAR |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 232 | select CPU_CACHE_VIVT |
| 233 | select CPU_CP15_MPU |
| 234 | help |
| 235 | ARM946E-S is a member of the ARM9E-S family of high- |
| 236 | performance, 32-bit system-on-chip processor solutions. |
| 237 | The TCM and ARMv5TE 32-bit instruction set is supported. |
| 238 | |
| 239 | Say Y if you want support for the ARM946E-S processor. |
| 240 | Otherwise, say N. |
| 241 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | # ARM1020 - needs validating |
| 243 | config CPU_ARM1020 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 244 | bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | select CPU_32v5 |
| 246 | select CPU_ABRT_EV4T |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 247 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | select CPU_CACHE_V4WT |
| 249 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 250 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 251 | select CPU_COPY_V4WB if MMU |
| 252 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 253 | help |
| 254 | The ARM1020 is the 32K cached version of the ARM10 processor, |
| 255 | with an addition of a floating-point unit. |
| 256 | |
| 257 | Say Y if you want support for the ARM1020 processor. |
| 258 | Otherwise, say N. |
| 259 | |
| 260 | # ARM1020E - needs validating |
| 261 | config CPU_ARM1020E |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 262 | bool "Support ARM1020E processor" if ARCH_INTEGRATOR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 263 | select CPU_32v5 |
| 264 | select CPU_ABRT_EV4T |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 265 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | select CPU_CACHE_V4WT |
| 267 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 268 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 269 | select CPU_COPY_V4WB if MMU |
| 270 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | depends on n |
| 272 | |
| 273 | # ARM1022E |
| 274 | config CPU_ARM1022 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 275 | bool "Support ARM1022E processor" if ARCH_INTEGRATOR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | select CPU_32v5 |
| 277 | select CPU_ABRT_EV4T |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 278 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 280 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 281 | select CPU_COPY_V4WB if MMU # can probably do better |
| 282 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | help |
| 284 | The ARM1022E is an implementation of the ARMv5TE architecture |
| 285 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, |
| 286 | embedded trace macrocell, and a floating-point unit. |
| 287 | |
| 288 | Say Y if you want support for the ARM1022E processor. |
| 289 | Otherwise, say N. |
| 290 | |
| 291 | # ARM1026EJ-S |
| 292 | config CPU_ARM1026 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 293 | bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | select CPU_32v5 |
| 295 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 296 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 298 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 299 | select CPU_COPY_V4WB if MMU # can probably do better |
| 300 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | help |
| 302 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture |
| 303 | based upon the ARM10 integer core. |
| 304 | |
| 305 | Say Y if you want support for the ARM1026EJ-S processor. |
| 306 | Otherwise, say N. |
| 307 | |
| 308 | # SA110 |
| 309 | config CPU_SA110 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 310 | bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 311 | select CPU_32v3 if ARCH_RPC |
| 312 | select CPU_32v4 if !ARCH_RPC |
| 313 | select CPU_ABRT_EV4 |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 314 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | select CPU_CACHE_V4WB |
| 316 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 317 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 318 | select CPU_COPY_V4WB if MMU |
| 319 | select CPU_TLB_V4WB if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 320 | help |
| 321 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and |
| 322 | is available at five speeds ranging from 100 MHz to 233 MHz. |
| 323 | More information is available at |
| 324 | <http://developer.intel.com/design/strong/sa110.htm>. |
| 325 | |
| 326 | Say Y if you want support for the SA-110 processor. |
| 327 | Otherwise, say N. |
| 328 | |
| 329 | # SA1100 |
| 330 | config CPU_SA1100 |
| 331 | bool |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | select CPU_32v4 |
| 333 | select CPU_ABRT_EV4 |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 334 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 335 | select CPU_CACHE_V4WB |
| 336 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 337 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 338 | select CPU_TLB_V4WB if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 339 | |
| 340 | # XScale |
| 341 | config CPU_XSCALE |
| 342 | bool |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 343 | select CPU_32v5 |
| 344 | select CPU_ABRT_EV5T |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 345 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 346 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 347 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 348 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 349 | |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 350 | # XScale Core Version 3 |
| 351 | config CPU_XSC3 |
| 352 | bool |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 353 | select CPU_32v5 |
| 354 | select CPU_ABRT_EV5T |
Catalin Marinas | 4a1fd55 | 2008-04-21 18:42:04 +0100 | [diff] [blame] | 355 | select CPU_PABRT_NOIFAR |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 356 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 357 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 358 | select CPU_TLB_V4WBI if MMU |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 359 | select IO_36 |
| 360 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 361 | # Marvell PJ1 (Mohawk) |
| 362 | config CPU_MOHAWK |
| 363 | bool |
| 364 | select CPU_32v5 |
| 365 | select CPU_ABRT_EV5T |
| 366 | select CPU_PABRT_NOIFAR |
| 367 | select CPU_CACHE_VIVT |
| 368 | select CPU_CP15_MMU |
| 369 | select CPU_TLB_V4WBI if MMU |
| 370 | select CPU_COPY_V4WB if MMU |
| 371 | |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 372 | # Feroceon |
| 373 | config CPU_FEROCEON |
| 374 | bool |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 375 | select CPU_32v5 |
| 376 | select CPU_ABRT_EV5T |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 377 | select CPU_PABRT_NOIFAR |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 378 | select CPU_CACHE_VIVT |
| 379 | select CPU_CP15_MMU |
Lennert Buytenhek | 0ed1507 | 2008-04-24 01:31:45 -0400 | [diff] [blame] | 380 | select CPU_COPY_FEROCEON if MMU |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 381 | select CPU_TLB_FEROCEON if MMU |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 382 | |
Tzachi Perelstein | d910a0a | 2007-11-06 10:35:40 +0200 | [diff] [blame] | 383 | config CPU_FEROCEON_OLD_ID |
| 384 | bool "Accept early Feroceon cores with an ARM926 ID" |
| 385 | depends on CPU_FEROCEON && !CPU_ARM926T |
| 386 | default y |
| 387 | help |
| 388 | This enables the usage of some old Feroceon cores |
| 389 | for which the CPU ID is equal to the ARM926 ID. |
| 390 | Relevant for Feroceon-1850 and early Feroceon-2850. |
| 391 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 392 | # ARMv6 |
| 393 | config CPU_V6 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 394 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | select CPU_32v6 |
| 396 | select CPU_ABRT_EV6 |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 397 | select CPU_PABRT_NOIFAR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 398 | select CPU_CACHE_V6 |
| 399 | select CPU_CACHE_VIPT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 400 | select CPU_CP15_MMU |
Catalin Marinas | 7b4c965 | 2007-07-20 11:42:57 +0100 | [diff] [blame] | 401 | select CPU_HAS_ASID if MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 402 | select CPU_COPY_V6 if MMU |
| 403 | select CPU_TLB_V6 if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 404 | |
Russell King | 4a5f79e | 2005-11-03 15:48:21 +0000 | [diff] [blame] | 405 | # ARMv6k |
| 406 | config CPU_32v6K |
| 407 | bool "Support ARM V6K processor extensions" if !SMP |
| 408 | depends on CPU_V6 |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 409 | default y if SMP && !ARCH_MX3 |
Russell King | 4a5f79e | 2005-11-03 15:48:21 +0000 | [diff] [blame] | 410 | help |
| 411 | Say Y here if your ARMv6 processor supports the 'K' extension. |
| 412 | This enables the kernel to use some instructions not present |
| 413 | on previous processors, and as such a kernel build with this |
| 414 | enabled will not boot on processors with do not support these |
| 415 | instructions. |
| 416 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 417 | # ARMv7 |
| 418 | config CPU_V7 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 419 | bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 420 | select CPU_32v6K |
| 421 | select CPU_32v7 |
| 422 | select CPU_ABRT_EV7 |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 423 | select CPU_PABRT_IFAR |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 424 | select CPU_CACHE_V7 |
| 425 | select CPU_CACHE_VIPT |
| 426 | select CPU_CP15_MMU |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 427 | select CPU_HAS_ASID if MMU |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 428 | select CPU_COPY_V6 if MMU |
Catalin Marinas | 2ccdd1e | 2007-05-18 11:25:31 +0100 | [diff] [blame] | 429 | select CPU_TLB_V7 if MMU |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 430 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 431 | # Figure out what processor architecture version we should be using. |
| 432 | # This defines the compiler instruction set which depends on the machine type. |
| 433 | config CPU_32v3 |
| 434 | bool |
Russell King | 60b6cf6 | 2006-06-19 17:36:43 +0100 | [diff] [blame] | 435 | select TLS_REG_EMUL if SMP || !MMU |
Russell King | 48fa14f | 2006-03-16 14:52:33 +0000 | [diff] [blame] | 436 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 437 | |
| 438 | config CPU_32v4 |
| 439 | bool |
Russell King | 60b6cf6 | 2006-06-19 17:36:43 +0100 | [diff] [blame] | 440 | select TLS_REG_EMUL if SMP || !MMU |
Russell King | 48fa14f | 2006-03-16 14:52:33 +0000 | [diff] [blame] | 441 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 442 | |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 443 | config CPU_32v4T |
| 444 | bool |
| 445 | select TLS_REG_EMUL if SMP || !MMU |
| 446 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
| 447 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | config CPU_32v5 |
| 449 | bool |
Russell King | 60b6cf6 | 2006-06-19 17:36:43 +0100 | [diff] [blame] | 450 | select TLS_REG_EMUL if SMP || !MMU |
Russell King | 48fa14f | 2006-03-16 14:52:33 +0000 | [diff] [blame] | 451 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 452 | |
| 453 | config CPU_32v6 |
| 454 | bool |
Catalin Marinas | 367afaf | 2007-07-20 11:42:51 +0100 | [diff] [blame] | 455 | select TLS_REG_EMUL if !CPU_32v6K && !MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 457 | config CPU_32v7 |
| 458 | bool |
| 459 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | # The abort model |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 461 | config CPU_ABRT_NOMMU |
| 462 | bool |
| 463 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | config CPU_ABRT_EV4 |
| 465 | bool |
| 466 | |
| 467 | config CPU_ABRT_EV4T |
| 468 | bool |
| 469 | |
| 470 | config CPU_ABRT_LV4T |
| 471 | bool |
| 472 | |
| 473 | config CPU_ABRT_EV5T |
| 474 | bool |
| 475 | |
| 476 | config CPU_ABRT_EV5TJ |
| 477 | bool |
| 478 | |
| 479 | config CPU_ABRT_EV6 |
| 480 | bool |
| 481 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 482 | config CPU_ABRT_EV7 |
| 483 | bool |
| 484 | |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 485 | config CPU_PABRT_IFAR |
| 486 | bool |
| 487 | |
| 488 | config CPU_PABRT_NOIFAR |
| 489 | bool |
| 490 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | # The cache model |
| 492 | config CPU_CACHE_V3 |
| 493 | bool |
| 494 | |
| 495 | config CPU_CACHE_V4 |
| 496 | bool |
| 497 | |
| 498 | config CPU_CACHE_V4WT |
| 499 | bool |
| 500 | |
| 501 | config CPU_CACHE_V4WB |
| 502 | bool |
| 503 | |
| 504 | config CPU_CACHE_V6 |
| 505 | bool |
| 506 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 507 | config CPU_CACHE_V7 |
| 508 | bool |
| 509 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 510 | config CPU_CACHE_VIVT |
| 511 | bool |
| 512 | |
| 513 | config CPU_CACHE_VIPT |
| 514 | bool |
| 515 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 516 | config CPU_CACHE_FA |
| 517 | bool |
| 518 | |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 519 | if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | # The copy-page model |
| 521 | config CPU_COPY_V3 |
| 522 | bool |
| 523 | |
| 524 | config CPU_COPY_V4WT |
| 525 | bool |
| 526 | |
| 527 | config CPU_COPY_V4WB |
| 528 | bool |
| 529 | |
Lennert Buytenhek | 0ed1507 | 2008-04-24 01:31:45 -0400 | [diff] [blame] | 530 | config CPU_COPY_FEROCEON |
| 531 | bool |
| 532 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 533 | config CPU_COPY_FA |
| 534 | bool |
| 535 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | config CPU_COPY_V6 |
| 537 | bool |
| 538 | |
| 539 | # This selects the TLB model |
| 540 | config CPU_TLB_V3 |
| 541 | bool |
| 542 | help |
| 543 | ARM Architecture Version 3 TLB. |
| 544 | |
| 545 | config CPU_TLB_V4WT |
| 546 | bool |
| 547 | help |
| 548 | ARM Architecture Version 4 TLB with writethrough cache. |
| 549 | |
| 550 | config CPU_TLB_V4WB |
| 551 | bool |
| 552 | help |
| 553 | ARM Architecture Version 4 TLB with writeback cache. |
| 554 | |
| 555 | config CPU_TLB_V4WBI |
| 556 | bool |
| 557 | help |
| 558 | ARM Architecture Version 4 TLB with writeback cache and invalidate |
| 559 | instruction cache entry. |
| 560 | |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 561 | config CPU_TLB_FEROCEON |
| 562 | bool |
| 563 | help |
| 564 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). |
| 565 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 566 | config CPU_TLB_FA |
| 567 | bool |
| 568 | help |
| 569 | Faraday ARM FA526 architecture, unified TLB with writeback cache |
| 570 | and invalidate instruction cache entry. Branch target buffer is |
| 571 | also supported. |
| 572 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 573 | config CPU_TLB_V6 |
| 574 | bool |
| 575 | |
Catalin Marinas | 2ccdd1e | 2007-05-18 11:25:31 +0100 | [diff] [blame] | 576 | config CPU_TLB_V7 |
| 577 | bool |
| 578 | |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 579 | endif |
| 580 | |
Russell King | 516793c | 2007-05-17 10:19:23 +0100 | [diff] [blame] | 581 | config CPU_HAS_ASID |
| 582 | bool |
| 583 | help |
| 584 | This indicates whether the CPU has the ASID register; used to |
| 585 | tag TLB and possibly cache entries. |
| 586 | |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 587 | config CPU_CP15 |
| 588 | bool |
| 589 | help |
| 590 | Processor has the CP15 register. |
| 591 | |
| 592 | config CPU_CP15_MMU |
| 593 | bool |
| 594 | select CPU_CP15 |
| 595 | help |
| 596 | Processor has the CP15 register, which has MMU related registers. |
| 597 | |
| 598 | config CPU_CP15_MPU |
| 599 | bool |
| 600 | select CPU_CP15 |
| 601 | help |
| 602 | Processor has the CP15 register, which has MPU related registers. |
| 603 | |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 604 | # |
| 605 | # CPU supports 36-bit I/O |
| 606 | # |
| 607 | config IO_36 |
| 608 | bool |
| 609 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 610 | comment "Processor Features" |
| 611 | |
| 612 | config ARM_THUMB |
| 613 | bool "Support Thumb user binaries" |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 614 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | default y |
| 616 | help |
| 617 | Say Y if you want to include kernel support for running user space |
| 618 | Thumb binaries. |
| 619 | |
| 620 | The Thumb instruction set is a compressed form of the standard ARM |
| 621 | instruction set resulting in smaller binaries at the expense of |
| 622 | slightly less efficient code. |
| 623 | |
| 624 | If you don't know what this all is, saying Y is a safe choice. |
| 625 | |
Catalin Marinas | d7f864b | 2008-04-18 22:43:06 +0100 | [diff] [blame] | 626 | config ARM_THUMBEE |
| 627 | bool "Enable ThumbEE CPU extension" |
| 628 | depends on CPU_V7 |
| 629 | help |
| 630 | Say Y here if you have a CPU with the ThumbEE extension and code to |
| 631 | make use of it. Say N for code that can run on CPUs without ThumbEE. |
| 632 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | config CPU_BIG_ENDIAN |
| 634 | bool "Build big-endian kernel" |
| 635 | depends on ARCH_SUPPORTS_BIG_ENDIAN |
| 636 | help |
| 637 | Say Y if you plan on running a kernel in big-endian mode. |
| 638 | Note that your board must be properly built and your board |
| 639 | port must properly enable any big-endian related features |
| 640 | of your chipset/board/processor. |
| 641 | |
Hyok S. Choi | 6afd6fa | 2006-09-28 21:46:34 +0900 | [diff] [blame] | 642 | config CPU_HIGH_VECTOR |
Robert P. J. Day | 6340aa6 | 2007-02-17 19:05:24 +0100 | [diff] [blame] | 643 | depends on !MMU && CPU_CP15 && !CPU_ARM740T |
Hyok S. Choi | 6afd6fa | 2006-09-28 21:46:34 +0900 | [diff] [blame] | 644 | bool "Select the High exception vector" |
| 645 | default n |
| 646 | help |
| 647 | Say Y here to select high exception vector(0xFFFF0000~). |
| 648 | The exception vector can be vary depending on the platform |
| 649 | design in nommu mode. If your platform needs to select |
| 650 | high exception vector, say Y. |
| 651 | Otherwise or if you are unsure, say N, and the low exception |
| 652 | vector (0x00000000~) will be used. |
| 653 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | config CPU_ICACHE_DISABLE |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 655 | bool "Disable I-Cache (I-bit)" |
| 656 | depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 657 | help |
| 658 | Say Y here to disable the processor instruction cache. Unless |
| 659 | you have a reason not to or are unsure, say N. |
| 660 | |
| 661 | config CPU_DCACHE_DISABLE |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 662 | bool "Disable D-Cache (C-bit)" |
| 663 | depends on CPU_CP15 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 664 | help |
| 665 | Say Y here to disable the processor data cache. Unless |
| 666 | you have a reason not to or are unsure, say N. |
| 667 | |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 668 | config CPU_DCACHE_SIZE |
| 669 | hex |
| 670 | depends on CPU_ARM740T || CPU_ARM946E |
| 671 | default 0x00001000 if CPU_ARM740T |
| 672 | default 0x00002000 # default size for ARM946E-S |
| 673 | help |
| 674 | Some cores are synthesizable to have various sized cache. For |
| 675 | ARM946E-S case, it can vary from 0KB to 1MB. |
| 676 | To support such cache operations, it is efficient to know the size |
| 677 | before compile time. |
| 678 | If your SoC is configured to have a different size, define the value |
| 679 | here with proper conditions. |
| 680 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 681 | config CPU_DCACHE_WRITETHROUGH |
| 682 | bool "Force write through D-cache" |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 683 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 684 | default y if CPU_ARM925T |
| 685 | help |
| 686 | Say Y here to use the data cache in writethrough mode. Unless you |
| 687 | specifically require this or are unsure, say N. |
| 688 | |
| 689 | config CPU_CACHE_ROUND_ROBIN |
| 690 | bool "Round robin I and D cache replacement algorithm" |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 691 | depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 692 | help |
| 693 | Say Y here to use the predictable round-robin cache replacement |
| 694 | policy. Unless you specifically require this or are unsure, say N. |
| 695 | |
| 696 | config CPU_BPREDICT_DISABLE |
| 697 | bool "Disable branch prediction" |
Russell King | 542f869 | 2009-03-26 23:10:11 +0000 | [diff] [blame] | 698 | depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 699 | help |
| 700 | Say Y here to disable branch prediction. If unsure, say N. |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 701 | |
Nicolas Pitre | 4b0e07a | 2005-05-05 23:24:45 +0100 | [diff] [blame] | 702 | config TLS_REG_EMUL |
| 703 | bool |
Nicolas Pitre | 4b0e07a | 2005-05-05 23:24:45 +0100 | [diff] [blame] | 704 | help |
Nicolas Pitre | 70489c8 | 2005-05-12 19:27:12 +0100 | [diff] [blame] | 705 | An SMP system using a pre-ARMv6 processor (there are apparently |
| 706 | a few prototypes like that in existence) and therefore access to |
| 707 | that required register must be emulated. |
Nicolas Pitre | 4b0e07a | 2005-05-05 23:24:45 +0100 | [diff] [blame] | 708 | |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 709 | config HAS_TLS_REG |
| 710 | bool |
Nicolas Pitre | 70489c8 | 2005-05-12 19:27:12 +0100 | [diff] [blame] | 711 | depends on !TLS_REG_EMUL |
| 712 | default y if SMP || CPU_32v7 |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 713 | help |
| 714 | This selects support for the CP15 thread register. |
Nicolas Pitre | 70489c8 | 2005-05-12 19:27:12 +0100 | [diff] [blame] | 715 | It is defined to be available on some ARMv6 processors (including |
| 716 | all SMP capable ARMv6's) or later processors. User space may |
| 717 | assume directly accessing that register and always obtain the |
| 718 | expected value only on ARMv7 and above. |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 719 | |
Nicolas Pitre | dcef1f6 | 2005-06-08 19:00:47 +0100 | [diff] [blame] | 720 | config NEEDS_SYSCALL_FOR_CMPXCHG |
| 721 | bool |
Nicolas Pitre | dcef1f6 | 2005-06-08 19:00:47 +0100 | [diff] [blame] | 722 | help |
| 723 | SMP on a pre-ARMv6 processor? Well OK then. |
| 724 | Forget about fast user space cmpxchg support. |
| 725 | It is just not possible. |
| 726 | |
Catalin Marinas | 953233d | 2007-02-05 14:48:08 +0100 | [diff] [blame] | 727 | config OUTER_CACHE |
| 728 | bool |
| 729 | default n |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 730 | |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 731 | config CACHE_FEROCEON_L2 |
| 732 | bool "Enable the Feroceon L2 cache controller" |
Stanislav Samsonov | 794d15b | 2008-06-22 22:45:10 +0200 | [diff] [blame] | 733 | depends on ARCH_KIRKWOOD || ARCH_MV78XX0 |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 734 | default y |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 735 | select OUTER_CACHE |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 736 | help |
| 737 | This option enables the Feroceon L2 cache controller. |
| 738 | |
Ronen Shitrit | 4360bb4 | 2008-09-23 15:28:10 +0300 | [diff] [blame] | 739 | config CACHE_FEROCEON_L2_WRITETHROUGH |
| 740 | bool "Force Feroceon L2 cache write through" |
| 741 | depends on CACHE_FEROCEON_L2 |
| 742 | default n |
| 743 | help |
| 744 | Say Y here to use the Feroceon L2 cache in writethrough mode. |
| 745 | Unless you specifically require this, say N for writeback mode. |
| 746 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | config CACHE_L2X0 |
Catalin Marinas | ba92795 | 2008-04-18 22:43:17 +0100 | [diff] [blame] | 748 | bool "Enable the L2x0 outer cache controller" |
Sascha Hauer | cb88214 | 2009-02-08 02:00:50 +0100 | [diff] [blame] | 749 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ |
| 750 | REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 |
Catalin Marinas | ba92795 | 2008-04-18 22:43:17 +0100 | [diff] [blame] | 751 | default y |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 752 | select OUTER_CACHE |
Catalin Marinas | ba92795 | 2008-04-18 22:43:17 +0100 | [diff] [blame] | 753 | help |
| 754 | This option enables the L2x0 PrimeCell. |
Eric Miao | 905a09d | 2008-06-06 16:34:03 +0800 | [diff] [blame] | 755 | |
| 756 | config CACHE_XSC3L2 |
| 757 | bool "Enable the L2 cache on XScale3" |
| 758 | depends on CPU_XSC3 |
| 759 | default y |
| 760 | select OUTER_CACHE |
| 761 | help |
| 762 | This option enables the L2 cache on XScale3. |