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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
Ayaz Abdulla87046e52006-12-19 23:33:32 -05006 * and Andrew de Quincey.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
Manfred Spraul18360982005-12-24 14:19:24 +010012 * Copyright (C) 2003,4,5 Manfred Spraul
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
Ayaz Abdullaf1405d322009-01-09 11:03:54 +000016 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
Ayaz Abdulla3e1a3ce2009-03-05 08:02:38 +000042#define FORCEDETH_VERSION "0.64"
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#define DRV_NAME "forcedeth"
44
45#include <linux/module.h>
46#include <linux/types.h>
47#include <linux/pci.h>
48#include <linux/interrupt.h>
49#include <linux/netdevice.h>
50#include <linux/etherdevice.h>
51#include <linux/delay.h>
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040052#include <linux/sched.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#include <linux/spinlock.h>
54#include <linux/ethtool.h>
55#include <linux/timer.h>
56#include <linux/skbuff.h>
57#include <linux/mii.h>
58#include <linux/random.h>
59#include <linux/init.h>
Manfred Spraul22c6d142005-04-19 21:17:09 +020060#include <linux/if_vlan.h>
Matthias Gehre910638a2006-03-28 01:56:48 -080061#include <linux/dma-mapping.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090062#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
64#include <asm/irq.h>
65#include <asm/io.h>
66#include <asm/uaccess.h>
67#include <asm/system.h>
68
69#if 0
70#define dprintk printk
71#else
72#define dprintk(x...) do { } while (0)
73#endif
74
Stephen Hemmingerbea33482007-10-03 16:41:36 -070075#define TX_WORK_PER_LOOP 64
76#define RX_WORK_PER_LOOP 64
Linus Torvalds1da177e2005-04-16 15:20:36 -070077
78/*
79 * Hardware access:
80 */
81
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +000082#define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
83#define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
84#define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
85#define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
86#define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
87#define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
88#define DEV_HAS_MSI 0x0000040 /* device supports MSI */
89#define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
90#define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
91#define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
92#define DEV_HAS_STATISTICS_V2 0x0000600 /* device supports hw statistics version 2 */
93#define DEV_HAS_STATISTICS_V3 0x0000e00 /* device supports hw statistics version 3 */
94#define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
95#define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
96#define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
97#define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
98#define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
99#define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
100#define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
101#define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
102#define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
103#define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
104#define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
105#define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
106#define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107
108enum {
109 NvRegIrqStatus = 0x000,
110#define NVREG_IRQSTAT_MIIEVENT 0x040
Ayaz Abdulladaa91a92009-02-07 00:25:00 -0800111#define NVREG_IRQSTAT_MASK 0x83ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 NvRegIrqMask = 0x004,
113#define NVREG_IRQ_RX_ERROR 0x0001
114#define NVREG_IRQ_RX 0x0002
115#define NVREG_IRQ_RX_NOBUF 0x0004
116#define NVREG_IRQ_TX_ERR 0x0008
Manfred Spraulc2dba062005-07-31 18:29:47 +0200117#define NVREG_IRQ_TX_OK 0x0010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118#define NVREG_IRQ_TIMER 0x0020
119#define NVREG_IRQ_LINK 0x0040
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500120#define NVREG_IRQ_RX_FORCED 0x0080
121#define NVREG_IRQ_TX_FORCED 0x0100
Ayaz Abdulladaa91a92009-02-07 00:25:00 -0800122#define NVREG_IRQ_RECOVER_ERROR 0x8200
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500123#define NVREG_IRQMASK_THROUGHPUT 0x00df
Ayaz Abdulla096a4582007-05-21 20:23:11 -0400124#define NVREG_IRQMASK_CPU 0x0060
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500125#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
126#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500127#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 NvRegUnknownSetupReg6 = 0x008,
130#define NVREG_UNKSETUP6_VAL 3
131
132/*
133 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
134 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
135 */
136 NvRegPollingInterval = 0x00c,
Ayaz Abdulla6cef67a2009-03-05 08:02:30 +0000137#define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500138#define NVREG_POLL_DEFAULT_CPU 13
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500139 NvRegMSIMap0 = 0x020,
140 NvRegMSIMap1 = 0x024,
141 NvRegMSIIrqMask = 0x030,
142#define NVREG_MSI_VECTOR_0_ENABLED 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 NvRegMisc1 = 0x080,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400144#define NVREG_MISC1_PAUSE_TX 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145#define NVREG_MISC1_HD 0x02
146#define NVREG_MISC1_FORCE 0x3b0f3c
147
Ayaz Abdulla0a626772008-01-13 16:02:42 -0500148 NvRegMacReset = 0x34,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400149#define NVREG_MAC_RESET_ASSERT 0x0F3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150 NvRegTransmitterControl = 0x084,
151#define NVREG_XMITCTL_START 0x01
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500152#define NVREG_XMITCTL_MGMT_ST 0x40000000
153#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
154#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
155#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
156#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
157#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
158#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
159#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
160#define NVREG_XMITCTL_HOST_LOADED 0x00004000
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500161#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800162#define NVREG_XMITCTL_DATA_START 0x00100000
163#define NVREG_XMITCTL_DATA_READY 0x00010000
164#define NVREG_XMITCTL_DATA_ERROR 0x00020000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165 NvRegTransmitterStatus = 0x088,
166#define NVREG_XMITSTAT_BUSY 0x01
167
168 NvRegPacketFilterFlags = 0x8c,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400169#define NVREG_PFF_PAUSE_RX 0x08
170#define NVREG_PFF_ALWAYS 0x7F0000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171#define NVREG_PFF_PROMISC 0x80
172#define NVREG_PFF_MYADDR 0x20
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400173#define NVREG_PFF_LOOPBACK 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174
175 NvRegOffloadConfig = 0x90,
176#define NVREG_OFFLOAD_HOMEPHY 0x601
177#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
178 NvRegReceiverControl = 0x094,
179#define NVREG_RCVCTL_START 0x01
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500180#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 NvRegReceiverStatus = 0x98,
182#define NVREG_RCVSTAT_BUSY 0x01
183
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700184 NvRegSlotTime = 0x9c,
185#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
186#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
187#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
188#define NVREG_SLOTTIME_HALF 0x0000ff00
189#define NVREG_SLOTTIME_DEFAULT 0x00007f00
190#define NVREG_SLOTTIME_MASK 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400192 NvRegTxDeferral = 0xA0,
Ayaz Abdullafd9b5582008-02-05 12:29:49 -0500193#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
194#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
195#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
196#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
197#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
198#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400199 NvRegRxDeferral = 0xA4,
200#define NVREG_RX_DEFERRAL_DEFAULT 0x16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 NvRegMacAddrA = 0xA8,
202 NvRegMacAddrB = 0xAC,
203 NvRegMulticastAddrA = 0xB0,
204#define NVREG_MCASTADDRA_FORCE 0x01
205 NvRegMulticastAddrB = 0xB4,
206 NvRegMulticastMaskA = 0xB8,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500207#define NVREG_MCASTMASKA_NONE 0xffffffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208 NvRegMulticastMaskB = 0xBC,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500209#define NVREG_MCASTMASKB_NONE 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210
211 NvRegPhyInterface = 0xC0,
212#define PHY_RGMII 0x10000000
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700213 NvRegBackOffControl = 0xC4,
214#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
215#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
216#define NVREG_BKOFFCTRL_SELECT 24
217#define NVREG_BKOFFCTRL_GEAR 12
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218
219 NvRegTxRingPhysAddr = 0x100,
220 NvRegRxRingPhysAddr = 0x104,
221 NvRegRingSizes = 0x108,
222#define NVREG_RINGSZ_TXSHIFT 0
223#define NVREG_RINGSZ_RXSHIFT 16
Ayaz Abdulla5070d342006-07-31 12:05:01 -0400224 NvRegTransmitPoll = 0x10c,
225#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226 NvRegLinkSpeed = 0x110,
227#define NVREG_LINKSPEED_FORCE 0x10000
228#define NVREG_LINKSPEED_10 1000
229#define NVREG_LINKSPEED_100 100
230#define NVREG_LINKSPEED_1000 50
231#define NVREG_LINKSPEED_MASK (0xFFF)
232 NvRegUnknownSetupReg5 = 0x130,
233#define NVREG_UNKSETUP5_BIT31 (1<<31)
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400234 NvRegTxWatermark = 0x13c,
235#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
236#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
237#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 NvRegTxRxControl = 0x144,
239#define NVREG_TXRXCTL_KICK 0x0001
240#define NVREG_TXRXCTL_BIT1 0x0002
241#define NVREG_TXRXCTL_BIT2 0x0004
242#define NVREG_TXRXCTL_IDLE 0x0008
243#define NVREG_TXRXCTL_RESET 0x0010
244#define NVREG_TXRXCTL_RXCHECK 0x0400
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400245#define NVREG_TXRXCTL_DESC_1 0
Ayaz Abdullad2f78412007-01-09 13:30:02 -0500246#define NVREG_TXRXCTL_DESC_2 0x002100
247#define NVREG_TXRXCTL_DESC_3 0xc02200
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500248#define NVREG_TXRXCTL_VLANSTRIP 0x00040
249#define NVREG_TXRXCTL_VLANINS 0x00080
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500250 NvRegTxRingPhysAddrHigh = 0x148,
251 NvRegRxRingPhysAddrHigh = 0x14C,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400252 NvRegTxPauseFrame = 0x170,
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -0500253#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
254#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
255#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
256#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
Ayaz Abdulla9a33e882008-08-06 12:12:34 -0400257 NvRegTxPauseFrameLimit = 0x174,
258#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259 NvRegMIIStatus = 0x180,
260#define NVREG_MIISTAT_ERROR 0x0001
261#define NVREG_MIISTAT_LINKCHANGE 0x0008
Ayaz Abdullaeb798422008-02-04 15:14:04 -0500262#define NVREG_MIISTAT_MASK_RW 0x0007
263#define NVREG_MIISTAT_MASK_ALL 0x000f
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500264 NvRegMIIMask = 0x184,
265#define NVREG_MII_LINKCHANGE 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266
267 NvRegAdapterControl = 0x188,
268#define NVREG_ADAPTCTL_START 0x02
269#define NVREG_ADAPTCTL_LINKUP 0x04
270#define NVREG_ADAPTCTL_PHYVALID 0x40000
271#define NVREG_ADAPTCTL_RUNNING 0x100000
272#define NVREG_ADAPTCTL_PHYSHIFT 24
273 NvRegMIISpeed = 0x18c,
274#define NVREG_MIISPEED_BIT8 (1<<8)
275#define NVREG_MIIDELAY 5
276 NvRegMIIControl = 0x190,
277#define NVREG_MIICTL_INUSE 0x08000
278#define NVREG_MIICTL_WRITE 0x00400
279#define NVREG_MIICTL_ADDRSHIFT 5
280 NvRegMIIData = 0x194,
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400281 NvRegTxUnicast = 0x1a0,
282 NvRegTxMulticast = 0x1a4,
283 NvRegTxBroadcast = 0x1a8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284 NvRegWakeUpFlags = 0x200,
285#define NVREG_WAKEUPFLAGS_VAL 0x7770
286#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
287#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
288#define NVREG_WAKEUPFLAGS_D3SHIFT 12
289#define NVREG_WAKEUPFLAGS_D2SHIFT 8
290#define NVREG_WAKEUPFLAGS_D1SHIFT 4
291#define NVREG_WAKEUPFLAGS_D0SHIFT 0
292#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
293#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
294#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
295#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
296
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800297 NvRegMgmtUnitGetVersion = 0x204,
298#define NVREG_MGMTUNITGETVERSION 0x01
299 NvRegMgmtUnitVersion = 0x208,
300#define NVREG_MGMTUNITVERSION 0x08
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 NvRegPowerCap = 0x268,
302#define NVREG_POWERCAP_D3SUPP (1<<30)
303#define NVREG_POWERCAP_D2SUPP (1<<26)
304#define NVREG_POWERCAP_D1SUPP (1<<25)
305 NvRegPowerState = 0x26c,
306#define NVREG_POWERSTATE_POWEREDUP 0x8000
307#define NVREG_POWERSTATE_VALID 0x0100
308#define NVREG_POWERSTATE_MASK 0x0003
309#define NVREG_POWERSTATE_D0 0x0000
310#define NVREG_POWERSTATE_D1 0x0001
311#define NVREG_POWERSTATE_D2 0x0002
312#define NVREG_POWERSTATE_D3 0x0003
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800313 NvRegMgmtUnitControl = 0x278,
314#define NVREG_MGMTUNITCONTROL_INUSE 0x20000
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400315 NvRegTxCnt = 0x280,
316 NvRegTxZeroReXmt = 0x284,
317 NvRegTxOneReXmt = 0x288,
318 NvRegTxManyReXmt = 0x28c,
319 NvRegTxLateCol = 0x290,
320 NvRegTxUnderflow = 0x294,
321 NvRegTxLossCarrier = 0x298,
322 NvRegTxExcessDef = 0x29c,
323 NvRegTxRetryErr = 0x2a0,
324 NvRegRxFrameErr = 0x2a4,
325 NvRegRxExtraByte = 0x2a8,
326 NvRegRxLateCol = 0x2ac,
327 NvRegRxRunt = 0x2b0,
328 NvRegRxFrameTooLong = 0x2b4,
329 NvRegRxOverflow = 0x2b8,
330 NvRegRxFCSErr = 0x2bc,
331 NvRegRxFrameAlignErr = 0x2c0,
332 NvRegRxLenErr = 0x2c4,
333 NvRegRxUnicast = 0x2c8,
334 NvRegRxMulticast = 0x2cc,
335 NvRegRxBroadcast = 0x2d0,
336 NvRegTxDef = 0x2d4,
337 NvRegTxFrame = 0x2d8,
338 NvRegRxCnt = 0x2dc,
339 NvRegTxPause = 0x2e0,
340 NvRegRxPause = 0x2e4,
341 NvRegRxDropFrame = 0x2e8,
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500342 NvRegVlanControl = 0x300,
343#define NVREG_VLANCONTROL_ENABLE 0x2000
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500344 NvRegMSIXMap0 = 0x3e0,
345 NvRegMSIXMap1 = 0x3e4,
346 NvRegMSIXIrqStatus = 0x3f0,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400347
348 NvRegPowerState2 = 0x600,
Ayaz Abdulla1545e202008-09-22 09:55:35 -0400349#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400350#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400351#define NVREG_POWERSTATE2_PHY_RESET 0x0004
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +0000352#define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353};
354
355/* Big endian: should work, but is untested */
356struct ring_desc {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700357 __le32 buf;
358 __le32 flaglen;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359};
360
Manfred Spraulee733622005-07-31 18:32:26 +0200361struct ring_desc_ex {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700362 __le32 bufhigh;
363 __le32 buflow;
364 __le32 txvlan;
365 __le32 flaglen;
Manfred Spraulee733622005-07-31 18:32:26 +0200366};
367
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700368union ring_type {
Manfred Spraulee733622005-07-31 18:32:26 +0200369 struct ring_desc* orig;
370 struct ring_desc_ex* ex;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700371};
Manfred Spraulee733622005-07-31 18:32:26 +0200372
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373#define FLAG_MASK_V1 0xffff0000
374#define FLAG_MASK_V2 0xffffc000
375#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
376#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
377
378#define NV_TX_LASTPACKET (1<<16)
379#define NV_TX_RETRYERROR (1<<19)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700380#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200381#define NV_TX_FORCED_INTERRUPT (1<<24)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382#define NV_TX_DEFERRED (1<<26)
383#define NV_TX_CARRIERLOST (1<<27)
384#define NV_TX_LATECOLLISION (1<<28)
385#define NV_TX_UNDERFLOW (1<<29)
386#define NV_TX_ERROR (1<<30)
387#define NV_TX_VALID (1<<31)
388
389#define NV_TX2_LASTPACKET (1<<29)
390#define NV_TX2_RETRYERROR (1<<18)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700391#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200392#define NV_TX2_FORCED_INTERRUPT (1<<30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393#define NV_TX2_DEFERRED (1<<25)
394#define NV_TX2_CARRIERLOST (1<<26)
395#define NV_TX2_LATECOLLISION (1<<27)
396#define NV_TX2_UNDERFLOW (1<<28)
397/* error and valid are the same for both */
398#define NV_TX2_ERROR (1<<30)
399#define NV_TX2_VALID (1<<31)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400400#define NV_TX2_TSO (1<<28)
401#define NV_TX2_TSO_SHIFT 14
Ayaz Abdullafa454592006-01-05 22:45:45 -0800402#define NV_TX2_TSO_MAX_SHIFT 14
403#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400404#define NV_TX2_CHECKSUM_L3 (1<<27)
405#define NV_TX2_CHECKSUM_L4 (1<<26)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500407#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
408
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409#define NV_RX_DESCRIPTORVALID (1<<16)
410#define NV_RX_MISSEDFRAME (1<<17)
411#define NV_RX_SUBSTRACT1 (1<<18)
412#define NV_RX_ERROR1 (1<<23)
413#define NV_RX_ERROR2 (1<<24)
414#define NV_RX_ERROR3 (1<<25)
415#define NV_RX_ERROR4 (1<<26)
416#define NV_RX_CRCERR (1<<27)
417#define NV_RX_OVERFLOW (1<<28)
418#define NV_RX_FRAMINGERR (1<<29)
419#define NV_RX_ERROR (1<<30)
420#define NV_RX_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400421#define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422
423#define NV_RX2_CHECKSUMMASK (0x1C000000)
Ayaz Abdullabfaffe82008-01-13 16:02:55 -0500424#define NV_RX2_CHECKSUM_IP (0x10000000)
425#define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
426#define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427#define NV_RX2_DESCRIPTORVALID (1<<29)
428#define NV_RX2_SUBSTRACT1 (1<<25)
429#define NV_RX2_ERROR1 (1<<18)
430#define NV_RX2_ERROR2 (1<<19)
431#define NV_RX2_ERROR3 (1<<20)
432#define NV_RX2_ERROR4 (1<<21)
433#define NV_RX2_CRCERR (1<<22)
434#define NV_RX2_OVERFLOW (1<<23)
435#define NV_RX2_FRAMINGERR (1<<24)
436/* error and avail are the same for both */
437#define NV_RX2_ERROR (1<<30)
438#define NV_RX2_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400439#define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500441#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
442#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
443
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444/* Miscelaneous hardware related defines: */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400445#define NV_PCI_REGSZ_VER1 0x270
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500446#define NV_PCI_REGSZ_VER2 0x2d4
447#define NV_PCI_REGSZ_VER3 0x604
Tobias Diedrich1a1ca862008-05-18 15:03:44 +0200448#define NV_PCI_REGSZ_MAX 0x604
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449
450/* various timeout delays: all in usec */
451#define NV_TXRX_RESET_DELAY 4
452#define NV_TXSTOP_DELAY1 10
453#define NV_TXSTOP_DELAY1MAX 500000
454#define NV_TXSTOP_DELAY2 100
455#define NV_RXSTOP_DELAY1 10
456#define NV_RXSTOP_DELAY1MAX 500000
457#define NV_RXSTOP_DELAY2 100
458#define NV_SETUP5_DELAY 5
459#define NV_SETUP5_DELAYMAX 50000
460#define NV_POWERUP_DELAY 5
461#define NV_POWERUP_DELAYMAX 5000
462#define NV_MIIBUSY_DELAY 50
463#define NV_MIIPHY_DELAY 10
464#define NV_MIIPHY_DELAYMAX 10000
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400465#define NV_MAC_RESET_DELAY 64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466
467#define NV_WAKEUPPATTERNS 5
468#define NV_WAKEUPMASKENTRIES 4
469
470/* General driver defaults */
471#define NV_WATCHDOG_TIMEO (5*HZ)
472
Ayaz Abdulla6cef67a2009-03-05 08:02:30 +0000473#define RX_RING_DEFAULT 512
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400474#define TX_RING_DEFAULT 256
475#define RX_RING_MIN 128
476#define TX_RING_MIN 64
477#define RING_MAX_DESC_VER_1 1024
478#define RING_MAX_DESC_VER_2_3 16384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479
480/* rx/tx mac addr + type + vlan + align + slack*/
Manfred Sprauld81c0982005-07-31 18:20:30 +0200481#define NV_RX_HEADERS (64)
482/* even more slack. */
483#define NV_RX_ALLOC_PAD (64)
484
485/* maximum mtu size */
486#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
487#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
489#define OOM_REFILL (1+HZ/20)
490#define POLL_WAIT (1+HZ/100)
491#define LINK_TIMEOUT (3*HZ)
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400492#define STATS_INTERVAL (10*HZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400494/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495 * desc_ver values:
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400496 * The nic supports three different descriptor types:
497 * - DESC_VER_1: Original
498 * - DESC_VER_2: support for jumbo frames.
499 * - DESC_VER_3: 64-bit format.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400501#define DESC_VER_1 1
502#define DESC_VER_2 2
503#define DESC_VER_3 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504
505/* PHY defines */
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400506#define PHY_OUI_MARVELL 0x5043
507#define PHY_OUI_CICADA 0x03f1
508#define PHY_OUI_VITESSE 0x01c1
509#define PHY_OUI_REALTEK 0x0732
510#define PHY_OUI_REALTEK2 0x0020
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511#define PHYID1_OUI_MASK 0x03ff
512#define PHYID1_OUI_SHFT 6
513#define PHYID2_OUI_MASK 0xfc00
514#define PHYID2_OUI_SHFT 10
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400515#define PHYID2_MODEL_MASK 0x03f0
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400516#define PHY_MODEL_REALTEK_8211 0x0110
517#define PHY_REV_MASK 0x0001
518#define PHY_REV_REALTEK_8211B 0x0000
519#define PHY_REV_REALTEK_8211C 0x0001
520#define PHY_MODEL_REALTEK_8201 0x0200
521#define PHY_MODEL_MARVELL_E3016 0x0220
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400522#define PHY_MARVELL_E3016_INITMASK 0x0300
Ayaz Abdulla14a67f32007-07-15 06:50:28 -0400523#define PHY_CICADA_INIT1 0x0f000
524#define PHY_CICADA_INIT2 0x0e00
525#define PHY_CICADA_INIT3 0x01000
526#define PHY_CICADA_INIT4 0x0200
527#define PHY_CICADA_INIT5 0x0004
528#define PHY_CICADA_INIT6 0x02000
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400529#define PHY_VITESSE_INIT_REG1 0x1f
530#define PHY_VITESSE_INIT_REG2 0x10
531#define PHY_VITESSE_INIT_REG3 0x11
532#define PHY_VITESSE_INIT_REG4 0x12
533#define PHY_VITESSE_INIT_MSK1 0xc
534#define PHY_VITESSE_INIT_MSK2 0x0180
535#define PHY_VITESSE_INIT1 0x52b5
536#define PHY_VITESSE_INIT2 0xaf8a
537#define PHY_VITESSE_INIT3 0x8
538#define PHY_VITESSE_INIT4 0x8f8a
539#define PHY_VITESSE_INIT5 0xaf86
540#define PHY_VITESSE_INIT6 0x8f86
541#define PHY_VITESSE_INIT7 0xaf82
542#define PHY_VITESSE_INIT8 0x0100
543#define PHY_VITESSE_INIT9 0x8f82
544#define PHY_VITESSE_INIT10 0x0
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400545#define PHY_REALTEK_INIT_REG1 0x1f
546#define PHY_REALTEK_INIT_REG2 0x19
547#define PHY_REALTEK_INIT_REG3 0x13
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400548#define PHY_REALTEK_INIT_REG4 0x14
549#define PHY_REALTEK_INIT_REG5 0x18
550#define PHY_REALTEK_INIT_REG6 0x11
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400551#define PHY_REALTEK_INIT_REG7 0x01
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400552#define PHY_REALTEK_INIT1 0x0000
553#define PHY_REALTEK_INIT2 0x8e00
554#define PHY_REALTEK_INIT3 0x0001
555#define PHY_REALTEK_INIT4 0xad17
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400556#define PHY_REALTEK_INIT5 0xfb54
557#define PHY_REALTEK_INIT6 0xf5c7
558#define PHY_REALTEK_INIT7 0x1000
559#define PHY_REALTEK_INIT8 0x0003
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400560#define PHY_REALTEK_INIT9 0x0008
561#define PHY_REALTEK_INIT10 0x0005
562#define PHY_REALTEK_INIT11 0x0200
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400563#define PHY_REALTEK_INIT_MSK1 0x0003
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400564
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565#define PHY_GIGABIT 0x0100
566
567#define PHY_TIMEOUT 0x1
568#define PHY_ERROR 0x2
569
570#define PHY_100 0x1
571#define PHY_1000 0x2
572#define PHY_HALF 0x100
573
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400574#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
575#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
576#define NV_PAUSEFRAME_RX_ENABLE 0x0004
577#define NV_PAUSEFRAME_TX_ENABLE 0x0008
Ayaz Abdullab6d07732006-06-10 22:47:42 -0400578#define NV_PAUSEFRAME_RX_REQ 0x0010
579#define NV_PAUSEFRAME_TX_REQ 0x0020
580#define NV_PAUSEFRAME_AUTONEG 0x0040
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500582/* MSI/MSI-X defines */
583#define NV_MSI_X_MAX_VECTORS 8
584#define NV_MSI_X_VECTORS_MASK 0x000f
585#define NV_MSI_CAPABLE 0x0010
586#define NV_MSI_X_CAPABLE 0x0020
587#define NV_MSI_ENABLED 0x0040
588#define NV_MSI_X_ENABLED 0x0080
589
590#define NV_MSI_X_VECTOR_ALL 0x0
591#define NV_MSI_X_VECTOR_RX 0x0
592#define NV_MSI_X_VECTOR_TX 0x1
593#define NV_MSI_X_VECTOR_OTHER 0x2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594
Ayaz Abdullab6e44052009-02-07 00:24:15 -0800595#define NV_MSI_PRIV_OFFSET 0x68
596#define NV_MSI_PRIV_VALUE 0xffffffff
597
Ayaz Abdullab2976d22008-02-04 15:13:59 -0500598#define NV_RESTART_TX 0x1
599#define NV_RESTART_RX 0x2
600
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500601#define NV_TX_LIMIT_COUNT 16
602
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000603#define NV_DYNAMIC_THRESHOLD 4
604#define NV_DYNAMIC_MAX_QUIET_COUNT 2048
605
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400606/* statistics */
607struct nv_ethtool_str {
608 char name[ETH_GSTRING_LEN];
609};
610
611static const struct nv_ethtool_str nv_estats_str[] = {
612 { "tx_bytes" },
613 { "tx_zero_rexmt" },
614 { "tx_one_rexmt" },
615 { "tx_many_rexmt" },
616 { "tx_late_collision" },
617 { "tx_fifo_errors" },
618 { "tx_carrier_errors" },
619 { "tx_excess_deferral" },
620 { "tx_retry_error" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400621 { "rx_frame_error" },
622 { "rx_extra_byte" },
623 { "rx_late_collision" },
624 { "rx_runt" },
625 { "rx_frame_too_long" },
626 { "rx_over_errors" },
627 { "rx_crc_errors" },
628 { "rx_frame_align_error" },
629 { "rx_length_error" },
630 { "rx_unicast" },
631 { "rx_multicast" },
632 { "rx_broadcast" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400633 { "rx_packets" },
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500634 { "rx_errors_total" },
635 { "tx_errors_total" },
636
637 /* version 2 stats */
638 { "tx_deferral" },
639 { "tx_packets" },
640 { "rx_bytes" },
641 { "tx_pause" },
642 { "rx_pause" },
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400643 { "rx_drop_frame" },
644
645 /* version 3 stats */
646 { "tx_unicast" },
647 { "tx_multicast" },
648 { "tx_broadcast" }
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400649};
650
651struct nv_ethtool_stats {
652 u64 tx_bytes;
653 u64 tx_zero_rexmt;
654 u64 tx_one_rexmt;
655 u64 tx_many_rexmt;
656 u64 tx_late_collision;
657 u64 tx_fifo_errors;
658 u64 tx_carrier_errors;
659 u64 tx_excess_deferral;
660 u64 tx_retry_error;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400661 u64 rx_frame_error;
662 u64 rx_extra_byte;
663 u64 rx_late_collision;
664 u64 rx_runt;
665 u64 rx_frame_too_long;
666 u64 rx_over_errors;
667 u64 rx_crc_errors;
668 u64 rx_frame_align_error;
669 u64 rx_length_error;
670 u64 rx_unicast;
671 u64 rx_multicast;
672 u64 rx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400673 u64 rx_packets;
674 u64 rx_errors_total;
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500675 u64 tx_errors_total;
676
677 /* version 2 stats */
678 u64 tx_deferral;
679 u64 tx_packets;
680 u64 rx_bytes;
681 u64 tx_pause;
682 u64 rx_pause;
683 u64 rx_drop_frame;
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400684
685 /* version 3 stats */
686 u64 tx_unicast;
687 u64 tx_multicast;
688 u64 tx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400689};
690
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400691#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
692#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500693#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
694
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400695/* diagnostics */
696#define NV_TEST_COUNT_BASE 3
697#define NV_TEST_COUNT_EXTENDED 4
698
699static const struct nv_ethtool_str nv_etests_str[] = {
700 { "link (online/offline)" },
701 { "register (offline) " },
702 { "interrupt (offline) " },
703 { "loopback (offline) " }
704};
705
706struct register_test {
Al Viro5bb7ea22007-12-09 16:06:41 +0000707 __u32 reg;
708 __u32 mask;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400709};
710
711static const struct register_test nv_registers_test[] = {
712 { NvRegUnknownSetupReg6, 0x01 },
713 { NvRegMisc1, 0x03c },
714 { NvRegOffloadConfig, 0x03ff },
715 { NvRegMulticastAddrA, 0xffffffff },
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400716 { NvRegTxWatermark, 0x0ff },
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400717 { NvRegWakeUpFlags, 0x07777 },
718 { 0,0 }
719};
720
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500721struct nv_skb_map {
722 struct sk_buff *skb;
723 dma_addr_t dma;
Eric Dumazet73a37072009-06-17 21:17:59 +0000724 unsigned int dma_len:31;
725 unsigned int dma_single:1;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500726 struct ring_desc_ex *first_tx_desc;
727 struct nv_skb_map *next_tx_ctx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500728};
729
Linus Torvalds1da177e2005-04-16 15:20:36 -0700730/*
731 * SMP locking:
Wang Chenb74ca3a2008-12-08 01:14:16 -0800732 * All hardware access under netdev_priv(dev)->lock, except the performance
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733 * critical parts:
734 * - rx is (pseudo-) lockless: it relies on the single-threading provided
735 * by the arch code for interrupts.
Herbert Xu932ff272006-06-09 12:20:56 -0700736 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
Wang Chenb74ca3a2008-12-08 01:14:16 -0800737 * needs netdev_priv(dev)->lock :-(
Herbert Xu932ff272006-06-09 12:20:56 -0700738 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739 */
740
741/* in dev: base, irq */
742struct fe_priv {
743 spinlock_t lock;
744
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700745 struct net_device *dev;
746 struct napi_struct napi;
747
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748 /* General data:
749 * Locking: spin_lock(&np->lock); */
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400750 struct nv_ethtool_stats estats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751 int in_shutdown;
752 u32 linkspeed;
753 int duplex;
754 int autoneg;
755 int fixed_mode;
756 int phyaddr;
757 int wolenabled;
758 unsigned int phy_oui;
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400759 unsigned int phy_model;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400760 unsigned int phy_rev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761 u16 gigabit;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400762 int intr_test;
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500763 int recover_error;
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000764 int quiet_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765
766 /* General data: RO fields */
767 dma_addr_t ring_addr;
768 struct pci_dev *pci_dev;
769 u32 orig_mac[2];
Ayaz Abdulla582806b2009-03-05 08:02:03 +0000770 u32 events;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771 u32 irqmask;
772 u32 desc_ver;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400773 u32 txrxctl_bits;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500774 u32 vlanctl_bits;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400775 u32 driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400776 u32 device_id;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400777 u32 register_size;
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -0400778 int rx_csum;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500779 u32 mac_in_use;
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800780 int mgmt_version;
781 int mgmt_sema;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782
783 void __iomem *base;
784
785 /* rx specific fields.
786 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
787 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500788 union ring_type get_rx, put_rx, first_rx, last_rx;
789 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
790 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
791 struct nv_skb_map *rx_skb;
792
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700793 union ring_type rx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794 unsigned int rx_buf_sz;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200795 unsigned int pkt_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796 struct timer_list oom_kick;
797 struct timer_list nic_poll;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400798 struct timer_list stats_poll;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500799 u32 nic_poll_irq;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400800 int rx_ring_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801
802 /* media detection workaround.
803 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
804 */
805 int need_linktimer;
806 unsigned long link_timeout;
807 /*
808 * tx specific fields.
809 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500810 union ring_type get_tx, put_tx, first_tx, last_tx;
811 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
812 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
813 struct nv_skb_map *tx_skb;
814
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700815 union ring_type tx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816 u32 tx_flags;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400817 int tx_ring_size;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500818 int tx_limit;
819 u32 tx_pkts_in_progress;
820 struct nv_skb_map *tx_change_owner;
821 struct nv_skb_map *tx_end_flip;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -0500822 int tx_stop;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500823
824 /* vlan fields */
825 struct vlan_group *vlangrp;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500826
827 /* msi/msi-x fields */
828 u32 msi_flags;
829 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400830
831 /* flow control */
832 u32 pause_flags;
Tobias Diedrich1a1ca862008-05-18 15:03:44 +0200833
834 /* power saved state */
835 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
Yinghai Luddb213f2009-02-06 01:29:23 -0800836
837 /* for different msi-x irq type */
838 char name_rx[IFNAMSIZ + 3]; /* -rx */
839 char name_tx[IFNAMSIZ + 3]; /* -tx */
840 char name_other[IFNAMSIZ + 6]; /* -other */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841};
842
843/*
844 * Maximum number of loops until we assume that a bit in the irq mask
845 * is stuck. Overridable with module param.
846 */
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000847static int max_interrupt_work = 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500849/*
850 * Optimization can be either throuput mode or cpu mode
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400851 *
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500852 * Throughput Mode: Every tx and rx packet will generate an interrupt.
853 * CPU Mode: Interrupts are controlled by a timer.
854 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400855enum {
856 NV_OPTIMIZATION_MODE_THROUGHPUT,
Ayaz Abdulla9e184762009-03-05 08:02:18 +0000857 NV_OPTIMIZATION_MODE_CPU,
858 NV_OPTIMIZATION_MODE_DYNAMIC
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400859};
Ayaz Abdulla9e184762009-03-05 08:02:18 +0000860static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500861
862/*
863 * Poll interval for timer irq
864 *
865 * This interval determines how frequent an interrupt is generated.
866 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
867 * Min = 0, and Max = 65535
868 */
869static int poll_interval = -1;
870
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500871/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400872 * MSI interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500873 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400874enum {
875 NV_MSI_INT_DISABLED,
876 NV_MSI_INT_ENABLED
877};
878static int msi = NV_MSI_INT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500879
880/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400881 * MSIX interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500882 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400883enum {
884 NV_MSIX_INT_DISABLED,
885 NV_MSIX_INT_ENABLED
886};
Yinghai Lu39482792009-02-06 01:31:12 -0800887static int msix = NV_MSIX_INT_ENABLED;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400888
889/*
890 * DMA 64bit
891 */
892enum {
893 NV_DMA_64BIT_DISABLED,
894 NV_DMA_64BIT_ENABLED
895};
896static int dma_64bit = NV_DMA_64BIT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500897
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400898/*
899 * Crossover Detection
900 * Realtek 8201 phy + some OEM boards do not work properly.
901 */
902enum {
903 NV_CROSSOVER_DETECTION_DISABLED,
904 NV_CROSSOVER_DETECTION_ENABLED
905};
906static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
907
Ed Swierk5a9a8e32009-06-02 00:19:52 -0700908/*
909 * Power down phy when interface is down (persists through reboot;
910 * older Linux and other OSes may not power it up again)
911 */
912static int phy_power_down = 0;
913
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914static inline struct fe_priv *get_nvpriv(struct net_device *dev)
915{
916 return netdev_priv(dev);
917}
918
919static inline u8 __iomem *get_hwbase(struct net_device *dev)
920{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400921 return ((struct fe_priv *)netdev_priv(dev))->base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922}
923
924static inline void pci_push(u8 __iomem *base)
925{
926 /* force out pending posted writes */
927 readl(base);
928}
929
930static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
931{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700932 return le32_to_cpu(prd->flaglen)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
934}
935
Manfred Spraulee733622005-07-31 18:32:26 +0200936static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
937{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700938 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
Manfred Spraulee733622005-07-31 18:32:26 +0200939}
940
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400941static bool nv_optimized(struct fe_priv *np)
942{
943 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
944 return false;
945 return true;
946}
947
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
949 int delay, int delaymax, const char *msg)
950{
951 u8 __iomem *base = get_hwbase(dev);
952
953 pci_push(base);
954 do {
955 udelay(delay);
956 delaymax -= delay;
957 if (delaymax < 0) {
958 if (msg)
Stephen Hemminger6a64cd62009-02-26 10:19:35 +0000959 printk("%s", msg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960 return 1;
961 }
962 } while ((readl(base + offset) & mask) != target);
963 return 0;
964}
965
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500966#define NV_SETUP_RX_RING 0x01
967#define NV_SETUP_TX_RING 0x02
968
Al Viro5bb7ea22007-12-09 16:06:41 +0000969static inline u32 dma_low(dma_addr_t addr)
970{
971 return addr;
972}
973
974static inline u32 dma_high(dma_addr_t addr)
975{
976 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
977}
978
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500979static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
980{
981 struct fe_priv *np = get_nvpriv(dev);
982 u8 __iomem *base = get_hwbase(dev);
983
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400984 if (!nv_optimized(np)) {
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500985 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000986 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500987 }
988 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000989 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500990 }
991 } else {
992 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000993 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
994 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500995 }
996 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000997 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
998 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500999 }
1000 }
1001}
1002
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001003static void free_rings(struct net_device *dev)
1004{
1005 struct fe_priv *np = get_nvpriv(dev);
1006
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001007 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001008 if (np->rx_ring.orig)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001009 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1010 np->rx_ring.orig, np->ring_addr);
1011 } else {
1012 if (np->rx_ring.ex)
1013 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1014 np->rx_ring.ex, np->ring_addr);
1015 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001016 if (np->rx_skb)
1017 kfree(np->rx_skb);
1018 if (np->tx_skb)
1019 kfree(np->tx_skb);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001020}
1021
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001022static int using_multi_irqs(struct net_device *dev)
1023{
1024 struct fe_priv *np = get_nvpriv(dev);
1025
1026 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1027 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1028 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1029 return 0;
1030 else
1031 return 1;
1032}
1033
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00001034static void nv_txrx_gate(struct net_device *dev, bool gate)
1035{
1036 struct fe_priv *np = get_nvpriv(dev);
1037 u8 __iomem *base = get_hwbase(dev);
1038 u32 powerstate;
1039
1040 if (!np->mac_in_use &&
1041 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1042 powerstate = readl(base + NvRegPowerState2);
1043 if (gate)
1044 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1045 else
1046 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1047 writel(powerstate, base + NvRegPowerState2);
1048 }
1049}
1050
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001051static void nv_enable_irq(struct net_device *dev)
1052{
1053 struct fe_priv *np = get_nvpriv(dev);
1054
1055 if (!using_multi_irqs(dev)) {
1056 if (np->msi_flags & NV_MSI_X_ENABLED)
1057 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1058 else
Manfred Spraula7475902007-10-17 21:52:33 +02001059 enable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001060 } else {
1061 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1062 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1063 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1064 }
1065}
1066
1067static void nv_disable_irq(struct net_device *dev)
1068{
1069 struct fe_priv *np = get_nvpriv(dev);
1070
1071 if (!using_multi_irqs(dev)) {
1072 if (np->msi_flags & NV_MSI_X_ENABLED)
1073 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1074 else
Manfred Spraula7475902007-10-17 21:52:33 +02001075 disable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001076 } else {
1077 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1078 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1079 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1080 }
1081}
1082
1083/* In MSIX mode, a write to irqmask behaves as XOR */
1084static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1085{
1086 u8 __iomem *base = get_hwbase(dev);
1087
1088 writel(mask, base + NvRegIrqMask);
1089}
1090
1091static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1092{
1093 struct fe_priv *np = get_nvpriv(dev);
1094 u8 __iomem *base = get_hwbase(dev);
1095
1096 if (np->msi_flags & NV_MSI_X_ENABLED) {
1097 writel(mask, base + NvRegIrqMask);
1098 } else {
1099 if (np->msi_flags & NV_MSI_ENABLED)
1100 writel(0, base + NvRegMSIIrqMask);
1101 writel(0, base + NvRegIrqMask);
1102 }
1103}
1104
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001105static void nv_napi_enable(struct net_device *dev)
1106{
1107#ifdef CONFIG_FORCEDETH_NAPI
1108 struct fe_priv *np = get_nvpriv(dev);
1109
1110 napi_enable(&np->napi);
1111#endif
1112}
1113
1114static void nv_napi_disable(struct net_device *dev)
1115{
1116#ifdef CONFIG_FORCEDETH_NAPI
1117 struct fe_priv *np = get_nvpriv(dev);
1118
1119 napi_disable(&np->napi);
1120#endif
1121}
1122
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123#define MII_READ (-1)
1124/* mii_rw: read/write a register on the PHY.
1125 *
1126 * Caller must guarantee serialization
1127 */
1128static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1129{
1130 u8 __iomem *base = get_hwbase(dev);
1131 u32 reg;
1132 int retval;
1133
Ayaz Abdullaeb798422008-02-04 15:14:04 -05001134 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135
1136 reg = readl(base + NvRegMIIControl);
1137 if (reg & NVREG_MIICTL_INUSE) {
1138 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1139 udelay(NV_MIIBUSY_DELAY);
1140 }
1141
1142 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1143 if (value != MII_READ) {
1144 writel(value, base + NvRegMIIData);
1145 reg |= NVREG_MIICTL_WRITE;
1146 }
1147 writel(reg, base + NvRegMIIControl);
1148
1149 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1150 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1151 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1152 dev->name, miireg, addr);
1153 retval = -1;
1154 } else if (value != MII_READ) {
1155 /* it was a write operation - fewer failures are detectable */
1156 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1157 dev->name, value, miireg, addr);
1158 retval = 0;
1159 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1160 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1161 dev->name, miireg, addr);
1162 retval = -1;
1163 } else {
1164 retval = readl(base + NvRegMIIData);
1165 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1166 dev->name, miireg, addr, retval);
1167 }
1168
1169 return retval;
1170}
1171
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001172static int phy_reset(struct net_device *dev, u32 bmcr_setup)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001174 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001175 u32 miicontrol;
1176 unsigned int tries = 0;
1177
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001178 miicontrol = BMCR_RESET | bmcr_setup;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1180 return -1;
1181 }
1182
1183 /* wait for 500ms */
1184 msleep(500);
1185
1186 /* must wait till reset is deasserted */
1187 while (miicontrol & BMCR_RESET) {
1188 msleep(10);
1189 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1190 /* FIXME: 100 tries seem excessive */
1191 if (tries++ > 100)
1192 return -1;
1193 }
1194 return 0;
1195}
1196
1197static int phy_init(struct net_device *dev)
1198{
1199 struct fe_priv *np = get_nvpriv(dev);
1200 u8 __iomem *base = get_hwbase(dev);
1201 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1202
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001203 /* phy errata for E3016 phy */
1204 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1205 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1206 reg &= ~PHY_MARVELL_E3016_INITMASK;
1207 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1208 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1209 return PHY_ERROR;
1210 }
1211 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001212 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001213 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1214 np->phy_rev == PHY_REV_REALTEK_8211B) {
1215 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1216 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1217 return PHY_ERROR;
1218 }
1219 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1220 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1221 return PHY_ERROR;
1222 }
1223 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1224 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1225 return PHY_ERROR;
1226 }
1227 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1228 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1229 return PHY_ERROR;
1230 }
1231 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1232 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1233 return PHY_ERROR;
1234 }
1235 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1236 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1237 return PHY_ERROR;
1238 }
1239 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1240 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1241 return PHY_ERROR;
1242 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001243 }
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001244 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1245 np->phy_rev == PHY_REV_REALTEK_8211C) {
1246 u32 powerstate = readl(base + NvRegPowerState2);
1247
1248 /* need to perform hw phy reset */
1249 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1250 writel(powerstate, base + NvRegPowerState2);
1251 msleep(25);
1252
1253 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1254 writel(powerstate, base + NvRegPowerState2);
1255 msleep(25);
1256
1257 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1258 reg |= PHY_REALTEK_INIT9;
1259 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1260 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1261 return PHY_ERROR;
1262 }
1263 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1264 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1265 return PHY_ERROR;
1266 }
1267 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1268 if (!(reg & PHY_REALTEK_INIT11)) {
1269 reg |= PHY_REALTEK_INIT11;
1270 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1271 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1272 return PHY_ERROR;
1273 }
1274 }
1275 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1276 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1277 return PHY_ERROR;
1278 }
1279 }
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001280 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00001281 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001282 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1283 phy_reserved |= PHY_REALTEK_INIT7;
1284 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1285 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1286 return PHY_ERROR;
1287 }
1288 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001289 }
1290 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001291
Linus Torvalds1da177e2005-04-16 15:20:36 -07001292 /* set advertise register */
1293 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001294 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001295 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1296 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1297 return PHY_ERROR;
1298 }
1299
1300 /* get phy interface type */
1301 phyinterface = readl(base + NvRegPhyInterface);
1302
1303 /* see if gigabit phy */
1304 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1305 if (mii_status & PHY_GIGABIT) {
1306 np->gigabit = PHY_GIGABIT;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001307 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308 mii_control_1000 &= ~ADVERTISE_1000HALF;
1309 if (phyinterface & PHY_RGMII)
1310 mii_control_1000 |= ADVERTISE_1000FULL;
1311 else
1312 mii_control_1000 &= ~ADVERTISE_1000FULL;
1313
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001314 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1316 return PHY_ERROR;
1317 }
1318 }
1319 else
1320 np->gigabit = 0;
1321
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001322 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1323 mii_control |= BMCR_ANENABLE;
1324
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001325 if (np->phy_oui == PHY_OUI_REALTEK &&
1326 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1327 np->phy_rev == PHY_REV_REALTEK_8211C) {
1328 /* start autoneg since we already performed hw reset above */
1329 mii_control |= BMCR_ANRESTART;
1330 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1331 printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1332 return PHY_ERROR;
1333 }
1334 } else {
1335 /* reset the phy
1336 * (certain phys need bmcr to be setup with reset)
1337 */
1338 if (phy_reset(dev, mii_control)) {
1339 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1340 return PHY_ERROR;
1341 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001342 }
1343
1344 /* phy vendor specific configuration */
1345 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1346 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001347 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1348 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1350 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1351 return PHY_ERROR;
1352 }
1353 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001354 phy_reserved |= PHY_CICADA_INIT5;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001355 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1356 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1357 return PHY_ERROR;
1358 }
1359 }
1360 if (np->phy_oui == PHY_OUI_CICADA) {
1361 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001362 phy_reserved |= PHY_CICADA_INIT6;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1364 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1365 return PHY_ERROR;
1366 }
1367 }
Ayaz Abdullad215d8a2007-07-15 06:50:53 -04001368 if (np->phy_oui == PHY_OUI_VITESSE) {
1369 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1370 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1371 return PHY_ERROR;
1372 }
1373 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1374 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1375 return PHY_ERROR;
1376 }
1377 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1378 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1379 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1380 return PHY_ERROR;
1381 }
1382 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1383 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1384 phy_reserved |= PHY_VITESSE_INIT3;
1385 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1386 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1387 return PHY_ERROR;
1388 }
1389 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1390 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1391 return PHY_ERROR;
1392 }
1393 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1394 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1395 return PHY_ERROR;
1396 }
1397 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1398 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1399 phy_reserved |= PHY_VITESSE_INIT3;
1400 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1401 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1402 return PHY_ERROR;
1403 }
1404 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1405 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1406 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1407 return PHY_ERROR;
1408 }
1409 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1410 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1411 return PHY_ERROR;
1412 }
1413 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1414 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1415 return PHY_ERROR;
1416 }
1417 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1418 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1419 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1420 return PHY_ERROR;
1421 }
1422 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1423 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1424 phy_reserved |= PHY_VITESSE_INIT8;
1425 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1426 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1427 return PHY_ERROR;
1428 }
1429 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1430 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1431 return PHY_ERROR;
1432 }
1433 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1434 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1435 return PHY_ERROR;
1436 }
1437 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001438 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001439 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1440 np->phy_rev == PHY_REV_REALTEK_8211B) {
1441 /* reset could have cleared these out, set them back */
1442 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1443 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1444 return PHY_ERROR;
1445 }
1446 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1447 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1448 return PHY_ERROR;
1449 }
1450 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1451 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1452 return PHY_ERROR;
1453 }
1454 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1455 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1456 return PHY_ERROR;
1457 }
1458 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1459 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1460 return PHY_ERROR;
1461 }
1462 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1463 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1464 return PHY_ERROR;
1465 }
1466 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1467 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1468 return PHY_ERROR;
1469 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001470 }
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001471 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00001472 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001473 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1474 phy_reserved |= PHY_REALTEK_INIT7;
1475 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1476 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1477 return PHY_ERROR;
1478 }
1479 }
1480 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1481 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1482 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1483 return PHY_ERROR;
1484 }
1485 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1486 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1487 phy_reserved |= PHY_REALTEK_INIT3;
1488 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1489 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1490 return PHY_ERROR;
1491 }
1492 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1493 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1494 return PHY_ERROR;
1495 }
1496 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001497 }
1498 }
1499
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001500 /* some phys clear out pause advertisment on reset, set it back */
1501 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502
Ed Swierkcb52deb2008-12-01 12:24:43 +00001503 /* restart auto negotiation, power down phy */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001504 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ed Swierk5a9a8e32009-06-02 00:19:52 -07001505 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1506 if (phy_power_down) {
1507 mii_control |= BMCR_PDOWN;
1508 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001509 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1510 return PHY_ERROR;
1511 }
1512
1513 return 0;
1514}
1515
1516static void nv_start_rx(struct net_device *dev)
1517{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001518 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001520 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521
1522 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1523 /* Already running? Stop it. */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001524 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1525 rx_ctrl &= ~NVREG_RCVCTL_START;
1526 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527 pci_push(base);
1528 }
1529 writel(np->linkspeed, base + NvRegLinkSpeed);
1530 pci_push(base);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001531 rx_ctrl |= NVREG_RCVCTL_START;
1532 if (np->mac_in_use)
1533 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1534 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1536 dev->name, np->duplex, np->linkspeed);
1537 pci_push(base);
1538}
1539
1540static void nv_stop_rx(struct net_device *dev)
1541{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001542 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001544 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545
1546 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001547 if (!np->mac_in_use)
1548 rx_ctrl &= ~NVREG_RCVCTL_START;
1549 else
1550 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1551 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001552 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1553 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1554 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1555
1556 udelay(NV_RXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001557 if (!np->mac_in_use)
1558 writel(0, base + NvRegLinkSpeed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559}
1560
1561static void nv_start_tx(struct net_device *dev)
1562{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001563 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001564 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001565 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001566
1567 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001568 tx_ctrl |= NVREG_XMITCTL_START;
1569 if (np->mac_in_use)
1570 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1571 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001572 pci_push(base);
1573}
1574
1575static void nv_stop_tx(struct net_device *dev)
1576{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001577 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001578 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001579 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001580
1581 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001582 if (!np->mac_in_use)
1583 tx_ctrl &= ~NVREG_XMITCTL_START;
1584 else
1585 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1586 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001587 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1588 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1589 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1590
1591 udelay(NV_TXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001592 if (!np->mac_in_use)
1593 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1594 base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001595}
1596
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001597static void nv_start_rxtx(struct net_device *dev)
1598{
1599 nv_start_rx(dev);
1600 nv_start_tx(dev);
1601}
1602
1603static void nv_stop_rxtx(struct net_device *dev)
1604{
1605 nv_stop_rx(dev);
1606 nv_stop_tx(dev);
1607}
1608
Linus Torvalds1da177e2005-04-16 15:20:36 -07001609static void nv_txrx_reset(struct net_device *dev)
1610{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001611 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001612 u8 __iomem *base = get_hwbase(dev);
1613
1614 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001615 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616 pci_push(base);
1617 udelay(NV_TXRX_RESET_DELAY);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001618 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001619 pci_push(base);
1620}
1621
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001622static void nv_mac_reset(struct net_device *dev)
1623{
1624 struct fe_priv *np = netdev_priv(dev);
1625 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001626 u32 temp1, temp2, temp3;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001627
1628 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001629
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001630 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1631 pci_push(base);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001632
1633 /* save registers since they will be cleared on reset */
1634 temp1 = readl(base + NvRegMacAddrA);
1635 temp2 = readl(base + NvRegMacAddrB);
1636 temp3 = readl(base + NvRegTransmitPoll);
1637
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001638 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1639 pci_push(base);
1640 udelay(NV_MAC_RESET_DELAY);
1641 writel(0, base + NvRegMacReset);
1642 pci_push(base);
1643 udelay(NV_MAC_RESET_DELAY);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001644
1645 /* restore saved registers */
1646 writel(temp1, base + NvRegMacAddrA);
1647 writel(temp2, base + NvRegMacAddrB);
1648 writel(temp3, base + NvRegTransmitPoll);
1649
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001650 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1651 pci_push(base);
1652}
1653
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001654static void nv_get_hw_stats(struct net_device *dev)
1655{
1656 struct fe_priv *np = netdev_priv(dev);
1657 u8 __iomem *base = get_hwbase(dev);
1658
1659 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1660 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1661 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1662 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1663 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1664 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1665 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1666 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1667 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1668 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1669 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1670 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1671 np->estats.rx_runt += readl(base + NvRegRxRunt);
1672 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1673 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1674 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1675 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1676 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1677 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1678 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1679 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1680 np->estats.rx_packets =
1681 np->estats.rx_unicast +
1682 np->estats.rx_multicast +
1683 np->estats.rx_broadcast;
1684 np->estats.rx_errors_total =
1685 np->estats.rx_crc_errors +
1686 np->estats.rx_over_errors +
1687 np->estats.rx_frame_error +
1688 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1689 np->estats.rx_late_collision +
1690 np->estats.rx_runt +
1691 np->estats.rx_frame_too_long;
1692 np->estats.tx_errors_total =
1693 np->estats.tx_late_collision +
1694 np->estats.tx_fifo_errors +
1695 np->estats.tx_carrier_errors +
1696 np->estats.tx_excess_deferral +
1697 np->estats.tx_retry_error;
1698
1699 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1700 np->estats.tx_deferral += readl(base + NvRegTxDef);
1701 np->estats.tx_packets += readl(base + NvRegTxFrame);
1702 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1703 np->estats.tx_pause += readl(base + NvRegTxPause);
1704 np->estats.rx_pause += readl(base + NvRegRxPause);
1705 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1706 }
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001707
1708 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1709 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1710 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1711 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1712 }
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001713}
1714
Linus Torvalds1da177e2005-04-16 15:20:36 -07001715/*
1716 * nv_get_stats: dev->get_stats function
1717 * Get latest stats value from the nic.
1718 * Called with read_lock(&dev_base_lock) held for read -
1719 * only synchronized against unregister_netdevice.
1720 */
1721static struct net_device_stats *nv_get_stats(struct net_device *dev)
1722{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001723 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724
Ayaz Abdulla21828162007-01-23 12:27:21 -05001725 /* If the nic supports hw counters then retrieve latest values */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001726 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05001727 nv_get_hw_stats(dev);
1728
1729 /* copy to net_device stats */
Jeff Garzik8148ff42007-10-16 20:56:09 -04001730 dev->stats.tx_bytes = np->estats.tx_bytes;
1731 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1732 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1733 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1734 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1735 dev->stats.rx_errors = np->estats.rx_errors_total;
1736 dev->stats.tx_errors = np->estats.tx_errors_total;
Ayaz Abdulla21828162007-01-23 12:27:21 -05001737 }
Jeff Garzik8148ff42007-10-16 20:56:09 -04001738
1739 return &dev->stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001740}
1741
1742/*
1743 * nv_alloc_rx: fill rx ring entries.
1744 * Return 1 if the allocations for the skbs failed and the
1745 * rx engine is without Available descriptors
1746 */
1747static int nv_alloc_rx(struct net_device *dev)
1748{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001749 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001750 struct ring_desc* less_rx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001751
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001752 less_rx = np->get_rx.orig;
1753 if (less_rx-- == np->first_rx.orig)
1754 less_rx = np->last_rx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001755
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001756 while (np->put_rx.orig != less_rx) {
1757 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001758 if (skb) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001759 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001760 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1761 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001762 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001763 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001764 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001765 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1766 wmb();
1767 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001768 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001769 np->put_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001770 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001771 np->put_rx_ctx = np->first_rx_ctx;
1772 } else {
1773 return 1;
1774 }
1775 }
1776 return 0;
1777}
1778
1779static int nv_alloc_rx_optimized(struct net_device *dev)
1780{
1781 struct fe_priv *np = netdev_priv(dev);
1782 struct ring_desc_ex* less_rx;
1783
1784 less_rx = np->get_rx.ex;
1785 if (less_rx-- == np->first_rx.ex)
1786 less_rx = np->last_rx.ex;
1787
1788 while (np->put_rx.ex != less_rx) {
1789 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1790 if (skb) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001791 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001792 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1793 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001794 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001795 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001796 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Al Viro5bb7ea22007-12-09 16:06:41 +00001797 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1798 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001799 wmb();
1800 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001801 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001802 np->put_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001803 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001804 np->put_rx_ctx = np->first_rx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001805 } else {
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001806 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001807 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001808 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001809 return 0;
1810}
1811
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001812/* If rx bufs are exhausted called after 50ms to attempt to refresh */
1813#ifdef CONFIG_FORCEDETH_NAPI
1814static void nv_do_rx_refill(unsigned long data)
1815{
1816 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001817 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001818
1819 /* Just reschedule NAPI rx processing */
Ben Hutchings288379f2009-01-19 16:43:59 -08001820 napi_schedule(&np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001821}
1822#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001823static void nv_do_rx_refill(unsigned long data)
1824{
1825 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001826 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001827 int retcode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001828
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001829 if (!using_multi_irqs(dev)) {
1830 if (np->msi_flags & NV_MSI_X_ENABLED)
1831 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1832 else
Manfred Spraula7475902007-10-17 21:52:33 +02001833 disable_irq(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05001834 } else {
1835 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1836 }
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001837 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001838 retcode = nv_alloc_rx(dev);
1839 else
1840 retcode = nv_alloc_rx_optimized(dev);
1841 if (retcode) {
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001842 spin_lock_irq(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001843 if (!np->in_shutdown)
1844 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001845 spin_unlock_irq(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001846 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001847 if (!using_multi_irqs(dev)) {
1848 if (np->msi_flags & NV_MSI_X_ENABLED)
1849 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1850 else
Manfred Spraula7475902007-10-17 21:52:33 +02001851 enable_irq(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05001852 } else {
1853 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1854 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001855}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001856#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001857
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001858static void nv_init_rx(struct net_device *dev)
Manfred Sprauld81c0982005-07-31 18:20:30 +02001859{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001860 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001861 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001862
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001863 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001864
1865 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001866 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1867 else
1868 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1869 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1870 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
Manfred Sprauld81c0982005-07-31 18:20:30 +02001871
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001872 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001873 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001874 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001875 np->rx_ring.orig[i].buf = 0;
1876 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001877 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001878 np->rx_ring.ex[i].txvlan = 0;
1879 np->rx_ring.ex[i].bufhigh = 0;
1880 np->rx_ring.ex[i].buflow = 0;
1881 }
1882 np->rx_skb[i].skb = NULL;
1883 np->rx_skb[i].dma = 0;
1884 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001885}
1886
1887static void nv_init_tx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001888{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001889 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001890 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001891
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001892 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001893
1894 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001895 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1896 else
1897 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1898 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1899 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001900 np->tx_pkts_in_progress = 0;
1901 np->tx_change_owner = NULL;
1902 np->tx_end_flip = NULL;
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00001903 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001904
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001905 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001906 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001907 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001908 np->tx_ring.orig[i].buf = 0;
1909 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001910 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001911 np->tx_ring.ex[i].txvlan = 0;
1912 np->tx_ring.ex[i].bufhigh = 0;
1913 np->tx_ring.ex[i].buflow = 0;
1914 }
1915 np->tx_skb[i].skb = NULL;
1916 np->tx_skb[i].dma = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001917 np->tx_skb[i].dma_len = 0;
Eric Dumazet73a37072009-06-17 21:17:59 +00001918 np->tx_skb[i].dma_single = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001919 np->tx_skb[i].first_tx_desc = NULL;
1920 np->tx_skb[i].next_tx_ctx = NULL;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001921 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001922}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001923
Manfred Sprauld81c0982005-07-31 18:20:30 +02001924static int nv_init_ring(struct net_device *dev)
1925{
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001926 struct fe_priv *np = netdev_priv(dev);
1927
Manfred Sprauld81c0982005-07-31 18:20:30 +02001928 nv_init_tx(dev);
1929 nv_init_rx(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001930
1931 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001932 return nv_alloc_rx(dev);
1933 else
1934 return nv_alloc_rx_optimized(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001935}
1936
Eric Dumazet73a37072009-06-17 21:17:59 +00001937static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001938{
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001939 if (tx_skb->dma) {
Eric Dumazet73a37072009-06-17 21:17:59 +00001940 if (tx_skb->dma_single)
1941 pci_unmap_single(np->pci_dev, tx_skb->dma,
1942 tx_skb->dma_len,
1943 PCI_DMA_TODEVICE);
1944 else
1945 pci_unmap_page(np->pci_dev, tx_skb->dma,
1946 tx_skb->dma_len,
1947 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001948 tx_skb->dma = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001949 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001950}
1951
1952static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1953{
1954 nv_unmap_txskb(np, tx_skb);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001955 if (tx_skb->skb) {
1956 dev_kfree_skb_any(tx_skb->skb);
1957 tx_skb->skb = NULL;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001958 return 1;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001959 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001960 return 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001961}
1962
Linus Torvalds1da177e2005-04-16 15:20:36 -07001963static void nv_drain_tx(struct net_device *dev)
1964{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001965 struct fe_priv *np = netdev_priv(dev);
1966 unsigned int i;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001967
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001968 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001969 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001970 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001971 np->tx_ring.orig[i].buf = 0;
1972 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001973 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001974 np->tx_ring.ex[i].txvlan = 0;
1975 np->tx_ring.ex[i].bufhigh = 0;
1976 np->tx_ring.ex[i].buflow = 0;
1977 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001978 if (nv_release_txskb(np, &np->tx_skb[i]))
Jeff Garzik8148ff42007-10-16 20:56:09 -04001979 dev->stats.tx_dropped++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001980 np->tx_skb[i].dma = 0;
1981 np->tx_skb[i].dma_len = 0;
Eric Dumazet73a37072009-06-17 21:17:59 +00001982 np->tx_skb[i].dma_single = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001983 np->tx_skb[i].first_tx_desc = NULL;
1984 np->tx_skb[i].next_tx_ctx = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001985 }
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001986 np->tx_pkts_in_progress = 0;
1987 np->tx_change_owner = NULL;
1988 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001989}
1990
1991static void nv_drain_rx(struct net_device *dev)
1992{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001993 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001994 int i;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001995
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001996 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001997 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001998 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001999 np->rx_ring.orig[i].buf = 0;
2000 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002001 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002002 np->rx_ring.ex[i].txvlan = 0;
2003 np->rx_ring.ex[i].bufhigh = 0;
2004 np->rx_ring.ex[i].buflow = 0;
2005 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002006 wmb();
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002007 if (np->rx_skb[i].skb) {
2008 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07002009 (skb_end_pointer(np->rx_skb[i].skb) -
2010 np->rx_skb[i].skb->data),
2011 PCI_DMA_FROMDEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002012 dev_kfree_skb(np->rx_skb[i].skb);
2013 np->rx_skb[i].skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002014 }
2015 }
2016}
2017
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002018static void nv_drain_rxtx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002019{
2020 nv_drain_tx(dev);
2021 nv_drain_rx(dev);
2022}
2023
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002024static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2025{
2026 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2027}
2028
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002029static void nv_legacybackoff_reseed(struct net_device *dev)
2030{
2031 u8 __iomem *base = get_hwbase(dev);
2032 u32 reg;
2033 u32 low;
2034 int tx_status = 0;
2035
2036 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2037 get_random_bytes(&low, sizeof(low));
2038 reg |= low & NVREG_SLOTTIME_MASK;
2039
2040 /* Need to stop tx before change takes effect.
2041 * Caller has already gained np->lock.
2042 */
2043 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2044 if (tx_status)
2045 nv_stop_tx(dev);
2046 nv_stop_rx(dev);
2047 writel(reg, base + NvRegSlotTime);
2048 if (tx_status)
2049 nv_start_tx(dev);
2050 nv_start_rx(dev);
2051}
2052
2053/* Gear Backoff Seeds */
2054#define BACKOFF_SEEDSET_ROWS 8
2055#define BACKOFF_SEEDSET_LFSRS 15
2056
2057/* Known Good seed sets */
2058static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2059 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2060 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2061 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2062 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2063 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2064 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2065 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2066 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2067
2068static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2069 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2070 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2071 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2072 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2073 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2074 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2075 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2076 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2077
2078static void nv_gear_backoff_reseed(struct net_device *dev)
2079{
2080 u8 __iomem *base = get_hwbase(dev);
2081 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2082 u32 temp, seedset, combinedSeed;
2083 int i;
2084
2085 /* Setup seed for free running LFSR */
2086 /* We are going to read the time stamp counter 3 times
2087 and swizzle bits around to increase randomness */
2088 get_random_bytes(&miniseed1, sizeof(miniseed1));
2089 miniseed1 &= 0x0fff;
2090 if (miniseed1 == 0)
2091 miniseed1 = 0xabc;
2092
2093 get_random_bytes(&miniseed2, sizeof(miniseed2));
2094 miniseed2 &= 0x0fff;
2095 if (miniseed2 == 0)
2096 miniseed2 = 0xabc;
2097 miniseed2_reversed =
2098 ((miniseed2 & 0xF00) >> 8) |
2099 (miniseed2 & 0x0F0) |
2100 ((miniseed2 & 0x00F) << 8);
2101
2102 get_random_bytes(&miniseed3, sizeof(miniseed3));
2103 miniseed3 &= 0x0fff;
2104 if (miniseed3 == 0)
2105 miniseed3 = 0xabc;
2106 miniseed3_reversed =
2107 ((miniseed3 & 0xF00) >> 8) |
2108 (miniseed3 & 0x0F0) |
2109 ((miniseed3 & 0x00F) << 8);
2110
2111 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2112 (miniseed2 ^ miniseed3_reversed);
2113
2114 /* Seeds can not be zero */
2115 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2116 combinedSeed |= 0x08;
2117 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2118 combinedSeed |= 0x8000;
2119
2120 /* No need to disable tx here */
2121 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2122 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2123 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2124 writel(temp,base + NvRegBackOffControl);
2125
2126 /* Setup seeds for all gear LFSRs. */
2127 get_random_bytes(&seedset, sizeof(seedset));
2128 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2129 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2130 {
2131 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2132 temp |= main_seedset[seedset][i-1] & 0x3ff;
2133 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2134 writel(temp, base + NvRegBackOffControl);
2135 }
2136}
2137
Linus Torvalds1da177e2005-04-16 15:20:36 -07002138/*
2139 * nv_start_xmit: dev->hard_start_xmit function
Herbert Xu932ff272006-06-09 12:20:56 -07002140 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002141 */
Stephen Hemminger613573252009-08-31 19:50:58 +00002142static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002143{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002144 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002145 u32 tx_flags = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002146 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2147 unsigned int fragments = skb_shinfo(skb)->nr_frags;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002148 unsigned int i;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002149 u32 offset = 0;
2150 u32 bcnt;
Eric Dumazete743d312010-04-14 15:59:40 -07002151 u32 size = skb_headlen(skb);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002152 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002153 u32 empty_slots;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002154 struct ring_desc* put_tx;
2155 struct ring_desc* start_tx;
2156 struct ring_desc* prev_tx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002157 struct nv_skb_map* prev_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002158 unsigned long flags;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002159
2160 /* add fragments to entries count */
2161 for (i = 0; i < fragments; i++) {
2162 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2163 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2164 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002165
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002166 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002167 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002168 if (unlikely(empty_slots <= entries)) {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002169 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002170 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002171 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002172 return NETDEV_TX_BUSY;
2173 }
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002174 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002175
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002176 start_tx = put_tx = np->put_tx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002177
Ayaz Abdullafa454592006-01-05 22:45:45 -08002178 /* setup the header buffer */
2179 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002180 prev_tx = put_tx;
2181 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002182 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002183 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
Ayaz Abdullafa454592006-01-05 22:45:45 -08002184 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002185 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002186 np->put_tx_ctx->dma_single = 1;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002187 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2188 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002189
Ayaz Abdullafa454592006-01-05 22:45:45 -08002190 tx_flags = np->tx_flags;
2191 offset += bcnt;
2192 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002193 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002194 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002195 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002196 np->put_tx_ctx = np->first_tx_ctx;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002197 } while (size);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002198
2199 /* setup the fragments */
2200 for (i = 0; i < fragments; i++) {
2201 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2202 u32 size = frag->size;
2203 offset = 0;
2204
2205 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002206 prev_tx = put_tx;
2207 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002208 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002209 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2210 PCI_DMA_TODEVICE);
2211 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002212 np->put_tx_ctx->dma_single = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002213 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2214 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002215
Ayaz Abdullafa454592006-01-05 22:45:45 -08002216 offset += bcnt;
2217 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002218 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002219 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002220 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002221 np->put_tx_ctx = np->first_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002222 } while (size);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002223 }
2224
Ayaz Abdullafa454592006-01-05 22:45:45 -08002225 /* set last fragment flag */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002226 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002227
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002228 /* save skb in this slot's context area */
2229 prev_tx_ctx->skb = skb;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002230
Herbert Xu89114af2006-07-08 13:34:32 -07002231 if (skb_is_gso(skb))
Herbert Xu79671682006-06-22 02:40:14 -07002232 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
Manfred Spraulee733622005-07-31 18:32:26 +02002233 else
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002234 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
Patrick McHardy84fa7932006-08-29 16:44:56 -07002235 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002236
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002237 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05002238
Ayaz Abdullafa454592006-01-05 22:45:45 -08002239 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002240 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2241 np->put_tx.orig = put_tx;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002242
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002243 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002244
2245 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2246 dev->name, entries, tx_flags_extra);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002247 {
2248 int j;
2249 for (j=0; j<64; j++) {
2250 if ((j%16) == 0)
2251 dprintk("\n%03x:", j);
2252 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2253 }
2254 dprintk("\n");
2255 }
2256
Linus Torvalds1da177e2005-04-16 15:20:36 -07002257 dev->trans_start = jiffies;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002258 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002259 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002260}
2261
Stephen Hemminger613573252009-08-31 19:50:58 +00002262static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2263 struct net_device *dev)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002264{
2265 struct fe_priv *np = netdev_priv(dev);
2266 u32 tx_flags = 0;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002267 u32 tx_flags_extra;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002268 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2269 unsigned int i;
2270 u32 offset = 0;
2271 u32 bcnt;
Eric Dumazete743d312010-04-14 15:59:40 -07002272 u32 size = skb_headlen(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002273 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2274 u32 empty_slots;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002275 struct ring_desc_ex* put_tx;
2276 struct ring_desc_ex* start_tx;
2277 struct ring_desc_ex* prev_tx;
2278 struct nv_skb_map* prev_tx_ctx;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002279 struct nv_skb_map* start_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002280 unsigned long flags;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002281
2282 /* add fragments to entries count */
2283 for (i = 0; i < fragments; i++) {
2284 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2285 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2286 }
2287
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002288 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002289 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002290 if (unlikely(empty_slots <= entries)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002291 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002292 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002293 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002294 return NETDEV_TX_BUSY;
2295 }
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002296 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002297
2298 start_tx = put_tx = np->put_tx.ex;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002299 start_tx_ctx = np->put_tx_ctx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002300
2301 /* setup the header buffer */
2302 do {
2303 prev_tx = put_tx;
2304 prev_tx_ctx = np->put_tx_ctx;
2305 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2306 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2307 PCI_DMA_TODEVICE);
2308 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002309 np->put_tx_ctx->dma_single = 1;
Al Viro5bb7ea22007-12-09 16:06:41 +00002310 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2311 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002312 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002313
2314 tx_flags = NV_TX2_VALID;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002315 offset += bcnt;
2316 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002317 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002318 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002319 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002320 np->put_tx_ctx = np->first_tx_ctx;
2321 } while (size);
2322
2323 /* setup the fragments */
2324 for (i = 0; i < fragments; i++) {
2325 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2326 u32 size = frag->size;
2327 offset = 0;
2328
2329 do {
2330 prev_tx = put_tx;
2331 prev_tx_ctx = np->put_tx_ctx;
2332 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2333 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2334 PCI_DMA_TODEVICE);
2335 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002336 np->put_tx_ctx->dma_single = 0;
Al Viro5bb7ea22007-12-09 16:06:41 +00002337 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2338 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002339 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002340
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002341 offset += bcnt;
2342 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002343 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002344 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002345 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002346 np->put_tx_ctx = np->first_tx_ctx;
2347 } while (size);
2348 }
2349
2350 /* set last fragment flag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002351 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002352
2353 /* save skb in this slot's context area */
2354 prev_tx_ctx->skb = skb;
2355
2356 if (skb_is_gso(skb))
2357 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2358 else
2359 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2360 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2361
2362 /* vlan tag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002363 if (likely(!np->vlangrp)) {
2364 start_tx->txvlan = 0;
2365 } else {
2366 if (vlan_tx_tag_present(skb))
2367 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2368 else
2369 start_tx->txvlan = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002370 }
2371
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002372 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002373
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002374 if (np->tx_limit) {
2375 /* Limit the number of outstanding tx. Setup all fragments, but
2376 * do not set the VALID bit on the first descriptor. Save a pointer
2377 * to that descriptor and also for next skb_map element.
2378 */
2379
2380 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2381 if (!np->tx_change_owner)
2382 np->tx_change_owner = start_tx_ctx;
2383
2384 /* remove VALID bit */
2385 tx_flags &= ~NV_TX2_VALID;
2386 start_tx_ctx->first_tx_desc = start_tx;
2387 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2388 np->tx_end_flip = np->put_tx_ctx;
2389 } else {
2390 np->tx_pkts_in_progress++;
2391 }
2392 }
2393
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002394 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002395 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2396 np->put_tx.ex = put_tx;
2397
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002398 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002399
2400 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2401 dev->name, entries, tx_flags_extra);
2402 {
2403 int j;
2404 for (j=0; j<64; j++) {
2405 if ((j%16) == 0)
2406 dprintk("\n%03x:", j);
2407 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2408 }
2409 dprintk("\n");
2410 }
2411
2412 dev->trans_start = jiffies;
2413 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002414 return NETDEV_TX_OK;
2415}
2416
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002417static inline void nv_tx_flip_ownership(struct net_device *dev)
2418{
2419 struct fe_priv *np = netdev_priv(dev);
2420
2421 np->tx_pkts_in_progress--;
2422 if (np->tx_change_owner) {
Al Viro30ecce92008-03-26 05:57:12 +00002423 np->tx_change_owner->first_tx_desc->flaglen |=
2424 cpu_to_le32(NV_TX2_VALID);
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002425 np->tx_pkts_in_progress++;
2426
2427 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2428 if (np->tx_change_owner == np->tx_end_flip)
2429 np->tx_change_owner = NULL;
2430
2431 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2432 }
2433}
2434
Linus Torvalds1da177e2005-04-16 15:20:36 -07002435/*
2436 * nv_tx_done: check for completed packets, release the skbs.
2437 *
2438 * Caller must own np->lock.
2439 */
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002440static int nv_tx_done(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002441{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002442 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002443 u32 flags;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002444 int tx_work = 0;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002445 struct ring_desc* orig_get_tx = np->get_tx.orig;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002446
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002447 while ((np->get_tx.orig != np->put_tx.orig) &&
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002448 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2449 (tx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002450
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002451 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2452 dev->name, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002453
Eric Dumazet73a37072009-06-17 21:17:59 +00002454 nv_unmap_txskb(np, np->get_tx_ctx);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002455
Linus Torvalds1da177e2005-04-16 15:20:36 -07002456 if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002457 if (flags & NV_TX_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002458 if (flags & NV_TX_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002459 if (flags & NV_TX_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002460 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002461 if (flags & NV_TX_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002462 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002463 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2464 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002465 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002466 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002467 dev->stats.tx_packets++;
2468 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002469 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002470 dev_kfree_skb_any(np->get_tx_ctx->skb);
2471 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002472 tx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002473 }
2474 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002475 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002476 if (flags & NV_TX2_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002477 if (flags & NV_TX2_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002478 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002479 if (flags & NV_TX2_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002480 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002481 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2482 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002483 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002484 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002485 dev->stats.tx_packets++;
2486 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002487 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002488 dev_kfree_skb_any(np->get_tx_ctx->skb);
2489 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002490 tx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002491 }
2492 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002493 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002494 np->get_tx.orig = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002495 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002496 np->get_tx_ctx = np->first_tx_ctx;
2497 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002498 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002499 np->tx_stop = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002500 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002501 }
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002502 return tx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002503}
2504
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002505static int nv_tx_done_optimized(struct net_device *dev, int limit)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002506{
2507 struct fe_priv *np = netdev_priv(dev);
2508 u32 flags;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002509 int tx_work = 0;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002510 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002511
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002512 while ((np->get_tx.ex != np->put_tx.ex) &&
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002513 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002514 (tx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002515
2516 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2517 dev->name, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002518
Eric Dumazet73a37072009-06-17 21:17:59 +00002519 nv_unmap_txskb(np, np->get_tx_ctx);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002520
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002521 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05002522 if (!(flags & NV_TX2_ERROR))
Jeff Garzik8148ff42007-10-16 20:56:09 -04002523 dev->stats.tx_packets++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002524 else {
2525 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2526 if (np->driver_data & DEV_HAS_GEAR_MODE)
2527 nv_gear_backoff_reseed(dev);
2528 else
2529 nv_legacybackoff_reseed(dev);
2530 }
2531 }
2532
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002533 dev_kfree_skb_any(np->get_tx_ctx->skb);
2534 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002535 tx_work++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002536
2537 if (np->tx_limit) {
2538 nv_tx_flip_ownership(dev);
2539 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002540 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002541 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002542 np->get_tx.ex = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002543 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002544 np->get_tx_ctx = np->first_tx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002545 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002546 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002547 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002548 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002549 }
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002550 return tx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002551}
2552
2553/*
2554 * nv_tx_timeout: dev->tx_timeout function
Herbert Xu932ff272006-06-09 12:20:56 -07002555 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002556 */
2557static void nv_tx_timeout(struct net_device *dev)
2558{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002559 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002560 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002561 u32 status;
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002562 union ring_type put_tx;
2563 int saved_tx_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002564
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002565 if (np->msi_flags & NV_MSI_X_ENABLED)
2566 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2567 else
2568 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2569
2570 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002571
Manfred Spraulc2dba062005-07-31 18:29:47 +02002572 {
2573 int i;
2574
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002575 printk(KERN_INFO "%s: Ring at %lx\n",
2576 dev->name, (unsigned long)np->ring_addr);
Manfred Spraulc2dba062005-07-31 18:29:47 +02002577 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04002578 for (i=0;i<=np->register_size;i+= 32) {
Manfred Spraulc2dba062005-07-31 18:29:47 +02002579 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2580 i,
2581 readl(base + i + 0), readl(base + i + 4),
2582 readl(base + i + 8), readl(base + i + 12),
2583 readl(base + i + 16), readl(base + i + 20),
2584 readl(base + i + 24), readl(base + i + 28));
2585 }
2586 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002587 for (i=0;i<np->tx_ring_size;i+= 4) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002588 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02002589 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002590 i,
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002591 le32_to_cpu(np->tx_ring.orig[i].buf),
2592 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2593 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2594 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2595 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2596 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2597 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2598 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
Manfred Spraulee733622005-07-31 18:32:26 +02002599 } else {
2600 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002601 i,
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002602 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2603 le32_to_cpu(np->tx_ring.ex[i].buflow),
2604 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2605 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2606 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2607 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2608 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2609 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2610 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2611 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2612 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2613 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
Manfred Spraulee733622005-07-31 18:32:26 +02002614 }
Manfred Spraulc2dba062005-07-31 18:29:47 +02002615 }
2616 }
2617
Linus Torvalds1da177e2005-04-16 15:20:36 -07002618 spin_lock_irq(&np->lock);
2619
2620 /* 1) stop tx engine */
2621 nv_stop_tx(dev);
2622
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002623 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2624 saved_tx_limit = np->tx_limit;
2625 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2626 np->tx_stop = 0; /* prevent waking tx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002627 if (!nv_optimized(np))
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002628 nv_tx_done(dev, np->tx_ring_size);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002629 else
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002630 nv_tx_done_optimized(dev, np->tx_ring_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002631
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002632 /* save current HW postion */
2633 if (np->tx_change_owner)
2634 put_tx.ex = np->tx_change_owner->first_tx_desc;
2635 else
2636 put_tx = np->put_tx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002637
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002638 /* 3) clear all tx state */
2639 nv_drain_tx(dev);
2640 nv_init_tx(dev);
Ayaz Abdulla3ba4d092007-03-23 05:50:02 -05002641
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002642 /* 4) restore state to current HW position */
2643 np->get_tx = np->put_tx = put_tx;
2644 np->tx_limit = saved_tx_limit;
2645
2646 /* 5) restart tx engine */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002647 nv_start_tx(dev);
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002648 netif_wake_queue(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002649 spin_unlock_irq(&np->lock);
2650}
2651
Manfred Spraul22c6d142005-04-19 21:17:09 +02002652/*
2653 * Called when the nic notices a mismatch between the actual data len on the
2654 * wire and the len indicated in the 802 header
2655 */
2656static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2657{
2658 int hdrlen; /* length of the 802 header */
2659 int protolen; /* length as stored in the proto field */
2660
2661 /* 1) calculate len according to header */
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002662 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
Manfred Spraul22c6d142005-04-19 21:17:09 +02002663 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2664 hdrlen = VLAN_HLEN;
2665 } else {
2666 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2667 hdrlen = ETH_HLEN;
2668 }
2669 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2670 dev->name, datalen, protolen, hdrlen);
2671 if (protolen > ETH_DATA_LEN)
2672 return datalen; /* Value in proto field not a len, no checks possible */
2673
2674 protolen += hdrlen;
2675 /* consistency checks: */
2676 if (datalen > ETH_ZLEN) {
2677 if (datalen >= protolen) {
2678 /* more data on wire than in 802 header, trim of
2679 * additional data.
2680 */
2681 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2682 dev->name, protolen);
2683 return protolen;
2684 } else {
2685 /* less data on wire than mentioned in header.
2686 * Discard the packet.
2687 */
2688 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2689 dev->name);
2690 return -1;
2691 }
2692 } else {
2693 /* short packet. Accept only if 802 values are also short */
2694 if (protolen > ETH_ZLEN) {
2695 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2696 dev->name);
2697 return -1;
2698 }
2699 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2700 dev->name, datalen);
2701 return datalen;
2702 }
2703}
2704
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002705static int nv_rx_process(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002706{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002707 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002708 u32 flags;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002709 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002710 struct sk_buff *skb;
2711 int len;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05002712
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002713 while((np->get_rx.orig != np->put_rx.orig) &&
2714 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002715 (rx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002716
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002717 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2718 dev->name, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002719
Linus Torvalds1da177e2005-04-16 15:20:36 -07002720 /*
2721 * the packet is for us - immediately tear down the pci mapping.
2722 * TODO: check if a prefetch of the first cacheline improves
2723 * the performance.
2724 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002725 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2726 np->get_rx_ctx->dma_len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002727 PCI_DMA_FROMDEVICE);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002728 skb = np->get_rx_ctx->skb;
2729 np->get_rx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002730
2731 {
2732 int j;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002733 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002734 for (j=0; j<64; j++) {
2735 if ((j%16) == 0)
2736 dprintk("\n%03x:", j);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002737 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002738 }
2739 dprintk("\n");
2740 }
2741 /* look at what we actually got: */
2742 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002743 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2744 len = flags & LEN_MASK_V1;
2745 if (unlikely(flags & NV_RX_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002746 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002747 len = nv_getlen(dev, skb->data, len);
2748 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002749 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002750 dev_kfree_skb(skb);
2751 goto next_pkt;
2752 }
2753 }
2754 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002755 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002756 if (flags & NV_RX_SUBSTRACT1) {
2757 len--;
2758 }
2759 }
2760 /* the rest are hard errors */
2761 else {
2762 if (flags & NV_RX_MISSEDFRAME)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002763 dev->stats.rx_missed_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002764 if (flags & NV_RX_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002765 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002766 if (flags & NV_RX_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002767 dev->stats.rx_over_errors++;
2768 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002769 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002770 goto next_pkt;
2771 }
2772 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002773 } else {
2774 dev_kfree_skb(skb);
2775 goto next_pkt;
Manfred Spraul22c6d142005-04-19 21:17:09 +02002776 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002777 } else {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002778 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2779 len = flags & LEN_MASK_V2;
2780 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002781 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002782 len = nv_getlen(dev, skb->data, len);
2783 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002784 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002785 dev_kfree_skb(skb);
2786 goto next_pkt;
2787 }
2788 }
2789 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002790 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002791 if (flags & NV_RX2_SUBSTRACT1) {
2792 len--;
2793 }
2794 }
2795 /* the rest are hard errors */
2796 else {
2797 if (flags & NV_RX2_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002798 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002799 if (flags & NV_RX2_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002800 dev->stats.rx_over_errors++;
2801 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002802 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002803 goto next_pkt;
2804 }
2805 }
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002806 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2807 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002808 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002809 } else {
2810 dev_kfree_skb(skb);
2811 goto next_pkt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002812 }
2813 }
2814 /* got a valid packet - forward it to the network core */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002815 skb_put(skb, len);
2816 skb->protocol = eth_type_trans(skb, dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002817 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2818 dev->name, len, skb->protocol);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002819#ifdef CONFIG_FORCEDETH_NAPI
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002820 netif_receive_skb(skb);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002821#else
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002822 netif_rx(skb);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002823#endif
Jeff Garzik8148ff42007-10-16 20:56:09 -04002824 dev->stats.rx_packets++;
2825 dev->stats.rx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002826next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002827 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002828 np->get_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002829 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002830 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002831
2832 rx_work++;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002833 }
2834
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002835 return rx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002836}
2837
2838static int nv_rx_process_optimized(struct net_device *dev, int limit)
2839{
2840 struct fe_priv *np = netdev_priv(dev);
2841 u32 flags;
2842 u32 vlanflags = 0;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002843 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002844 struct sk_buff *skb;
2845 int len;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002846
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002847 while((np->get_rx.ex != np->put_rx.ex) &&
2848 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
Ingo Molnarc1b71512007-10-17 12:18:23 +02002849 (rx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002850
2851 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2852 dev->name, flags);
2853
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002854 /*
2855 * the packet is for us - immediately tear down the pci mapping.
2856 * TODO: check if a prefetch of the first cacheline improves
2857 * the performance.
2858 */
2859 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2860 np->get_rx_ctx->dma_len,
2861 PCI_DMA_FROMDEVICE);
2862 skb = np->get_rx_ctx->skb;
2863 np->get_rx_ctx->skb = NULL;
2864
2865 {
2866 int j;
2867 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2868 for (j=0; j<64; j++) {
2869 if ((j%16) == 0)
2870 dprintk("\n%03x:", j);
2871 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2872 }
2873 dprintk("\n");
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002874 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002875 /* look at what we actually got: */
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002876 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2877 len = flags & LEN_MASK_V2;
2878 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002879 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002880 len = nv_getlen(dev, skb->data, len);
2881 if (len < 0) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002882 dev_kfree_skb(skb);
2883 goto next_pkt;
2884 }
2885 }
2886 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002887 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002888 if (flags & NV_RX2_SUBSTRACT1) {
2889 len--;
2890 }
2891 }
2892 /* the rest are hard errors */
2893 else {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002894 dev_kfree_skb(skb);
2895 goto next_pkt;
2896 }
2897 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002898
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002899 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2900 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002901 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002902
2903 /* got a valid packet - forward it to the network core */
2904 skb_put(skb, len);
2905 skb->protocol = eth_type_trans(skb, dev);
2906 prefetch(skb->data);
2907
2908 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2909 dev->name, len, skb->protocol);
2910
2911 if (likely(!np->vlangrp)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002912#ifdef CONFIG_FORCEDETH_NAPI
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002913 netif_receive_skb(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002914#else
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002915 netif_rx(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002916#endif
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002917 } else {
2918 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2919 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2920#ifdef CONFIG_FORCEDETH_NAPI
2921 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2922 vlanflags & NV_RX3_VLAN_TAG_MASK);
2923#else
2924 vlan_hwaccel_rx(skb, np->vlangrp,
2925 vlanflags & NV_RX3_VLAN_TAG_MASK);
2926#endif
2927 } else {
2928#ifdef CONFIG_FORCEDETH_NAPI
2929 netif_receive_skb(skb);
2930#else
2931 netif_rx(skb);
2932#endif
2933 }
2934 }
2935
Jeff Garzik8148ff42007-10-16 20:56:09 -04002936 dev->stats.rx_packets++;
2937 dev->stats.rx_bytes += len;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002938 } else {
2939 dev_kfree_skb(skb);
2940 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002941next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002942 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002943 np->get_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002944 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002945 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002946
2947 rx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002948 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002949
Ingo Molnarc1b71512007-10-17 12:18:23 +02002950 return rx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002951}
2952
Manfred Sprauld81c0982005-07-31 18:20:30 +02002953static void set_bufsize(struct net_device *dev)
2954{
2955 struct fe_priv *np = netdev_priv(dev);
2956
2957 if (dev->mtu <= ETH_DATA_LEN)
2958 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2959 else
2960 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2961}
2962
Linus Torvalds1da177e2005-04-16 15:20:36 -07002963/*
2964 * nv_change_mtu: dev->change_mtu function
2965 * Called with dev_base_lock held for read.
2966 */
2967static int nv_change_mtu(struct net_device *dev, int new_mtu)
2968{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002969 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002970 int old_mtu;
2971
2972 if (new_mtu < 64 || new_mtu > np->pkt_limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002973 return -EINVAL;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002974
2975 old_mtu = dev->mtu;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002976 dev->mtu = new_mtu;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002977
2978 /* return early if the buffer sizes will not change */
2979 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2980 return 0;
2981 if (old_mtu == new_mtu)
2982 return 0;
2983
2984 /* synchronized against open : rtnl_lock() held by caller */
2985 if (netif_running(dev)) {
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002986 u8 __iomem *base = get_hwbase(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002987 /*
2988 * It seems that the nic preloads valid ring entries into an
2989 * internal buffer. The procedure for flushing everything is
2990 * guessed, there is probably a simpler approach.
2991 * Changing the MTU is a rare event, it shouldn't matter.
2992 */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002993 nv_disable_irq(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00002994 nv_napi_disable(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002995 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002996 netif_addr_lock(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002997 spin_lock(&np->lock);
2998 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002999 nv_stop_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003000 nv_txrx_reset(dev);
3001 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003002 nv_drain_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003003 /* reinit driver view of the rx queue */
Manfred Sprauld81c0982005-07-31 18:20:30 +02003004 set_bufsize(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04003005 if (nv_init_ring(dev)) {
Manfred Sprauld81c0982005-07-31 18:20:30 +02003006 if (!np->in_shutdown)
3007 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3008 }
3009 /* reinit nic view of the rx queue */
3010 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05003011 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04003012 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Manfred Sprauld81c0982005-07-31 18:20:30 +02003013 base + NvRegRingSizes);
3014 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04003015 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003016 pci_push(base);
3017
3018 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003019 nv_start_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003020 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07003021 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07003022 netif_tx_unlock_bh(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00003023 nv_napi_enable(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003024 nv_enable_irq(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02003025 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003026 return 0;
3027}
3028
Manfred Spraul72b31782005-07-31 18:33:34 +02003029static void nv_copy_mac_to_hw(struct net_device *dev)
3030{
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01003031 u8 __iomem *base = get_hwbase(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02003032 u32 mac[2];
3033
3034 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3035 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3036 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3037
3038 writel(mac[0], base + NvRegMacAddrA);
3039 writel(mac[1], base + NvRegMacAddrB);
3040}
3041
3042/*
3043 * nv_set_mac_address: dev->set_mac_address function
3044 * Called with rtnl_lock() held.
3045 */
3046static int nv_set_mac_address(struct net_device *dev, void *addr)
3047{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003048 struct fe_priv *np = netdev_priv(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02003049 struct sockaddr *macaddr = (struct sockaddr*)addr;
3050
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003051 if (!is_valid_ether_addr(macaddr->sa_data))
Manfred Spraul72b31782005-07-31 18:33:34 +02003052 return -EADDRNOTAVAIL;
3053
3054 /* synchronized against open : rtnl_lock() held by caller */
3055 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3056
3057 if (netif_running(dev)) {
Herbert Xu932ff272006-06-09 12:20:56 -07003058 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07003059 netif_addr_lock(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02003060 spin_lock_irq(&np->lock);
3061
3062 /* stop rx engine */
3063 nv_stop_rx(dev);
3064
3065 /* set mac address */
3066 nv_copy_mac_to_hw(dev);
3067
3068 /* restart rx engine */
3069 nv_start_rx(dev);
3070 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07003071 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07003072 netif_tx_unlock_bh(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02003073 } else {
3074 nv_copy_mac_to_hw(dev);
3075 }
3076 return 0;
3077}
3078
Linus Torvalds1da177e2005-04-16 15:20:36 -07003079/*
3080 * nv_set_multicast: dev->set_multicast function
Herbert Xu932ff272006-06-09 12:20:56 -07003081 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003082 */
3083static void nv_set_multicast(struct net_device *dev)
3084{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003085 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003086 u8 __iomem *base = get_hwbase(dev);
3087 u32 addr[2];
3088 u32 mask[2];
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003089 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003090
3091 memset(addr, 0, sizeof(addr));
3092 memset(mask, 0, sizeof(mask));
3093
3094 if (dev->flags & IFF_PROMISC) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003095 pff |= NVREG_PFF_PROMISC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003096 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003097 pff |= NVREG_PFF_MYADDR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003098
Jiri Pirko48e2f182010-02-22 09:22:26 +00003099 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003100 u32 alwaysOff[2];
3101 u32 alwaysOn[2];
3102
3103 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3104 if (dev->flags & IFF_ALLMULTI) {
3105 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3106 } else {
Jiri Pirko22bedad32010-04-01 21:22:57 +00003107 struct netdev_hw_addr *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003108
Jiri Pirko22bedad32010-04-01 21:22:57 +00003109 netdev_for_each_mc_addr(ha, dev) {
3110 unsigned char *addr = ha->addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003111 u32 a, b;
Jiri Pirko22bedad32010-04-01 21:22:57 +00003112
3113 a = le32_to_cpu(*(__le32 *) addr);
3114 b = le16_to_cpu(*(__le16 *) (&addr[4]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07003115 alwaysOn[0] &= a;
3116 alwaysOff[0] &= ~a;
3117 alwaysOn[1] &= b;
3118 alwaysOff[1] &= ~b;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003119 }
3120 }
3121 addr[0] = alwaysOn[0];
3122 addr[1] = alwaysOn[1];
3123 mask[0] = alwaysOn[0] | alwaysOff[0];
3124 mask[1] = alwaysOn[1] | alwaysOff[1];
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05003125 } else {
3126 mask[0] = NVREG_MCASTMASKA_NONE;
3127 mask[1] = NVREG_MCASTMASKB_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003128 }
3129 }
3130 addr[0] |= NVREG_MCASTADDRA_FORCE;
3131 pff |= NVREG_PFF_ALWAYS;
3132 spin_lock_irq(&np->lock);
3133 nv_stop_rx(dev);
3134 writel(addr[0], base + NvRegMulticastAddrA);
3135 writel(addr[1], base + NvRegMulticastAddrB);
3136 writel(mask[0], base + NvRegMulticastMaskA);
3137 writel(mask[1], base + NvRegMulticastMaskB);
3138 writel(pff, base + NvRegPacketFilterFlags);
3139 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3140 dev->name);
3141 nv_start_rx(dev);
3142 spin_unlock_irq(&np->lock);
3143}
3144
Adrian Bunkc7985052006-06-22 12:03:29 +02003145static void nv_update_pause(struct net_device *dev, u32 pause_flags)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003146{
3147 struct fe_priv *np = netdev_priv(dev);
3148 u8 __iomem *base = get_hwbase(dev);
3149
3150 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3151
3152 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3153 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3154 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3155 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3156 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3157 } else {
3158 writel(pff, base + NvRegPacketFilterFlags);
3159 }
3160 }
3161 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3162 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3163 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003164 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3165 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3166 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003167 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003168 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003169 /* limit the number of tx pause frames to a default of 8 */
3170 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3171 }
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003172 writel(pause_enable, base + NvRegTxPauseFrame);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003173 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3174 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3175 } else {
3176 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3177 writel(regmisc, base + NvRegMisc1);
3178 }
3179 }
3180}
3181
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003182/**
3183 * nv_update_linkspeed: Setup the MAC according to the link partner
3184 * @dev: Network device to be configured
3185 *
3186 * The function queries the PHY and checks if there is a link partner.
3187 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3188 * set to 10 MBit HD.
3189 *
3190 * The function returns 0 if there is no link partner and 1 if there is
3191 * a good link partner.
3192 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003193static int nv_update_linkspeed(struct net_device *dev)
3194{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003195 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003196 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003197 int adv = 0;
3198 int lpa = 0;
3199 int adv_lpa, adv_pause, lpa_pause;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003200 int newls = np->linkspeed;
3201 int newdup = np->duplex;
3202 int mii_status;
3203 int retval = 0;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003204 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003205 u32 txrxFlags = 0;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003206 u32 phy_exp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003207
3208 /* BMSR_LSTATUS is latched, read it twice:
3209 * we want the current value.
3210 */
3211 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3212 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3213
3214 if (!(mii_status & BMSR_LSTATUS)) {
3215 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3216 dev->name);
3217 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3218 newdup = 0;
3219 retval = 0;
3220 goto set_speed;
3221 }
3222
3223 if (np->autoneg == 0) {
3224 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3225 dev->name, np->fixed_mode);
3226 if (np->fixed_mode & LPA_100FULL) {
3227 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3228 newdup = 1;
3229 } else if (np->fixed_mode & LPA_100HALF) {
3230 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3231 newdup = 0;
3232 } else if (np->fixed_mode & LPA_10FULL) {
3233 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3234 newdup = 1;
3235 } else {
3236 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3237 newdup = 0;
3238 }
3239 retval = 1;
3240 goto set_speed;
3241 }
3242 /* check auto negotiation is complete */
3243 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3244 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3245 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3246 newdup = 0;
3247 retval = 0;
3248 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3249 goto set_speed;
3250 }
3251
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003252 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3253 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3254 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3255 dev->name, adv, lpa);
3256
Linus Torvalds1da177e2005-04-16 15:20:36 -07003257 retval = 1;
3258 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003259 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3260 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003261
3262 if ((control_1000 & ADVERTISE_1000FULL) &&
3263 (status_1000 & LPA_1000FULL)) {
3264 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3265 dev->name);
3266 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3267 newdup = 1;
3268 goto set_speed;
3269 }
3270 }
3271
Linus Torvalds1da177e2005-04-16 15:20:36 -07003272 /* FIXME: handle parallel detection properly */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003273 adv_lpa = lpa & adv;
3274 if (adv_lpa & LPA_100FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003275 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3276 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003277 } else if (adv_lpa & LPA_100HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003278 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3279 newdup = 0;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003280 } else if (adv_lpa & LPA_10FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003281 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3282 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003283 } else if (adv_lpa & LPA_10HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003284 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3285 newdup = 0;
3286 } else {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003287 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003288 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3289 newdup = 0;
3290 }
3291
3292set_speed:
3293 if (np->duplex == newdup && np->linkspeed == newls)
3294 return retval;
3295
3296 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3297 dev->name, np->linkspeed, np->duplex, newls, newdup);
3298
3299 np->duplex = newdup;
3300 np->linkspeed = newls;
3301
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003302 /* The transmitter and receiver must be restarted for safe update */
3303 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3304 txrxFlags |= NV_RESTART_TX;
3305 nv_stop_tx(dev);
3306 }
3307 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3308 txrxFlags |= NV_RESTART_RX;
3309 nv_stop_rx(dev);
3310 }
3311
Linus Torvalds1da177e2005-04-16 15:20:36 -07003312 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003313 phyreg = readl(base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003314 phyreg &= ~(0x3FF00);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003315 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3316 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3317 phyreg |= NVREG_SLOTTIME_10_100_FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003318 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003319 phyreg |= NVREG_SLOTTIME_1000_FULL;
3320 writel(phyreg, base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003321 }
3322
3323 phyreg = readl(base + NvRegPhyInterface);
3324 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3325 if (np->duplex == 0)
3326 phyreg |= PHY_HALF;
3327 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3328 phyreg |= PHY_100;
3329 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3330 phyreg |= PHY_1000;
3331 writel(phyreg, base + NvRegPhyInterface);
3332
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003333 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003334 if (phyreg & PHY_RGMII) {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003335 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003336 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003337 } else {
3338 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3339 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3340 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3341 else
3342 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3343 } else {
3344 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3345 }
3346 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003347 } else {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003348 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3349 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3350 else
3351 txreg = NVREG_TX_DEFERRAL_DEFAULT;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003352 }
3353 writel(txreg, base + NvRegTxDeferral);
3354
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04003355 if (np->desc_ver == DESC_VER_1) {
3356 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3357 } else {
3358 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3359 txreg = NVREG_TX_WM_DESC2_3_1000;
3360 else
3361 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3362 }
3363 writel(txreg, base + NvRegTxWatermark);
3364
Linus Torvalds1da177e2005-04-16 15:20:36 -07003365 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3366 base + NvRegMisc1);
3367 pci_push(base);
3368 writel(np->linkspeed, base + NvRegLinkSpeed);
3369 pci_push(base);
3370
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003371 pause_flags = 0;
3372 /* setup pause frame */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003373 if (np->duplex != 0) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003374 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3375 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3376 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003377
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003378 switch (adv_pause) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003379 case ADVERTISE_PAUSE_CAP:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003380 if (lpa_pause & LPA_PAUSE_CAP) {
3381 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3382 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3383 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3384 }
3385 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003386 case ADVERTISE_PAUSE_ASYM:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003387 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3388 {
3389 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3390 }
3391 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003392 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003393 if (lpa_pause & LPA_PAUSE_CAP)
3394 {
3395 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3396 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3397 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3398 }
3399 if (lpa_pause == LPA_PAUSE_ASYM)
3400 {
3401 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3402 }
3403 break;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003404 }
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003405 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003406 pause_flags = np->pause_flags;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003407 }
3408 }
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003409 nv_update_pause(dev, pause_flags);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003410
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003411 if (txrxFlags & NV_RESTART_TX)
3412 nv_start_tx(dev);
3413 if (txrxFlags & NV_RESTART_RX)
3414 nv_start_rx(dev);
3415
Linus Torvalds1da177e2005-04-16 15:20:36 -07003416 return retval;
3417}
3418
3419static void nv_linkchange(struct net_device *dev)
3420{
3421 if (nv_update_linkspeed(dev)) {
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003422 if (!netif_carrier_ok(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003423 netif_carrier_on(dev);
3424 printk(KERN_INFO "%s: link up.\n", dev->name);
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00003425 nv_txrx_gate(dev, false);
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003426 nv_start_rx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003427 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003428 } else {
3429 if (netif_carrier_ok(dev)) {
3430 netif_carrier_off(dev);
3431 printk(KERN_INFO "%s: link down.\n", dev->name);
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00003432 nv_txrx_gate(dev, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003433 nv_stop_rx(dev);
3434 }
3435 }
3436}
3437
3438static void nv_link_irq(struct net_device *dev)
3439{
3440 u8 __iomem *base = get_hwbase(dev);
3441 u32 miistat;
3442
3443 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05003444 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003445 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3446
3447 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3448 nv_linkchange(dev);
3449 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3450}
3451
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003452static void nv_msi_workaround(struct fe_priv *np)
3453{
3454
3455 /* Need to toggle the msi irq mask within the ethernet device,
3456 * otherwise, future interrupts will not be detected.
3457 */
3458 if (np->msi_flags & NV_MSI_ENABLED) {
3459 u8 __iomem *base = np->base;
3460
3461 writel(0, base + NvRegMSIIrqMask);
3462 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3463 }
3464}
3465
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003466static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3467{
3468 struct fe_priv *np = netdev_priv(dev);
3469
3470 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3471 if (total_work > NV_DYNAMIC_THRESHOLD) {
3472 /* transition to poll based interrupts */
3473 np->quiet_count = 0;
3474 if (np->irqmask != NVREG_IRQMASK_CPU) {
3475 np->irqmask = NVREG_IRQMASK_CPU;
3476 return 1;
3477 }
3478 } else {
3479 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3480 np->quiet_count++;
3481 } else {
3482 /* reached a period of low activity, switch
3483 to per tx/rx packet interrupts */
3484 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3485 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3486 return 1;
3487 }
3488 }
3489 }
3490 }
3491 return 0;
3492}
3493
David Howells7d12e782006-10-05 14:55:46 +01003494static irqreturn_t nv_nic_irq(int foo, void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003495{
3496 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003497 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003498 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003499#ifndef CONFIG_FORCEDETH_NAPI
3500 int total_work = 0;
3501 int loop_count = 0;
3502#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003503
3504 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3505
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003506 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3507 np->events = readl(base + NvRegIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003508 writel(np->events, base + NvRegIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003509 } else {
3510 np->events = readl(base + NvRegMSIXIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003511 writel(np->events, base + NvRegMSIXIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003512 }
3513 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3514 if (!(np->events & np->irqmask))
3515 return IRQ_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003516
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003517 nv_msi_workaround(np);
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003518
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003519#ifdef CONFIG_FORCEDETH_NAPI
Eric Dumazet78c29bd2009-07-02 04:04:45 +00003520 if (napi_schedule_prep(&np->napi)) {
3521 /*
3522 * Disable further irq's (msix not enabled with napi)
3523 */
3524 writel(0, base + NvRegIrqMask);
3525 __napi_schedule(&np->napi);
3526 }
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003527
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003528#else
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003529 do
3530 {
3531 int work = 0;
3532 if ((work = nv_rx_process(dev, RX_WORK_PER_LOOP))) {
3533 if (unlikely(nv_alloc_rx(dev))) {
3534 spin_lock(&np->lock);
3535 if (!np->in_shutdown)
3536 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3537 spin_unlock(&np->lock);
3538 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003539 }
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003540
3541 spin_lock(&np->lock);
3542 work += nv_tx_done(dev, TX_WORK_PER_LOOP);
3543 spin_unlock(&np->lock);
3544
3545 if (!work)
3546 break;
3547
3548 total_work += work;
3549
3550 loop_count++;
3551 }
3552 while (loop_count < max_interrupt_work);
3553
3554 if (nv_change_interrupt_mode(dev, total_work)) {
3555 /* setup new irq mask */
3556 writel(np->irqmask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003557 }
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003558
3559 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3560 spin_lock(&np->lock);
3561 nv_link_irq(dev);
3562 spin_unlock(&np->lock);
3563 }
3564 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3565 spin_lock(&np->lock);
3566 nv_linkchange(dev);
3567 spin_unlock(&np->lock);
3568 np->link_timeout = jiffies + LINK_TIMEOUT;
3569 }
3570 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3571 spin_lock(&np->lock);
3572 /* disable interrupts on the nic */
3573 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3574 writel(0, base + NvRegIrqMask);
3575 else
3576 writel(np->irqmask, base + NvRegIrqMask);
3577 pci_push(base);
3578
3579 if (!np->in_shutdown) {
3580 np->nic_poll_irq = np->irqmask;
3581 np->recover_error = 1;
3582 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3583 }
3584 spin_unlock(&np->lock);
3585 }
3586#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003587 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3588
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003589 return IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003590}
3591
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003592/**
3593 * All _optimized functions are used to help increase performance
3594 * (reduce CPU and increase throughput). They use descripter version 3,
3595 * compiler directives, and reduce memory accesses.
3596 */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003597static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3598{
3599 struct net_device *dev = (struct net_device *) data;
3600 struct fe_priv *np = netdev_priv(dev);
3601 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003602#ifndef CONFIG_FORCEDETH_NAPI
3603 int total_work = 0;
3604 int loop_count = 0;
3605#endif
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003606
3607 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3608
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003609 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3610 np->events = readl(base + NvRegIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003611 writel(np->events, base + NvRegIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003612 } else {
3613 np->events = readl(base + NvRegMSIXIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003614 writel(np->events, base + NvRegMSIXIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003615 }
3616 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3617 if (!(np->events & np->irqmask))
3618 return IRQ_NONE;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003619
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003620 nv_msi_workaround(np);
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003621
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003622#ifdef CONFIG_FORCEDETH_NAPI
Eric Dumazet78c29bd2009-07-02 04:04:45 +00003623 if (napi_schedule_prep(&np->napi)) {
3624 /*
3625 * Disable further irq's (msix not enabled with napi)
3626 */
3627 writel(0, base + NvRegIrqMask);
3628 __napi_schedule(&np->napi);
3629 }
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003630#else
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003631 do
3632 {
3633 int work = 0;
3634 if ((work = nv_rx_process_optimized(dev, RX_WORK_PER_LOOP))) {
3635 if (unlikely(nv_alloc_rx_optimized(dev))) {
3636 spin_lock(&np->lock);
3637 if (!np->in_shutdown)
3638 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3639 spin_unlock(&np->lock);
3640 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003641 }
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003642
3643 spin_lock(&np->lock);
3644 work += nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3645 spin_unlock(&np->lock);
3646
3647 if (!work)
3648 break;
3649
3650 total_work += work;
3651
3652 loop_count++;
3653 }
3654 while (loop_count < max_interrupt_work);
3655
3656 if (nv_change_interrupt_mode(dev, total_work)) {
3657 /* setup new irq mask */
3658 writel(np->irqmask, base + NvRegIrqMask);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003659 }
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003660
3661 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3662 spin_lock(&np->lock);
3663 nv_link_irq(dev);
3664 spin_unlock(&np->lock);
3665 }
3666 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3667 spin_lock(&np->lock);
3668 nv_linkchange(dev);
3669 spin_unlock(&np->lock);
3670 np->link_timeout = jiffies + LINK_TIMEOUT;
3671 }
3672 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3673 spin_lock(&np->lock);
3674 /* disable interrupts on the nic */
3675 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3676 writel(0, base + NvRegIrqMask);
3677 else
3678 writel(np->irqmask, base + NvRegIrqMask);
3679 pci_push(base);
3680
3681 if (!np->in_shutdown) {
3682 np->nic_poll_irq = np->irqmask;
3683 np->recover_error = 1;
3684 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3685 }
3686 spin_unlock(&np->lock);
3687 }
3688
3689#endif
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003690 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3691
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003692 return IRQ_HANDLED;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003693}
3694
David Howells7d12e782006-10-05 14:55:46 +01003695static irqreturn_t nv_nic_irq_tx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003696{
3697 struct net_device *dev = (struct net_device *) data;
3698 struct fe_priv *np = netdev_priv(dev);
3699 u8 __iomem *base = get_hwbase(dev);
3700 u32 events;
3701 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003702 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003703
3704 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3705
3706 for (i=0; ; i++) {
3707 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3708 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003709 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3710 if (!(events & np->irqmask))
3711 break;
3712
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003713 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003714 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003715 spin_unlock_irqrestore(&np->lock, flags);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003716
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003717 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003718 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003719 /* disable interrupts on the nic */
3720 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3721 pci_push(base);
3722
3723 if (!np->in_shutdown) {
3724 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3725 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3726 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003727 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003728 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003729 break;
3730 }
3731
3732 }
3733 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3734
3735 return IRQ_RETVAL(i);
3736}
3737
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003738#ifdef CONFIG_FORCEDETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003739static int nv_napi_poll(struct napi_struct *napi, int budget)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003740{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003741 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3742 struct net_device *dev = np->dev;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003743 u8 __iomem *base = get_hwbase(dev);
Francois Romieud15e9c42006-12-17 23:03:15 +01003744 unsigned long flags;
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003745 int retcode;
stephen hemminger81a2e362010-04-28 08:25:28 +00003746 int rx_count, tx_work=0, rx_work=0;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003747
stephen hemminger81a2e362010-04-28 08:25:28 +00003748 do {
3749 if (!nv_optimized(np)) {
3750 spin_lock_irqsave(&np->lock, flags);
3751 tx_work += nv_tx_done(dev, np->tx_ring_size);
3752 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003753
stephen hemminger81a2e362010-04-28 08:25:28 +00003754 rx_count = nv_rx_process(dev, budget);
3755 retcode = nv_alloc_rx(dev);
3756 } else {
3757 spin_lock_irqsave(&np->lock, flags);
3758 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3759 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003760
stephen hemminger81a2e362010-04-28 08:25:28 +00003761 rx_count = nv_rx_process_optimized(dev, budget);
3762 retcode = nv_alloc_rx_optimized(dev);
3763 }
3764 } while (retcode == 0 &&
3765 rx_count > 0 && (rx_work += rx_count) < budget);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003766
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003767 if (retcode) {
Francois Romieud15e9c42006-12-17 23:03:15 +01003768 spin_lock_irqsave(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003769 if (!np->in_shutdown)
3770 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Francois Romieud15e9c42006-12-17 23:03:15 +01003771 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003772 }
3773
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003774 nv_change_interrupt_mode(dev, tx_work + rx_work);
3775
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003776 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3777 spin_lock_irqsave(&np->lock, flags);
3778 nv_link_irq(dev);
3779 spin_unlock_irqrestore(&np->lock, flags);
3780 }
3781 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3782 spin_lock_irqsave(&np->lock, flags);
3783 nv_linkchange(dev);
3784 spin_unlock_irqrestore(&np->lock, flags);
3785 np->link_timeout = jiffies + LINK_TIMEOUT;
3786 }
3787 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3788 spin_lock_irqsave(&np->lock, flags);
3789 if (!np->in_shutdown) {
3790 np->nic_poll_irq = np->irqmask;
3791 np->recover_error = 1;
3792 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3793 }
3794 spin_unlock_irqrestore(&np->lock, flags);
David S. Miller6c2da9c2009-04-09 01:09:33 -07003795 napi_complete(napi);
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003796 return rx_work;
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003797 }
3798
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003799 if (rx_work < budget) {
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003800 /* re-enable interrupts
3801 (msix not enabled in napi) */
David S. Miller6c2da9c2009-04-09 01:09:33 -07003802 napi_complete(napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003803
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003804 writel(np->irqmask, base + NvRegIrqMask);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003805 }
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003806 return rx_work;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003807}
3808#endif
3809
David Howells7d12e782006-10-05 14:55:46 +01003810static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003811{
3812 struct net_device *dev = (struct net_device *) data;
3813 struct fe_priv *np = netdev_priv(dev);
3814 u8 __iomem *base = get_hwbase(dev);
3815 u32 events;
3816 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003817 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003818
3819 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3820
3821 for (i=0; ; i++) {
3822 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3823 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003824 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3825 if (!(events & np->irqmask))
3826 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003827
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003828 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003829 if (unlikely(nv_alloc_rx_optimized(dev))) {
3830 spin_lock_irqsave(&np->lock, flags);
3831 if (!np->in_shutdown)
3832 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3833 spin_unlock_irqrestore(&np->lock, flags);
3834 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003835 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003836
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003837 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003838 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003839 /* disable interrupts on the nic */
3840 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3841 pci_push(base);
3842
3843 if (!np->in_shutdown) {
3844 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3845 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3846 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003847 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003848 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003849 break;
3850 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003851 }
3852 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3853
3854 return IRQ_RETVAL(i);
3855}
3856
David Howells7d12e782006-10-05 14:55:46 +01003857static irqreturn_t nv_nic_irq_other(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003858{
3859 struct net_device *dev = (struct net_device *) data;
3860 struct fe_priv *np = netdev_priv(dev);
3861 u8 __iomem *base = get_hwbase(dev);
3862 u32 events;
3863 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003864 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003865
3866 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3867
3868 for (i=0; ; i++) {
3869 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3870 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003871 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3872 if (!(events & np->irqmask))
3873 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003874
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003875 /* check tx in case we reached max loop limit in tx isr */
3876 spin_lock_irqsave(&np->lock, flags);
3877 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3878 spin_unlock_irqrestore(&np->lock, flags);
3879
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003880 if (events & NVREG_IRQ_LINK) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003881 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003882 nv_link_irq(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003883 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003884 }
3885 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003886 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003887 nv_linkchange(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003888 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003889 np->link_timeout = jiffies + LINK_TIMEOUT;
3890 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003891 if (events & NVREG_IRQ_RECOVER_ERROR) {
3892 spin_lock_irq(&np->lock);
3893 /* disable interrupts on the nic */
3894 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3895 pci_push(base);
3896
3897 if (!np->in_shutdown) {
3898 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3899 np->recover_error = 1;
3900 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3901 }
3902 spin_unlock_irq(&np->lock);
3903 break;
3904 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003905 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003906 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003907 /* disable interrupts on the nic */
3908 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3909 pci_push(base);
3910
3911 if (!np->in_shutdown) {
3912 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3913 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3914 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003915 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003916 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003917 break;
3918 }
3919
3920 }
3921 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3922
3923 return IRQ_RETVAL(i);
3924}
3925
David Howells7d12e782006-10-05 14:55:46 +01003926static irqreturn_t nv_nic_irq_test(int foo, void *data)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003927{
3928 struct net_device *dev = (struct net_device *) data;
3929 struct fe_priv *np = netdev_priv(dev);
3930 u8 __iomem *base = get_hwbase(dev);
3931 u32 events;
3932
3933 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3934
3935 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3936 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3937 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3938 } else {
3939 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3940 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3941 }
3942 pci_push(base);
3943 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3944 if (!(events & NVREG_IRQ_TIMER))
3945 return IRQ_RETVAL(0);
3946
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003947 nv_msi_workaround(np);
3948
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003949 spin_lock(&np->lock);
3950 np->intr_test = 1;
3951 spin_unlock(&np->lock);
3952
3953 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3954
3955 return IRQ_RETVAL(1);
3956}
3957
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003958static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3959{
3960 u8 __iomem *base = get_hwbase(dev);
3961 int i;
3962 u32 msixmap = 0;
3963
3964 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3965 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3966 * the remaining 8 interrupts.
3967 */
3968 for (i = 0; i < 8; i++) {
3969 if ((irqmask >> i) & 0x1) {
3970 msixmap |= vector << (i << 2);
3971 }
3972 }
3973 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3974
3975 msixmap = 0;
3976 for (i = 0; i < 8; i++) {
3977 if ((irqmask >> (i + 8)) & 0x1) {
3978 msixmap |= vector << (i << 2);
3979 }
3980 }
3981 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3982}
3983
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003984static int nv_request_irq(struct net_device *dev, int intr_test)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003985{
3986 struct fe_priv *np = get_nvpriv(dev);
3987 u8 __iomem *base = get_hwbase(dev);
3988 int ret = 1;
3989 int i;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003990 irqreturn_t (*handler)(int foo, void *data);
3991
3992 if (intr_test) {
3993 handler = nv_nic_irq_test;
3994 } else {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003995 if (nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003996 handler = nv_nic_irq_optimized;
3997 else
3998 handler = nv_nic_irq;
3999 }
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004000
4001 if (np->msi_flags & NV_MSI_X_CAPABLE) {
4002 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4003 np->msi_x_entry[i].entry = i;
4004 }
4005 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
4006 np->msi_flags |= NV_MSI_X_ENABLED;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004007 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004008 /* Request irq for rx handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08004009 sprintf(np->name_rx, "%s-rx", dev->name);
4010 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08004011 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004012 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
4013 pci_disable_msix(np->pci_dev);
4014 np->msi_flags &= ~NV_MSI_X_ENABLED;
4015 goto out_err;
4016 }
4017 /* Request irq for tx handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08004018 sprintf(np->name_tx, "%s-tx", dev->name);
4019 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08004020 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004021 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
4022 pci_disable_msix(np->pci_dev);
4023 np->msi_flags &= ~NV_MSI_X_ENABLED;
4024 goto out_free_rx;
4025 }
4026 /* Request irq for link and timer handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08004027 sprintf(np->name_other, "%s-other", dev->name);
4028 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08004029 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004030 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
4031 pci_disable_msix(np->pci_dev);
4032 np->msi_flags &= ~NV_MSI_X_ENABLED;
4033 goto out_free_tx;
4034 }
4035 /* map interrupts to their respective vector */
4036 writel(0, base + NvRegMSIXMap0);
4037 writel(0, base + NvRegMSIXMap1);
4038 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4039 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4040 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4041 } else {
4042 /* Request irq for all interrupts */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05004043 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004044 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4045 pci_disable_msix(np->pci_dev);
4046 np->msi_flags &= ~NV_MSI_X_ENABLED;
4047 goto out_err;
4048 }
4049
4050 /* map interrupts to vector 0 */
4051 writel(0, base + NvRegMSIXMap0);
4052 writel(0, base + NvRegMSIXMap1);
4053 }
4054 }
4055 }
4056 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
4057 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
4058 np->msi_flags |= NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02004059 dev->irq = np->pci_dev->irq;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05004060 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004061 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4062 pci_disable_msi(np->pci_dev);
4063 np->msi_flags &= ~NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02004064 dev->irq = np->pci_dev->irq;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004065 goto out_err;
4066 }
4067
4068 /* map interrupts to vector 0 */
4069 writel(0, base + NvRegMSIMap0);
4070 writel(0, base + NvRegMSIMap1);
4071 /* enable msi vector 0 */
4072 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4073 }
4074 }
4075 if (ret != 0) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05004076 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004077 goto out_err;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004078
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04004079 }
4080
4081 return 0;
4082out_free_tx:
4083 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4084out_free_rx:
4085 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4086out_err:
4087 return 1;
4088}
4089
4090static void nv_free_irq(struct net_device *dev)
4091{
4092 struct fe_priv *np = get_nvpriv(dev);
4093 int i;
4094
4095 if (np->msi_flags & NV_MSI_X_ENABLED) {
4096 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4097 free_irq(np->msi_x_entry[i].vector, dev);
4098 }
4099 pci_disable_msix(np->pci_dev);
4100 np->msi_flags &= ~NV_MSI_X_ENABLED;
4101 } else {
4102 free_irq(np->pci_dev->irq, dev);
4103 if (np->msi_flags & NV_MSI_ENABLED) {
4104 pci_disable_msi(np->pci_dev);
4105 np->msi_flags &= ~NV_MSI_ENABLED;
4106 }
4107 }
4108}
4109
Linus Torvalds1da177e2005-04-16 15:20:36 -07004110static void nv_do_nic_poll(unsigned long data)
4111{
4112 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004113 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004114 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004115 u32 mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004116
Linus Torvalds1da177e2005-04-16 15:20:36 -07004117 /*
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004118 * First disable irq(s) and then
Linus Torvalds1da177e2005-04-16 15:20:36 -07004119 * reenable interrupts on the nic, we have to do this before calling
4120 * nv_nic_irq because that may decide to do otherwise
4121 */
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004122
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004123 if (!using_multi_irqs(dev)) {
4124 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004125 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004126 else
Manfred Spraula7475902007-10-17 21:52:33 +02004127 disable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004128 mask = np->irqmask;
4129 } else {
4130 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004131 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004132 mask |= NVREG_IRQ_RX_ALL;
4133 }
4134 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004135 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004136 mask |= NVREG_IRQ_TX_ALL;
4137 }
4138 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004139 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004140 mask |= NVREG_IRQ_OTHER;
4141 }
4142 }
Manfred Spraula7475902007-10-17 21:52:33 +02004143 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4144
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004145 if (np->recover_error) {
4146 np->recover_error = 0;
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08004147 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004148 if (netif_running(dev)) {
4149 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004150 netif_addr_lock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004151 spin_lock(&np->lock);
4152 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004153 nv_stop_rxtx(dev);
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08004154 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4155 nv_mac_reset(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004156 nv_txrx_reset(dev);
4157 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004158 nv_drain_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004159 /* reinit driver view of the rx queue */
4160 set_bufsize(dev);
4161 if (nv_init_ring(dev)) {
4162 if (!np->in_shutdown)
4163 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4164 }
4165 /* reinit nic view of the rx queue */
4166 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4167 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4168 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4169 base + NvRegRingSizes);
4170 pci_push(base);
4171 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4172 pci_push(base);
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08004173 /* clear interrupts */
4174 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4175 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4176 else
4177 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004178
4179 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004180 nv_start_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004181 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004182 netif_addr_unlock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004183 netif_tx_unlock_bh(dev);
4184 }
4185 }
4186
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004187 writel(mask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004188 pci_push(base);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004189
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004190 if (!using_multi_irqs(dev)) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08004191 np->nic_poll_irq = 0;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004192 if (nv_optimized(np))
Ayaz Abdullafcc5f262007-03-23 05:49:37 -05004193 nv_nic_irq_optimized(0, dev);
4194 else
4195 nv_nic_irq(0, dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004196 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004197 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004198 else
Manfred Spraula7475902007-10-17 21:52:33 +02004199 enable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004200 } else {
4201 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08004202 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
David Howells7d12e782006-10-05 14:55:46 +01004203 nv_nic_irq_rx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004204 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004205 }
4206 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08004207 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
David Howells7d12e782006-10-05 14:55:46 +01004208 nv_nic_irq_tx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004209 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004210 }
4211 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08004212 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
David Howells7d12e782006-10-05 14:55:46 +01004213 nv_nic_irq_other(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004214 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004215 }
4216 }
Yinghai Lu79d30a52009-02-06 01:30:01 -08004217
Linus Torvalds1da177e2005-04-16 15:20:36 -07004218}
4219
Michal Schmidt2918c352005-05-12 19:42:06 -04004220#ifdef CONFIG_NET_POLL_CONTROLLER
4221static void nv_poll_controller(struct net_device *dev)
4222{
4223 nv_do_nic_poll((unsigned long) dev);
4224}
4225#endif
4226
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004227static void nv_do_stats_poll(unsigned long data)
4228{
4229 struct net_device *dev = (struct net_device *) data;
4230 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004231
Ayaz Abdulla57fff692007-01-23 12:27:00 -05004232 nv_get_hw_stats(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004233
4234 if (!np->in_shutdown)
Daniel Drakebfebbb82008-03-18 11:07:18 +00004235 mod_timer(&np->stats_poll,
4236 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004237}
4238
Linus Torvalds1da177e2005-04-16 15:20:36 -07004239static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4240{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004241 struct fe_priv *np = netdev_priv(dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04004242 strcpy(info->driver, DRV_NAME);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004243 strcpy(info->version, FORCEDETH_VERSION);
4244 strcpy(info->bus_info, pci_name(np->pci_dev));
4245}
4246
4247static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4248{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004249 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004250 wolinfo->supported = WAKE_MAGIC;
4251
4252 spin_lock_irq(&np->lock);
4253 if (np->wolenabled)
4254 wolinfo->wolopts = WAKE_MAGIC;
4255 spin_unlock_irq(&np->lock);
4256}
4257
4258static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4259{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004260 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004261 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004262 u32 flags = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004263
Linus Torvalds1da177e2005-04-16 15:20:36 -07004264 if (wolinfo->wolopts == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004265 np->wolenabled = 0;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004266 } else if (wolinfo->wolopts & WAKE_MAGIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004267 np->wolenabled = 1;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004268 flags = NVREG_WAKEUPFLAGS_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004269 }
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004270 if (netif_running(dev)) {
4271 spin_lock_irq(&np->lock);
4272 writel(flags, base + NvRegWakeUpFlags);
4273 spin_unlock_irq(&np->lock);
4274 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004275 return 0;
4276}
4277
4278static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4279{
4280 struct fe_priv *np = netdev_priv(dev);
4281 int adv;
4282
4283 spin_lock_irq(&np->lock);
4284 ecmd->port = PORT_MII;
4285 if (!netif_running(dev)) {
4286 /* We do not track link speed / duplex setting if the
4287 * interface is disabled. Force a link check */
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004288 if (nv_update_linkspeed(dev)) {
4289 if (!netif_carrier_ok(dev))
4290 netif_carrier_on(dev);
4291 } else {
4292 if (netif_carrier_ok(dev))
4293 netif_carrier_off(dev);
4294 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004295 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004296
4297 if (netif_carrier_ok(dev)) {
4298 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004299 case NVREG_LINKSPEED_10:
4300 ecmd->speed = SPEED_10;
4301 break;
4302 case NVREG_LINKSPEED_100:
4303 ecmd->speed = SPEED_100;
4304 break;
4305 case NVREG_LINKSPEED_1000:
4306 ecmd->speed = SPEED_1000;
4307 break;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004308 }
4309 ecmd->duplex = DUPLEX_HALF;
4310 if (np->duplex)
4311 ecmd->duplex = DUPLEX_FULL;
4312 } else {
4313 ecmd->speed = -1;
4314 ecmd->duplex = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004315 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004316
4317 ecmd->autoneg = np->autoneg;
4318
4319 ecmd->advertising = ADVERTISED_MII;
4320 if (np->autoneg) {
4321 ecmd->advertising |= ADVERTISED_Autoneg;
4322 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004323 if (adv & ADVERTISE_10HALF)
4324 ecmd->advertising |= ADVERTISED_10baseT_Half;
4325 if (adv & ADVERTISE_10FULL)
4326 ecmd->advertising |= ADVERTISED_10baseT_Full;
4327 if (adv & ADVERTISE_100HALF)
4328 ecmd->advertising |= ADVERTISED_100baseT_Half;
4329 if (adv & ADVERTISE_100FULL)
4330 ecmd->advertising |= ADVERTISED_100baseT_Full;
4331 if (np->gigabit == PHY_GIGABIT) {
4332 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4333 if (adv & ADVERTISE_1000FULL)
4334 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4335 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004336 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004337 ecmd->supported = (SUPPORTED_Autoneg |
4338 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4339 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4340 SUPPORTED_MII);
4341 if (np->gigabit == PHY_GIGABIT)
4342 ecmd->supported |= SUPPORTED_1000baseT_Full;
4343
4344 ecmd->phy_address = np->phyaddr;
4345 ecmd->transceiver = XCVR_EXTERNAL;
4346
4347 /* ignore maxtxpkt, maxrxpkt for now */
4348 spin_unlock_irq(&np->lock);
4349 return 0;
4350}
4351
4352static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4353{
4354 struct fe_priv *np = netdev_priv(dev);
4355
4356 if (ecmd->port != PORT_MII)
4357 return -EINVAL;
4358 if (ecmd->transceiver != XCVR_EXTERNAL)
4359 return -EINVAL;
4360 if (ecmd->phy_address != np->phyaddr) {
4361 /* TODO: support switching between multiple phys. Should be
4362 * trivial, but not enabled due to lack of test hardware. */
4363 return -EINVAL;
4364 }
4365 if (ecmd->autoneg == AUTONEG_ENABLE) {
4366 u32 mask;
4367
4368 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4369 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4370 if (np->gigabit == PHY_GIGABIT)
4371 mask |= ADVERTISED_1000baseT_Full;
4372
4373 if ((ecmd->advertising & mask) == 0)
4374 return -EINVAL;
4375
4376 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4377 /* Note: autonegotiation disable, speed 1000 intentionally
4378 * forbidden - noone should need that. */
4379
4380 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4381 return -EINVAL;
4382 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4383 return -EINVAL;
4384 } else {
4385 return -EINVAL;
4386 }
4387
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004388 netif_carrier_off(dev);
4389 if (netif_running(dev)) {
Tobias Diedrich97bff092008-07-03 23:54:56 -07004390 unsigned long flags;
4391
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004392 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004393 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004394 netif_addr_lock(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004395 /* with plain spinlock lockdep complains */
4396 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004397 /* stop engines */
Tobias Diedrich97bff092008-07-03 23:54:56 -07004398 /* FIXME:
4399 * this can take some time, and interrupts are disabled
4400 * due to spin_lock_irqsave, but let's hope no daemon
4401 * is going to change the settings very often...
4402 * Worst case:
4403 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4404 * + some minor delays, which is up to a second approximately
4405 */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004406 nv_stop_rxtx(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004407 spin_unlock_irqrestore(&np->lock, flags);
David S. Millere308a5d2008-07-15 00:13:44 -07004408 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004409 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004410 }
4411
Linus Torvalds1da177e2005-04-16 15:20:36 -07004412 if (ecmd->autoneg == AUTONEG_ENABLE) {
4413 int adv, bmcr;
4414
4415 np->autoneg = 1;
4416
4417 /* advertise only what has been requested */
4418 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004419 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004420 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4421 adv |= ADVERTISE_10HALF;
4422 if (ecmd->advertising & ADVERTISED_10baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004423 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004424 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4425 adv |= ADVERTISE_100HALF;
4426 if (ecmd->advertising & ADVERTISED_100baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004427 adv |= ADVERTISE_100FULL;
4428 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4429 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4430 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4431 adv |= ADVERTISE_PAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004432 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4433
4434 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004435 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004436 adv &= ~ADVERTISE_1000FULL;
4437 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4438 adv |= ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004439 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004440 }
4441
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004442 if (netif_running(dev))
4443 printk(KERN_INFO "%s: link down.\n", dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004444 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004445 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4446 bmcr |= BMCR_ANENABLE;
4447 /* reset the phy in order for settings to stick,
4448 * and cause autoneg to start */
4449 if (phy_reset(dev, bmcr)) {
4450 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4451 return -EINVAL;
4452 }
4453 } else {
4454 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4455 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4456 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004457 } else {
4458 int adv, bmcr;
4459
4460 np->autoneg = 0;
4461
4462 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004463 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004464 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4465 adv |= ADVERTISE_10HALF;
4466 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004467 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004468 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4469 adv |= ADVERTISE_100HALF;
4470 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004471 adv |= ADVERTISE_100FULL;
4472 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4473 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4474 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4475 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4476 }
4477 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4478 adv |= ADVERTISE_PAUSE_ASYM;
4479 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4480 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004481 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4482 np->fixed_mode = adv;
4483
4484 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004485 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004486 adv &= ~ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004487 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004488 }
4489
4490 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004491 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4492 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004493 bmcr |= BMCR_FULLDPLX;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004494 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004495 bmcr |= BMCR_SPEED100;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004496 if (np->phy_oui == PHY_OUI_MARVELL) {
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004497 /* reset the phy in order for forced mode settings to stick */
4498 if (phy_reset(dev, bmcr)) {
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004499 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4500 return -EINVAL;
4501 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004502 } else {
4503 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4504 if (netif_running(dev)) {
4505 /* Wait a bit and then reconfigure the nic. */
4506 udelay(10);
4507 nv_linkchange(dev);
4508 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004509 }
4510 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004511
4512 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004513 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004514 nv_enable_irq(dev);
4515 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004516
4517 return 0;
4518}
4519
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004520#define FORCEDETH_REGS_VER 1
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004521
4522static int nv_get_regs_len(struct net_device *dev)
4523{
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004524 struct fe_priv *np = netdev_priv(dev);
4525 return np->register_size;
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004526}
4527
4528static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4529{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004530 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004531 u8 __iomem *base = get_hwbase(dev);
4532 u32 *rbuf = buf;
4533 int i;
4534
4535 regs->version = FORCEDETH_REGS_VER;
4536 spin_lock_irq(&np->lock);
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004537 for (i = 0;i <= np->register_size/sizeof(u32); i++)
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004538 rbuf[i] = readl(base + i*sizeof(u32));
4539 spin_unlock_irq(&np->lock);
4540}
4541
4542static int nv_nway_reset(struct net_device *dev)
4543{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004544 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004545 int ret;
4546
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004547 if (np->autoneg) {
4548 int bmcr;
4549
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004550 netif_carrier_off(dev);
4551 if (netif_running(dev)) {
4552 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004553 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004554 netif_addr_lock(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004555 spin_lock(&np->lock);
4556 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004557 nv_stop_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004558 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004559 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004560 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004561 printk(KERN_INFO "%s: link down.\n", dev->name);
4562 }
4563
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004564 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004565 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4566 bmcr |= BMCR_ANENABLE;
4567 /* reset the phy in order for settings to stick*/
4568 if (phy_reset(dev, bmcr)) {
4569 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4570 return -EINVAL;
4571 }
4572 } else {
4573 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4574 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4575 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004576
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004577 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004578 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004579 nv_enable_irq(dev);
4580 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004581 ret = 0;
4582 } else {
4583 ret = -EINVAL;
4584 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004585
4586 return ret;
4587}
4588
Zachary Amsden0674d592006-06-04 02:51:38 -07004589static int nv_set_tso(struct net_device *dev, u32 value)
4590{
4591 struct fe_priv *np = netdev_priv(dev);
4592
4593 if ((np->driver_data & DEV_HAS_CHECKSUM))
4594 return ethtool_op_set_tso(dev, value);
4595 else
Ayaz Abdulla6a788142006-06-10 22:47:26 -04004596 return -EOPNOTSUPP;
Zachary Amsden0674d592006-06-04 02:51:38 -07004597}
Zachary Amsden0674d592006-06-04 02:51:38 -07004598
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004599static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4600{
4601 struct fe_priv *np = netdev_priv(dev);
4602
4603 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4604 ring->rx_mini_max_pending = 0;
4605 ring->rx_jumbo_max_pending = 0;
4606 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4607
4608 ring->rx_pending = np->rx_ring_size;
4609 ring->rx_mini_pending = 0;
4610 ring->rx_jumbo_pending = 0;
4611 ring->tx_pending = np->tx_ring_size;
4612}
4613
4614static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4615{
4616 struct fe_priv *np = netdev_priv(dev);
4617 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004618 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004619 dma_addr_t ring_addr;
4620
4621 if (ring->rx_pending < RX_RING_MIN ||
4622 ring->tx_pending < TX_RING_MIN ||
4623 ring->rx_mini_pending != 0 ||
4624 ring->rx_jumbo_pending != 0 ||
4625 (np->desc_ver == DESC_VER_1 &&
4626 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4627 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4628 (np->desc_ver != DESC_VER_1 &&
4629 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4630 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4631 return -EINVAL;
4632 }
4633
4634 /* allocate new rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004635 if (!nv_optimized(np)) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004636 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4637 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4638 &ring_addr);
4639 } else {
4640 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4641 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4642 &ring_addr);
4643 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004644 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4645 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4646 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004647 /* fall back to old rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004648 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004649 if (rxtx_ring)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004650 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4651 rxtx_ring, ring_addr);
4652 } else {
4653 if (rxtx_ring)
4654 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4655 rxtx_ring, ring_addr);
4656 }
4657 if (rx_skbuff)
4658 kfree(rx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004659 if (tx_skbuff)
4660 kfree(tx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004661 goto exit;
4662 }
4663
4664 if (netif_running(dev)) {
4665 nv_disable_irq(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004666 nv_napi_disable(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004667 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004668 netif_addr_lock(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004669 spin_lock(&np->lock);
4670 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004671 nv_stop_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004672 nv_txrx_reset(dev);
4673 /* drain queues */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004674 nv_drain_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004675 /* delete queues */
4676 free_rings(dev);
4677 }
4678
4679 /* set new values */
4680 np->rx_ring_size = ring->rx_pending;
4681 np->tx_ring_size = ring->tx_pending;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004682
4683 if (!nv_optimized(np)) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004684 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4685 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4686 } else {
4687 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4688 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4689 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004690 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4691 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004692 np->ring_addr = ring_addr;
4693
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004694 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4695 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004696
4697 if (netif_running(dev)) {
4698 /* reinit driver view of the queues */
4699 set_bufsize(dev);
4700 if (nv_init_ring(dev)) {
4701 if (!np->in_shutdown)
4702 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4703 }
4704
4705 /* reinit nic view of the queues */
4706 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4707 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4708 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4709 base + NvRegRingSizes);
4710 pci_push(base);
4711 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4712 pci_push(base);
4713
4714 /* restart engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004715 nv_start_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004716 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004717 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004718 netif_tx_unlock_bh(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004719 nv_napi_enable(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004720 nv_enable_irq(dev);
4721 }
4722 return 0;
4723exit:
4724 return -ENOMEM;
4725}
4726
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004727static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4728{
4729 struct fe_priv *np = netdev_priv(dev);
4730
4731 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4732 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4733 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4734}
4735
4736static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4737{
4738 struct fe_priv *np = netdev_priv(dev);
4739 int adv, bmcr;
4740
4741 if ((!np->autoneg && np->duplex == 0) ||
4742 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4743 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4744 dev->name);
4745 return -EINVAL;
4746 }
4747 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4748 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4749 return -EINVAL;
4750 }
4751
4752 netif_carrier_off(dev);
4753 if (netif_running(dev)) {
4754 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004755 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004756 netif_addr_lock(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004757 spin_lock(&np->lock);
4758 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004759 nv_stop_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004760 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004761 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004762 netif_tx_unlock_bh(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004763 }
4764
4765 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4766 if (pause->rx_pause)
4767 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4768 if (pause->tx_pause)
4769 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4770
4771 if (np->autoneg && pause->autoneg) {
4772 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4773
4774 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4775 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4776 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4777 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4778 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4779 adv |= ADVERTISE_PAUSE_ASYM;
4780 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4781
4782 if (netif_running(dev))
4783 printk(KERN_INFO "%s: link down.\n", dev->name);
4784 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4785 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4786 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4787 } else {
4788 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4789 if (pause->rx_pause)
4790 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4791 if (pause->tx_pause)
4792 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4793
4794 if (!netif_running(dev))
4795 nv_update_linkspeed(dev);
4796 else
4797 nv_update_pause(dev, np->pause_flags);
4798 }
4799
4800 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004801 nv_start_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004802 nv_enable_irq(dev);
4803 }
4804 return 0;
4805}
4806
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004807static u32 nv_get_rx_csum(struct net_device *dev)
4808{
4809 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004810 return (np->rx_csum) != 0;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004811}
4812
4813static int nv_set_rx_csum(struct net_device *dev, u32 data)
4814{
4815 struct fe_priv *np = netdev_priv(dev);
4816 u8 __iomem *base = get_hwbase(dev);
4817 int retcode = 0;
4818
4819 if (np->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004820 if (data) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004821 np->rx_csum = 1;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004822 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004823 } else {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004824 np->rx_csum = 0;
4825 /* vlan is dependent on rx checksum offload */
4826 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4827 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004828 }
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004829 if (netif_running(dev)) {
4830 spin_lock_irq(&np->lock);
4831 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4832 spin_unlock_irq(&np->lock);
4833 }
4834 } else {
4835 return -EINVAL;
4836 }
4837
4838 return retcode;
4839}
4840
4841static int nv_set_tx_csum(struct net_device *dev, u32 data)
4842{
4843 struct fe_priv *np = netdev_priv(dev);
4844
4845 if (np->driver_data & DEV_HAS_CHECKSUM)
Ayaz Abdullac1086cd2009-02-07 00:24:39 -08004846 return ethtool_op_set_tx_csum(dev, data);
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004847 else
4848 return -EOPNOTSUPP;
4849}
4850
4851static int nv_set_sg(struct net_device *dev, u32 data)
4852{
4853 struct fe_priv *np = netdev_priv(dev);
4854
4855 if (np->driver_data & DEV_HAS_CHECKSUM)
4856 return ethtool_op_set_sg(dev, data);
4857 else
4858 return -EOPNOTSUPP;
4859}
4860
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004861static int nv_get_sset_count(struct net_device *dev, int sset)
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004862{
4863 struct fe_priv *np = netdev_priv(dev);
4864
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004865 switch (sset) {
4866 case ETH_SS_TEST:
4867 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4868 return NV_TEST_COUNT_EXTENDED;
4869 else
4870 return NV_TEST_COUNT_BASE;
4871 case ETH_SS_STATS:
Ayaz Abdulla8ed14542009-03-05 08:01:49 +00004872 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4873 return NV_DEV_STATISTICS_V3_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004874 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4875 return NV_DEV_STATISTICS_V2_COUNT;
Ayaz Abdulla8ed14542009-03-05 08:01:49 +00004876 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4877 return NV_DEV_STATISTICS_V1_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004878 else
4879 return 0;
4880 default:
4881 return -EOPNOTSUPP;
4882 }
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004883}
4884
4885static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4886{
4887 struct fe_priv *np = netdev_priv(dev);
4888
4889 /* update stats */
4890 nv_do_stats_poll((unsigned long)dev);
4891
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004892 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004893}
4894
4895static int nv_link_test(struct net_device *dev)
4896{
4897 struct fe_priv *np = netdev_priv(dev);
4898 int mii_status;
4899
4900 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4901 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4902
4903 /* check phy link status */
4904 if (!(mii_status & BMSR_LSTATUS))
4905 return 0;
4906 else
4907 return 1;
4908}
4909
4910static int nv_register_test(struct net_device *dev)
4911{
4912 u8 __iomem *base = get_hwbase(dev);
4913 int i = 0;
4914 u32 orig_read, new_read;
4915
4916 do {
4917 orig_read = readl(base + nv_registers_test[i].reg);
4918
4919 /* xor with mask to toggle bits */
4920 orig_read ^= nv_registers_test[i].mask;
4921
4922 writel(orig_read, base + nv_registers_test[i].reg);
4923
4924 new_read = readl(base + nv_registers_test[i].reg);
4925
4926 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4927 return 0;
4928
4929 /* restore original value */
4930 orig_read ^= nv_registers_test[i].mask;
4931 writel(orig_read, base + nv_registers_test[i].reg);
4932
4933 } while (nv_registers_test[++i].reg != 0);
4934
4935 return 1;
4936}
4937
4938static int nv_interrupt_test(struct net_device *dev)
4939{
4940 struct fe_priv *np = netdev_priv(dev);
4941 u8 __iomem *base = get_hwbase(dev);
4942 int ret = 1;
4943 int testcnt;
4944 u32 save_msi_flags, save_poll_interval = 0;
4945
4946 if (netif_running(dev)) {
4947 /* free current irq */
4948 nv_free_irq(dev);
4949 save_poll_interval = readl(base+NvRegPollingInterval);
4950 }
4951
4952 /* flag to test interrupt handler */
4953 np->intr_test = 0;
4954
4955 /* setup test irq */
4956 save_msi_flags = np->msi_flags;
4957 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4958 np->msi_flags |= 0x001; /* setup 1 vector */
4959 if (nv_request_irq(dev, 1))
4960 return 0;
4961
4962 /* setup timer interrupt */
4963 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4964 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4965
4966 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4967
4968 /* wait for at least one interrupt */
4969 msleep(100);
4970
4971 spin_lock_irq(&np->lock);
4972
4973 /* flag should be set within ISR */
4974 testcnt = np->intr_test;
4975 if (!testcnt)
4976 ret = 2;
4977
4978 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4979 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4980 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4981 else
4982 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4983
4984 spin_unlock_irq(&np->lock);
4985
4986 nv_free_irq(dev);
4987
4988 np->msi_flags = save_msi_flags;
4989
4990 if (netif_running(dev)) {
4991 writel(save_poll_interval, base + NvRegPollingInterval);
4992 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4993 /* restore original irq */
4994 if (nv_request_irq(dev, 0))
4995 return 0;
4996 }
4997
4998 return ret;
4999}
5000
5001static int nv_loopback_test(struct net_device *dev)
5002{
5003 struct fe_priv *np = netdev_priv(dev);
5004 u8 __iomem *base = get_hwbase(dev);
5005 struct sk_buff *tx_skb, *rx_skb;
5006 dma_addr_t test_dma_addr;
5007 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005008 u32 flags;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005009 int len, i, pkt_len;
5010 u8 *pkt_data;
5011 u32 filter_flags = 0;
5012 u32 misc1_flags = 0;
5013 int ret = 1;
5014
5015 if (netif_running(dev)) {
5016 nv_disable_irq(dev);
5017 filter_flags = readl(base + NvRegPacketFilterFlags);
5018 misc1_flags = readl(base + NvRegMisc1);
5019 } else {
5020 nv_txrx_reset(dev);
5021 }
5022
5023 /* reinit driver view of the rx queue */
5024 set_bufsize(dev);
5025 nv_init_ring(dev);
5026
5027 /* setup hardware for loopback */
5028 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5029 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5030
5031 /* reinit nic view of the rx queue */
5032 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5033 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5034 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5035 base + NvRegRingSizes);
5036 pci_push(base);
5037
5038 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005039 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005040
5041 /* setup packet for tx */
5042 pkt_len = ETH_DATA_LEN;
5043 tx_skb = dev_alloc_skb(pkt_len);
Jesper Juhl46798c82006-09-25 16:39:24 -07005044 if (!tx_skb) {
5045 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
5046 " of %s\n", dev->name);
5047 ret = 0;
5048 goto out;
5049 }
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03005050 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5051 skb_tailroom(tx_skb),
5052 PCI_DMA_FROMDEVICE);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005053 pkt_data = skb_put(tx_skb, pkt_len);
5054 for (i = 0; i < pkt_len; i++)
5055 pkt_data[i] = (u8)(i & 0xff);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005056
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005057 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005058 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5059 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005060 } else {
Al Viro5bb7ea22007-12-09 16:06:41 +00005061 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5062 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005063 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005064 }
5065 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5066 pci_push(get_hwbase(dev));
5067
5068 msleep(500);
5069
5070 /* check for rx of the packet */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005071 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005072 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005073 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5074
5075 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005076 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005077 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5078 }
5079
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005080 if (flags & NV_RX_AVAIL) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005081 ret = 0;
5082 } else if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005083 if (flags & NV_RX_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005084 ret = 0;
5085 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07005086 if (flags & NV_RX2_ERROR) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005087 ret = 0;
5088 }
5089 }
5090
5091 if (ret) {
5092 if (len != pkt_len) {
5093 ret = 0;
5094 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5095 dev->name, len, pkt_len);
5096 } else {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05005097 rx_skb = np->rx_skb[0].skb;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005098 for (i = 0; i < pkt_len; i++) {
5099 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5100 ret = 0;
5101 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5102 dev->name, i);
5103 break;
5104 }
5105 }
5106 }
5107 } else {
5108 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5109 }
5110
Eric Dumazet73a37072009-06-17 21:17:59 +00005111 pci_unmap_single(np->pci_dev, test_dma_addr,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07005112 (skb_end_pointer(tx_skb) - tx_skb->data),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005113 PCI_DMA_TODEVICE);
5114 dev_kfree_skb_any(tx_skb);
Jesper Juhl46798c82006-09-25 16:39:24 -07005115 out:
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005116 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005117 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005118 nv_txrx_reset(dev);
5119 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005120 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005121
5122 if (netif_running(dev)) {
5123 writel(misc1_flags, base + NvRegMisc1);
5124 writel(filter_flags, base + NvRegPacketFilterFlags);
5125 nv_enable_irq(dev);
5126 }
5127
5128 return ret;
5129}
5130
5131static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5132{
5133 struct fe_priv *np = netdev_priv(dev);
5134 u8 __iomem *base = get_hwbase(dev);
5135 int result;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005136 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005137
5138 if (!nv_link_test(dev)) {
5139 test->flags |= ETH_TEST_FL_FAILED;
5140 buffer[0] = 1;
5141 }
5142
5143 if (test->flags & ETH_TEST_FL_OFFLINE) {
5144 if (netif_running(dev)) {
5145 netif_stop_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005146 nv_napi_disable(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10005147 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07005148 netif_addr_lock(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005149 spin_lock_irq(&np->lock);
5150 nv_disable_hw_interrupts(dev, np->irqmask);
5151 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5152 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5153 } else {
5154 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5155 }
5156 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005157 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005158 nv_txrx_reset(dev);
5159 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005160 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005161 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07005162 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10005163 netif_tx_unlock_bh(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005164 }
5165
5166 if (!nv_register_test(dev)) {
5167 test->flags |= ETH_TEST_FL_FAILED;
5168 buffer[1] = 1;
5169 }
5170
5171 result = nv_interrupt_test(dev);
5172 if (result != 1) {
5173 test->flags |= ETH_TEST_FL_FAILED;
5174 buffer[2] = 1;
5175 }
5176 if (result == 0) {
5177 /* bail out */
5178 return;
5179 }
5180
5181 if (!nv_loopback_test(dev)) {
5182 test->flags |= ETH_TEST_FL_FAILED;
5183 buffer[3] = 1;
5184 }
5185
5186 if (netif_running(dev)) {
5187 /* reinit driver view of the rx queue */
5188 set_bufsize(dev);
5189 if (nv_init_ring(dev)) {
5190 if (!np->in_shutdown)
5191 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5192 }
5193 /* reinit nic view of the rx queue */
5194 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5195 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5196 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5197 base + NvRegRingSizes);
5198 pci_push(base);
5199 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5200 pci_push(base);
5201 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005202 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005203 netif_start_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005204 nv_napi_enable(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005205 nv_enable_hw_interrupts(dev, np->irqmask);
5206 }
5207 }
5208}
5209
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005210static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5211{
5212 switch (stringset) {
5213 case ETH_SS_STATS:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005214 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005215 break;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005216 case ETH_SS_TEST:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005217 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005218 break;
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005219 }
5220}
5221
Jeff Garzik7282d492006-09-13 14:30:00 -04005222static const struct ethtool_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005223 .get_drvinfo = nv_get_drvinfo,
5224 .get_link = ethtool_op_get_link,
5225 .get_wol = nv_get_wol,
5226 .set_wol = nv_set_wol,
5227 .get_settings = nv_get_settings,
5228 .set_settings = nv_set_settings,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005229 .get_regs_len = nv_get_regs_len,
5230 .get_regs = nv_get_regs,
5231 .nway_reset = nv_nway_reset,
Ayaz Abdulla6a788142006-06-10 22:47:26 -04005232 .set_tso = nv_set_tso,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005233 .get_ringparam = nv_get_ringparam,
5234 .set_ringparam = nv_set_ringparam,
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005235 .get_pauseparam = nv_get_pauseparam,
5236 .set_pauseparam = nv_set_pauseparam,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005237 .get_rx_csum = nv_get_rx_csum,
5238 .set_rx_csum = nv_set_rx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005239 .set_tx_csum = nv_set_tx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005240 .set_sg = nv_set_sg,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005241 .get_strings = nv_get_strings,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005242 .get_ethtool_stats = nv_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005243 .get_sset_count = nv_get_sset_count,
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005244 .self_test = nv_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005245};
5246
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005247static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5248{
5249 struct fe_priv *np = get_nvpriv(dev);
5250
5251 spin_lock_irq(&np->lock);
5252
5253 /* save vlan group */
5254 np->vlangrp = grp;
5255
5256 if (grp) {
5257 /* enable vlan on MAC */
5258 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5259 } else {
5260 /* disable vlan on MAC */
5261 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5262 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5263 }
5264
5265 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5266
5267 spin_unlock_irq(&np->lock);
Stephen Hemminger25805dc2007-06-01 09:44:01 -07005268}
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005269
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005270/* The mgmt unit and driver use a semaphore to access the phy during init */
5271static int nv_mgmt_acquire_sema(struct net_device *dev)
5272{
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005273 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005274 u8 __iomem *base = get_hwbase(dev);
5275 int i;
5276 u32 tx_ctrl, mgmt_sema;
5277
5278 for (i = 0; i < 10; i++) {
5279 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5280 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5281 break;
5282 msleep(500);
5283 }
5284
5285 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5286 return 0;
5287
5288 for (i = 0; i < 2; i++) {
5289 tx_ctrl = readl(base + NvRegTransmitterControl);
5290 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5291 writel(tx_ctrl, base + NvRegTransmitterControl);
5292
5293 /* verify that semaphore was acquired */
5294 tx_ctrl = readl(base + NvRegTransmitterControl);
5295 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005296 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5297 np->mgmt_sema = 1;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005298 return 1;
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005299 }
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005300 else
5301 udelay(50);
5302 }
5303
5304 return 0;
5305}
5306
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005307static void nv_mgmt_release_sema(struct net_device *dev)
5308{
5309 struct fe_priv *np = netdev_priv(dev);
5310 u8 __iomem *base = get_hwbase(dev);
5311 u32 tx_ctrl;
5312
5313 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5314 if (np->mgmt_sema) {
5315 tx_ctrl = readl(base + NvRegTransmitterControl);
5316 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5317 writel(tx_ctrl, base + NvRegTransmitterControl);
5318 }
5319 }
5320}
5321
5322
5323static int nv_mgmt_get_version(struct net_device *dev)
5324{
5325 struct fe_priv *np = netdev_priv(dev);
5326 u8 __iomem *base = get_hwbase(dev);
5327 u32 data_ready = readl(base + NvRegTransmitterControl);
5328 u32 data_ready2 = 0;
5329 unsigned long start;
5330 int ready = 0;
5331
5332 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5333 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5334 start = jiffies;
5335 while (time_before(jiffies, start + 5*HZ)) {
5336 data_ready2 = readl(base + NvRegTransmitterControl);
5337 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5338 ready = 1;
5339 break;
5340 }
5341 schedule_timeout_uninterruptible(1);
5342 }
5343
5344 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5345 return 0;
5346
5347 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5348
5349 return 1;
5350}
5351
Linus Torvalds1da177e2005-04-16 15:20:36 -07005352static int nv_open(struct net_device *dev)
5353{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005354 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005355 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005356 int ret = 1;
5357 int oom, i;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005358 u32 low;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005359
5360 dprintk(KERN_DEBUG "nv_open: begin\n");
5361
Ed Swierkcb52deb2008-12-01 12:24:43 +00005362 /* power up phy */
5363 mii_rw(dev, np->phyaddr, MII_BMCR,
5364 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5365
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005366 nv_txrx_gate(dev, false);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005367 /* erase previous misconfiguration */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005368 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5369 nv_mac_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005370 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5371 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005372 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5373 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005374 writel(0, base + NvRegPacketFilterFlags);
5375
5376 writel(0, base + NvRegTransmitterControl);
5377 writel(0, base + NvRegReceiverControl);
5378
5379 writel(0, base + NvRegAdapterControl);
5380
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005381 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5382 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5383
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005384 /* initialize descriptor rings */
Manfred Sprauld81c0982005-07-31 18:20:30 +02005385 set_bufsize(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005386 oom = nv_init_ring(dev);
5387
5388 writel(0, base + NvRegLinkSpeed);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005389 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005390 nv_txrx_reset(dev);
5391 writel(0, base + NvRegUnknownSetupReg6);
5392
5393 np->in_shutdown = 0;
5394
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005395 /* give hw rings */
Ayaz Abdulla0832b252006-02-04 13:13:26 -05005396 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005397 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Linus Torvalds1da177e2005-04-16 15:20:36 -07005398 base + NvRegRingSizes);
5399
Linus Torvalds1da177e2005-04-16 15:20:36 -07005400 writel(np->linkspeed, base + NvRegLinkSpeed);
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04005401 if (np->desc_ver == DESC_VER_1)
5402 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5403 else
5404 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005405 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005406 writel(np->vlanctl_bits, base + NvRegVlanControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005407 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005408 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005409 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5410 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5411 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5412
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005413 writel(0, base + NvRegMIIMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005414 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005415 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005416
Linus Torvalds1da177e2005-04-16 15:20:36 -07005417 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5418 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5419 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
Manfred Sprauld81c0982005-07-31 18:20:30 +02005420 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005421
5422 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005423
5424 get_random_bytes(&low, sizeof(low));
5425 low &= NVREG_SLOTTIME_MASK;
5426 if (np->desc_ver == DESC_VER_1) {
5427 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5428 } else {
5429 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5430 /* setup legacy backoff */
5431 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5432 } else {
5433 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5434 nv_gear_backoff_reseed(dev);
5435 }
5436 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04005437 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5438 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005439 if (poll_interval == -1) {
5440 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5441 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5442 else
5443 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5444 }
5445 else
5446 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005447 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5448 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5449 base + NvRegAdapterControl);
5450 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005451 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04005452 if (np->wolenabled)
5453 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005454
5455 i = readl(base + NvRegPowerState);
5456 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5457 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5458
5459 pci_push(base);
5460 udelay(10);
5461 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5462
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005463 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005464 pci_push(base);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005465 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005466 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5467 pci_push(base);
5468
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005469 if (nv_request_irq(dev, 0)) {
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005470 goto out_drain;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005471 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005472
5473 /* ask for interrupts */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005474 nv_enable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005475
5476 spin_lock_irq(&np->lock);
5477 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5478 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005479 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5480 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005481 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5482 /* One manual link speed update: Interrupts are enabled, future link
5483 * speed changes cause interrupts and are handled by nv_link_irq().
5484 */
5485 {
5486 u32 miistat;
5487 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005488 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005489 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5490 }
Manfred Spraul1b1b3c92005-08-06 23:47:55 +02005491 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5492 * to init hw */
5493 np->linkspeed = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005494 ret = nv_update_linkspeed(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005495 nv_start_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005496 netif_start_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005497 nv_napi_enable(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005498
Linus Torvalds1da177e2005-04-16 15:20:36 -07005499 if (ret) {
5500 netif_carrier_on(dev);
5501 } else {
Ed Swierkf7ab6972007-09-28 22:42:13 -07005502 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005503 netif_carrier_off(dev);
5504 }
5505 if (oom)
5506 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005507
5508 /* start statistics timer */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005509 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Daniel Drakebfebbb82008-03-18 11:07:18 +00005510 mod_timer(&np->stats_poll,
5511 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005512
Linus Torvalds1da177e2005-04-16 15:20:36 -07005513 spin_unlock_irq(&np->lock);
5514
5515 return 0;
5516out_drain:
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005517 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005518 return ret;
5519}
5520
5521static int nv_close(struct net_device *dev)
5522{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005523 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005524 u8 __iomem *base;
5525
5526 spin_lock_irq(&np->lock);
5527 np->in_shutdown = 1;
5528 spin_unlock_irq(&np->lock);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005529 nv_napi_disable(dev);
Manfred Spraula7475902007-10-17 21:52:33 +02005530 synchronize_irq(np->pci_dev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005531
5532 del_timer_sync(&np->oom_kick);
5533 del_timer_sync(&np->nic_poll);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005534 del_timer_sync(&np->stats_poll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005535
5536 netif_stop_queue(dev);
5537 spin_lock_irq(&np->lock);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005538 nv_stop_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005539 nv_txrx_reset(dev);
5540
5541 /* disable interrupts on the nic or we will lock up */
5542 base = get_hwbase(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005543 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005544 pci_push(base);
5545 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5546
5547 spin_unlock_irq(&np->lock);
5548
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005549 nv_free_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005550
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005551 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005552
Ed Swierk5a9a8e32009-06-02 00:19:52 -07005553 if (np->wolenabled || !phy_power_down) {
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005554 nv_txrx_gate(dev, false);
Tim Mann2cc49a52007-06-14 13:16:38 -07005555 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005556 nv_start_rx(dev);
Ed Swierkcb52deb2008-12-01 12:24:43 +00005557 } else {
5558 /* power down phy */
5559 mii_rw(dev, np->phyaddr, MII_BMCR,
5560 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005561 nv_txrx_gate(dev, true);
Tim Mann2cc49a52007-06-14 13:16:38 -07005562 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005563
5564 /* FIXME: power down nic */
5565
5566 return 0;
5567}
5568
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005569static const struct net_device_ops nv_netdev_ops = {
5570 .ndo_open = nv_open,
5571 .ndo_stop = nv_close,
5572 .ndo_get_stats = nv_get_stats,
Stephen Hemminger00829822008-11-20 20:14:53 -08005573 .ndo_start_xmit = nv_start_xmit,
5574 .ndo_tx_timeout = nv_tx_timeout,
5575 .ndo_change_mtu = nv_change_mtu,
5576 .ndo_validate_addr = eth_validate_addr,
5577 .ndo_set_mac_address = nv_set_mac_address,
5578 .ndo_set_multicast_list = nv_set_multicast,
5579 .ndo_vlan_rx_register = nv_vlan_rx_register,
5580#ifdef CONFIG_NET_POLL_CONTROLLER
5581 .ndo_poll_controller = nv_poll_controller,
5582#endif
5583};
5584
5585static const struct net_device_ops nv_netdev_ops_optimized = {
5586 .ndo_open = nv_open,
5587 .ndo_stop = nv_close,
5588 .ndo_get_stats = nv_get_stats,
5589 .ndo_start_xmit = nv_start_xmit_optimized,
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005590 .ndo_tx_timeout = nv_tx_timeout,
5591 .ndo_change_mtu = nv_change_mtu,
5592 .ndo_validate_addr = eth_validate_addr,
5593 .ndo_set_mac_address = nv_set_mac_address,
5594 .ndo_set_multicast_list = nv_set_multicast,
5595 .ndo_vlan_rx_register = nv_vlan_rx_register,
5596#ifdef CONFIG_NET_POLL_CONTROLLER
5597 .ndo_poll_controller = nv_poll_controller,
5598#endif
5599};
5600
Linus Torvalds1da177e2005-04-16 15:20:36 -07005601static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5602{
5603 struct net_device *dev;
5604 struct fe_priv *np;
5605 unsigned long addr;
5606 u8 __iomem *base;
5607 int err, i;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005608 u32 powerstate, txreg;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005609 u32 phystate_orig = 0, phystate;
5610 int phyinitialized = 0;
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005611 static int printed_version;
5612
5613 if (!printed_version++)
5614 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5615 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005616
5617 dev = alloc_etherdev(sizeof(struct fe_priv));
5618 err = -ENOMEM;
5619 if (!dev)
5620 goto out;
5621
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005622 np = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005623 np->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005624 np->pci_dev = pci_dev;
5625 spin_lock_init(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005626 SET_NETDEV_DEV(dev, &pci_dev->dev);
5627
5628 init_timer(&np->oom_kick);
5629 np->oom_kick.data = (unsigned long) dev;
5630 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
5631 init_timer(&np->nic_poll);
5632 np->nic_poll.data = (unsigned long) dev;
5633 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005634 init_timer(&np->stats_poll);
5635 np->stats_poll.data = (unsigned long) dev;
5636 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005637
5638 err = pci_enable_device(pci_dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005639 if (err)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005640 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005641
5642 pci_set_master(pci_dev);
5643
5644 err = pci_request_regions(pci_dev, DRV_NAME);
5645 if (err < 0)
5646 goto out_disable;
5647
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005648 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005649 np->register_size = NV_PCI_REGSZ_VER3;
5650 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005651 np->register_size = NV_PCI_REGSZ_VER2;
5652 else
5653 np->register_size = NV_PCI_REGSZ_VER1;
5654
Linus Torvalds1da177e2005-04-16 15:20:36 -07005655 err = -EINVAL;
5656 addr = 0;
5657 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5658 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5659 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5660 pci_resource_len(pci_dev, i),
5661 pci_resource_flags(pci_dev, i));
5662 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005663 pci_resource_len(pci_dev, i) >= np->register_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005664 addr = pci_resource_start(pci_dev, i);
5665 break;
5666 }
5667 }
5668 if (i == DEVICE_COUNT_RESOURCE) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005669 dev_printk(KERN_INFO, &pci_dev->dev,
5670 "Couldn't find register window\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005671 goto out_relreg;
5672 }
5673
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005674 /* copy of driver data */
5675 np->driver_data = id->driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005676 /* copy of device id */
5677 np->device_id = id->device;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005678
Linus Torvalds1da177e2005-04-16 15:20:36 -07005679 /* handle different descriptor versions */
Manfred Spraulee733622005-07-31 18:32:26 +02005680 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5681 /* packet format 3: supports 40-bit addressing */
5682 np->desc_ver = DESC_VER_3;
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005683 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005684 if (dma_64bit) {
Yang Hongyang6afd1422009-04-06 19:01:15 -07005685 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005686 dev_printk(KERN_INFO, &pci_dev->dev,
5687 "64-bit DMA failed, using 32-bit addressing\n");
5688 else
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005689 dev->features |= NETIF_F_HIGHDMA;
Yang Hongyang6afd1422009-04-06 19:01:15 -07005690 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005691 dev_printk(KERN_INFO, &pci_dev->dev,
5692 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005693 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005694 }
Manfred Spraulee733622005-07-31 18:32:26 +02005695 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5696 /* packet format 2: supports jumbo frames */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005697 np->desc_ver = DESC_VER_2;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005698 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
Manfred Spraulee733622005-07-31 18:32:26 +02005699 } else {
5700 /* original packet format */
5701 np->desc_ver = DESC_VER_1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005702 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
Manfred Sprauld81c0982005-07-31 18:20:30 +02005703 }
Manfred Spraulee733622005-07-31 18:32:26 +02005704
5705 np->pkt_limit = NV_PKTLIMIT_1;
5706 if (id->driver_data & DEV_HAS_LARGEDESC)
5707 np->pkt_limit = NV_PKTLIMIT_2;
5708
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005709 if (id->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04005710 np->rx_csum = 1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005711 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdullaedcfe5f2008-08-20 16:34:37 -07005712 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Ayaz Abdullafa454592006-01-05 22:45:45 -08005713 dev->features |= NETIF_F_TSO;
Ayaz Abdulla21828162007-01-23 12:27:21 -05005714 }
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005715
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005716 np->vlanctl_bits = 0;
5717 if (id->driver_data & DEV_HAS_VLAN) {
5718 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5719 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005720 }
5721
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005722 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005723 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5724 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5725 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005726 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005727 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005728
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005729
Linus Torvalds1da177e2005-04-16 15:20:36 -07005730 err = -ENOMEM;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005731 np->base = ioremap(addr, np->register_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005732 if (!np->base)
5733 goto out_relreg;
5734 dev->base_addr = (unsigned long)np->base;
Manfred Spraulee733622005-07-31 18:32:26 +02005735
Linus Torvalds1da177e2005-04-16 15:20:36 -07005736 dev->irq = pci_dev->irq;
Manfred Spraulee733622005-07-31 18:32:26 +02005737
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005738 np->rx_ring_size = RX_RING_DEFAULT;
5739 np->tx_ring_size = TX_RING_DEFAULT;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005740
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005741 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02005742 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005743 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005744 &np->ring_addr);
5745 if (!np->rx_ring.orig)
5746 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005747 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005748 } else {
5749 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005750 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005751 &np->ring_addr);
5752 if (!np->rx_ring.ex)
5753 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005754 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005755 }
Yoann Padioleaudd00cc42007-07-19 01:49:03 -07005756 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5757 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05005758 if (!np->rx_skb || !np->tx_skb)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005759 goto out_freering;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005760
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005761 if (!nv_optimized(np))
Stephen Hemminger00829822008-11-20 20:14:53 -08005762 dev->netdev_ops = &nv_netdev_ops;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05005763 else
Stephen Hemminger00829822008-11-20 20:14:53 -08005764 dev->netdev_ops = &nv_netdev_ops_optimized;
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005765
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005766#ifdef CONFIG_FORCEDETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005767 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005768#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07005769 SET_ETHTOOL_OPS(dev, &ops);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005770 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5771
5772 pci_set_drvdata(pci_dev, dev);
5773
5774 /* read the mac address */
5775 base = get_hwbase(dev);
5776 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5777 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5778
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005779 /* check the workaround bit for correct mac address order */
5780 txreg = readl(base + NvRegTransmitPoll);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005781 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005782 /* mac address is already in correct order */
5783 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5784 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5785 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5786 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5787 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5788 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005789 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5790 /* mac address is already in correct order */
5791 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5792 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5793 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5794 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5795 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5796 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5797 /*
5798 * Set orig mac address back to the reversed version.
5799 * This flag will be cleared during low power transition.
5800 * Therefore, we should always put back the reversed address.
5801 */
5802 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5803 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5804 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005805 } else {
5806 /* need to reverse mac address to correct order */
5807 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5808 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5809 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5810 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5811 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5812 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005813 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005814 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005815 }
John W. Linvillec704b852005-09-12 10:48:56 -04005816 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005817
John W. Linvillec704b852005-09-12 10:48:56 -04005818 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005819 /*
5820 * Bad mac address. At least one bios sets the mac address
5821 * to 01:23:45:67:89:ab
5822 */
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005823 dev_printk(KERN_ERR, &pci_dev->dev,
Johannes Berge1749612008-10-27 15:59:26 -07005824 "Invalid Mac address detected: %pM\n",
5825 dev->dev_addr);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005826 dev_printk(KERN_ERR, &pci_dev->dev,
5827 "Please complain to your hardware vendor. Switching to a random MAC.\n");
Stanislav O. Bezzubtsev655a6592009-11-15 21:17:02 -08005828 random_ether_addr(dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005829 }
5830
Johannes Berge1749612008-10-27 15:59:26 -07005831 dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5832 pci_name(pci_dev), dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005833
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005834 /* set mac address */
5835 nv_copy_mac_to_hw(dev);
5836
Tobias Diedrich9a60a822008-06-01 00:54:42 +02005837 /* Workaround current PCI init glitch: wakeup bits aren't
5838 * being set from PCI PM capability.
5839 */
5840 device_init_wakeup(&pci_dev->dev, 1);
5841
Linus Torvalds1da177e2005-04-16 15:20:36 -07005842 /* disable WOL */
5843 writel(0, base + NvRegWakeUpFlags);
5844 np->wolenabled = 0;
5845
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005846 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005847
5848 /* take phy and nic out of low power mode */
5849 powerstate = readl(base + NvRegPowerState2);
5850 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005851 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
Auke Kok44c10132007-06-08 15:46:36 -07005852 pci_dev->revision >= 0xA3)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005853 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5854 writel(powerstate, base + NvRegPowerState2);
5855 }
5856
Linus Torvalds1da177e2005-04-16 15:20:36 -07005857 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005858 np->tx_flags = NV_TX_VALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005859 } else {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005860 np->tx_flags = NV_TX2_VALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005861 }
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005862
5863 np->msi_flags = 0;
5864 if ((id->driver_data & DEV_HAS_MSI) && msi) {
5865 np->msi_flags |= NV_MSI_CAPABLE;
5866 }
5867 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5868 /* msix has had reported issues when modifying irqmask
5869 as in the case of napi, therefore, disable for now
5870 */
5871#ifndef CONFIG_FORCEDETH_NAPI
5872 np->msi_flags |= NV_MSI_X_CAPABLE;
5873#endif
5874 }
5875
5876 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005877 np->irqmask = NVREG_IRQMASK_CPU;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005878 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5879 np->msi_flags |= 0x0001;
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005880 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5881 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5882 /* start off in throughput mode */
5883 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5884 /* remove support for msix mode */
5885 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5886 } else {
5887 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5888 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5889 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5890 np->msi_flags |= 0x0003;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005891 }
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005892
Linus Torvalds1da177e2005-04-16 15:20:36 -07005893 if (id->driver_data & DEV_NEED_TIMERIRQ)
5894 np->irqmask |= NVREG_IRQ_TIMER;
5895 if (id->driver_data & DEV_NEED_LINKTIMER) {
5896 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5897 np->need_linktimer = 1;
5898 np->link_timeout = jiffies + LINK_TIMEOUT;
5899 } else {
5900 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5901 np->need_linktimer = 0;
5902 }
5903
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005904 /* Limit the number of tx's outstanding for hw bug */
5905 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5906 np->tx_limit = 1;
Ayaz Abdulla5c659322010-04-13 18:49:51 -07005907 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005908 pci_dev->revision >= 0xA2)
5909 np->tx_limit = 0;
5910 }
5911
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005912 /* clear phy state and temporarily halt phy interrupts */
5913 writel(0, base + NvRegMIIMask);
5914 phystate = readl(base + NvRegAdapterControl);
5915 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5916 phystate_orig = 1;
5917 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5918 writel(phystate, base + NvRegAdapterControl);
5919 }
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005920 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005921
5922 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005923 /* management unit running on the mac? */
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005924 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5925 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5926 nv_mgmt_acquire_sema(dev) &&
5927 nv_mgmt_get_version(dev)) {
5928 np->mac_in_use = 1;
5929 if (np->mgmt_version > 0) {
5930 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5931 }
5932 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5933 pci_name(pci_dev), np->mac_in_use);
5934 /* management unit setup the phy already? */
5935 if (np->mac_in_use &&
5936 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5937 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5938 /* phy is inited by mgmt unit */
5939 phyinitialized = 1;
5940 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5941 pci_name(pci_dev));
5942 } else {
5943 /* we need to init the phy */
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005944 }
5945 }
5946 }
5947
Linus Torvalds1da177e2005-04-16 15:20:36 -07005948 /* find a suitable phy */
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005949 for (i = 1; i <= 32; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005950 int id1, id2;
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005951 int phyaddr = i & 0x1F;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005952
5953 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005954 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005955 spin_unlock_irq(&np->lock);
5956 if (id1 < 0 || id1 == 0xffff)
5957 continue;
5958 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005959 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005960 spin_unlock_irq(&np->lock);
5961 if (id2 < 0 || id2 == 0xffff)
5962 continue;
5963
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04005964 np->phy_model = id2 & PHYID2_MODEL_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005965 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5966 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5967 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005968 pci_name(pci_dev), id1, id2, phyaddr);
5969 np->phyaddr = phyaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005970 np->phy_oui = id1 | id2;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005971
5972 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5973 if (np->phy_oui == PHY_OUI_REALTEK2)
5974 np->phy_oui = PHY_OUI_REALTEK;
5975 /* Setup phy revision for Realtek */
5976 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5977 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5978
Linus Torvalds1da177e2005-04-16 15:20:36 -07005979 break;
5980 }
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005981 if (i == 33) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005982 dev_printk(KERN_INFO, &pci_dev->dev,
5983 "open: Could not find a valid PHY.\n");
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005984 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005985 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005986
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005987 if (!phyinitialized) {
5988 /* reset it */
5989 phy_init(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005990 } else {
5991 /* see if it is a gigabit phy */
5992 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5993 if (mii_status & PHY_GIGABIT) {
5994 np->gigabit = PHY_GIGABIT;
5995 }
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005996 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005997
5998 /* set default link speed settings */
5999 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
6000 np->duplex = 0;
6001 np->autoneg = 1;
6002
6003 err = register_netdev(dev);
6004 if (err) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04006005 dev_printk(KERN_INFO, &pci_dev->dev,
6006 "unable to register netdev: %d\n", err);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04006007 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006008 }
Jeff Garzik3f88ce42007-10-16 04:09:09 -04006009
6010 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
6011 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
6012 dev->name,
6013 np->phy_oui,
6014 np->phyaddr,
6015 dev->dev_addr[0],
6016 dev->dev_addr[1],
6017 dev->dev_addr[2],
6018 dev->dev_addr[3],
6019 dev->dev_addr[4],
6020 dev->dev_addr[5]);
6021
6022 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6023 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
Ayaz Abdullaedcfe5f2008-08-20 16:34:37 -07006024 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
Jeff Garzik3f88ce42007-10-16 04:09:09 -04006025 "csum " : "",
6026 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
6027 "vlan " : "",
6028 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6029 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6030 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6031 np->gigabit == PHY_GIGABIT ? "gbit " : "",
6032 np->need_linktimer ? "lnktim " : "",
6033 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6034 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6035 np->desc_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006036
6037 return 0;
6038
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04006039out_error:
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05006040 if (phystate_orig)
6041 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006042 pci_set_drvdata(pci_dev, NULL);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04006043out_freering:
6044 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006045out_unmap:
6046 iounmap(get_hwbase(dev));
6047out_relreg:
6048 pci_release_regions(pci_dev);
6049out_disable:
6050 pci_disable_device(pci_dev);
6051out_free:
6052 free_netdev(dev);
6053out:
6054 return err;
6055}
6056
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006057static void nv_restore_phy(struct net_device *dev)
6058{
6059 struct fe_priv *np = netdev_priv(dev);
6060 u16 phy_reserved, mii_control;
6061
6062 if (np->phy_oui == PHY_OUI_REALTEK &&
6063 np->phy_model == PHY_MODEL_REALTEK_8201 &&
6064 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6065 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6066 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6067 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6068 phy_reserved |= PHY_REALTEK_INIT8;
6069 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6070 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6071
6072 /* restart auto negotiation */
6073 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6074 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6075 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6076 }
6077}
6078
Yinghai Luf55c21f2008-09-13 13:10:31 -07006079static void nv_restore_mac_addr(struct pci_dev *pci_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006080{
6081 struct net_device *dev = pci_get_drvdata(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04006082 struct fe_priv *np = netdev_priv(dev);
6083 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006084
Ayaz Abdullaf1489652006-07-31 12:04:45 -04006085 /* special op: write back the misordered MAC address - otherwise
6086 * the next nv_probe would see a wrong address.
6087 */
6088 writel(np->orig_mac[0], base + NvRegMacAddrA);
6089 writel(np->orig_mac[1], base + NvRegMacAddrB);
Björn Steinbrink2e3884b2008-01-07 23:22:53 -08006090 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6091 base + NvRegTransmitPoll);
Yinghai Luf55c21f2008-09-13 13:10:31 -07006092}
6093
6094static void __devexit nv_remove(struct pci_dev *pci_dev)
6095{
6096 struct net_device *dev = pci_get_drvdata(pci_dev);
6097
6098 unregister_netdev(dev);
6099
6100 nv_restore_mac_addr(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04006101
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006102 /* restore any phy related changes */
6103 nv_restore_phy(dev);
6104
Ayaz Abdullacac1c522009-02-07 00:23:57 -08006105 nv_mgmt_release_sema(dev);
6106
Linus Torvalds1da177e2005-04-16 15:20:36 -07006107 /* free all structures */
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04006108 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006109 iounmap(get_hwbase(dev));
6110 pci_release_regions(pci_dev);
6111 pci_disable_device(pci_dev);
6112 free_netdev(dev);
6113 pci_set_drvdata(pci_dev, NULL);
6114}
6115
Francois Romieua1893172006-10-10 14:33:27 -07006116#ifdef CONFIG_PM
6117static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
6118{
6119 struct net_device *dev = pci_get_drvdata(pdev);
6120 struct fe_priv *np = netdev_priv(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006121 u8 __iomem *base = get_hwbase(dev);
6122 int i;
Francois Romieua1893172006-10-10 14:33:27 -07006123
Tobias Diedrich25d90812008-05-18 15:04:29 +02006124 if (netif_running(dev)) {
6125 // Gross.
6126 nv_close(dev);
6127 }
Francois Romieua1893172006-10-10 14:33:27 -07006128 netif_device_detach(dev);
6129
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006130 /* save non-pci configuration space */
6131 for (i = 0;i <= np->register_size/sizeof(u32); i++)
6132 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6133
Francois Romieua1893172006-10-10 14:33:27 -07006134 pci_save_state(pdev);
6135 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
Tobias Diedrich25d90812008-05-18 15:04:29 +02006136 pci_disable_device(pdev);
Francois Romieua1893172006-10-10 14:33:27 -07006137 pci_set_power_state(pdev, pci_choose_state(pdev, state));
Francois Romieua1893172006-10-10 14:33:27 -07006138 return 0;
6139}
6140
6141static int nv_resume(struct pci_dev *pdev)
6142{
6143 struct net_device *dev = pci_get_drvdata(pdev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006144 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07006145 u8 __iomem *base = get_hwbase(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006146 int i, rc = 0;
Francois Romieua1893172006-10-10 14:33:27 -07006147
Francois Romieua1893172006-10-10 14:33:27 -07006148 pci_set_power_state(pdev, PCI_D0);
6149 pci_restore_state(pdev);
Tobias Diedrich25d90812008-05-18 15:04:29 +02006150 /* ack any pending wake events, disable PME */
Francois Romieua1893172006-10-10 14:33:27 -07006151 pci_enable_wake(pdev, PCI_D0, 0);
6152
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02006153 /* restore non-pci configuration space */
6154 for (i = 0;i <= np->register_size/sizeof(u32); i++)
6155 writel(np->saved_config_space[i], base+i*sizeof(u32));
Ayaz Abdullaa376e792008-04-10 21:30:35 -07006156
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006157 if (np->driver_data & DEV_NEED_MSI_FIX)
6158 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
Ayaz Abdullab6e44052009-02-07 00:24:15 -08006159
Ed Swierk35a74332009-04-06 17:49:12 -07006160 /* restore phy state, including autoneg */
6161 phy_init(dev);
6162
Tobias Diedrich25d90812008-05-18 15:04:29 +02006163 netif_device_attach(dev);
6164 if (netif_running(dev)) {
6165 rc = nv_open(dev);
6166 nv_set_multicast(dev);
6167 }
Francois Romieua1893172006-10-10 14:33:27 -07006168 return rc;
6169}
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006170
6171static void nv_shutdown(struct pci_dev *pdev)
6172{
6173 struct net_device *dev = pci_get_drvdata(pdev);
6174 struct fe_priv *np = netdev_priv(dev);
6175
6176 if (netif_running(dev))
6177 nv_close(dev);
6178
Tobias Diedrich34edaa82009-02-16 00:13:20 -08006179 /*
6180 * Restore the MAC so a kernel started by kexec won't get confused.
6181 * If we really go for poweroff, we must not restore the MAC,
6182 * otherwise the MAC for WOL will be reversed at least on some boards.
6183 */
6184 if (system_state != SYSTEM_POWER_OFF) {
6185 nv_restore_mac_addr(pdev);
6186 }
Yinghai Luf55c21f2008-09-13 13:10:31 -07006187
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006188 pci_disable_device(pdev);
Tobias Diedrich34edaa82009-02-16 00:13:20 -08006189 /*
6190 * Apparently it is not possible to reinitialise from D3 hot,
6191 * only put the device into D3 if we really go for poweroff.
6192 */
Rafael J. Wysocki3cb55992008-09-05 14:00:19 -07006193 if (system_state == SYSTEM_POWER_OFF) {
6194 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6195 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6196 pci_set_power_state(pdev, PCI_D3hot);
6197 }
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006198}
Francois Romieua1893172006-10-10 14:33:27 -07006199#else
6200#define nv_suspend NULL
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006201#define nv_shutdown NULL
Francois Romieua1893172006-10-10 14:33:27 -07006202#define nv_resume NULL
6203#endif /* CONFIG_PM */
6204
Alexey Dobriyana3aa1882010-01-07 11:58:11 +00006205static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07006206 { /* nForce Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006207 PCI_DEVICE(0x10DE, 0x01C3),
Manfred Spraulc2dba062005-07-31 18:29:47 +02006208 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006209 },
6210 { /* nForce2 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006211 PCI_DEVICE(0x10DE, 0x0066),
Manfred Spraulc2dba062005-07-31 18:29:47 +02006212 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006213 },
6214 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006215 PCI_DEVICE(0x10DE, 0x00D6),
Manfred Spraulc2dba062005-07-31 18:29:47 +02006216 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006217 },
6218 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006219 PCI_DEVICE(0x10DE, 0x0086),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006220 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006221 },
6222 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006223 PCI_DEVICE(0x10DE, 0x008C),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006224 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006225 },
6226 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006227 PCI_DEVICE(0x10DE, 0x00E6),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006228 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006229 },
6230 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006231 PCI_DEVICE(0x10DE, 0x00DF),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006232 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006233 },
6234 { /* CK804 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006235 PCI_DEVICE(0x10DE, 0x0056),
Yinghai Lu033e97b2009-02-06 01:30:56 -08006236 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006237 },
6238 { /* CK804 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006239 PCI_DEVICE(0x10DE, 0x0057),
Yinghai Lu033e97b2009-02-06 01:30:56 -08006240 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006241 },
6242 { /* MCP04 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006243 PCI_DEVICE(0x10DE, 0x0037),
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006244 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006245 },
6246 { /* MCP04 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006247 PCI_DEVICE(0x10DE, 0x0038),
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006248 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006249 },
6250 { /* MCP51 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006251 PCI_DEVICE(0x10DE, 0x0268),
6252 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006253 },
Manfred Spraul9992d4a2005-06-05 17:36:11 +02006254 { /* MCP51 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006255 PCI_DEVICE(0x10DE, 0x0269),
6256 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02006257 },
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006258 { /* MCP55 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006259 PCI_DEVICE(0x10DE, 0x0372),
6260 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006261 },
6262 { /* MCP55 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006263 PCI_DEVICE(0x10DE, 0x0373),
6264 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006265 },
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006266 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006267 PCI_DEVICE(0x10DE, 0x03E5),
6268 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006269 },
6270 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006271 PCI_DEVICE(0x10DE, 0x03E6),
6272 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006273 },
6274 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006275 PCI_DEVICE(0x10DE, 0x03EE),
6276 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006277 },
6278 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006279 PCI_DEVICE(0x10DE, 0x03EF),
6280 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006281 },
6282 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006283 PCI_DEVICE(0x10DE, 0x0450),
6284 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006285 },
6286 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006287 PCI_DEVICE(0x10DE, 0x0451),
6288 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006289 },
6290 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006291 PCI_DEVICE(0x10DE, 0x0452),
6292 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006293 },
6294 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006295 PCI_DEVICE(0x10DE, 0x0453),
6296 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006297 },
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006298 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006299 PCI_DEVICE(0x10DE, 0x054C),
6300 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006301 },
6302 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006303 PCI_DEVICE(0x10DE, 0x054D),
6304 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006305 },
6306 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006307 PCI_DEVICE(0x10DE, 0x054E),
6308 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006309 },
6310 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006311 PCI_DEVICE(0x10DE, 0x054F),
6312 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006313 },
Ayaz Abdulla13986612007-07-22 20:43:26 -04006314 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006315 PCI_DEVICE(0x10DE, 0x07DC),
6316 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006317 },
6318 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006319 PCI_DEVICE(0x10DE, 0x07DD),
6320 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006321 },
6322 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006323 PCI_DEVICE(0x10DE, 0x07DE),
6324 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006325 },
6326 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006327 PCI_DEVICE(0x10DE, 0x07DF),
6328 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006329 },
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006330 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006331 PCI_DEVICE(0x10DE, 0x0760),
6332 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006333 },
6334 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006335 PCI_DEVICE(0x10DE, 0x0761),
6336 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006337 },
6338 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006339 PCI_DEVICE(0x10DE, 0x0762),
6340 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006341 },
6342 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006343 PCI_DEVICE(0x10DE, 0x0763),
6344 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006345 },
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006346 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006347 PCI_DEVICE(0x10DE, 0x0AB0),
6348 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006349 },
6350 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006351 PCI_DEVICE(0x10DE, 0x0AB1),
6352 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006353 },
6354 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006355 PCI_DEVICE(0x10DE, 0x0AB2),
6356 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006357 },
6358 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006359 PCI_DEVICE(0x10DE, 0x0AB3),
6360 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006361 },
Ayaz Abdulla3df81c42009-06-03 15:05:35 +00006362 { /* MCP89 Ethernet Controller */
6363 PCI_DEVICE(0x10DE, 0x0D7D),
6364 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6365 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07006366 {0,},
6367};
6368
6369static struct pci_driver driver = {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04006370 .name = DRV_NAME,
6371 .id_table = pci_tbl,
6372 .probe = nv_probe,
6373 .remove = __devexit_p(nv_remove),
6374 .suspend = nv_suspend,
6375 .resume = nv_resume,
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006376 .shutdown = nv_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006377};
6378
Linus Torvalds1da177e2005-04-16 15:20:36 -07006379static int __init init_nic(void)
6380{
Jeff Garzik29917622006-08-19 17:48:59 -04006381 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006382}
6383
6384static void __exit exit_nic(void)
6385{
6386 pci_unregister_driver(&driver);
6387}
6388
6389module_param(max_interrupt_work, int, 0);
6390MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05006391module_param(optimization_mode, int, 0);
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006392MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05006393module_param(poll_interval, int, 0);
6394MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04006395module_param(msi, int, 0);
6396MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6397module_param(msix, int, 0);
6398MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6399module_param(dma_64bit, int, 0);
6400MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006401module_param(phy_cross, int, 0);
6402MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
Ed Swierk5a9a8e32009-06-02 00:19:52 -07006403module_param(phy_power_down, int, 0);
6404MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
Linus Torvalds1da177e2005-04-16 15:20:36 -07006405
6406MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6407MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6408MODULE_LICENSE("GPL");
6409
6410MODULE_DEVICE_TABLE(pci, pci_tbl);
6411
6412module_init(init_nic);
6413module_exit(exit_nic);