blob: 7d388d5cf54852136da06d0ca08b04c646fc7199 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
3 */
4
Jesse Barnesf8977d02005-10-25 10:28:42 -07005#include <linux/delay.h>
6#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#include <linux/pci.h>
8#include <linux/init.h>
Jaswinder Singh Rajput82487712008-12-27 18:32:28 +05309#include <asm/pci_x86.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070010
11static void __devinit pci_fixup_i450nx(struct pci_dev *d)
12{
13 /*
14 * i450NX -- Find and scan all secondary buses on all PXB's.
15 */
16 int pxb, reg;
17 u8 busno, suba, subb;
18
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070019 dev_warn(&d->dev, "Searching for i450NX host bridges\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 reg = 0xd0;
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +010021 for(pxb = 0; pxb < 2; pxb++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070022 pci_read_config_byte(d, reg++, &busno);
23 pci_read_config_byte(d, reg++, &suba);
24 pci_read_config_byte(d, reg++, &subb);
Bjorn Helgaas12c0b202008-07-23 17:00:13 -060025 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
26 suba, subb);
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 if (busno)
Muli Ben-Yehuda73c59af2007-08-10 13:01:19 -070028 pci_scan_bus_with_sysdata(busno); /* Bus A */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 if (suba < subb)
Muli Ben-Yehuda73c59af2007-08-10 13:01:19 -070030 pci_scan_bus_with_sysdata(suba+1); /* Bus B */
Linus Torvalds1da177e2005-04-16 15:20:36 -070031 }
32 pcibios_last_bus = -1;
33}
34DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
35
36static void __devinit pci_fixup_i450gx(struct pci_dev *d)
37{
38 /*
39 * i450GX and i450KX -- Find and scan all secondary buses.
40 * (called separately for each PCI bridge found)
41 */
42 u8 busno;
43 pci_read_config_byte(d, 0x4a, &busno);
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070044 dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
Muli Ben-Yehuda73c59af2007-08-10 13:01:19 -070045 pci_scan_bus_with_sysdata(busno);
Linus Torvalds1da177e2005-04-16 15:20:36 -070046 pcibios_last_bus = -1;
47}
48DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
49
50static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
51{
52 /*
53 * UM8886BF IDE controller sets region type bits incorrectly,
54 * therefore they look like memory despite of them being I/O.
55 */
56 int i;
57
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070058 dev_warn(&d->dev, "Fixing base address flags\n");
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +010059 for(i = 0; i < 4; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -070060 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
61}
62DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
63
64static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
65{
66 /*
67 * NCR 53C810 returns class code 0 (at least on some systems).
68 * Fix class to be PCI_CLASS_STORAGE_SCSI
69 */
70 if (!d->class) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070071 dev_warn(&d->dev, "Fixing NCR 53C810 class code\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 d->class = PCI_CLASS_STORAGE_SCSI << 8;
73 }
74}
75DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
76
Linus Torvalds1da177e2005-04-16 15:20:36 -070077static void __devinit pci_fixup_latency(struct pci_dev *d)
78{
79 /*
80 * SiS 5597 and 5598 chipsets require latency timer set to
81 * at most 32 to avoid lockups.
82 */
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070083 dev_dbg(&d->dev, "Setting max latency to 32\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 pcibios_max_latency = 32;
85}
86DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
87DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
88
89static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
90{
91 /*
92 * PIIX4 ACPI device: hardwired IRQ9
93 */
94 d->irq = 9;
95}
96DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
97
98/*
99 * Addresses issues with problems in the memory write queue timer in
100 * certain VIA Northbridges. This bugfix is per VIA's specifications,
101 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
102 * to trigger a bug in its integrated ProSavage video card, which
103 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
104 * until VIA can provide us with definitive information on why screen
105 * corruption occurs, and what exactly those bits do.
106 *
107 * VIA 8363,8622,8361 Northbridges:
108 * - bits 5, 6, 7 at offset 0x55 need to be turned off
109 * VIA 8367 (KT266x) Northbridges:
110 * - bits 5, 6, 7 at offset 0x95 need to be turned off
111 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
112 * - bits 6, 7 at offset 0x55 need to be turned off
113 */
114
115#define VIA_8363_KL133_REVISION_ID 0x81
116#define VIA_8363_KM133_REVISION_ID 0x84
117
Alan Cox1597cac2006-12-04 15:14:45 -0800118static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119{
120 u8 v;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 int where = 0x55;
122 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
123
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
125 /* fix pci bus latency issues resulted by NB bios error
126 it appears on bug free^Wreduced kt266x's bios forces
127 NB latency to zero */
128 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
129
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100130 where = 0x95; /* the memory write queue timer register is
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 different for the KT266x's: 0x95 not 0x55 */
132 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
Auke Kok44c10132007-06-08 15:46:36 -0700133 (d->revision == VIA_8363_KL133_REVISION_ID ||
134 d->revision == VIA_8363_KM133_REVISION_ID)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
136 causes screen corruption on the KL133/KM133 */
137 }
138
139 pci_read_config_byte(d, where, &v);
140 if (v & ~mask) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700141 dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
Auke Kok44c10132007-06-08 15:46:36 -0700142 d->device, d->revision, where, v, mask, v & mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 v &= mask;
144 pci_write_config_byte(d, where, v);
145 }
146}
147DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
150DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
Alan Cox1597cac2006-12-04 15:14:45 -0800151DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
152DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
153DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
154DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155
156/*
157 * For some reasons Intel decided that certain parts of their
158 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
159 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
160 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
161 * to Intel terminology. These devices do forward all addresses from
162 * system to PCI bus no matter what are their window settings, so they are
163 * "transparent" (or subtractive decoding) from programmers point of view.
164 */
165static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
166{
167 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
168 (dev->device & 0xff00) == 0x2400)
169 dev->transparent = 1;
170}
171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
172
173/*
174 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
175 *
176 * From information provided by "Allen Martin" <AMartin@nvidia.com>:
177 *
178 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
179 * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
180 * This allows the state-machine and timer to return to a proper state within
181 * 80 ns of the CONNECT and probe appearing together. Since the CPU will not
182 * issue another HALT within 80 ns of the initial HALT, the failure condition
183 * is avoided.
184 */
Alan Cox1597cac2006-12-04 15:14:45 -0800185static void pci_fixup_nforce2(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186{
187 u32 val;
188
189 /*
190 * Chip Old value New value
191 * C17 0x1F0FFF01 0x1F01FF01
192 * C18D 0x9F0FFF01 0x9F01FF01
193 *
194 * Northbridge chip version may be determined by
195 * reading the PCI revision ID (0xC1 or greater is C18D).
196 */
197 pci_read_config_dword(dev, 0x6c, &val);
198
199 /*
200 * Apply fixup if needed, but don't touch disconnect state
201 */
202 if ((val & 0x00FF0000) != 0x00010000) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700203 dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
205 }
206}
207DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
Alan Cox1597cac2006-12-04 15:14:45 -0800208DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209
210/* Max PCI Express root ports */
211#define MAX_PCIEROOT 6
212static int quirk_aspm_offset[MAX_PCIEROOT << 3];
213
Christoph Lameterff0d2f92005-05-17 08:48:16 -0700214#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215
216static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
217{
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -0500218 return raw_pci_read(pci_domain_nr(bus), bus->number,
219 devfn, where, size, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220}
221
222/*
223 * Replace the original pci bus ops for write with a new one that will filter
224 * the request to insure ASPM cannot be enabled.
225 */
226static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
227{
228 u8 offset;
229
230 offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
231
232 if ((offset) && (where == offset))
233 value = value & 0xfffffffc;
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100234
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -0500235 return raw_pci_write(pci_domain_nr(bus), bus->number,
236 devfn, where, size, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237}
238
239static struct pci_ops quirk_pcie_aspm_ops = {
240 .read = quirk_pcie_aspm_read,
241 .write = quirk_pcie_aspm_write,
242};
243
244/*
245 * Prevents PCI Express ASPM (Active State Power Management) being enabled.
246 *
247 * Save the register offset, where the ASPM control bits are located,
248 * for each PCI Express device that is in the device list of
249 * the root port in an array for fast indexing. Replace the bus ops
250 * with the modified one.
251 */
252static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
253{
254 int cap_base, i;
255 struct pci_bus *pbus;
256 struct pci_dev *dev;
257
258 if ((pbus = pdev->subordinate) == NULL)
259 return;
260
261 /*
262 * Check if the DID of pdev matches one of the six root ports. This
263 * check is needed in the case this function is called directly by the
264 * hot-plug driver.
265 */
266 if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
267 (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
268 return;
269
270 if (list_empty(&pbus->devices)) {
271 /*
272 * If no device is attached to the root port at power-up or
273 * after hot-remove, the pbus->devices is empty and this code
274 * will set the offsets to zero and the bus ops to parent's bus
275 * ops, which is unmodified.
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100276 */
277 for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 quirk_aspm_offset[i] = 0;
279
280 pbus->ops = pbus->parent->ops;
281 } else {
282 /*
283 * If devices are attached to the root port at power-up or
284 * after hot-add, the code loops through the device list of
285 * each root port to save the register offsets and replace the
286 * bus ops.
287 */
288 list_for_each_entry(dev, &pbus->devices, bus_list) {
289 /* There are 0 to 8 devices attached to this bus */
290 cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100291 quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = cap_base + 0x10;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292 }
293 pbus->ops = &quirk_pcie_aspm_ops;
294 }
295}
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100296DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk);
297DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk);
298DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk);
299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk);
300DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk);
301DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302
303/*
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900304 * Fixup to mark boot BIOS video selected by BIOS before it changes
305 *
306 * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
307 *
308 * The standard boot ROM sequence for an x86 machine uses the BIOS
309 * to select an initial video card for boot display. This boot video
310 * card will have it's BIOS copied to C0000 in system RAM.
311 * IORESOURCE_ROM_SHADOW is used to associate the boot video
312 * card with this copy. On laptops this copy has to be used since
313 * the main ROM may be compressed or combined with another image.
314 * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
315 * is marked here since the boot video device will be the only enabled
316 * video device at this point.
317 */
318
319static void __devinit pci_fixup_video(struct pci_dev *pdev)
320{
321 struct pci_dev *bridge;
322 struct pci_bus *bus;
323 u16 config;
324
325 if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
326 return;
327
328 /* Is VGA routed to us? */
329 bus = pdev->bus;
330 while (bus) {
331 bridge = bus->self;
332
333 /*
334 * From information provided by
335 * "David Miller" <davem@davemloft.net>
336 * The bridge control register is valid for PCI header
337 * type BRIDGE, or CARDBUS. Host to PCI controllers use
338 * PCI header type NORMAL.
339 */
340 if (bridge
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100341 && ((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE)
342 || (bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) {
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900343 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
344 &config);
345 if (!(config & PCI_BRIDGE_CTL_VGA))
346 return;
347 }
348 bus = bus->parent;
349 }
350 pci_read_config_word(pdev, PCI_COMMAND, &config);
351 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
352 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700353 dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900354 }
355}
Jesse Barnes40ee9e92007-03-24 11:03:32 -0700356DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900357
Johannes Goecke346ca042007-09-10 10:46:52 +0200358
359static struct dmi_system_id __devinitdata msi_k8t_dmi_table[] = {
360 {
361 .ident = "MSI-K8T-Neo2Fir",
362 .matches = {
363 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
364 DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
365 },
366 },
367 {}
368};
369
370/*
371 * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound
372 * card if a PCI-soundcard is added.
373 *
374 * The BIOS only gives options "DISABLED" and "AUTO". This code sets
375 * the corresponding register-value to enable the soundcard.
376 *
377 * The soundcard is only enabled, if the mainborad is identified
378 * via DMI-tables and the soundcard is detected to be off.
379 */
380static void __devinit pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
381{
382 unsigned char val;
383 if (!dmi_check_system(msi_k8t_dmi_table))
384 return; /* only applies to MSI K8T Neo2-FIR */
385
386 pci_read_config_byte(dev, 0x50, &val);
387 if (val & 0x40) {
388 pci_write_config_byte(dev, 0x50, val & (~0x40));
389
390 /* verify the change for status output */
391 pci_read_config_byte(dev, 0x50, &val);
392 if (val & 0x40)
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700393 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
Johannes Goecke346ca042007-09-10 10:46:52 +0200394 "can't enable onboard soundcard!\n");
395 else
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700396 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
397 "enabled onboard soundcard\n");
Johannes Goecke346ca042007-09-10 10:46:52 +0200398 }
399}
400DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
401 pci_fixup_msi_k8t_onboard_sound);
402DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
403 pci_fixup_msi_k8t_onboard_sound);
404
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900405/*
Jesse Barnesf8977d02005-10-25 10:28:42 -0700406 * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
407 *
408 * We pretend to bring them out of full D3 state, and restore the proper
409 * IRQ, PCI cache line size, and BARs, otherwise the device won't function
410 * properly. In some cases, the device will generate an interrupt on
Matt LaPlante4b3f6862006-10-03 22:21:02 +0200411 * the wrong IRQ line, causing any devices sharing the line it's
Jesse Barnesf8977d02005-10-25 10:28:42 -0700412 * *supposed* to use to be disabled by the kernel's IRQ debug code.
413 */
414static u16 toshiba_line_size;
415
Roland Dreier1d373742005-10-28 21:50:35 -0700416static struct dmi_system_id __devinitdata toshiba_ohci1394_dmi_table[] = {
Jesse Barnesf8977d02005-10-25 10:28:42 -0700417 {
418 .ident = "Toshiba PS5 based laptop",
419 .matches = {
420 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
421 DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
422 },
423 },
424 {
425 .ident = "Toshiba PSM4 based laptop",
426 .matches = {
427 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
428 DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
429 },
430 },
Jesse Barnes19272682005-12-17 09:27:50 -0800431 {
432 .ident = "Toshiba A40 based laptop",
433 .matches = {
434 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
435 DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
436 },
437 },
Jesse Barnesf8977d02005-10-25 10:28:42 -0700438 { }
439};
440
441static void __devinit pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
442{
443 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
444 return; /* only applies to certain Toshibas (so far) */
445
446 dev->current_state = PCI_D3cold;
447 pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
448}
449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
450 pci_pre_fixup_toshiba_ohci1394);
451
452static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
453{
454 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
455 return; /* only applies to certain Toshibas (so far) */
456
457 /* Restore config space on Toshiba laptops */
Jesse Barnesf8977d02005-10-25 10:28:42 -0700458 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
Jesse Barnes6e6ece52005-11-08 20:13:02 -0800459 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
Jesse Barnesf8977d02005-10-25 10:28:42 -0700460 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
461 pci_resource_start(dev, 0));
462 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
463 pci_resource_start(dev, 1));
464}
465DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
466 pci_post_fixup_toshiba_ohci1394);
David Vrabela80da732006-01-14 13:21:23 -0800467
468
469/*
470 * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
471 * configuration space.
472 */
Alan Cox1597cac2006-12-04 15:14:45 -0800473static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
David Vrabela80da732006-01-14 13:21:23 -0800474{
475 u8 r;
476 /* clear 'F4 Video Configuration Trap' bit */
477 pci_read_config_byte(dev, 0x42, &r);
478 r &= 0xfd;
479 pci_write_config_byte(dev, 0x42, r);
480}
481DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
482 pci_early_fixup_cyrix_5530);
Alan Cox1597cac2006-12-04 15:14:45 -0800483DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
484 pci_early_fixup_cyrix_5530);
Ivan Kokshaysky73a74ed2007-05-23 14:50:02 -0700485
486/*
487 * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller:
488 * prevent update of the BAR0, which doesn't look like a normal BAR.
489 */
490static void __devinit pci_siemens_interrupt_controller(struct pci_dev *dev)
491{
492 dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
493}
494DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
495 pci_siemens_interrupt_controller);
Yinghai Lu57741a72008-02-15 01:32:50 -0800496
497/*
Andreas Herrmannffd565a2008-11-25 17:18:03 +0100498 * Regular PCI devices have 256 bytes, but AMD Family 10h/11h CPUs have
499 * 4096 bytes configuration space for each function of their processor
500 * configuration space.
Yinghai Lu57741a72008-02-15 01:32:50 -0800501 */
Andreas Herrmannffd565a2008-11-25 17:18:03 +0100502static void amd_cpu_pci_cfg_space_size(struct pci_dev *dev)
Yinghai Lu57741a72008-02-15 01:32:50 -0800503{
Yinghai Lu70b9f7d2008-04-28 16:27:23 -0700504 dev->cfg_size = pci_cfg_space_size_ext(dev);
Yinghai Lu57741a72008-02-15 01:32:50 -0800505}
Andreas Herrmannffd565a2008-11-25 17:18:03 +0100506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, amd_cpu_pci_cfg_space_size);
507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, amd_cpu_pci_cfg_space_size);
508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, amd_cpu_pci_cfg_space_size);
509DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, amd_cpu_pci_cfg_space_size);
510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, amd_cpu_pci_cfg_space_size);
511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1300, amd_cpu_pci_cfg_space_size);
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1301, amd_cpu_pci_cfg_space_size);
513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1302, amd_cpu_pci_cfg_space_size);
514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1303, amd_cpu_pci_cfg_space_size);
515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1304, amd_cpu_pci_cfg_space_size);
Jordan Croused7451fc2008-09-12 11:45:22 -0600516
517/*
518 * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
519 * confusing the PCI engine:
520 */
521static void sb600_disable_hpet_bar(struct pci_dev *dev)
522{
523 u8 val;
524
525 /*
526 * The SB600 and SB700 both share the same device
527 * ID, but the PM register 0x55 does something different
528 * for the SB700, so make sure we are dealing with the
529 * SB600 before touching the bit:
530 */
531
532 pci_read_config_byte(dev, 0x08, &val);
533
534 if (val < 0x2F) {
535 outb(0x55, 0xCD6);
536 val = inb(0xCD7);
537
538 /* Set bit 7 in PM register 0x55 */
539 outb(0x55, 0xCD6);
540 outb(val | 0x80, 0xCD7);
541 }
542}
543DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);