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gerrit-public.fairphone.software / kernel / msm-4.9 / 82f6b6da703e784b923763cc7161116829b2ca66 / . / drivers / pinctrl / sh-pfc / pfc-sh73a0.c
blob: ed5cbaf66ac23168e3fc5e986e92474e63211111 [file] [log] [blame]
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1/*
2 * sh73a0 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Copyright (C) 2010 NISHIMOTO Hiroki
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]21#include <linux/io.h>
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]22#include <linux/kernel.h>
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]23#include <linux/pinctrl/pinconf-generic.h>
24
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]25#include <mach/sh73a0.h>
26#include <mach/irqs.h>
27
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]28#include "core.h"
Laurent Pinchartc3323802012-12-15 23:51:55 +0100[diff] [blame]29#include "sh_pfc.h"
30
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]31#define CPU_ALL_PORT(fn, pfx, sfx) \
Guennadi Liakhovetski942785d2013-02-12 16:34:31 +0100[diff] [blame]32 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]33 PORT_10(fn, pfx##10, sfx), \
34 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
35 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
36 PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
37 PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
38 PORT_1(fn, pfx##118, sfx), \
39 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
40 PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
41 PORT_10(fn, pfx##15, sfx), \
42 PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
43 PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
44 PORT_1(fn, pfx##164, sfx), \
45 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
46 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
47 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
48 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
49 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
50 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
51 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
52 PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
53 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
54 PORT_1(fn, pfx##282, sfx), \
55 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
56 PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
57
58enum {
59 PINMUX_RESERVED = 0,
60
61 PINMUX_DATA_BEGIN,
62 PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
63 PINMUX_DATA_END,
64
65 PINMUX_INPUT_BEGIN,
66 PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
67 PINMUX_INPUT_END,
68
69 PINMUX_INPUT_PULLUP_BEGIN,
70 PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
71 PINMUX_INPUT_PULLUP_END,
72
73 PINMUX_INPUT_PULLDOWN_BEGIN,
74 PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
75 PINMUX_INPUT_PULLDOWN_END,
76
77 PINMUX_OUTPUT_BEGIN,
78 PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
79 PINMUX_OUTPUT_END,
80
81 PINMUX_FUNCTION_BEGIN,
82 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
83 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
84 PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
85 PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
86 PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
87 PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
88 PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
89 PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
90 PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
91 PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
92
93 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
94 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
95 MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
96 MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
97 MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
98 MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
99 MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
100 MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
101 MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
102 MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
103 MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
104 MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
105 MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
106 MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
107 MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
108 MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
109 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
110 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
111 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
112 MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
113 MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
114 MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
115 MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
116 MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
117 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
118 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
119 MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
120 MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
121 MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
122 MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
123 MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
124 MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
125 MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
126 MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
127 MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
128 MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
129 MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
130 MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
131 MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
132 MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
133 MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
134 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
135 PINMUX_FUNCTION_END,
136
137 PINMUX_MARK_BEGIN,
138 /* Hardware manual Table 25-1 (Function 0-7) */
139 VBUS_0_MARK,
140 GPI0_MARK,
141 GPI1_MARK,
142 GPI2_MARK,
143 GPI3_MARK,
144 GPI4_MARK,
145 GPI5_MARK,
146 GPI6_MARK,
147 GPI7_MARK,
148 SCIFA7_RXD_MARK,
149 SCIFA7_CTS__MARK,
150 GPO7_MARK, MFG0_OUT2_MARK,
151 GPO6_MARK, MFG1_OUT2_MARK,
152 GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
153 SCIFA0_TXD_MARK,
154 SCIFA7_TXD_MARK,
155 SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
156 GPO0_MARK,
157 GPO1_MARK,
158 GPO2_MARK, STATUS0_MARK,
159 GPO3_MARK, STATUS1_MARK,
160 GPO4_MARK, STATUS2_MARK,
161 VINT_MARK,
162 TCKON_MARK,
163 XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
164 MFG0_OUT1_MARK, PORT27_IROUT_MARK,
165 XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
166 PORT28_TPU1TO1_MARK,
167 SIM_RST_MARK, PORT29_TPU1TO1_MARK,
168 SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
169 SIM_D_MARK, PORT31_IROUT_MARK,
170 SCIFA4_TXD_MARK,
171 SCIFA4_RXD_MARK, XWUP_MARK,
172 SCIFA4_RTS__MARK,
173 SCIFA4_CTS__MARK,
174 FSIBOBT_MARK, FSIBIBT_MARK,
175 FSIBOLR_MARK, FSIBILR_MARK,
176 FSIBOSLD_MARK,
177 FSIBISLD_MARK,
178 VACK_MARK,
179 XTAL1L_MARK,
180 SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
181 SCIFA0_RXD_MARK,
182 SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
183 FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
184 FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
185 FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
186 FSICISLD_MARK, FSIDISLD_MARK,
187 FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
188 FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
189
190 FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
191 FSIAOSLD_MARK, BBIF2_TXD2_MARK,
192 FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
193 PORT53_FSICSPDIF_MARK,
194 FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
195 FSICCK_MARK, FSICOMC_MARK,
196 FSIAISLD_MARK, TPU0TO0_MARK,
197 A0_MARK, BS__MARK,
198 A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
199 A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
200 A14_MARK, KEYOUT5_MARK,
201 A15_MARK, KEYOUT4_MARK,
202 A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
203 A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
204 A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
205 A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
206 A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
207 A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
208 A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
209 A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
210 A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
211 A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
212 A26_MARK, KEYIN6_MARK,
213 KEYIN7_MARK,
214 D0_NAF0_MARK,
215 D1_NAF1_MARK,
216 D2_NAF2_MARK,
217 D3_NAF3_MARK,
218 D4_NAF4_MARK,
219 D5_NAF5_MARK,
220 D6_NAF6_MARK,
221 D7_NAF7_MARK,
222 D8_NAF8_MARK,
223 D9_NAF9_MARK,
224 D10_NAF10_MARK,
225 D11_NAF11_MARK,
226 D12_NAF12_MARK,
227 D13_NAF13_MARK,
228 D14_NAF14_MARK,
229 D15_NAF15_MARK,
230 CS4__MARK,
231 CS5A__MARK, PORT91_RDWR_MARK,
232 CS5B__MARK, FCE1__MARK,
233 CS6B__MARK, DACK0_MARK,
234 FCE0__MARK, CS6A__MARK,
235 WAIT__MARK, DREQ0_MARK,
236 RD__FSC_MARK,
237 WE0__FWE_MARK, RDWR_FWE_MARK,
238 WE1__MARK,
239 FRB_MARK,
240 CKO_MARK,
241 NBRSTOUT__MARK,
242 NBRST__MARK,
243 BBIF2_TXD_MARK,
244 BBIF2_RXD_MARK,
245 BBIF2_SYNC_MARK,
246 BBIF2_SCK_MARK,
247 SCIFA3_CTS__MARK, MFG3_IN2_MARK,
248 SCIFA3_RXD_MARK, MFG3_IN1_MARK,
249 BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
250 SCIFA3_TXD_MARK,
251 HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
252 HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
253 HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
254 HSI_TX_READY_MARK, BBIF1_TXD_MARK,
255 HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
256 PORT115_I2C_SCL3_MARK,
257 HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
258 PORT116_I2C_SDA3_MARK,
259 HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
260 HSI_TX_FLAG_MARK,
261 VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
262
263 VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
264 VIO2_HD_MARK, LCD2D1_MARK,
265 VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
266 VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
267 PORT131_KEYOUT11_MARK, LCD2D11_MARK,
268 VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
269 PORT132_KEYOUT10_MARK, LCD2D12_MARK,
270 VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
271 VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
272 VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
273 VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
274 VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
275 VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
276 VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
277 VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
278 VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
279 VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
280 VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
281 VIO2_D5_MARK, LCD2D3_MARK,
282 VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
283 VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
284 PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
285 VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
286 LCD2D18_MARK,
287 VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
288 VIO_CKO_MARK,
289 A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
290 MFG0_IN2_MARK,
291 TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
292 TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
293 TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
294 SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
295 SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
296 SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
297 SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
298 DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
299 PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
300 PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
301 PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
302 PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
303 PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
304 LCDD0_MARK,
305 LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
306 LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
307 LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
308 LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
309 LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
310 LCDD6_MARK,
311 LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
312 LCDD8_MARK, D16_MARK,
313 LCDD9_MARK, D17_MARK,
314 LCDD10_MARK, D18_MARK,
315 LCDD11_MARK, D19_MARK,
316 LCDD12_MARK, D20_MARK,
317 LCDD13_MARK, D21_MARK,
318 LCDD14_MARK, D22_MARK,
319 LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
320 LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
321 LCDD17_MARK, D25_MARK,
322 LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
323 LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
324 LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
325 LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
326 LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
327 LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
328 LCDDCK_MARK, LCDWR__MARK,
329 LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
330 VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
331 LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
332 PORT218_VIO_CKOR_MARK,
333 LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
334 MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
335 LCDVSYN_MARK, LCDVSYN2_MARK,
336 LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
337 MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
338 LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
339 VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
340
341 SCIFA1_TXD_MARK, OVCN2_MARK,
342 EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
343 SCIFA1_RTS__MARK, IDIN_MARK,
344 SCIFA1_RXD_MARK,
345 SCIFA1_CTS__MARK, MFG1_IN1_MARK,
346 MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
347 MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
348 MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
349 MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
350 MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
351 MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
352 MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
353 MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
354 MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
355 MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
356 SCIFA6_TXD_MARK,
357 PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
358 PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
359 PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
360 PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
361 MSIOF2R_RXD_MARK,
362 PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
363 MSIOF2R_TXD_MARK,
364 PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
365 TPU1TO0_MARK,
366 PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
367 TPU3TO1_MARK,
368 PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
369 TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
370 PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
371 MSIOF2R_TSYNC_MARK,
372 SDHICLK0_MARK,
373 SDHICD0_MARK,
374 SDHID0_0_MARK,
375 SDHID0_1_MARK,
376 SDHID0_2_MARK,
377 SDHID0_3_MARK,
378 SDHICMD0_MARK,
379 SDHIWP0_MARK,
380 SDHICLK1_MARK,
381 SDHID1_0_MARK, TS_SPSYNC2_MARK,
382 SDHID1_1_MARK, TS_SDAT2_MARK,
383 SDHID1_2_MARK, TS_SDEN2_MARK,
384 SDHID1_3_MARK, TS_SCK2_MARK,
385 SDHICMD1_MARK,
386 SDHICLK2_MARK,
387 SDHID2_0_MARK, TS_SPSYNC4_MARK,
388 SDHID2_1_MARK, TS_SDAT4_MARK,
389 SDHID2_2_MARK, TS_SDEN4_MARK,
390 SDHID2_3_MARK, TS_SCK4_MARK,
391 SDHICMD2_MARK,
392 MMCCLK0_MARK,
393 MMCD0_0_MARK,
394 MMCD0_1_MARK,
395 MMCD0_2_MARK,
396 MMCD0_3_MARK,
397 MMCD0_4_MARK, TS_SPSYNC5_MARK,
398 MMCD0_5_MARK, TS_SDAT5_MARK,
399 MMCD0_6_MARK, TS_SDEN5_MARK,
400 MMCD0_7_MARK, TS_SCK5_MARK,
401 MMCCMD0_MARK,
402 RESETOUTS__MARK, EXTAL2OUT_MARK,
403 MCP_WAIT__MCP_FRB_MARK,
404 MCP_CKO_MARK, MMCCLK1_MARK,
405 MCP_D15_MCP_NAF15_MARK,
406 MCP_D14_MCP_NAF14_MARK,
407 MCP_D13_MCP_NAF13_MARK,
408 MCP_D12_MCP_NAF12_MARK,
409 MCP_D11_MCP_NAF11_MARK,
410 MCP_D10_MCP_NAF10_MARK,
411 MCP_D9_MCP_NAF9_MARK,
412 MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
413 MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
414
415 MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
416 MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
417 MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
418 MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
419 MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
420 MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
421 MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
422 MCP_NBRSTOUT__MARK,
423 MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
424
425 /* MSEL2 special cases */
426 TSIF2_TS_XX1_MARK,
427 TSIF2_TS_XX2_MARK,
428 TSIF2_TS_XX3_MARK,
429 TSIF2_TS_XX4_MARK,
430 TSIF2_TS_XX5_MARK,
431 TSIF1_TS_XX1_MARK,
432 TSIF1_TS_XX2_MARK,
433 TSIF1_TS_XX3_MARK,
434 TSIF1_TS_XX4_MARK,
435 TSIF1_TS_XX5_MARK,
436 TSIF0_TS_XX1_MARK,
437 TSIF0_TS_XX2_MARK,
438 TSIF0_TS_XX3_MARK,
439 TSIF0_TS_XX4_MARK,
440 TSIF0_TS_XX5_MARK,
441 MST1_TS_XX1_MARK,
442 MST1_TS_XX2_MARK,
443 MST1_TS_XX3_MARK,
444 MST1_TS_XX4_MARK,
445 MST1_TS_XX5_MARK,
446 MST0_TS_XX1_MARK,
447 MST0_TS_XX2_MARK,
448 MST0_TS_XX3_MARK,
449 MST0_TS_XX4_MARK,
450 MST0_TS_XX5_MARK,
451
452 /* MSEL3 special cases */
453 SDHI0_VCCQ_MC0_ON_MARK,
454 SDHI0_VCCQ_MC0_OFF_MARK,
455 DEBUG_MON_VIO_MARK,
456 DEBUG_MON_LCDD_MARK,
457 LCDC_LCDC0_MARK,
458 LCDC_LCDC1_MARK,
459
460 /* MSEL4 special cases */
461 IRQ9_MEM_INT_MARK,
462 IRQ9_MCP_INT_MARK,
463 A11_MARK,
464 KEYOUT8_MARK,
465 TPU4TO3_MARK,
466 RESETA_N_PU_ON_MARK,
467 RESETA_N_PU_OFF_MARK,
468 EDBGREQ_PD_MARK,
469 EDBGREQ_PU_MARK,
470
471 /* Functions with pull-ups */
472 KEYIN0_PU_MARK,
473 KEYIN1_PU_MARK,
474 KEYIN2_PU_MARK,
475 KEYIN3_PU_MARK,
476 KEYIN4_PU_MARK,
477 KEYIN5_PU_MARK,
478 KEYIN6_PU_MARK,
479 KEYIN7_PU_MARK,
480 SDHICD0_PU_MARK,
481 SDHID0_0_PU_MARK,
482 SDHID0_1_PU_MARK,
483 SDHID0_2_PU_MARK,
484 SDHID0_3_PU_MARK,
485 SDHICMD0_PU_MARK,
486 SDHIWP0_PU_MARK,
487 SDHID1_0_PU_MARK,
488 SDHID1_1_PU_MARK,
489 SDHID1_2_PU_MARK,
490 SDHID1_3_PU_MARK,
491 SDHICMD1_PU_MARK,
492 SDHID2_0_PU_MARK,
493 SDHID2_1_PU_MARK,
494 SDHID2_2_PU_MARK,
495 SDHID2_3_PU_MARK,
496 SDHICMD2_PU_MARK,
497 MMCCMD0_PU_MARK,
498 MMCCMD1_PU_MARK,
499 MMCD0_0_PU_MARK,
500 MMCD0_1_PU_MARK,
501 MMCD0_2_PU_MARK,
502 MMCD0_3_PU_MARK,
503 MMCD0_4_PU_MARK,
504 MMCD0_5_PU_MARK,
505 MMCD0_6_PU_MARK,
506 MMCD0_7_PU_MARK,
507 FSIBISLD_PU_MARK,
508 FSIACK_PU_MARK,
509 FSIAILR_PU_MARK,
510 FSIAIBT_PU_MARK,
511 FSIAISLD_PU_MARK,
512
513 PINMUX_MARK_END,
514};
515
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]516static const pinmux_enum_t pinmux_data[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]517 /* specify valid pin states for each pin in GPIO mode */
518
519 /* Table 25-1 (I/O and Pull U/D) */
520 PORT_DATA_I_PD(0),
521 PORT_DATA_I_PU(1),
522 PORT_DATA_I_PU(2),
523 PORT_DATA_I_PU(3),
524 PORT_DATA_I_PU(4),
525 PORT_DATA_I_PU(5),
526 PORT_DATA_I_PU(6),
527 PORT_DATA_I_PU(7),
528 PORT_DATA_I_PU(8),
529 PORT_DATA_I_PD(9),
530 PORT_DATA_I_PD(10),
531 PORT_DATA_I_PU_PD(11),
532 PORT_DATA_IO_PU_PD(12),
533 PORT_DATA_IO_PU_PD(13),
534 PORT_DATA_IO_PU_PD(14),
535 PORT_DATA_IO_PU_PD(15),
536 PORT_DATA_IO_PD(16),
537 PORT_DATA_IO_PD(17),
538 PORT_DATA_IO_PU(18),
539 PORT_DATA_IO_PU(19),
540 PORT_DATA_O(20),
541 PORT_DATA_O(21),
542 PORT_DATA_O(22),
543 PORT_DATA_O(23),
544 PORT_DATA_O(24),
545 PORT_DATA_I_PD(25),
546 PORT_DATA_I_PD(26),
547 PORT_DATA_IO_PU(27),
548 PORT_DATA_IO_PU(28),
549 PORT_DATA_IO_PD(29),
550 PORT_DATA_IO_PD(30),
551 PORT_DATA_IO_PU(31),
552 PORT_DATA_IO_PD(32),
553 PORT_DATA_I_PU_PD(33),
554 PORT_DATA_IO_PD(34),
555 PORT_DATA_I_PU_PD(35),
556 PORT_DATA_IO_PD(36),
557 PORT_DATA_IO(37),
558 PORT_DATA_O(38),
559 PORT_DATA_I_PU(39),
560 PORT_DATA_I_PU_PD(40),
561 PORT_DATA_O(41),
562 PORT_DATA_IO_PD(42),
563 PORT_DATA_IO_PU_PD(43),
564 PORT_DATA_IO_PU_PD(44),
565 PORT_DATA_IO_PD(45),
566 PORT_DATA_IO_PD(46),
567 PORT_DATA_IO_PD(47),
568 PORT_DATA_I_PD(48),
569 PORT_DATA_IO_PU_PD(49),
570 PORT_DATA_IO_PD(50),
571
572 PORT_DATA_IO_PD(51),
573 PORT_DATA_O(52),
574 PORT_DATA_IO_PU_PD(53),
575 PORT_DATA_IO_PU_PD(54),
576 PORT_DATA_IO_PD(55),
577 PORT_DATA_I_PU_PD(56),
578 PORT_DATA_IO(57),
579 PORT_DATA_IO(58),
580 PORT_DATA_IO(59),
581 PORT_DATA_IO(60),
582 PORT_DATA_IO(61),
583 PORT_DATA_IO_PD(62),
584 PORT_DATA_IO_PD(63),
585 PORT_DATA_IO_PU_PD(64),
586 PORT_DATA_IO_PD(65),
587 PORT_DATA_IO_PU_PD(66),
588 PORT_DATA_IO_PU_PD(67),
589 PORT_DATA_IO_PU_PD(68),
590 PORT_DATA_IO_PU_PD(69),
591 PORT_DATA_IO_PU_PD(70),
592 PORT_DATA_IO_PU_PD(71),
593 PORT_DATA_IO_PU_PD(72),
594 PORT_DATA_I_PU_PD(73),
595 PORT_DATA_IO_PU(74),
596 PORT_DATA_IO_PU(75),
597 PORT_DATA_IO_PU(76),
598 PORT_DATA_IO_PU(77),
599 PORT_DATA_IO_PU(78),
600 PORT_DATA_IO_PU(79),
601 PORT_DATA_IO_PU(80),
602 PORT_DATA_IO_PU(81),
603 PORT_DATA_IO_PU(82),
604 PORT_DATA_IO_PU(83),
605 PORT_DATA_IO_PU(84),
606 PORT_DATA_IO_PU(85),
607 PORT_DATA_IO_PU(86),
608 PORT_DATA_IO_PU(87),
609 PORT_DATA_IO_PU(88),
610 PORT_DATA_IO_PU(89),
611 PORT_DATA_O(90),
612 PORT_DATA_IO_PU(91),
613 PORT_DATA_O(92),
614 PORT_DATA_IO_PU(93),
615 PORT_DATA_O(94),
616 PORT_DATA_I_PU_PD(95),
617 PORT_DATA_IO(96),
618 PORT_DATA_IO(97),
619 PORT_DATA_IO(98),
620 PORT_DATA_I_PU(99),
621 PORT_DATA_O(100),
622 PORT_DATA_O(101),
623 PORT_DATA_I_PU(102),
624 PORT_DATA_IO_PD(103),
625 PORT_DATA_I_PU_PD(104),
626 PORT_DATA_I_PD(105),
627 PORT_DATA_I_PD(106),
628 PORT_DATA_I_PU_PD(107),
629 PORT_DATA_I_PU_PD(108),
630 PORT_DATA_IO_PD(109),
631 PORT_DATA_IO_PD(110),
632 PORT_DATA_IO_PU_PD(111),
633 PORT_DATA_IO_PU_PD(112),
634 PORT_DATA_IO_PU_PD(113),
635 PORT_DATA_IO_PD(114),
636 PORT_DATA_IO_PU(115),
637 PORT_DATA_IO_PU(116),
638 PORT_DATA_IO_PU_PD(117),
639 PORT_DATA_IO_PU_PD(118),
640 PORT_DATA_IO_PD(128),
641
642 PORT_DATA_IO_PD(129),
643 PORT_DATA_IO_PU_PD(130),
644 PORT_DATA_IO_PD(131),
645 PORT_DATA_IO_PD(132),
646 PORT_DATA_IO_PD(133),
647 PORT_DATA_IO_PU_PD(134),
648 PORT_DATA_IO_PU_PD(135),
649 PORT_DATA_IO_PU_PD(136),
650 PORT_DATA_IO_PU_PD(137),
651 PORT_DATA_IO_PD(138),
652 PORT_DATA_IO_PD(139),
653 PORT_DATA_IO_PD(140),
654 PORT_DATA_IO_PD(141),
655 PORT_DATA_IO_PD(142),
656 PORT_DATA_IO_PD(143),
657 PORT_DATA_IO_PU_PD(144),
658 PORT_DATA_IO_PD(145),
659 PORT_DATA_IO_PU_PD(146),
660 PORT_DATA_IO_PU_PD(147),
661 PORT_DATA_IO_PU_PD(148),
662 PORT_DATA_IO_PU_PD(149),
663 PORT_DATA_I_PU_PD(150),
664 PORT_DATA_IO_PU_PD(151),
665 PORT_DATA_IO_PU_PD(152),
666 PORT_DATA_IO_PD(153),
667 PORT_DATA_IO_PD(154),
668 PORT_DATA_I_PU_PD(155),
669 PORT_DATA_IO_PU_PD(156),
670 PORT_DATA_I_PD(157),
671 PORT_DATA_IO_PD(158),
672 PORT_DATA_IO_PU_PD(159),
673 PORT_DATA_IO_PU_PD(160),
674 PORT_DATA_I_PU_PD(161),
675 PORT_DATA_I_PU_PD(162),
676 PORT_DATA_IO_PU_PD(163),
677 PORT_DATA_I_PU_PD(164),
678 PORT_DATA_IO_PD(192),
679 PORT_DATA_IO_PU_PD(193),
680 PORT_DATA_IO_PD(194),
681 PORT_DATA_IO_PU_PD(195),
682 PORT_DATA_IO_PD(196),
683 PORT_DATA_IO_PD(197),
684 PORT_DATA_IO_PD(198),
685 PORT_DATA_IO_PD(199),
686 PORT_DATA_IO_PU_PD(200),
687 PORT_DATA_IO_PU_PD(201),
688 PORT_DATA_IO_PU_PD(202),
689 PORT_DATA_IO_PU_PD(203),
690 PORT_DATA_IO_PU_PD(204),
691 PORT_DATA_IO_PU_PD(205),
692 PORT_DATA_IO_PU_PD(206),
693 PORT_DATA_IO_PD(207),
694 PORT_DATA_IO_PD(208),
695 PORT_DATA_IO_PD(209),
696 PORT_DATA_IO_PD(210),
697 PORT_DATA_IO_PD(211),
698 PORT_DATA_IO_PD(212),
699 PORT_DATA_IO_PD(213),
700 PORT_DATA_IO_PU_PD(214),
701 PORT_DATA_IO_PU_PD(215),
702 PORT_DATA_IO_PD(216),
703 PORT_DATA_IO_PD(217),
704 PORT_DATA_O(218),
705 PORT_DATA_IO_PD(219),
706 PORT_DATA_IO_PD(220),
707 PORT_DATA_IO_PU_PD(221),
708 PORT_DATA_IO_PU_PD(222),
709 PORT_DATA_I_PU_PD(223),
710 PORT_DATA_I_PU_PD(224),
711
712 PORT_DATA_IO_PU_PD(225),
713 PORT_DATA_O(226),
714 PORT_DATA_IO_PU_PD(227),
715 PORT_DATA_I_PU_PD(228),
716 PORT_DATA_I_PD(229),
717 PORT_DATA_IO(230),
718 PORT_DATA_IO_PU_PD(231),
719 PORT_DATA_IO_PU_PD(232),
720 PORT_DATA_I_PU_PD(233),
721 PORT_DATA_IO_PU_PD(234),
722 PORT_DATA_IO_PU_PD(235),
723 PORT_DATA_IO_PU_PD(236),
724 PORT_DATA_IO_PD(237),
725 PORT_DATA_IO_PU_PD(238),
726 PORT_DATA_IO_PU_PD(239),
727 PORT_DATA_IO_PU_PD(240),
728 PORT_DATA_O(241),
729 PORT_DATA_I_PD(242),
730 PORT_DATA_IO_PU_PD(243),
731 PORT_DATA_IO_PU_PD(244),
732 PORT_DATA_IO_PU_PD(245),
733 PORT_DATA_IO_PU_PD(246),
734 PORT_DATA_IO_PU_PD(247),
735 PORT_DATA_IO_PU_PD(248),
736 PORT_DATA_IO_PU_PD(249),
737 PORT_DATA_IO_PU_PD(250),
738 PORT_DATA_IO_PU_PD(251),
739 PORT_DATA_IO_PU_PD(252),
740 PORT_DATA_IO_PU_PD(253),
741 PORT_DATA_IO_PU_PD(254),
742 PORT_DATA_IO_PU_PD(255),
743 PORT_DATA_IO_PU_PD(256),
744 PORT_DATA_IO_PU_PD(257),
745 PORT_DATA_IO_PU_PD(258),
746 PORT_DATA_IO_PU_PD(259),
747 PORT_DATA_IO_PU_PD(260),
748 PORT_DATA_IO_PU_PD(261),
749 PORT_DATA_IO_PU_PD(262),
750 PORT_DATA_IO_PU_PD(263),
751 PORT_DATA_IO_PU_PD(264),
752 PORT_DATA_IO_PU_PD(265),
753 PORT_DATA_IO_PU_PD(266),
754 PORT_DATA_IO_PU_PD(267),
755 PORT_DATA_IO_PU_PD(268),
756 PORT_DATA_IO_PU_PD(269),
757 PORT_DATA_IO_PU_PD(270),
758 PORT_DATA_IO_PU_PD(271),
759 PORT_DATA_IO_PU_PD(272),
760 PORT_DATA_IO_PU_PD(273),
761 PORT_DATA_IO_PU_PD(274),
762 PORT_DATA_IO_PU_PD(275),
763 PORT_DATA_IO_PU_PD(276),
764 PORT_DATA_IO_PU_PD(277),
765 PORT_DATA_IO_PU_PD(278),
766 PORT_DATA_IO_PU_PD(279),
767 PORT_DATA_IO_PU_PD(280),
768 PORT_DATA_O(281),
769 PORT_DATA_O(282),
770 PORT_DATA_I_PU(288),
771 PORT_DATA_IO_PU_PD(289),
772 PORT_DATA_IO_PU_PD(290),
773 PORT_DATA_IO_PU_PD(291),
774 PORT_DATA_IO_PU_PD(292),
775 PORT_DATA_IO_PU_PD(293),
776 PORT_DATA_IO_PU_PD(294),
777 PORT_DATA_IO_PU_PD(295),
778 PORT_DATA_IO_PU_PD(296),
779 PORT_DATA_IO_PU_PD(297),
780 PORT_DATA_IO_PU_PD(298),
781
782 PORT_DATA_IO_PU_PD(299),
783 PORT_DATA_IO_PU_PD(300),
784 PORT_DATA_IO_PU_PD(301),
785 PORT_DATA_IO_PU_PD(302),
786 PORT_DATA_IO_PU_PD(303),
787 PORT_DATA_IO_PU_PD(304),
788 PORT_DATA_IO_PU_PD(305),
789 PORT_DATA_O(306),
790 PORT_DATA_O(307),
791 PORT_DATA_I_PU(308),
792 PORT_DATA_O(309),
793
794 /* Table 25-1 (Function 0-7) */
795 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
796 PINMUX_DATA(GPI0_MARK, PORT1_FN1),
797 PINMUX_DATA(GPI1_MARK, PORT2_FN1),
798 PINMUX_DATA(GPI2_MARK, PORT3_FN1),
799 PINMUX_DATA(GPI3_MARK, PORT4_FN1),
800 PINMUX_DATA(GPI4_MARK, PORT5_FN1),
801 PINMUX_DATA(GPI5_MARK, PORT6_FN1),
802 PINMUX_DATA(GPI6_MARK, PORT7_FN1),
803 PINMUX_DATA(GPI7_MARK, PORT8_FN1),
804 PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
805 PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
806 PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
807 PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
808 PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
809 PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
810 PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
811 PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
812 PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
813 PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
814 PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
815 PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
816 PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
817 PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
818 PINMUX_DATA(GPO0_MARK, PORT20_FN1),
819 PINMUX_DATA(GPO1_MARK, PORT21_FN1),
820 PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
821 PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
822 PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
823 PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
824 PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
825 PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
826 PINMUX_DATA(VINT_MARK, PORT25_FN1),
827 PINMUX_DATA(TCKON_MARK, PORT26_FN1),
828 PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
829 PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
830 MSEL2CR_MSEL16_1), \
831 PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
832 MSEL2CR_MSEL18_1), \
833 PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
834 PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
835 PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
836 PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
837 MSEL2CR_MSEL16_1), \
838 PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
839 MSEL2CR_MSEL18_1), \
840 PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
841 PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
842 PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
843 PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
844 PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
845 PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
846 PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
847 PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
848 PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
849 PINMUX_DATA(XWUP_MARK, PORT33_FN3),
850 PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
851 PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
852 PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
853 PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
854 PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
855 PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
856 PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
857 PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
858 PINMUX_DATA(VACK_MARK, PORT40_FN1),
859 PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
860 PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
861 PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
862 PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
863 PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
864 PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
865 PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
866 PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
867 PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
868 PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
869 PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
870 PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
871 PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
872 PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
873 PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
874 PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
875 PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
876 PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
877 PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
878 PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
879 PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
880 PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
881 PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
882 PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
883 PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
884 PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
885
886 PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
887 PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
888 PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
889 PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
890 PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
891 PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
892 PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
893 PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
894 PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
895 PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
896 PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
897 PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
898 PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
899 PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
900 PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
901 PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
902 PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
903 PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
904 PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
905 PINMUX_DATA(A0_MARK, PORT57_FN1), \
906 PINMUX_DATA(BS__MARK, PORT57_FN2),
907 PINMUX_DATA(A12_MARK, PORT58_FN1), \
908 PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
909 PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
910 PINMUX_DATA(A13_MARK, PORT59_FN1), \
911 PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
912 PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
913 PINMUX_DATA(A14_MARK, PORT60_FN1), \
914 PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
915 PINMUX_DATA(A15_MARK, PORT61_FN1), \
916 PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
917 PINMUX_DATA(A16_MARK, PORT62_FN1), \
918 PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
919 PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
920 PINMUX_DATA(A17_MARK, PORT63_FN1), \
921 PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
922 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
923 PINMUX_DATA(A18_MARK, PORT64_FN1), \
924 PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
925 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
926 PINMUX_DATA(A19_MARK, PORT65_FN1), \
927 PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
928 PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
929 PINMUX_DATA(A20_MARK, PORT66_FN1), \
930 PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
931 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
932 PINMUX_DATA(A21_MARK, PORT67_FN1), \
933 PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
934 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
935 PINMUX_DATA(A22_MARK, PORT68_FN1), \
936 PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
937 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
938 PINMUX_DATA(A23_MARK, PORT69_FN1), \
939 PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
940 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
941 PINMUX_DATA(A24_MARK, PORT70_FN1), \
942 PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
943 PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
944 PINMUX_DATA(A25_MARK, PORT71_FN1), \
945 PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
946 PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
947 PINMUX_DATA(A26_MARK, PORT72_FN1), \
948 PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
949 PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
950 PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
951 PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
952 PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
953 PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
954 PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
955 PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
956 PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
957 PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
958 PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
959 PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
960 PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
961 PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
962 PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
963 PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
964 PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
965 PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
966 PINMUX_DATA(CS4__MARK, PORT90_FN1),
967 PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
968 PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
969 PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
970 PINMUX_DATA(FCE1__MARK, PORT92_FN2),
971 PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
972 PINMUX_DATA(DACK0_MARK, PORT93_FN4),
973 PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
974 PINMUX_DATA(CS6A__MARK, PORT94_FN2),
975 PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
976 PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
977 PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
978 PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
979 PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
980 PINMUX_DATA(WE1__MARK, PORT98_FN1),
981 PINMUX_DATA(FRB_MARK, PORT99_FN1),
982 PINMUX_DATA(CKO_MARK, PORT100_FN1),
983 PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
984 PINMUX_DATA(NBRST__MARK, PORT102_FN1),
985 PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
986 PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
987 PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
988 PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
989 PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
990 PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
991 PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
992 PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
993 PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
994 PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
995 PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
996 PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
997 PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
998 PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
999 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
1000 PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
1001 PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
1002 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
1003 PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
1004 PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
1005 PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
1006 PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
1007 PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
1008 PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
1009 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
1010 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
1011 PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
1012 PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
1013 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
1014 PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
1015 PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
1016 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
1017 PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
1018 PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
1019 PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
1020 PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
1021
1022 PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
1023 PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
1024 PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
1025 PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
1026 PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
1027 PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
1028 PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
1029 MSEL4CR_MSEL10_1), \
1030 PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
1031 PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
1032 PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
1033 PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
1034 PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
1035 PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
1036 PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
1037 PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
1038 PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
1039 PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
1040 PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
1041 PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
1042 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
1043 PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
1044 PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
1045 PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
1046 PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
1047 PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
1048 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
1049 PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
1050 PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
1051 PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
1052 PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
1053 PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
1054 PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
1055 PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
1056 PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
1057 PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
1058 PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
1059 PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
1060 PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
1061 PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
1062 PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
1063 PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
1064 PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
1065 PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
1066 PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
1067 PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
1068 PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
1069 PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
1070 PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
1071 PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
1072 PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
1073 PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
1074 PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
1075 PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
1076 PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
1077 PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
1078 PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
1079 PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
1080 PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
1081 PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
1082 PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
1083 PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
1084 PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
1085 PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
1086 PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
1087 PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
1088 PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
1089 PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
1090 PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
1091 PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
1092 PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
1093 PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
1094 PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
1095 PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
1096 PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
1097 PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
1098 PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
1099 PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
1100 PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
1101 PINMUX_DATA(A27_MARK, PORT149_FN1), \
1102 PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
1103 PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
1104 PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
1105 PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
1106 PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
1107 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
1108 PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
1109 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
1110 PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
1111 PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
1112 PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
1113 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
1114 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
1115 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
1116 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
1117 PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
1118 PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
1119 PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
1120 PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
1121 MSEL4CR_MSEL10_0),
1122 PINMUX_DATA(DINT__MARK, PORT158_FN1), \
1123 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
1124 PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
1125 PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
1126 PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
1127 PINMUX_DATA(NMI_MARK, PORT159_FN3),
1128 PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
1129 PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
1130 PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
1131 PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
1132 PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
1133 PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
1134 PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
1135 PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
1136 PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
1137 PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
1138 PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
1139 PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
1140 MSEL4CR_MSEL20_1), \
1141 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
1142 PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
1143 PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
1144 MSEL4CR_MSEL20_1), \
1145 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
1146 PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
1147 PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
1148 MSEL4CR_MSEL20_1), \
1149 PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
1150 PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
1151 PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
1152 MSEL4CR_MSEL20_1),
1153 PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
1154 PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
1155 MSEL4CR_MSEL20_1), \
1156 PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
1157 PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
1158 PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
1159 PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
1160 PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
1161 PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
1162 PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
1163 PINMUX_DATA(D16_MARK, PORT200_FN6),
1164 PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
1165 PINMUX_DATA(D17_MARK, PORT201_FN6),
1166 PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
1167 PINMUX_DATA(D18_MARK, PORT202_FN6),
1168 PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
1169 PINMUX_DATA(D19_MARK, PORT203_FN6),
1170 PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
1171 PINMUX_DATA(D20_MARK, PORT204_FN6),
1172 PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
1173 PINMUX_DATA(D21_MARK, PORT205_FN6),
1174 PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
1175 PINMUX_DATA(D22_MARK, PORT206_FN6),
1176 PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
1177 PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
1178 PINMUX_DATA(D23_MARK, PORT207_FN6),
1179 PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
1180 PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
1181 PINMUX_DATA(D24_MARK, PORT208_FN6),
1182 PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
1183 PINMUX_DATA(D25_MARK, PORT209_FN6),
1184 PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
1185 PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
1186 PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
1187 PINMUX_DATA(D26_MARK, PORT210_FN6),
1188 PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
1189 PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
1190 PINMUX_DATA(D27_MARK, PORT211_FN6),
1191 PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
1192 PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
1193 PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
1194 PINMUX_DATA(D28_MARK, PORT212_FN6),
1195 PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
1196 PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
1197 PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
1198 PINMUX_DATA(D29_MARK, PORT213_FN6),
1199 PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
1200 PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
1201 PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
1202 PINMUX_DATA(D30_MARK, PORT214_FN6),
1203 PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
1204 PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
1205 PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
1206 PINMUX_DATA(D31_MARK, PORT215_FN6),
1207 PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
1208 PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
1209 PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
1210 PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
1211 PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
1212 PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
1213 PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
1214 MSEL4CR_MSEL26_1), \
1215 PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
1216 PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
1217 PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
1218 PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
1219 PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
1220 PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
1221 PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
1222 PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
1223 PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
1224 PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
1225 PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
1226 PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
1227 MSEL4CR_MSEL26_1), \
1228 PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
1229 PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
1230 PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
1231 PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
1232 PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
1233 PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
1234 PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
1235 PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
1236 PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
1237 MSEL4CR_MSEL26_1), \
1238 PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
1239 PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
1240 PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
1241 PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
1242 PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
1243 PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
1244 PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
1245 MSEL4CR_MSEL26_1), \
1246 PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
1247
1248 PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
1249 PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
1250 PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
1251 PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
1252 PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
1253 PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
1254 PINMUX_DATA(IDIN_MARK, PORT227_FN4),
1255 PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
1256 PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
1257 PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
1258 PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
1259 PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
1260 PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
1261 PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
1262 PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
1263 PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
1264 PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
1265 PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
1266 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
1267 PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
1268 PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
1269 MSEL4CR_MSEL26_0), \
1270 PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
1271 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
1272 PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
1273 PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
1274 MSEL4CR_MSEL26_0), \
1275 PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
1276 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
1277 PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
1278 MSEL2CR_MSEL16_0),
1279 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
1280 PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
1281 MSEL2CR_MSEL16_0),
1282 PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
1283 PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
1284 MSEL4CR_MSEL26_0), \
1285 PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
1286 PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
1287 PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
1288 MSEL4CR_MSEL26_0), \
1289 PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
1290 PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
1291 PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
1292 PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
1293 PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
1294 PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
1295 PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
1296 PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
1297 PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
1298 PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
1299 PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
1300 MSEL4CR_MSEL20_0), \
1301 PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
1302 PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
1303 PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
1304 PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
1305 MSEL4CR_MSEL20_0), \
1306 PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
1307 PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
1308 PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
1309 PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
1310 MSEL4CR_MSEL20_0), \
1311 PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
1312 PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
1313 PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
1314 PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
1315 MSEL4CR_MSEL20_0), \
1316 PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
1317 PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
1318 PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
1319 PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
1320 MSEL4CR_MSEL20_0), \
1321 PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
1322 PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
1323 PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
1324 PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
1325 MSEL2CR_MSEL18_0), \
1326 PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
1327 PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
1328 PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
1329 PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
1330 MSEL2CR_MSEL18_0), \
1331 PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
1332 PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
1333 PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1334 PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1335 PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1336 PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1337 PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1338 PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1339 PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1340 PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1341 PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1342 PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1343 PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1344 PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1345 PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1346 PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1347 PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1348 PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1349 PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1350 PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1351 PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1352 PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1353 PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1354 PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1355 PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1356 PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1357 PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1358 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1359 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1360 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1361 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
1362 MSEL4CR_MSEL15_0),
1363 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
1364 MSEL4CR_MSEL15_0),
1365 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
1366 MSEL4CR_MSEL15_0),
1367 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
1368 MSEL4CR_MSEL15_0),
1369 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
1370 MSEL4CR_MSEL15_0), \
1371 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1372 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
1373 MSEL4CR_MSEL15_0), \
1374 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1375 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
1376 MSEL4CR_MSEL15_0), \
1377 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1378 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
1379 MSEL4CR_MSEL15_0), \
1380 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1381 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
1382 MSEL4CR_MSEL15_0),
1383 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1384 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1385 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1386 PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1387 PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1388 PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1389 PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1390 PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1391 PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1392 PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1393 PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1394 PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1395 PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1396 PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1397 PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1398 PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1399
1400 PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1401 PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1402 PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1403 PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1404 PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1405 PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1406 PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1407 PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1408 PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1409 PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1410 PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1411 PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1412 PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1413 PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1414 PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1415 PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1416 PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1417
1418 /* MSEL2 special cases */
1419 PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1420 MSEL2CR_MSEL12_0),
1421 PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1422 MSEL2CR_MSEL12_1),
1423 PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1424 MSEL2CR_MSEL12_0),
1425 PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1426 MSEL2CR_MSEL12_1),
1427 PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1428 MSEL2CR_MSEL12_0),
1429 PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1430 MSEL2CR_MSEL9_0),
1431 PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1432 MSEL2CR_MSEL9_1),
1433 PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1434 MSEL2CR_MSEL9_0),
1435 PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1436 MSEL2CR_MSEL9_1),
1437 PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1438 MSEL2CR_MSEL9_0),
1439 PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1440 MSEL2CR_MSEL6_0),
1441 PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1442 MSEL2CR_MSEL6_1),
1443 PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1444 MSEL2CR_MSEL6_0),
1445 PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1446 MSEL2CR_MSEL6_1),
1447 PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1448 MSEL2CR_MSEL6_0),
1449 PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1450 MSEL2CR_MSEL3_0),
1451 PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1452 MSEL2CR_MSEL3_1),
1453 PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1454 MSEL2CR_MSEL3_0),
1455 PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1456 MSEL2CR_MSEL3_1),
1457 PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1458 MSEL2CR_MSEL3_0),
1459 PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1460 MSEL2CR_MSEL0_0),
1461 PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1462 MSEL2CR_MSEL0_1),
1463 PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1464 MSEL2CR_MSEL0_0),
1465 PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1466 MSEL2CR_MSEL0_1),
1467 PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1468 MSEL2CR_MSEL0_0),
1469
1470 /* MSEL3 special cases */
1471 PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1472 PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1473 PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1474 PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1475 PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1476 PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1477
1478 /* MSEL4 special cases */
1479 PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1480 PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1481 PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1482 PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1483 PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1484 PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1485 PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1486 PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1487 PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1488
1489 /* Functions with pull-ups */
1490 PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
1491 PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
1492 PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
1493 PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
1494 PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
1495 PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
1496 PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
1497 PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
1498
1499 PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU),
1500 PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU),
1501 PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU),
1502 PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
1503 PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
1504 PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
Guennadi Liakhovetski942785d2013-02-12 16:34:31 +0100[diff] [blame]1505 PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT257_IN_PU),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1506 PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
1507 PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
1508 PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
1509 PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU),
1510 PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU),
1511 PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU),
1512 PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU),
1513 PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU),
1514 PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU),
1515 PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU),
1516
1517 PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
1518 MSEL4CR_MSEL15_0),
1519 PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
1520 MSEL4CR_MSEL15_1),
1521
1522 PINMUX_DATA(MMCD0_0_PU_MARK,
1523 PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
1524 PINMUX_DATA(MMCD0_1_PU_MARK,
1525 PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
1526 PINMUX_DATA(MMCD0_2_PU_MARK,
1527 PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
1528 PINMUX_DATA(MMCD0_3_PU_MARK,
1529 PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
1530 PINMUX_DATA(MMCD0_4_PU_MARK,
1531 PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
1532 PINMUX_DATA(MMCD0_5_PU_MARK,
1533 PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
1534 PINMUX_DATA(MMCD0_6_PU_MARK,
1535 PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
1536 PINMUX_DATA(MMCD0_7_PU_MARK,
1537 PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
1538
1539 PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
1540 PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
1541 PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
1542 PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
1543 PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
1544};
1545
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]1546#define SH73A0_PIN(pin, cfgs) \
1547 { \
1548 .name = __stringify(PORT##pin), \
1549 .enum_id = PORT##pin##_DATA, \
1550 .configs = cfgs, \
1551 }
1552
1553#define __I (SH_PFC_PIN_CFG_INPUT)
1554#define __O (SH_PFC_PIN_CFG_OUTPUT)
1555#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1556#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1557#define __PU (SH_PFC_PIN_CFG_PULL_UP)
1558#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1559
1560#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
1561#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
1562#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
1563#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
1564#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
1565#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
1566#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
1567#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
1568
Laurent Pincharta3db40a62013-01-02 14:53:37 +0100[diff] [blame]1569static struct sh_pfc_pin pinmux_pins[] = {
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]1570 /* Table 25-1 (I/O and Pull U/D) */
1571 SH73A0_PIN_I_PD(0),
1572 SH73A0_PIN_I_PU(1),
1573 SH73A0_PIN_I_PU(2),
1574 SH73A0_PIN_I_PU(3),
1575 SH73A0_PIN_I_PU(4),
1576 SH73A0_PIN_I_PU(5),
1577 SH73A0_PIN_I_PU(6),
1578 SH73A0_PIN_I_PU(7),
1579 SH73A0_PIN_I_PU(8),
1580 SH73A0_PIN_I_PD(9),
1581 SH73A0_PIN_I_PD(10),
1582 SH73A0_PIN_I_PU_PD(11),
1583 SH73A0_PIN_IO_PU_PD(12),
1584 SH73A0_PIN_IO_PU_PD(13),
1585 SH73A0_PIN_IO_PU_PD(14),
1586 SH73A0_PIN_IO_PU_PD(15),
1587 SH73A0_PIN_IO_PD(16),
1588 SH73A0_PIN_IO_PD(17),
1589 SH73A0_PIN_IO_PU(18),
1590 SH73A0_PIN_IO_PU(19),
1591 SH73A0_PIN_O(20),
1592 SH73A0_PIN_O(21),
1593 SH73A0_PIN_O(22),
1594 SH73A0_PIN_O(23),
1595 SH73A0_PIN_O(24),
1596 SH73A0_PIN_I_PD(25),
1597 SH73A0_PIN_I_PD(26),
1598 SH73A0_PIN_IO_PU(27),
1599 SH73A0_PIN_IO_PU(28),
1600 SH73A0_PIN_IO_PD(29),
1601 SH73A0_PIN_IO_PD(30),
1602 SH73A0_PIN_IO_PU(31),
1603 SH73A0_PIN_IO_PD(32),
1604 SH73A0_PIN_I_PU_PD(33),
1605 SH73A0_PIN_IO_PD(34),
1606 SH73A0_PIN_I_PU_PD(35),
1607 SH73A0_PIN_IO_PD(36),
1608 SH73A0_PIN_IO(37),
1609 SH73A0_PIN_O(38),
1610 SH73A0_PIN_I_PU(39),
1611 SH73A0_PIN_I_PU_PD(40),
1612 SH73A0_PIN_O(41),
1613 SH73A0_PIN_IO_PD(42),
1614 SH73A0_PIN_IO_PU_PD(43),
1615 SH73A0_PIN_IO_PU_PD(44),
1616 SH73A0_PIN_IO_PD(45),
1617 SH73A0_PIN_IO_PD(46),
1618 SH73A0_PIN_IO_PD(47),
1619 SH73A0_PIN_I_PD(48),
1620 SH73A0_PIN_IO_PU_PD(49),
1621 SH73A0_PIN_IO_PD(50),
1622 SH73A0_PIN_IO_PD(51),
1623 SH73A0_PIN_O(52),
1624 SH73A0_PIN_IO_PU_PD(53),
1625 SH73A0_PIN_IO_PU_PD(54),
1626 SH73A0_PIN_IO_PD(55),
1627 SH73A0_PIN_I_PU_PD(56),
1628 SH73A0_PIN_IO(57),
1629 SH73A0_PIN_IO(58),
1630 SH73A0_PIN_IO(59),
1631 SH73A0_PIN_IO(60),
1632 SH73A0_PIN_IO(61),
1633 SH73A0_PIN_IO_PD(62),
1634 SH73A0_PIN_IO_PD(63),
1635 SH73A0_PIN_IO_PU_PD(64),
1636 SH73A0_PIN_IO_PD(65),
1637 SH73A0_PIN_IO_PU_PD(66),
1638 SH73A0_PIN_IO_PU_PD(67),
1639 SH73A0_PIN_IO_PU_PD(68),
1640 SH73A0_PIN_IO_PU_PD(69),
1641 SH73A0_PIN_IO_PU_PD(70),
1642 SH73A0_PIN_IO_PU_PD(71),
1643 SH73A0_PIN_IO_PU_PD(72),
1644 SH73A0_PIN_I_PU_PD(73),
1645 SH73A0_PIN_IO_PU(74),
1646 SH73A0_PIN_IO_PU(75),
1647 SH73A0_PIN_IO_PU(76),
1648 SH73A0_PIN_IO_PU(77),
1649 SH73A0_PIN_IO_PU(78),
1650 SH73A0_PIN_IO_PU(79),
1651 SH73A0_PIN_IO_PU(80),
1652 SH73A0_PIN_IO_PU(81),
1653 SH73A0_PIN_IO_PU(82),
1654 SH73A0_PIN_IO_PU(83),
1655 SH73A0_PIN_IO_PU(84),
1656 SH73A0_PIN_IO_PU(85),
1657 SH73A0_PIN_IO_PU(86),
1658 SH73A0_PIN_IO_PU(87),
1659 SH73A0_PIN_IO_PU(88),
1660 SH73A0_PIN_IO_PU(89),
1661 SH73A0_PIN_O(90),
1662 SH73A0_PIN_IO_PU(91),
1663 SH73A0_PIN_O(92),
1664 SH73A0_PIN_IO_PU(93),
1665 SH73A0_PIN_O(94),
1666 SH73A0_PIN_I_PU_PD(95),
1667 SH73A0_PIN_IO(96),
1668 SH73A0_PIN_IO(97),
1669 SH73A0_PIN_IO(98),
1670 SH73A0_PIN_I_PU(99),
1671 SH73A0_PIN_O(100),
1672 SH73A0_PIN_O(101),
1673 SH73A0_PIN_I_PU(102),
1674 SH73A0_PIN_IO_PD(103),
1675 SH73A0_PIN_I_PU_PD(104),
1676 SH73A0_PIN_I_PD(105),
1677 SH73A0_PIN_I_PD(106),
1678 SH73A0_PIN_I_PU_PD(107),
1679 SH73A0_PIN_I_PU_PD(108),
1680 SH73A0_PIN_IO_PD(109),
1681 SH73A0_PIN_IO_PD(110),
1682 SH73A0_PIN_IO_PU_PD(111),
1683 SH73A0_PIN_IO_PU_PD(112),
1684 SH73A0_PIN_IO_PU_PD(113),
1685 SH73A0_PIN_IO_PD(114),
1686 SH73A0_PIN_IO_PU(115),
1687 SH73A0_PIN_IO_PU(116),
1688 SH73A0_PIN_IO_PU_PD(117),
1689 SH73A0_PIN_IO_PU_PD(118),
1690 SH73A0_PIN_IO_PD(128),
1691 SH73A0_PIN_IO_PD(129),
1692 SH73A0_PIN_IO_PU_PD(130),
1693 SH73A0_PIN_IO_PD(131),
1694 SH73A0_PIN_IO_PD(132),
1695 SH73A0_PIN_IO_PD(133),
1696 SH73A0_PIN_IO_PU_PD(134),
1697 SH73A0_PIN_IO_PU_PD(135),
1698 SH73A0_PIN_IO_PU_PD(136),
1699 SH73A0_PIN_IO_PU_PD(137),
1700 SH73A0_PIN_IO_PD(138),
1701 SH73A0_PIN_IO_PD(139),
1702 SH73A0_PIN_IO_PD(140),
1703 SH73A0_PIN_IO_PD(141),
1704 SH73A0_PIN_IO_PD(142),
1705 SH73A0_PIN_IO_PD(143),
1706 SH73A0_PIN_IO_PU_PD(144),
1707 SH73A0_PIN_IO_PD(145),
1708 SH73A0_PIN_IO_PU_PD(146),
1709 SH73A0_PIN_IO_PU_PD(147),
1710 SH73A0_PIN_IO_PU_PD(148),
1711 SH73A0_PIN_IO_PU_PD(149),
1712 SH73A0_PIN_I_PU_PD(150),
1713 SH73A0_PIN_IO_PU_PD(151),
1714 SH73A0_PIN_IO_PU_PD(152),
1715 SH73A0_PIN_IO_PD(153),
1716 SH73A0_PIN_IO_PD(154),
1717 SH73A0_PIN_I_PU_PD(155),
1718 SH73A0_PIN_IO_PU_PD(156),
1719 SH73A0_PIN_I_PD(157),
1720 SH73A0_PIN_IO_PD(158),
1721 SH73A0_PIN_IO_PU_PD(159),
1722 SH73A0_PIN_IO_PU_PD(160),
1723 SH73A0_PIN_I_PU_PD(161),
1724 SH73A0_PIN_I_PU_PD(162),
1725 SH73A0_PIN_IO_PU_PD(163),
1726 SH73A0_PIN_I_PU_PD(164),
1727 SH73A0_PIN_IO_PD(192),
1728 SH73A0_PIN_IO_PU_PD(193),
1729 SH73A0_PIN_IO_PD(194),
1730 SH73A0_PIN_IO_PU_PD(195),
1731 SH73A0_PIN_IO_PD(196),
1732 SH73A0_PIN_IO_PD(197),
1733 SH73A0_PIN_IO_PD(198),
1734 SH73A0_PIN_IO_PD(199),
1735 SH73A0_PIN_IO_PU_PD(200),
1736 SH73A0_PIN_IO_PU_PD(201),
1737 SH73A0_PIN_IO_PU_PD(202),
1738 SH73A0_PIN_IO_PU_PD(203),
1739 SH73A0_PIN_IO_PU_PD(204),
1740 SH73A0_PIN_IO_PU_PD(205),
1741 SH73A0_PIN_IO_PU_PD(206),
1742 SH73A0_PIN_IO_PD(207),
1743 SH73A0_PIN_IO_PD(208),
1744 SH73A0_PIN_IO_PD(209),
1745 SH73A0_PIN_IO_PD(210),
1746 SH73A0_PIN_IO_PD(211),
1747 SH73A0_PIN_IO_PD(212),
1748 SH73A0_PIN_IO_PD(213),
1749 SH73A0_PIN_IO_PU_PD(214),
1750 SH73A0_PIN_IO_PU_PD(215),
1751 SH73A0_PIN_IO_PD(216),
1752 SH73A0_PIN_IO_PD(217),
1753 SH73A0_PIN_O(218),
1754 SH73A0_PIN_IO_PD(219),
1755 SH73A0_PIN_IO_PD(220),
1756 SH73A0_PIN_IO_PU_PD(221),
1757 SH73A0_PIN_IO_PU_PD(222),
1758 SH73A0_PIN_I_PU_PD(223),
1759 SH73A0_PIN_I_PU_PD(224),
1760 SH73A0_PIN_IO_PU_PD(225),
1761 SH73A0_PIN_O(226),
1762 SH73A0_PIN_IO_PU_PD(227),
1763 SH73A0_PIN_I_PU_PD(228),
1764 SH73A0_PIN_I_PD(229),
1765 SH73A0_PIN_IO(230),
1766 SH73A0_PIN_IO_PU_PD(231),
1767 SH73A0_PIN_IO_PU_PD(232),
1768 SH73A0_PIN_I_PU_PD(233),
1769 SH73A0_PIN_IO_PU_PD(234),
1770 SH73A0_PIN_IO_PU_PD(235),
1771 SH73A0_PIN_IO_PU_PD(236),
1772 SH73A0_PIN_IO_PD(237),
1773 SH73A0_PIN_IO_PU_PD(238),
1774 SH73A0_PIN_IO_PU_PD(239),
1775 SH73A0_PIN_IO_PU_PD(240),
1776 SH73A0_PIN_O(241),
1777 SH73A0_PIN_I_PD(242),
1778 SH73A0_PIN_IO_PU_PD(243),
1779 SH73A0_PIN_IO_PU_PD(244),
1780 SH73A0_PIN_IO_PU_PD(245),
1781 SH73A0_PIN_IO_PU_PD(246),
1782 SH73A0_PIN_IO_PU_PD(247),
1783 SH73A0_PIN_IO_PU_PD(248),
1784 SH73A0_PIN_IO_PU_PD(249),
1785 SH73A0_PIN_IO_PU_PD(250),
1786 SH73A0_PIN_IO_PU_PD(251),
1787 SH73A0_PIN_IO_PU_PD(252),
1788 SH73A0_PIN_IO_PU_PD(253),
1789 SH73A0_PIN_IO_PU_PD(254),
1790 SH73A0_PIN_IO_PU_PD(255),
1791 SH73A0_PIN_IO_PU_PD(256),
1792 SH73A0_PIN_IO_PU_PD(257),
1793 SH73A0_PIN_IO_PU_PD(258),
1794 SH73A0_PIN_IO_PU_PD(259),
1795 SH73A0_PIN_IO_PU_PD(260),
1796 SH73A0_PIN_IO_PU_PD(261),
1797 SH73A0_PIN_IO_PU_PD(262),
1798 SH73A0_PIN_IO_PU_PD(263),
1799 SH73A0_PIN_IO_PU_PD(264),
1800 SH73A0_PIN_IO_PU_PD(265),
1801 SH73A0_PIN_IO_PU_PD(266),
1802 SH73A0_PIN_IO_PU_PD(267),
1803 SH73A0_PIN_IO_PU_PD(268),
1804 SH73A0_PIN_IO_PU_PD(269),
1805 SH73A0_PIN_IO_PU_PD(270),
1806 SH73A0_PIN_IO_PU_PD(271),
1807 SH73A0_PIN_IO_PU_PD(272),
1808 SH73A0_PIN_IO_PU_PD(273),
1809 SH73A0_PIN_IO_PU_PD(274),
1810 SH73A0_PIN_IO_PU_PD(275),
1811 SH73A0_PIN_IO_PU_PD(276),
1812 SH73A0_PIN_IO_PU_PD(277),
1813 SH73A0_PIN_IO_PU_PD(278),
1814 SH73A0_PIN_IO_PU_PD(279),
1815 SH73A0_PIN_IO_PU_PD(280),
1816 SH73A0_PIN_O(281),
1817 SH73A0_PIN_O(282),
1818 SH73A0_PIN_I_PU(288),
1819 SH73A0_PIN_IO_PU_PD(289),
1820 SH73A0_PIN_IO_PU_PD(290),
1821 SH73A0_PIN_IO_PU_PD(291),
1822 SH73A0_PIN_IO_PU_PD(292),
1823 SH73A0_PIN_IO_PU_PD(293),
1824 SH73A0_PIN_IO_PU_PD(294),
1825 SH73A0_PIN_IO_PU_PD(295),
1826 SH73A0_PIN_IO_PU_PD(296),
1827 SH73A0_PIN_IO_PU_PD(297),
1828 SH73A0_PIN_IO_PU_PD(298),
1829 SH73A0_PIN_IO_PU_PD(299),
1830 SH73A0_PIN_IO_PU_PD(300),
1831 SH73A0_PIN_IO_PU_PD(301),
1832 SH73A0_PIN_IO_PU_PD(302),
1833 SH73A0_PIN_IO_PU_PD(303),
1834 SH73A0_PIN_IO_PU_PD(304),
1835 SH73A0_PIN_IO_PU_PD(305),
1836 SH73A0_PIN_O(306),
1837 SH73A0_PIN_O(307),
1838 SH73A0_PIN_I_PU(308),
1839 SH73A0_PIN_O(309),
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]1840};
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1841
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]1842static const struct pinmux_range pinmux_ranges[] = {
Guennadi Liakhovetskib58e5fa2013-02-12 16:50:02 +0100[diff] [blame]1843 {.begin = 0, .end = 118,},
1844 {.begin = 128, .end = 164,},
1845 {.begin = 192, .end = 282,},
1846 {.begin = 288, .end = 309,},
1847};
1848
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]1849/* - FSIA ------------------------------------------------------------------- */
1850static const unsigned int fsia_mclk_in_pins[] = {
1851 /* CK */
1852 49,
1853};
1854static const unsigned int fsia_mclk_in_mux[] = {
1855 FSIACK_MARK,
1856};
1857static const unsigned int fsia_mclk_out_pins[] = {
1858 /* OMC */
1859 49,
1860};
1861static const unsigned int fsia_mclk_out_mux[] = {
1862 FSIAOMC_MARK,
1863};
1864static const unsigned int fsia_sclk_in_pins[] = {
1865 /* ILR, IBT */
1866 50, 51,
1867};
1868static const unsigned int fsia_sclk_in_mux[] = {
1869 FSIAILR_MARK, FSIAIBT_MARK,
1870};
1871static const unsigned int fsia_sclk_out_pins[] = {
1872 /* OLR, OBT */
1873 50, 51,
1874};
1875static const unsigned int fsia_sclk_out_mux[] = {
1876 FSIAOLR_MARK, FSIAOBT_MARK,
1877};
1878static const unsigned int fsia_data_in_pins[] = {
1879 /* ISLD */
1880 55,
1881};
1882static const unsigned int fsia_data_in_mux[] = {
1883 FSIAISLD_MARK,
1884};
1885static const unsigned int fsia_data_out_pins[] = {
1886 /* OSLD */
1887 52,
1888};
1889static const unsigned int fsia_data_out_mux[] = {
1890 FSIAOSLD_MARK,
1891};
1892static const unsigned int fsia_spdif_pins[] = {
1893 /* SPDIF */
1894 53,
1895};
1896static const unsigned int fsia_spdif_mux[] = {
1897 FSIASPDIF_MARK,
1898};
1899/* - FSIB ------------------------------------------------------------------- */
1900static const unsigned int fsib_mclk_in_pins[] = {
1901 /* CK */
1902 54,
1903};
1904static const unsigned int fsib_mclk_in_mux[] = {
1905 FSIBCK_MARK,
1906};
1907static const unsigned int fsib_mclk_out_pins[] = {
1908 /* OMC */
1909 54,
1910};
1911static const unsigned int fsib_mclk_out_mux[] = {
1912 FSIBOMC_MARK,
1913};
1914static const unsigned int fsib_sclk_in_pins[] = {
1915 /* ILR, IBT */
1916 37, 36,
1917};
1918static const unsigned int fsib_sclk_in_mux[] = {
1919 FSIBILR_MARK, FSIBIBT_MARK,
1920};
1921static const unsigned int fsib_sclk_out_pins[] = {
1922 /* OLR, OBT */
1923 37, 36,
1924};
1925static const unsigned int fsib_sclk_out_mux[] = {
1926 FSIBOLR_MARK, FSIBOBT_MARK,
1927};
1928static const unsigned int fsib_data_in_pins[] = {
1929 /* ISLD */
1930 39,
1931};
1932static const unsigned int fsib_data_in_mux[] = {
1933 FSIBISLD_MARK,
1934};
1935static const unsigned int fsib_data_out_pins[] = {
1936 /* OSLD */
1937 38,
1938};
1939static const unsigned int fsib_data_out_mux[] = {
1940 FSIBOSLD_MARK,
1941};
1942static const unsigned int fsib_spdif_pins[] = {
1943 /* SPDIF */
1944 53,
1945};
1946static const unsigned int fsib_spdif_mux[] = {
1947 FSIBSPDIF_MARK,
1948};
1949/* - FSIC ------------------------------------------------------------------- */
1950static const unsigned int fsic_mclk_in_pins[] = {
1951 /* CK */
1952 54,
1953};
1954static const unsigned int fsic_mclk_in_mux[] = {
1955 FSICCK_MARK,
1956};
1957static const unsigned int fsic_mclk_out_pins[] = {
1958 /* OMC */
1959 54,
1960};
1961static const unsigned int fsic_mclk_out_mux[] = {
1962 FSICOMC_MARK,
1963};
1964static const unsigned int fsic_sclk_in_pins[] = {
1965 /* ILR, IBT */
1966 46, 45,
1967};
1968static const unsigned int fsic_sclk_in_mux[] = {
1969 FSICILR_MARK, FSICIBT_MARK,
1970};
1971static const unsigned int fsic_sclk_out_pins[] = {
1972 /* OLR, OBT */
1973 46, 45,
1974};
1975static const unsigned int fsic_sclk_out_mux[] = {
1976 FSICOLR_MARK, FSICOBT_MARK,
1977};
1978static const unsigned int fsic_data_in_pins[] = {
1979 /* ISLD */
1980 48,
1981};
1982static const unsigned int fsic_data_in_mux[] = {
1983 FSICISLD_MARK,
1984};
1985static const unsigned int fsic_data_out_pins[] = {
1986 /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1987 47, 44, 42, 16,
1988};
1989static const unsigned int fsic_data_out_mux[] = {
1990 FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1991};
1992static const unsigned int fsic_spdif_0_pins[] = {
1993 /* SPDIF */
1994 53,
1995};
1996static const unsigned int fsic_spdif_0_mux[] = {
1997 PORT53_FSICSPDIF_MARK,
1998};
1999static const unsigned int fsic_spdif_1_pins[] = {
2000 /* SPDIF */
2001 47,
2002};
2003static const unsigned int fsic_spdif_1_mux[] = {
2004 PORT47_FSICSPDIF_MARK,
2005};
2006/* - FSID ------------------------------------------------------------------- */
2007static const unsigned int fsid_sclk_in_pins[] = {
2008 /* ILR, IBT */
2009 46, 45,
2010};
2011static const unsigned int fsid_sclk_in_mux[] = {
2012 FSIDILR_MARK, FSIDIBT_MARK,
2013};
2014static const unsigned int fsid_sclk_out_pins[] = {
2015 /* OLR, OBT */
2016 46, 45,
2017};
2018static const unsigned int fsid_sclk_out_mux[] = {
2019 FSIDOLR_MARK, FSIDOBT_MARK,
2020};
2021static const unsigned int fsid_data_in_pins[] = {
2022 /* ISLD */
2023 48,
2024};
2025static const unsigned int fsid_data_in_mux[] = {
2026 FSIDISLD_MARK,
2027};
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]2028/* - I2C2 ------------------------------------------------------------------- */
2029static const unsigned int i2c2_0_pins[] = {
2030 /* SCL, SDA */
2031 237, 236,
2032};
2033static const unsigned int i2c2_0_mux[] = {
2034 PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
2035};
2036static const unsigned int i2c2_1_pins[] = {
2037 /* SCL, SDA */
2038 27, 28,
2039};
2040static const unsigned int i2c2_1_mux[] = {
2041 PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
2042};
2043static const unsigned int i2c2_2_pins[] = {
2044 /* SCL, SDA */
2045 115, 116,
2046};
2047static const unsigned int i2c2_2_mux[] = {
2048 PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
2049};
2050/* - I2C3 ------------------------------------------------------------------- */
2051static const unsigned int i2c3_0_pins[] = {
2052 /* SCL, SDA */
2053 248, 249,
2054};
2055static const unsigned int i2c3_0_mux[] = {
2056 PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
2057};
2058static const unsigned int i2c3_1_pins[] = {
2059 /* SCL, SDA */
2060 27, 28,
2061};
2062static const unsigned int i2c3_1_mux[] = {
2063 PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
2064};
2065static const unsigned int i2c3_2_pins[] = {
2066 /* SCL, SDA */
2067 115, 116,
2068};
2069static const unsigned int i2c3_2_mux[] = {
2070 PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
2071};
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2072/* - LCD -------------------------------------------------------------------- */
2073static const unsigned int lcd_data8_pins[] = {
2074 /* D[0:7] */
2075 192, 193, 194, 195, 196, 197, 198, 199,
2076};
2077static const unsigned int lcd_data8_mux[] = {
2078 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2079 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2080};
2081static const unsigned int lcd_data9_pins[] = {
2082 /* D[0:8] */
2083 192, 193, 194, 195, 196, 197, 198, 199,
2084 200,
2085};
2086static const unsigned int lcd_data9_mux[] = {
2087 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2088 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2089 LCDD8_MARK,
2090};
2091static const unsigned int lcd_data12_pins[] = {
2092 /* D[0:11] */
2093 192, 193, 194, 195, 196, 197, 198, 199,
2094 200, 201, 202, 203,
2095};
2096static const unsigned int lcd_data12_mux[] = {
2097 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2098 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2099 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2100};
2101static const unsigned int lcd_data16_pins[] = {
2102 /* D[0:15] */
2103 192, 193, 194, 195, 196, 197, 198, 199,
2104 200, 201, 202, 203, 204, 205, 206, 207,
2105};
2106static const unsigned int lcd_data16_mux[] = {
2107 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2108 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2109 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2110 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2111};
2112static const unsigned int lcd_data18_pins[] = {
2113 /* D[0:17] */
2114 192, 193, 194, 195, 196, 197, 198, 199,
2115 200, 201, 202, 203, 204, 205, 206, 207,
2116 208, 209,
2117};
2118static const unsigned int lcd_data18_mux[] = {
2119 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2120 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2121 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2122 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2123 LCDD16_MARK, LCDD17_MARK,
2124};
2125static const unsigned int lcd_data24_pins[] = {
2126 /* D[0:23] */
2127 192, 193, 194, 195, 196, 197, 198, 199,
2128 200, 201, 202, 203, 204, 205, 206, 207,
2129 208, 209, 210, 211, 212, 213, 214, 215
2130};
2131static const unsigned int lcd_data24_mux[] = {
2132 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2133 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2134 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2135 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2136 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2137 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2138};
2139static const unsigned int lcd_display_pins[] = {
2140 /* DON */
2141 222,
2142};
2143static const unsigned int lcd_display_mux[] = {
2144 LCDDON_MARK,
2145};
2146static const unsigned int lcd_lclk_pins[] = {
2147 /* LCLK */
2148 221,
2149};
2150static const unsigned int lcd_lclk_mux[] = {
2151 LCDLCLK_MARK,
2152};
2153static const unsigned int lcd_sync_pins[] = {
2154 /* VSYN, HSYN, DCK, DISP */
2155 220, 218, 216, 219,
2156};
2157static const unsigned int lcd_sync_mux[] = {
2158 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2159};
2160static const unsigned int lcd_sys_pins[] = {
2161 /* CS, WR, RD, RS */
2162 218, 216, 217, 219,
2163};
2164static const unsigned int lcd_sys_mux[] = {
2165 LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2166};
2167/* - LCD2 ------------------------------------------------------------------- */
2168static const unsigned int lcd2_data8_pins[] = {
2169 /* D[0:7] */
2170 128, 129, 142, 143, 144, 145, 138, 139,
2171};
2172static const unsigned int lcd2_data8_mux[] = {
2173 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2174 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2175};
2176static const unsigned int lcd2_data9_pins[] = {
2177 /* D[0:8] */
2178 128, 129, 142, 143, 144, 145, 138, 139,
2179 140,
2180};
2181static const unsigned int lcd2_data9_mux[] = {
2182 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2183 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2184 LCD2D8_MARK,
2185};
2186static const unsigned int lcd2_data12_pins[] = {
2187 /* D[0:12] */
2188 128, 129, 142, 143, 144, 145, 138, 139,
2189 140, 141, 130, 131,
2190};
2191static const unsigned int lcd2_data12_mux[] = {
2192 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2193 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2194 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2195};
2196static const unsigned int lcd2_data16_pins[] = {
2197 /* D[0:15] */
2198 128, 129, 142, 143, 144, 145, 138, 139,
2199 140, 141, 130, 131, 132, 133, 134, 135,
2200};
2201static const unsigned int lcd2_data16_mux[] = {
2202 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2203 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2204 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2205 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2206};
2207static const unsigned int lcd2_data18_pins[] = {
2208 /* D[0:17] */
2209 128, 129, 142, 143, 144, 145, 138, 139,
2210 140, 141, 130, 131, 132, 133, 134, 135,
2211 136, 137,
2212};
2213static const unsigned int lcd2_data18_mux[] = {
2214 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2215 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2216 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2217 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2218 LCD2D16_MARK, LCD2D17_MARK,
2219};
2220static const unsigned int lcd2_data24_pins[] = {
2221 /* D[0:23] */
2222 128, 129, 142, 143, 144, 145, 138, 139,
2223 140, 141, 130, 131, 132, 133, 134, 135,
2224 136, 137, 146, 147, 234, 235, 238, 239
2225};
2226static const unsigned int lcd2_data24_mux[] = {
2227 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2228 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2229 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2230 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2231 LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2232 LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2233};
2234static const unsigned int lcd2_sync_0_pins[] = {
2235 /* VSYN, HSYN, DCK, DISP */
2236 128, 129, 146, 145,
2237};
2238static const unsigned int lcd2_sync_0_mux[] = {
2239 PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2240 LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2241};
2242static const unsigned int lcd2_sync_1_pins[] = {
2243 /* VSYN, HSYN, DCK, DISP */
2244 222, 221, 219, 217,
2245};
2246static const unsigned int lcd2_sync_1_mux[] = {
2247 PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2248 LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2249};
2250static const unsigned int lcd2_sys_0_pins[] = {
2251 /* CS, WR, RD, RS */
2252 129, 146, 147, 145,
2253};
2254static const unsigned int lcd2_sys_0_mux[] = {
2255 PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2256 LCD2RD__MARK, PORT145_LCD2RS_MARK,
2257};
2258static const unsigned int lcd2_sys_1_pins[] = {
2259 /* CS, WR, RD, RS */
2260 221, 219, 147, 217,
2261};
2262static const unsigned int lcd2_sys_1_mux[] = {
2263 PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2264 LCD2RD__MARK, PORT217_LCD2RS_MARK,
2265};
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame^]2266/* - MMCIF ------------------------------------------------------------------ */
2267static const unsigned int mmc0_data1_0_pins[] = {
2268 /* D[0] */
2269 271,
2270};
2271static const unsigned int mmc0_data1_0_mux[] = {
2272 MMCD0_0_MARK,
2273};
2274static const unsigned int mmc0_data4_0_pins[] = {
2275 /* D[0:3] */
2276 271, 272, 273, 274,
2277};
2278static const unsigned int mmc0_data4_0_mux[] = {
2279 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2280};
2281static const unsigned int mmc0_data8_0_pins[] = {
2282 /* D[0:7] */
2283 271, 272, 273, 274, 275, 276, 277, 278,
2284};
2285static const unsigned int mmc0_data8_0_mux[] = {
2286 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2287 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2288};
2289static const unsigned int mmc0_ctrl_0_pins[] = {
2290 /* CMD, CLK */
2291 279, 270,
2292};
2293static const unsigned int mmc0_ctrl_0_mux[] = {
2294 MMCCMD0_MARK, MMCCLK0_MARK,
2295};
2296
2297static const unsigned int mmc0_data1_1_pins[] = {
2298 /* D[0] */
2299 305,
2300};
2301static const unsigned int mmc0_data1_1_mux[] = {
2302 MMCD1_0_MARK,
2303};
2304static const unsigned int mmc0_data4_1_pins[] = {
2305 /* D[0:3] */
2306 305, 304, 303, 302,
2307};
2308static const unsigned int mmc0_data4_1_mux[] = {
2309 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2310};
2311static const unsigned int mmc0_data8_1_pins[] = {
2312 /* D[0:7] */
2313 305, 304, 303, 302, 301, 300, 299, 298,
2314};
2315static const unsigned int mmc0_data8_1_mux[] = {
2316 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2317 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
2318};
2319static const unsigned int mmc0_ctrl_1_pins[] = {
2320 /* CMD, CLK */
2321 297, 289,
2322};
2323static const unsigned int mmc0_ctrl_1_mux[] = {
2324 MMCCMD1_MARK, MMCCLK1_MARK,
2325};
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]2326/* - SCIFA0 ----------------------------------------------------------------- */
2327static const unsigned int scifa0_data_pins[] = {
2328 /* RXD, TXD */
2329 43, 17,
2330};
2331static const unsigned int scifa0_data_mux[] = {
2332 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2333};
2334static const unsigned int scifa0_clk_pins[] = {
2335 /* SCK */
2336 16,
2337};
2338static const unsigned int scifa0_clk_mux[] = {
2339 SCIFA0_SCK_MARK,
2340};
2341static const unsigned int scifa0_ctrl_pins[] = {
2342 /* RTS, CTS */
2343 42, 44,
2344};
2345static const unsigned int scifa0_ctrl_mux[] = {
2346 SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2347};
2348/* - SCIFA1 ----------------------------------------------------------------- */
2349static const unsigned int scifa1_data_pins[] = {
2350 /* RXD, TXD */
2351 228, 225,
2352};
2353static const unsigned int scifa1_data_mux[] = {
2354 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2355};
2356static const unsigned int scifa1_clk_pins[] = {
2357 /* SCK */
2358 226,
2359};
2360static const unsigned int scifa1_clk_mux[] = {
2361 SCIFA1_SCK_MARK,
2362};
2363static const unsigned int scifa1_ctrl_pins[] = {
2364 /* RTS, CTS */
2365 227, 229,
2366};
2367static const unsigned int scifa1_ctrl_mux[] = {
2368 SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2369};
2370/* - SCIFA2 ----------------------------------------------------------------- */
2371static const unsigned int scifa2_data_0_pins[] = {
2372 /* RXD, TXD */
2373 155, 154,
2374};
2375static const unsigned int scifa2_data_0_mux[] = {
2376 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2377};
2378static const unsigned int scifa2_clk_0_pins[] = {
2379 /* SCK */
2380 158,
2381};
2382static const unsigned int scifa2_clk_0_mux[] = {
2383 SCIFA2_SCK1_MARK,
2384};
2385static const unsigned int scifa2_ctrl_0_pins[] = {
2386 /* RTS, CTS */
2387 156, 157,
2388};
2389static const unsigned int scifa2_ctrl_0_mux[] = {
2390 SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2391};
2392static const unsigned int scifa2_data_1_pins[] = {
2393 /* RXD, TXD */
2394 233, 230,
2395};
2396static const unsigned int scifa2_data_1_mux[] = {
2397 SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2398};
2399static const unsigned int scifa2_clk_1_pins[] = {
2400 /* SCK */
2401 232,
2402};
2403static const unsigned int scifa2_clk_1_mux[] = {
2404 SCIFA2_SCK2_MARK,
2405};
2406static const unsigned int scifa2_ctrl_1_pins[] = {
2407 /* RTS, CTS */
2408 234, 231,
2409};
2410static const unsigned int scifa2_ctrl_1_mux[] = {
2411 SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2412};
2413/* - SCIFA3 ----------------------------------------------------------------- */
2414static const unsigned int scifa3_data_pins[] = {
2415 /* RXD, TXD */
2416 108, 110,
2417};
2418static const unsigned int scifa3_data_mux[] = {
2419 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2420};
2421static const unsigned int scifa3_ctrl_pins[] = {
2422 /* RTS, CTS */
2423 109, 107,
2424};
2425static const unsigned int scifa3_ctrl_mux[] = {
2426 SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2427};
2428/* - SCIFA4 ----------------------------------------------------------------- */
2429static const unsigned int scifa4_data_pins[] = {
2430 /* RXD, TXD */
2431 33, 32,
2432};
2433static const unsigned int scifa4_data_mux[] = {
2434 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2435};
2436static const unsigned int scifa4_ctrl_pins[] = {
2437 /* RTS, CTS */
2438 34, 35,
2439};
2440static const unsigned int scifa4_ctrl_mux[] = {
2441 SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2442};
2443/* - SCIFA5 ----------------------------------------------------------------- */
2444static const unsigned int scifa5_data_0_pins[] = {
2445 /* RXD, TXD */
2446 246, 247,
2447};
2448static const unsigned int scifa5_data_0_mux[] = {
2449 PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2450};
2451static const unsigned int scifa5_clk_0_pins[] = {
2452 /* SCK */
2453 248,
2454};
2455static const unsigned int scifa5_clk_0_mux[] = {
2456 PORT248_SCIFA5_SCK_MARK,
2457};
2458static const unsigned int scifa5_ctrl_0_pins[] = {
2459 /* RTS, CTS */
2460 245, 244,
2461};
2462static const unsigned int scifa5_ctrl_0_mux[] = {
2463 PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2464};
2465static const unsigned int scifa5_data_1_pins[] = {
2466 /* RXD, TXD */
2467 195, 196,
2468};
2469static const unsigned int scifa5_data_1_mux[] = {
2470 PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2471};
2472static const unsigned int scifa5_clk_1_pins[] = {
2473 /* SCK */
2474 197,
2475};
2476static const unsigned int scifa5_clk_1_mux[] = {
2477 PORT197_SCIFA5_SCK_MARK,
2478};
2479static const unsigned int scifa5_ctrl_1_pins[] = {
2480 /* RTS, CTS */
2481 194, 193,
2482};
2483static const unsigned int scifa5_ctrl_1_mux[] = {
2484 PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2485};
2486static const unsigned int scifa5_data_2_pins[] = {
2487 /* RXD, TXD */
2488 162, 160,
2489};
2490static const unsigned int scifa5_data_2_mux[] = {
2491 PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2492};
2493static const unsigned int scifa5_clk_2_pins[] = {
2494 /* SCK */
2495 159,
2496};
2497static const unsigned int scifa5_clk_2_mux[] = {
2498 PORT159_SCIFA5_SCK_MARK,
2499};
2500static const unsigned int scifa5_ctrl_2_pins[] = {
2501 /* RTS, CTS */
2502 163, 161,
2503};
2504static const unsigned int scifa5_ctrl_2_mux[] = {
2505 PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2506};
2507/* - SCIFA6 ----------------------------------------------------------------- */
2508static const unsigned int scifa6_pins[] = {
2509 /* TXD */
2510 240,
2511};
2512static const unsigned int scifa6_mux[] = {
2513 SCIFA6_TXD_MARK,
2514};
2515/* - SCIFA7 ----------------------------------------------------------------- */
2516static const unsigned int scifa7_data_pins[] = {
2517 /* RXD, TXD */
2518 12, 18,
2519};
2520static const unsigned int scifa7_data_mux[] = {
2521 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2522};
2523static const unsigned int scifa7_ctrl_pins[] = {
2524 /* RTS, CTS */
2525 19, 13,
2526};
2527static const unsigned int scifa7_ctrl_mux[] = {
2528 SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2529};
2530/* - SCIFB ------------------------------------------------------------------ */
2531static const unsigned int scifb_data_0_pins[] = {
2532 /* RXD, TXD */
2533 162, 160,
2534};
2535static const unsigned int scifb_data_0_mux[] = {
2536 PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2537};
2538static const unsigned int scifb_clk_0_pins[] = {
2539 /* SCK */
2540 159,
2541};
2542static const unsigned int scifb_clk_0_mux[] = {
2543 PORT159_SCIFB_SCK_MARK,
2544};
2545static const unsigned int scifb_ctrl_0_pins[] = {
2546 /* RTS, CTS */
2547 163, 161,
2548};
2549static const unsigned int scifb_ctrl_0_mux[] = {
2550 PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2551};
2552static const unsigned int scifb_data_1_pins[] = {
2553 /* RXD, TXD */
2554 246, 247,
2555};
2556static const unsigned int scifb_data_1_mux[] = {
2557 PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2558};
2559static const unsigned int scifb_clk_1_pins[] = {
2560 /* SCK */
2561 248,
2562};
2563static const unsigned int scifb_clk_1_mux[] = {
2564 PORT248_SCIFB_SCK_MARK,
2565};
2566static const unsigned int scifb_ctrl_1_pins[] = {
2567 /* RTS, CTS */
2568 245, 244,
2569};
2570static const unsigned int scifb_ctrl_1_mux[] = {
2571 PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2572};
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame^]2573/* - SDHI0 ------------------------------------------------------------------ */
2574static const unsigned int sdhi0_data1_pins[] = {
2575 /* D0 */
2576 252,
2577};
2578static const unsigned int sdhi0_data1_mux[] = {
2579 SDHID0_0_MARK,
2580};
2581static const unsigned int sdhi0_data4_pins[] = {
2582 /* D[0:3] */
2583 252, 253, 254, 255,
2584};
2585static const unsigned int sdhi0_data4_mux[] = {
2586 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2587};
2588static const unsigned int sdhi0_ctrl_pins[] = {
2589 /* CMD, CLK */
2590 256, 250,
2591};
2592static const unsigned int sdhi0_ctrl_mux[] = {
2593 SDHICMD0_MARK, SDHICLK0_MARK,
2594};
2595static const unsigned int sdhi0_cd_pins[] = {
2596 /* CD */
2597 251,
2598};
2599static const unsigned int sdhi0_cd_mux[] = {
2600 SDHICD0_MARK,
2601};
2602static const unsigned int sdhi0_wp_pins[] = {
2603 /* WP */
2604 257,
2605};
2606static const unsigned int sdhi0_wp_mux[] = {
2607 SDHIWP0_MARK,
2608};
2609/* - SDHI1 ------------------------------------------------------------------ */
2610static const unsigned int sdhi1_data1_pins[] = {
2611 /* D0 */
2612 259,
2613};
2614static const unsigned int sdhi1_data1_mux[] = {
2615 SDHID1_0_MARK,
2616};
2617static const unsigned int sdhi1_data4_pins[] = {
2618 /* D[0:3] */
2619 259, 260, 261, 262,
2620};
2621static const unsigned int sdhi1_data4_mux[] = {
2622 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2623};
2624static const unsigned int sdhi1_ctrl_pins[] = {
2625 /* CMD, CLK */
2626 263, 258,
2627};
2628static const unsigned int sdhi1_ctrl_mux[] = {
2629 SDHICMD1_MARK, SDHICLK1_MARK,
2630};
2631/* - SDHI2 ------------------------------------------------------------------ */
2632static const unsigned int sdhi2_data1_pins[] = {
2633 /* D0 */
2634 265,
2635};
2636static const unsigned int sdhi2_data1_mux[] = {
2637 SDHID2_0_MARK,
2638};
2639static const unsigned int sdhi2_data4_pins[] = {
2640 /* D[0:3] */
2641 265, 266, 267, 268,
2642};
2643static const unsigned int sdhi2_data4_mux[] = {
2644 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2645};
2646static const unsigned int sdhi2_ctrl_pins[] = {
2647 /* CMD, CLK */
2648 269, 264,
2649};
2650static const unsigned int sdhi2_ctrl_mux[] = {
2651 SDHICMD2_MARK, SDHICLK2_MARK,
2652};
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2653
2654static const struct sh_pfc_pin_group pinmux_groups[] = {
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]2655 SH_PFC_PIN_GROUP(fsia_mclk_in),
2656 SH_PFC_PIN_GROUP(fsia_mclk_out),
2657 SH_PFC_PIN_GROUP(fsia_sclk_in),
2658 SH_PFC_PIN_GROUP(fsia_sclk_out),
2659 SH_PFC_PIN_GROUP(fsia_data_in),
2660 SH_PFC_PIN_GROUP(fsia_data_out),
2661 SH_PFC_PIN_GROUP(fsia_spdif),
2662 SH_PFC_PIN_GROUP(fsib_mclk_in),
2663 SH_PFC_PIN_GROUP(fsib_mclk_out),
2664 SH_PFC_PIN_GROUP(fsib_sclk_in),
2665 SH_PFC_PIN_GROUP(fsib_sclk_out),
2666 SH_PFC_PIN_GROUP(fsib_data_in),
2667 SH_PFC_PIN_GROUP(fsib_data_out),
2668 SH_PFC_PIN_GROUP(fsib_spdif),
2669 SH_PFC_PIN_GROUP(fsic_mclk_in),
2670 SH_PFC_PIN_GROUP(fsic_mclk_out),
2671 SH_PFC_PIN_GROUP(fsic_sclk_in),
2672 SH_PFC_PIN_GROUP(fsic_sclk_out),
2673 SH_PFC_PIN_GROUP(fsic_data_in),
2674 SH_PFC_PIN_GROUP(fsic_data_out),
2675 SH_PFC_PIN_GROUP(fsic_spdif_0),
2676 SH_PFC_PIN_GROUP(fsic_spdif_1),
2677 SH_PFC_PIN_GROUP(fsid_sclk_in),
2678 SH_PFC_PIN_GROUP(fsid_sclk_out),
2679 SH_PFC_PIN_GROUP(fsid_data_in),
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]2680 SH_PFC_PIN_GROUP(i2c2_0),
2681 SH_PFC_PIN_GROUP(i2c2_1),
2682 SH_PFC_PIN_GROUP(i2c2_2),
2683 SH_PFC_PIN_GROUP(i2c3_0),
2684 SH_PFC_PIN_GROUP(i2c3_1),
2685 SH_PFC_PIN_GROUP(i2c3_2),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2686 SH_PFC_PIN_GROUP(lcd_data8),
2687 SH_PFC_PIN_GROUP(lcd_data9),
2688 SH_PFC_PIN_GROUP(lcd_data12),
2689 SH_PFC_PIN_GROUP(lcd_data16),
2690 SH_PFC_PIN_GROUP(lcd_data18),
2691 SH_PFC_PIN_GROUP(lcd_data24),
2692 SH_PFC_PIN_GROUP(lcd_display),
2693 SH_PFC_PIN_GROUP(lcd_lclk),
2694 SH_PFC_PIN_GROUP(lcd_sync),
2695 SH_PFC_PIN_GROUP(lcd_sys),
2696 SH_PFC_PIN_GROUP(lcd2_data8),
2697 SH_PFC_PIN_GROUP(lcd2_data9),
2698 SH_PFC_PIN_GROUP(lcd2_data12),
2699 SH_PFC_PIN_GROUP(lcd2_data16),
2700 SH_PFC_PIN_GROUP(lcd2_data18),
2701 SH_PFC_PIN_GROUP(lcd2_data24),
2702 SH_PFC_PIN_GROUP(lcd2_sync_0),
2703 SH_PFC_PIN_GROUP(lcd2_sync_1),
2704 SH_PFC_PIN_GROUP(lcd2_sys_0),
2705 SH_PFC_PIN_GROUP(lcd2_sys_1),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame^]2706 SH_PFC_PIN_GROUP(mmc0_data1_0),
2707 SH_PFC_PIN_GROUP(mmc0_data4_0),
2708 SH_PFC_PIN_GROUP(mmc0_data8_0),
2709 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2710 SH_PFC_PIN_GROUP(mmc0_data1_1),
2711 SH_PFC_PIN_GROUP(mmc0_data4_1),
2712 SH_PFC_PIN_GROUP(mmc0_data8_1),
2713 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]2714 SH_PFC_PIN_GROUP(scifa0_data),
2715 SH_PFC_PIN_GROUP(scifa0_clk),
2716 SH_PFC_PIN_GROUP(scifa0_ctrl),
2717 SH_PFC_PIN_GROUP(scifa1_data),
2718 SH_PFC_PIN_GROUP(scifa1_clk),
2719 SH_PFC_PIN_GROUP(scifa1_ctrl),
2720 SH_PFC_PIN_GROUP(scifa2_data_0),
2721 SH_PFC_PIN_GROUP(scifa2_clk_0),
2722 SH_PFC_PIN_GROUP(scifa2_ctrl_0),
2723 SH_PFC_PIN_GROUP(scifa2_data_1),
2724 SH_PFC_PIN_GROUP(scifa2_clk_1),
2725 SH_PFC_PIN_GROUP(scifa2_ctrl_1),
2726 SH_PFC_PIN_GROUP(scifa3_data),
2727 SH_PFC_PIN_GROUP(scifa3_ctrl),
2728 SH_PFC_PIN_GROUP(scifa4_data),
2729 SH_PFC_PIN_GROUP(scifa4_ctrl),
2730 SH_PFC_PIN_GROUP(scifa5_data_0),
2731 SH_PFC_PIN_GROUP(scifa5_clk_0),
2732 SH_PFC_PIN_GROUP(scifa5_ctrl_0),
2733 SH_PFC_PIN_GROUP(scifa5_data_1),
2734 SH_PFC_PIN_GROUP(scifa5_clk_1),
2735 SH_PFC_PIN_GROUP(scifa5_ctrl_1),
2736 SH_PFC_PIN_GROUP(scifa5_data_2),
2737 SH_PFC_PIN_GROUP(scifa5_clk_2),
2738 SH_PFC_PIN_GROUP(scifa5_ctrl_2),
2739 SH_PFC_PIN_GROUP(scifa6),
2740 SH_PFC_PIN_GROUP(scifa7_data),
2741 SH_PFC_PIN_GROUP(scifa7_ctrl),
2742 SH_PFC_PIN_GROUP(scifb_data_0),
2743 SH_PFC_PIN_GROUP(scifb_clk_0),
2744 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2745 SH_PFC_PIN_GROUP(scifb_data_1),
2746 SH_PFC_PIN_GROUP(scifb_clk_1),
2747 SH_PFC_PIN_GROUP(scifb_ctrl_1),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame^]2748 SH_PFC_PIN_GROUP(sdhi0_data1),
2749 SH_PFC_PIN_GROUP(sdhi0_data4),
2750 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2751 SH_PFC_PIN_GROUP(sdhi0_cd),
2752 SH_PFC_PIN_GROUP(sdhi0_wp),
2753 SH_PFC_PIN_GROUP(sdhi1_data1),
2754 SH_PFC_PIN_GROUP(sdhi1_data4),
2755 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2756 SH_PFC_PIN_GROUP(sdhi2_data1),
2757 SH_PFC_PIN_GROUP(sdhi2_data4),
2758 SH_PFC_PIN_GROUP(sdhi2_ctrl),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2759};
2760
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]2761static const char * const fsia_groups[] = {
2762 "fsia_mclk_in",
2763 "fsia_mclk_out",
2764 "fsia_sclk_in",
2765 "fsia_sclk_out",
2766 "fsia_data_in",
2767 "fsia_data_out",
2768 "fsia_spdif",
2769};
2770
2771static const char * const fsib_groups[] = {
2772 "fsib_mclk_in",
2773 "fsib_mclk_out",
2774 "fsib_sclk_in",
2775 "fsib_sclk_out",
2776 "fsib_data_in",
2777 "fsib_data_out",
2778 "fsib_spdif",
2779};
2780
2781static const char * const fsic_groups[] = {
2782 "fsic_mclk_in",
2783 "fsic_mclk_out",
2784 "fsic_sclk_in",
2785 "fsic_sclk_out",
2786 "fsic_data_in",
2787 "fsic_data_out",
2788 "fsic_spdif",
2789};
2790
2791static const char * const fsid_groups[] = {
2792 "fsid_sclk_in",
2793 "fsid_sclk_out",
2794 "fsid_data_in",
2795};
2796
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]2797static const char * const i2c2_groups[] = {
2798 "i2c2_0",
2799 "i2c2_1",
2800 "i2c2_2",
2801};
2802
2803static const char * const i2c3_groups[] = {
2804 "i2c3_0",
2805 "i2c3_1",
2806 "i2c3_2",
2807};
2808
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2809static const char * const lcd_groups[] = {
2810 "lcd_data8",
2811 "lcd_data9",
2812 "lcd_data12",
2813 "lcd_data16",
2814 "lcd_data18",
2815 "lcd_data24",
2816 "lcd_display",
2817 "lcd_lclk",
2818 "lcd_sync",
2819 "lcd_sys",
2820};
2821
2822static const char * const lcd2_groups[] = {
2823 "lcd2_data8",
2824 "lcd2_data9",
2825 "lcd2_data12",
2826 "lcd2_data16",
2827 "lcd2_data18",
2828 "lcd2_data24",
2829 "lcd2_sync_0",
2830 "lcd2_sync_1",
2831 "lcd2_sys_0",
2832 "lcd2_sys_1",
2833};
2834
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame^]2835static const char * const mmc0_groups[] = {
2836 "mmc0_data1_0",
2837 "mmc0_data4_0",
2838 "mmc0_data8_0",
2839 "mmc0_ctrl_0",
2840 "mmc0_data1_1",
2841 "mmc0_data4_1",
2842 "mmc0_data8_1",
2843 "mmc0_ctrl_1",
2844};
2845
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]2846static const char * const scifa0_groups[] = {
2847 "scifa0_data",
2848 "scifa0_clk",
2849 "scifa0_ctrl",
2850};
2851
2852static const char * const scifa1_groups[] = {
2853 "scifa1_data",
2854 "scifa1_clk",
2855 "scifa1_ctrl",
2856};
2857
2858static const char * const scifa2_groups[] = {
2859 "scifa2_data_0",
2860 "scifa2_clk_0",
2861 "scifa2_ctrl_0",
2862 "scifa2_data_1",
2863 "scifa2_clk_1",
2864 "scifa2_ctrl_1",
2865};
2866
2867static const char * const scifa3_groups[] = {
2868 "scifa3_data",
2869 "scifa3_ctrl",
2870};
2871
2872static const char * const scifa4_groups[] = {
2873 "scifa4_data",
2874 "scifa4_ctrl",
2875};
2876
2877static const char * const scifa5_groups[] = {
2878 "scifa5_data_0",
2879 "scifa5_clk_0",
2880 "scifa5_ctrl_0",
2881 "scifa5_data_1",
2882 "scifa5_clk_1",
2883 "scifa5_ctrl_1",
2884 "scifa5_data_2",
2885 "scifa5_clk_2",
2886 "scifa5_ctrl_2",
2887};
2888
2889static const char * const scifa6_groups[] = {
2890 "scifa6",
2891};
2892
2893static const char * const scifa7_groups[] = {
2894 "scifa7_data",
2895 "scifa7_ctrl",
2896};
2897
2898static const char * const scifb_groups[] = {
2899 "scifb_data_0",
2900 "scifb_clk_0",
2901 "scifb_ctrl_0",
2902 "scifb_data_1",
2903 "scifb_clk_1",
2904 "scifb_ctrl_1",
2905};
2906
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame^]2907static const char * const sdhi0_groups[] = {
2908 "sdhi0_data1",
2909 "sdhi0_data4",
2910 "sdhi0_ctrl",
2911 "sdhi0_cd",
2912 "sdhi0_wp",
2913};
2914
2915static const char * const sdhi1_groups[] = {
2916 "sdhi1_data1",
2917 "sdhi1_data4",
2918 "sdhi1_ctrl",
2919};
2920
2921static const char * const sdhi2_groups[] = {
2922 "sdhi2_data1",
2923 "sdhi2_data4",
2924 "sdhi2_ctrl",
2925};
2926
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2927static const struct sh_pfc_function pinmux_functions[] = {
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]2928 SH_PFC_FUNCTION(fsia),
2929 SH_PFC_FUNCTION(fsib),
2930 SH_PFC_FUNCTION(fsic),
2931 SH_PFC_FUNCTION(fsid),
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]2932 SH_PFC_FUNCTION(i2c2),
2933 SH_PFC_FUNCTION(i2c3),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2934 SH_PFC_FUNCTION(lcd),
2935 SH_PFC_FUNCTION(lcd2),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame^]2936 SH_PFC_FUNCTION(mmc0),
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]2937 SH_PFC_FUNCTION(scifa0),
2938 SH_PFC_FUNCTION(scifa1),
2939 SH_PFC_FUNCTION(scifa2),
2940 SH_PFC_FUNCTION(scifa3),
2941 SH_PFC_FUNCTION(scifa4),
2942 SH_PFC_FUNCTION(scifa5),
2943 SH_PFC_FUNCTION(scifa6),
2944 SH_PFC_FUNCTION(scifa7),
2945 SH_PFC_FUNCTION(scifb),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame^]2946 SH_PFC_FUNCTION(sdhi0),
2947 SH_PFC_FUNCTION(sdhi1),
2948 SH_PFC_FUNCTION(sdhi2),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2949};
2950
Guennadi Liakhovetskib58e5fa2013-02-12 16:50:02 +0100[diff] [blame]2951#define PINMUX_FN_BASE GPIO_FN_VBUS_0
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]2952
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]2953static const struct pinmux_func pinmux_func_gpios[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]2954 /* Table 25-1 (Functions 0-7) */
2955 GPIO_FN(VBUS_0),
2956 GPIO_FN(GPI0),
2957 GPIO_FN(GPI1),
2958 GPIO_FN(GPI2),
2959 GPIO_FN(GPI3),
2960 GPIO_FN(GPI4),
2961 GPIO_FN(GPI5),
2962 GPIO_FN(GPI6),
2963 GPIO_FN(GPI7),
2964 GPIO_FN(SCIFA7_RXD),
2965 GPIO_FN(SCIFA7_CTS_),
2966 GPIO_FN(GPO7), \
2967 GPIO_FN(MFG0_OUT2),
2968 GPIO_FN(GPO6), \
2969 GPIO_FN(MFG1_OUT2),
2970 GPIO_FN(GPO5), \
2971 GPIO_FN(SCIFA0_SCK), \
2972 GPIO_FN(FSICOSLDT3), \
2973 GPIO_FN(PORT16_VIO_CKOR),
2974 GPIO_FN(SCIFA0_TXD),
2975 GPIO_FN(SCIFA7_TXD),
2976 GPIO_FN(SCIFA7_RTS_), \
2977 GPIO_FN(PORT19_VIO_CKO2),
2978 GPIO_FN(GPO0),
2979 GPIO_FN(GPO1),
2980 GPIO_FN(GPO2), \
2981 GPIO_FN(STATUS0),
2982 GPIO_FN(GPO3), \
2983 GPIO_FN(STATUS1),
2984 GPIO_FN(GPO4), \
2985 GPIO_FN(STATUS2),
2986 GPIO_FN(VINT),
2987 GPIO_FN(TCKON),
2988 GPIO_FN(XDVFS1), \
2989 GPIO_FN(PORT27_I2C_SCL2), \
2990 GPIO_FN(PORT27_I2C_SCL3), \
2991 GPIO_FN(MFG0_OUT1), \
2992 GPIO_FN(PORT27_IROUT),
2993 GPIO_FN(XDVFS2), \
2994 GPIO_FN(PORT28_I2C_SDA2), \
2995 GPIO_FN(PORT28_I2C_SDA3), \
2996 GPIO_FN(PORT28_TPU1TO1),
2997 GPIO_FN(SIM_RST), \
2998 GPIO_FN(PORT29_TPU1TO1),
2999 GPIO_FN(SIM_CLK), \
3000 GPIO_FN(PORT30_VIO_CKOR),
3001 GPIO_FN(SIM_D), \
3002 GPIO_FN(PORT31_IROUT),
3003 GPIO_FN(SCIFA4_TXD),
3004 GPIO_FN(SCIFA4_RXD), \
3005 GPIO_FN(XWUP),
3006 GPIO_FN(SCIFA4_RTS_),
3007 GPIO_FN(SCIFA4_CTS_),
3008 GPIO_FN(FSIBOBT), \
3009 GPIO_FN(FSIBIBT),
3010 GPIO_FN(FSIBOLR), \
3011 GPIO_FN(FSIBILR),
3012 GPIO_FN(FSIBOSLD),
3013 GPIO_FN(FSIBISLD),
3014 GPIO_FN(VACK),
3015 GPIO_FN(XTAL1L),
3016 GPIO_FN(SCIFA0_RTS_), \
3017 GPIO_FN(FSICOSLDT2),
3018 GPIO_FN(SCIFA0_RXD),
3019 GPIO_FN(SCIFA0_CTS_), \
3020 GPIO_FN(FSICOSLDT1),
3021 GPIO_FN(FSICOBT), \
3022 GPIO_FN(FSICIBT), \
3023 GPIO_FN(FSIDOBT), \
3024 GPIO_FN(FSIDIBT),
3025 GPIO_FN(FSICOLR), \
3026 GPIO_FN(FSICILR), \
3027 GPIO_FN(FSIDOLR), \
3028 GPIO_FN(FSIDILR),
3029 GPIO_FN(FSICOSLD), \
3030 GPIO_FN(PORT47_FSICSPDIF),
3031 GPIO_FN(FSICISLD), \
3032 GPIO_FN(FSIDISLD),
3033 GPIO_FN(FSIACK), \
3034 GPIO_FN(PORT49_IRDA_OUT), \
3035 GPIO_FN(PORT49_IROUT), \
3036 GPIO_FN(FSIAOMC),
3037 GPIO_FN(FSIAOLR), \
3038 GPIO_FN(BBIF2_TSYNC2), \
3039 GPIO_FN(TPU2TO2), \
3040 GPIO_FN(FSIAILR),
3041
3042 GPIO_FN(FSIAOBT), \
3043 GPIO_FN(BBIF2_TSCK2), \
3044 GPIO_FN(TPU2TO3), \
3045 GPIO_FN(FSIAIBT),
3046 GPIO_FN(FSIAOSLD), \
3047 GPIO_FN(BBIF2_TXD2),
3048 GPIO_FN(FSIASPDIF), \
3049 GPIO_FN(PORT53_IRDA_IN), \
3050 GPIO_FN(TPU3TO3), \
3051 GPIO_FN(FSIBSPDIF), \
3052 GPIO_FN(PORT53_FSICSPDIF),
3053 GPIO_FN(FSIBCK), \
3054 GPIO_FN(PORT54_IRDA_FIRSEL), \
3055 GPIO_FN(TPU3TO2), \
3056 GPIO_FN(FSIBOMC), \
3057 GPIO_FN(FSICCK), \
3058 GPIO_FN(FSICOMC),
3059 GPIO_FN(FSIAISLD), \
3060 GPIO_FN(TPU0TO0),
3061 GPIO_FN(A0), \
3062 GPIO_FN(BS_),
3063 GPIO_FN(A12), \
3064 GPIO_FN(PORT58_KEYOUT7), \
3065 GPIO_FN(TPU4TO2),
3066 GPIO_FN(A13), \
3067 GPIO_FN(PORT59_KEYOUT6), \
3068 GPIO_FN(TPU0TO1),
3069 GPIO_FN(A14), \
3070 GPIO_FN(KEYOUT5),
3071 GPIO_FN(A15), \
3072 GPIO_FN(KEYOUT4),
3073 GPIO_FN(A16), \
3074 GPIO_FN(KEYOUT3), \
3075 GPIO_FN(MSIOF0_SS1),
3076 GPIO_FN(A17), \
3077 GPIO_FN(KEYOUT2), \
3078 GPIO_FN(MSIOF0_TSYNC),
3079 GPIO_FN(A18), \
3080 GPIO_FN(KEYOUT1), \
3081 GPIO_FN(MSIOF0_TSCK),
3082 GPIO_FN(A19), \
3083 GPIO_FN(KEYOUT0), \
3084 GPIO_FN(MSIOF0_TXD),
3085 GPIO_FN(A20), \
3086 GPIO_FN(KEYIN0), \
3087 GPIO_FN(MSIOF0_RSCK),
3088 GPIO_FN(A21), \
3089 GPIO_FN(KEYIN1), \
3090 GPIO_FN(MSIOF0_RSYNC),
3091 GPIO_FN(A22), \
3092 GPIO_FN(KEYIN2), \
3093 GPIO_FN(MSIOF0_MCK0),
3094 GPIO_FN(A23), \
3095 GPIO_FN(KEYIN3), \
3096 GPIO_FN(MSIOF0_MCK1),
3097 GPIO_FN(A24), \
3098 GPIO_FN(KEYIN4), \
3099 GPIO_FN(MSIOF0_RXD),
3100 GPIO_FN(A25), \
3101 GPIO_FN(KEYIN5), \
3102 GPIO_FN(MSIOF0_SS2),
3103 GPIO_FN(A26), \
3104 GPIO_FN(KEYIN6),
3105 GPIO_FN(KEYIN7),
3106 GPIO_FN(D0_NAF0),
3107 GPIO_FN(D1_NAF1),
3108 GPIO_FN(D2_NAF2),
3109 GPIO_FN(D3_NAF3),
3110 GPIO_FN(D4_NAF4),
3111 GPIO_FN(D5_NAF5),
3112 GPIO_FN(D6_NAF6),
3113 GPIO_FN(D7_NAF7),
3114 GPIO_FN(D8_NAF8),
3115 GPIO_FN(D9_NAF9),
3116 GPIO_FN(D10_NAF10),
3117 GPIO_FN(D11_NAF11),
3118 GPIO_FN(D12_NAF12),
3119 GPIO_FN(D13_NAF13),
3120 GPIO_FN(D14_NAF14),
3121 GPIO_FN(D15_NAF15),
3122 GPIO_FN(CS4_),
3123 GPIO_FN(CS5A_), \
3124 GPIO_FN(PORT91_RDWR),
3125 GPIO_FN(CS5B_), \
3126 GPIO_FN(FCE1_),
3127 GPIO_FN(CS6B_), \
3128 GPIO_FN(DACK0),
3129 GPIO_FN(FCE0_), \
3130 GPIO_FN(CS6A_),
3131 GPIO_FN(WAIT_), \
3132 GPIO_FN(DREQ0),
3133 GPIO_FN(RD__FSC),
3134 GPIO_FN(WE0__FWE), \
3135 GPIO_FN(RDWR_FWE),
3136 GPIO_FN(WE1_),
3137 GPIO_FN(FRB),
3138 GPIO_FN(CKO),
3139 GPIO_FN(NBRSTOUT_),
3140 GPIO_FN(NBRST_),
3141 GPIO_FN(BBIF2_TXD),
3142 GPIO_FN(BBIF2_RXD),
3143 GPIO_FN(BBIF2_SYNC),
3144 GPIO_FN(BBIF2_SCK),
3145 GPIO_FN(SCIFA3_CTS_), \
3146 GPIO_FN(MFG3_IN2),
3147 GPIO_FN(SCIFA3_RXD), \
3148 GPIO_FN(MFG3_IN1),
3149 GPIO_FN(BBIF1_SS2), \
3150 GPIO_FN(SCIFA3_RTS_), \
3151 GPIO_FN(MFG3_OUT1),
3152 GPIO_FN(SCIFA3_TXD),
3153 GPIO_FN(HSI_RX_DATA), \
3154 GPIO_FN(BBIF1_RXD),
3155 GPIO_FN(HSI_TX_WAKE), \
3156 GPIO_FN(BBIF1_TSCK),
3157 GPIO_FN(HSI_TX_DATA), \
3158 GPIO_FN(BBIF1_TSYNC),
3159 GPIO_FN(HSI_TX_READY), \
3160 GPIO_FN(BBIF1_TXD),
3161 GPIO_FN(HSI_RX_READY), \
3162 GPIO_FN(BBIF1_RSCK), \
3163 GPIO_FN(PORT115_I2C_SCL2), \
3164 GPIO_FN(PORT115_I2C_SCL3),
3165 GPIO_FN(HSI_RX_WAKE), \
3166 GPIO_FN(BBIF1_RSYNC), \
3167 GPIO_FN(PORT116_I2C_SDA2), \
3168 GPIO_FN(PORT116_I2C_SDA3),
3169 GPIO_FN(HSI_RX_FLAG), \
3170 GPIO_FN(BBIF1_SS1), \
3171 GPIO_FN(BBIF1_FLOW),
3172 GPIO_FN(HSI_TX_FLAG),
3173 GPIO_FN(VIO_VD), \
3174 GPIO_FN(PORT128_LCD2VSYN), \
3175 GPIO_FN(VIO2_VD), \
3176 GPIO_FN(LCD2D0),
3177
3178 GPIO_FN(VIO_HD), \
3179 GPIO_FN(PORT129_LCD2HSYN), \
3180 GPIO_FN(PORT129_LCD2CS_), \
3181 GPIO_FN(VIO2_HD), \
3182 GPIO_FN(LCD2D1),
3183 GPIO_FN(VIO_D0), \
3184 GPIO_FN(PORT130_MSIOF2_RXD), \
3185 GPIO_FN(LCD2D10),
3186 GPIO_FN(VIO_D1), \
3187 GPIO_FN(PORT131_KEYOUT6), \
3188 GPIO_FN(PORT131_MSIOF2_SS1), \
3189 GPIO_FN(PORT131_KEYOUT11), \
3190 GPIO_FN(LCD2D11),
3191 GPIO_FN(VIO_D2), \
3192 GPIO_FN(PORT132_KEYOUT7), \
3193 GPIO_FN(PORT132_MSIOF2_SS2), \
3194 GPIO_FN(PORT132_KEYOUT10), \
3195 GPIO_FN(LCD2D12),
3196 GPIO_FN(VIO_D3), \
3197 GPIO_FN(MSIOF2_TSYNC), \
3198 GPIO_FN(LCD2D13),
3199 GPIO_FN(VIO_D4), \
3200 GPIO_FN(MSIOF2_TXD), \
3201 GPIO_FN(LCD2D14),
3202 GPIO_FN(VIO_D5), \
3203 GPIO_FN(MSIOF2_TSCK), \
3204 GPIO_FN(LCD2D15),
3205 GPIO_FN(VIO_D6), \
3206 GPIO_FN(PORT136_KEYOUT8), \
3207 GPIO_FN(LCD2D16),
3208 GPIO_FN(VIO_D7), \
3209 GPIO_FN(PORT137_KEYOUT9), \
3210 GPIO_FN(LCD2D17),
3211 GPIO_FN(VIO_D8), \
3212 GPIO_FN(PORT138_KEYOUT8), \
3213 GPIO_FN(VIO2_D0), \
3214 GPIO_FN(LCD2D6),
3215 GPIO_FN(VIO_D9), \
3216 GPIO_FN(PORT139_KEYOUT9), \
3217 GPIO_FN(VIO2_D1), \
3218 GPIO_FN(LCD2D7),
3219 GPIO_FN(VIO_D10), \
3220 GPIO_FN(TPU0TO2), \
3221 GPIO_FN(VIO2_D2), \
3222 GPIO_FN(LCD2D8),
3223 GPIO_FN(VIO_D11), \
3224 GPIO_FN(TPU0TO3), \
3225 GPIO_FN(VIO2_D3), \
3226 GPIO_FN(LCD2D9),
3227 GPIO_FN(VIO_D12), \
3228 GPIO_FN(PORT142_KEYOUT10), \
3229 GPIO_FN(VIO2_D4), \
3230 GPIO_FN(LCD2D2),
3231 GPIO_FN(VIO_D13), \
3232 GPIO_FN(PORT143_KEYOUT11), \
3233 GPIO_FN(PORT143_KEYOUT6), \
3234 GPIO_FN(VIO2_D5), \
3235 GPIO_FN(LCD2D3),
3236 GPIO_FN(VIO_D14), \
3237 GPIO_FN(PORT144_KEYOUT7), \
3238 GPIO_FN(VIO2_D6), \
3239 GPIO_FN(LCD2D4),
3240 GPIO_FN(VIO_D15), \
3241 GPIO_FN(TPU1TO3), \
3242 GPIO_FN(PORT145_LCD2DISP), \
3243 GPIO_FN(PORT145_LCD2RS), \
3244 GPIO_FN(VIO2_D7), \
3245 GPIO_FN(LCD2D5),
3246 GPIO_FN(VIO_CLK), \
3247 GPIO_FN(LCD2DCK), \
3248 GPIO_FN(PORT146_LCD2WR_), \
3249 GPIO_FN(VIO2_CLK), \
3250 GPIO_FN(LCD2D18),
3251 GPIO_FN(VIO_FIELD), \
3252 GPIO_FN(LCD2RD_), \
3253 GPIO_FN(VIO2_FIELD), \
3254 GPIO_FN(LCD2D19),
3255 GPIO_FN(VIO_CKO),
3256 GPIO_FN(A27), \
3257 GPIO_FN(PORT149_RDWR), \
3258 GPIO_FN(MFG0_IN1), \
3259 GPIO_FN(PORT149_KEYOUT9),
3260 GPIO_FN(MFG0_IN2),
3261 GPIO_FN(TS_SPSYNC3), \
3262 GPIO_FN(MSIOF2_RSCK),
3263 GPIO_FN(TS_SDAT3), \
3264 GPIO_FN(MSIOF2_RSYNC),
3265 GPIO_FN(TPU1TO2), \
3266 GPIO_FN(TS_SDEN3), \
3267 GPIO_FN(PORT153_MSIOF2_SS1),
3268 GPIO_FN(SCIFA2_TXD1), \
3269 GPIO_FN(MSIOF2_MCK0),
3270 GPIO_FN(SCIFA2_RXD1), \
3271 GPIO_FN(MSIOF2_MCK1),
3272 GPIO_FN(SCIFA2_RTS1_), \
3273 GPIO_FN(PORT156_MSIOF2_SS2),
3274 GPIO_FN(SCIFA2_CTS1_), \
3275 GPIO_FN(PORT157_MSIOF2_RXD),
3276 GPIO_FN(DINT_), \
3277 GPIO_FN(SCIFA2_SCK1), \
3278 GPIO_FN(TS_SCK3),
3279 GPIO_FN(PORT159_SCIFB_SCK), \
3280 GPIO_FN(PORT159_SCIFA5_SCK), \
3281 GPIO_FN(NMI),
3282 GPIO_FN(PORT160_SCIFB_TXD), \
3283 GPIO_FN(PORT160_SCIFA5_TXD),
3284 GPIO_FN(PORT161_SCIFB_CTS_), \
3285 GPIO_FN(PORT161_SCIFA5_CTS_),
3286 GPIO_FN(PORT162_SCIFB_RXD), \
3287 GPIO_FN(PORT162_SCIFA5_RXD),
3288 GPIO_FN(PORT163_SCIFB_RTS_), \
3289 GPIO_FN(PORT163_SCIFA5_RTS_), \
3290 GPIO_FN(TPU3TO0),
3291 GPIO_FN(LCDD0),
3292 GPIO_FN(LCDD1), \
3293 GPIO_FN(PORT193_SCIFA5_CTS_), \
3294 GPIO_FN(BBIF2_TSYNC1),
3295 GPIO_FN(LCDD2), \
3296 GPIO_FN(PORT194_SCIFA5_RTS_), \
3297 GPIO_FN(BBIF2_TSCK1),
3298 GPIO_FN(LCDD3), \
3299 GPIO_FN(PORT195_SCIFA5_RXD), \
3300 GPIO_FN(BBIF2_TXD1),
3301 GPIO_FN(LCDD4), \
3302 GPIO_FN(PORT196_SCIFA5_TXD),
3303 GPIO_FN(LCDD5), \
3304 GPIO_FN(PORT197_SCIFA5_SCK), \
3305 GPIO_FN(MFG2_OUT2), \
3306 GPIO_FN(TPU2TO1),
3307 GPIO_FN(LCDD6),
3308 GPIO_FN(LCDD7), \
3309 GPIO_FN(TPU4TO1), \
3310 GPIO_FN(MFG4_OUT2),
3311 GPIO_FN(LCDD8), \
3312 GPIO_FN(D16),
3313 GPIO_FN(LCDD9), \
3314 GPIO_FN(D17),
3315 GPIO_FN(LCDD10), \
3316 GPIO_FN(D18),
3317 GPIO_FN(LCDD11), \
3318 GPIO_FN(D19),
3319 GPIO_FN(LCDD12), \
3320 GPIO_FN(D20),
3321 GPIO_FN(LCDD13), \
3322 GPIO_FN(D21),
3323 GPIO_FN(LCDD14), \
3324 GPIO_FN(D22),
3325 GPIO_FN(LCDD15), \
3326 GPIO_FN(PORT207_MSIOF0L_SS1), \
3327 GPIO_FN(D23),
3328 GPIO_FN(LCDD16), \
3329 GPIO_FN(PORT208_MSIOF0L_SS2), \
3330 GPIO_FN(D24),
3331 GPIO_FN(LCDD17), \
3332 GPIO_FN(D25),
3333 GPIO_FN(LCDD18), \
3334 GPIO_FN(DREQ2), \
3335 GPIO_FN(PORT210_MSIOF0L_SS1), \
3336 GPIO_FN(D26),
3337 GPIO_FN(LCDD19), \
3338 GPIO_FN(PORT211_MSIOF0L_SS2), \
3339 GPIO_FN(D27),
3340 GPIO_FN(LCDD20), \
3341 GPIO_FN(TS_SPSYNC1), \
3342 GPIO_FN(MSIOF0L_MCK0), \
3343 GPIO_FN(D28),
3344 GPIO_FN(LCDD21), \
3345 GPIO_FN(TS_SDAT1), \
3346 GPIO_FN(MSIOF0L_MCK1), \
3347 GPIO_FN(D29),
3348 GPIO_FN(LCDD22), \
3349 GPIO_FN(TS_SDEN1), \
3350 GPIO_FN(MSIOF0L_RSCK), \
3351 GPIO_FN(D30),
3352 GPIO_FN(LCDD23), \
3353 GPIO_FN(TS_SCK1), \
3354 GPIO_FN(MSIOF0L_RSYNC), \
3355 GPIO_FN(D31),
3356 GPIO_FN(LCDDCK), \
3357 GPIO_FN(LCDWR_),
3358 GPIO_FN(LCDRD_), \
3359 GPIO_FN(DACK2), \
3360 GPIO_FN(PORT217_LCD2RS), \
3361 GPIO_FN(MSIOF0L_TSYNC), \
3362 GPIO_FN(VIO2_FIELD3), \
3363 GPIO_FN(PORT217_LCD2DISP),
3364 GPIO_FN(LCDHSYN), \
3365 GPIO_FN(LCDCS_), \
3366 GPIO_FN(LCDCS2_), \
3367 GPIO_FN(DACK3), \
3368 GPIO_FN(PORT218_VIO_CKOR),
3369 GPIO_FN(LCDDISP), \
3370 GPIO_FN(LCDRS), \
3371 GPIO_FN(PORT219_LCD2WR_), \
3372 GPIO_FN(DREQ3), \
3373 GPIO_FN(MSIOF0L_TSCK), \
3374 GPIO_FN(VIO2_CLK3), \
3375 GPIO_FN(LCD2DCK_2),
3376 GPIO_FN(LCDVSYN), \
3377 GPIO_FN(LCDVSYN2),
3378 GPIO_FN(LCDLCLK), \
3379 GPIO_FN(DREQ1), \
3380 GPIO_FN(PORT221_LCD2CS_), \
3381 GPIO_FN(PWEN), \
3382 GPIO_FN(MSIOF0L_RXD), \
3383 GPIO_FN(VIO2_HD3), \
3384 GPIO_FN(PORT221_LCD2HSYN),
3385 GPIO_FN(LCDDON), \
3386 GPIO_FN(LCDDON2), \
3387 GPIO_FN(DACK1), \
3388 GPIO_FN(OVCN), \
3389 GPIO_FN(MSIOF0L_TXD), \
3390 GPIO_FN(VIO2_VD3), \
3391 GPIO_FN(PORT222_LCD2VSYN),
3392
3393 GPIO_FN(SCIFA1_TXD), \
3394 GPIO_FN(OVCN2),
3395 GPIO_FN(EXTLP), \
3396 GPIO_FN(SCIFA1_SCK), \
3397 GPIO_FN(PORT226_VIO_CKO2),
3398 GPIO_FN(SCIFA1_RTS_), \
3399 GPIO_FN(IDIN),
3400 GPIO_FN(SCIFA1_RXD),
3401 GPIO_FN(SCIFA1_CTS_), \
3402 GPIO_FN(MFG1_IN1),
3403 GPIO_FN(MSIOF1_TXD), \
3404 GPIO_FN(SCIFA2_TXD2),
3405 GPIO_FN(MSIOF1_TSYNC), \
3406 GPIO_FN(SCIFA2_CTS2_),
3407 GPIO_FN(MSIOF1_TSCK), \
3408 GPIO_FN(SCIFA2_SCK2),
3409 GPIO_FN(MSIOF1_RXD), \
3410 GPIO_FN(SCIFA2_RXD2),
3411 GPIO_FN(MSIOF1_RSCK), \
3412 GPIO_FN(SCIFA2_RTS2_), \
3413 GPIO_FN(VIO2_CLK2), \
3414 GPIO_FN(LCD2D20),
3415 GPIO_FN(MSIOF1_RSYNC), \
3416 GPIO_FN(MFG1_IN2), \
3417 GPIO_FN(VIO2_VD2), \
3418 GPIO_FN(LCD2D21),
3419 GPIO_FN(MSIOF1_MCK0), \
3420 GPIO_FN(PORT236_I2C_SDA2),
3421 GPIO_FN(MSIOF1_MCK1), \
3422 GPIO_FN(PORT237_I2C_SCL2),
3423 GPIO_FN(MSIOF1_SS1), \
3424 GPIO_FN(VIO2_FIELD2), \
3425 GPIO_FN(LCD2D22),
3426 GPIO_FN(MSIOF1_SS2), \
3427 GPIO_FN(VIO2_HD2), \
3428 GPIO_FN(LCD2D23),
3429 GPIO_FN(SCIFA6_TXD),
3430 GPIO_FN(PORT241_IRDA_OUT), \
3431 GPIO_FN(PORT241_IROUT), \
3432 GPIO_FN(MFG4_OUT1), \
3433 GPIO_FN(TPU4TO0),
3434 GPIO_FN(PORT242_IRDA_IN), \
3435 GPIO_FN(MFG4_IN2),
3436 GPIO_FN(PORT243_IRDA_FIRSEL), \
3437 GPIO_FN(PORT243_VIO_CKO2),
3438 GPIO_FN(PORT244_SCIFA5_CTS_), \
3439 GPIO_FN(MFG2_IN1), \
3440 GPIO_FN(PORT244_SCIFB_CTS_), \
3441 GPIO_FN(MSIOF2R_RXD),
3442 GPIO_FN(PORT245_SCIFA5_RTS_), \
3443 GPIO_FN(MFG2_IN2), \
3444 GPIO_FN(PORT245_SCIFB_RTS_), \
3445 GPIO_FN(MSIOF2R_TXD),
3446 GPIO_FN(PORT246_SCIFA5_RXD), \
3447 GPIO_FN(MFG1_OUT1), \
3448 GPIO_FN(PORT246_SCIFB_RXD), \
3449 GPIO_FN(TPU1TO0),
3450 GPIO_FN(PORT247_SCIFA5_TXD), \
3451 GPIO_FN(MFG3_OUT2), \
3452 GPIO_FN(PORT247_SCIFB_TXD), \
3453 GPIO_FN(TPU3TO1),
3454 GPIO_FN(PORT248_SCIFA5_SCK), \
3455 GPIO_FN(MFG2_OUT1), \
3456 GPIO_FN(PORT248_SCIFB_SCK), \
3457 GPIO_FN(TPU2TO0), \
3458 GPIO_FN(PORT248_I2C_SCL3), \
3459 GPIO_FN(MSIOF2R_TSCK),
3460 GPIO_FN(PORT249_IROUT), \
3461 GPIO_FN(MFG4_IN1), \
3462 GPIO_FN(PORT249_I2C_SDA3), \
3463 GPIO_FN(MSIOF2R_TSYNC),
3464 GPIO_FN(SDHICLK0),
3465 GPIO_FN(SDHICD0),
3466 GPIO_FN(SDHID0_0),
3467 GPIO_FN(SDHID0_1),
3468 GPIO_FN(SDHID0_2),
3469 GPIO_FN(SDHID0_3),
3470 GPIO_FN(SDHICMD0),
3471 GPIO_FN(SDHIWP0),
3472 GPIO_FN(SDHICLK1),
3473 GPIO_FN(SDHID1_0), \
3474 GPIO_FN(TS_SPSYNC2),
3475 GPIO_FN(SDHID1_1), \
3476 GPIO_FN(TS_SDAT2),
3477 GPIO_FN(SDHID1_2), \
3478 GPIO_FN(TS_SDEN2),
3479 GPIO_FN(SDHID1_3), \
3480 GPIO_FN(TS_SCK2),
3481 GPIO_FN(SDHICMD1),
3482 GPIO_FN(SDHICLK2),
3483 GPIO_FN(SDHID2_0), \
3484 GPIO_FN(TS_SPSYNC4),
3485 GPIO_FN(SDHID2_1), \
3486 GPIO_FN(TS_SDAT4),
3487 GPIO_FN(SDHID2_2), \
3488 GPIO_FN(TS_SDEN4),
3489 GPIO_FN(SDHID2_3), \
3490 GPIO_FN(TS_SCK4),
3491 GPIO_FN(SDHICMD2),
3492 GPIO_FN(MMCCLK0),
3493 GPIO_FN(MMCD0_0),
3494 GPIO_FN(MMCD0_1),
3495 GPIO_FN(MMCD0_2),
3496 GPIO_FN(MMCD0_3),
3497 GPIO_FN(MMCD0_4), \
3498 GPIO_FN(TS_SPSYNC5),
3499 GPIO_FN(MMCD0_5), \
3500 GPIO_FN(TS_SDAT5),
3501 GPIO_FN(MMCD0_6), \
3502 GPIO_FN(TS_SDEN5),
3503 GPIO_FN(MMCD0_7), \
3504 GPIO_FN(TS_SCK5),
3505 GPIO_FN(MMCCMD0),
3506 GPIO_FN(RESETOUTS_), \
3507 GPIO_FN(EXTAL2OUT),
3508 GPIO_FN(MCP_WAIT__MCP_FRB),
3509 GPIO_FN(MCP_CKO), \
3510 GPIO_FN(MMCCLK1),
3511 GPIO_FN(MCP_D15_MCP_NAF15),
3512 GPIO_FN(MCP_D14_MCP_NAF14),
3513 GPIO_FN(MCP_D13_MCP_NAF13),
3514 GPIO_FN(MCP_D12_MCP_NAF12),
3515 GPIO_FN(MCP_D11_MCP_NAF11),
3516 GPIO_FN(MCP_D10_MCP_NAF10),
3517 GPIO_FN(MCP_D9_MCP_NAF9),
3518 GPIO_FN(MCP_D8_MCP_NAF8), \
3519 GPIO_FN(MMCCMD1),
3520 GPIO_FN(MCP_D7_MCP_NAF7), \
3521 GPIO_FN(MMCD1_7),
3522
3523 GPIO_FN(MCP_D6_MCP_NAF6), \
3524 GPIO_FN(MMCD1_6),
3525 GPIO_FN(MCP_D5_MCP_NAF5), \
3526 GPIO_FN(MMCD1_5),
3527 GPIO_FN(MCP_D4_MCP_NAF4), \
3528 GPIO_FN(MMCD1_4),
3529 GPIO_FN(MCP_D3_MCP_NAF3), \
3530 GPIO_FN(MMCD1_3),
3531 GPIO_FN(MCP_D2_MCP_NAF2), \
3532 GPIO_FN(MMCD1_2),
3533 GPIO_FN(MCP_D1_MCP_NAF1), \
3534 GPIO_FN(MMCD1_1),
3535 GPIO_FN(MCP_D0_MCP_NAF0), \
3536 GPIO_FN(MMCD1_0),
3537 GPIO_FN(MCP_NBRSTOUT_),
3538 GPIO_FN(MCP_WE0__MCP_FWE), \
3539 GPIO_FN(MCP_RDWR_MCP_FWE),
3540
3541 /* MSEL2 special cases */
3542 GPIO_FN(TSIF2_TS_XX1),
3543 GPIO_FN(TSIF2_TS_XX2),
3544 GPIO_FN(TSIF2_TS_XX3),
3545 GPIO_FN(TSIF2_TS_XX4),
3546 GPIO_FN(TSIF2_TS_XX5),
3547 GPIO_FN(TSIF1_TS_XX1),
3548 GPIO_FN(TSIF1_TS_XX2),
3549 GPIO_FN(TSIF1_TS_XX3),
3550 GPIO_FN(TSIF1_TS_XX4),
3551 GPIO_FN(TSIF1_TS_XX5),
3552 GPIO_FN(TSIF0_TS_XX1),
3553 GPIO_FN(TSIF0_TS_XX2),
3554 GPIO_FN(TSIF0_TS_XX3),
3555 GPIO_FN(TSIF0_TS_XX4),
3556 GPIO_FN(TSIF0_TS_XX5),
3557 GPIO_FN(MST1_TS_XX1),
3558 GPIO_FN(MST1_TS_XX2),
3559 GPIO_FN(MST1_TS_XX3),
3560 GPIO_FN(MST1_TS_XX4),
3561 GPIO_FN(MST1_TS_XX5),
3562 GPIO_FN(MST0_TS_XX1),
3563 GPIO_FN(MST0_TS_XX2),
3564 GPIO_FN(MST0_TS_XX3),
3565 GPIO_FN(MST0_TS_XX4),
3566 GPIO_FN(MST0_TS_XX5),
3567
3568 /* MSEL3 special cases */
3569 GPIO_FN(SDHI0_VCCQ_MC0_ON),
3570 GPIO_FN(SDHI0_VCCQ_MC0_OFF),
3571 GPIO_FN(DEBUG_MON_VIO),
3572 GPIO_FN(DEBUG_MON_LCDD),
3573 GPIO_FN(LCDC_LCDC0),
3574 GPIO_FN(LCDC_LCDC1),
3575
3576 /* MSEL4 special cases */
3577 GPIO_FN(IRQ9_MEM_INT),
3578 GPIO_FN(IRQ9_MCP_INT),
3579 GPIO_FN(A11),
3580 GPIO_FN(KEYOUT8),
3581 GPIO_FN(TPU4TO3),
3582 GPIO_FN(RESETA_N_PU_ON),
3583 GPIO_FN(RESETA_N_PU_OFF),
3584 GPIO_FN(EDBGREQ_PD),
3585 GPIO_FN(EDBGREQ_PU),
3586
3587 /* Functions with pull-ups */
3588 GPIO_FN(KEYIN0_PU),
3589 GPIO_FN(KEYIN1_PU),
3590 GPIO_FN(KEYIN2_PU),
3591 GPIO_FN(KEYIN3_PU),
3592 GPIO_FN(KEYIN4_PU),
3593 GPIO_FN(KEYIN5_PU),
3594 GPIO_FN(KEYIN6_PU),
3595 GPIO_FN(KEYIN7_PU),
3596 GPIO_FN(SDHICD0_PU),
3597 GPIO_FN(SDHID0_0_PU),
3598 GPIO_FN(SDHID0_1_PU),
3599 GPIO_FN(SDHID0_2_PU),
3600 GPIO_FN(SDHID0_3_PU),
3601 GPIO_FN(SDHICMD0_PU),
3602 GPIO_FN(SDHIWP0_PU),
3603 GPIO_FN(SDHID1_0_PU),
3604 GPIO_FN(SDHID1_1_PU),
3605 GPIO_FN(SDHID1_2_PU),
3606 GPIO_FN(SDHID1_3_PU),
3607 GPIO_FN(SDHICMD1_PU),
3608 GPIO_FN(SDHID2_0_PU),
3609 GPIO_FN(SDHID2_1_PU),
3610 GPIO_FN(SDHID2_2_PU),
3611 GPIO_FN(SDHID2_3_PU),
3612 GPIO_FN(SDHICMD2_PU),
3613 GPIO_FN(MMCCMD0_PU),
3614 GPIO_FN(MMCCMD1_PU),
3615 GPIO_FN(MMCD0_0_PU),
3616 GPIO_FN(MMCD0_1_PU),
3617 GPIO_FN(MMCD0_2_PU),
3618 GPIO_FN(MMCD0_3_PU),
3619 GPIO_FN(MMCD0_4_PU),
3620 GPIO_FN(MMCD0_5_PU),
3621 GPIO_FN(MMCD0_6_PU),
3622 GPIO_FN(MMCD0_7_PU),
3623 GPIO_FN(FSIACK_PU),
3624 GPIO_FN(FSIAILR_PU),
3625 GPIO_FN(FSIAIBT_PU),
3626 GPIO_FN(FSIAISLD_PU),
3627};
3628
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3629static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3630 PORTCR(0, 0xe6050000), /* PORT0CR */
3631 PORTCR(1, 0xe6050001), /* PORT1CR */
3632 PORTCR(2, 0xe6050002), /* PORT2CR */
3633 PORTCR(3, 0xe6050003), /* PORT3CR */
3634 PORTCR(4, 0xe6050004), /* PORT4CR */
3635 PORTCR(5, 0xe6050005), /* PORT5CR */
3636 PORTCR(6, 0xe6050006), /* PORT6CR */
3637 PORTCR(7, 0xe6050007), /* PORT7CR */
3638 PORTCR(8, 0xe6050008), /* PORT8CR */
3639 PORTCR(9, 0xe6050009), /* PORT9CR */
3640
3641 PORTCR(10, 0xe605000a), /* PORT10CR */
3642 PORTCR(11, 0xe605000b), /* PORT11CR */
3643 PORTCR(12, 0xe605000c), /* PORT12CR */
3644 PORTCR(13, 0xe605000d), /* PORT13CR */
3645 PORTCR(14, 0xe605000e), /* PORT14CR */
3646 PORTCR(15, 0xe605000f), /* PORT15CR */
3647 PORTCR(16, 0xe6050010), /* PORT16CR */
3648 PORTCR(17, 0xe6050011), /* PORT17CR */
3649 PORTCR(18, 0xe6050012), /* PORT18CR */
3650 PORTCR(19, 0xe6050013), /* PORT19CR */
3651
3652 PORTCR(20, 0xe6050014), /* PORT20CR */
3653 PORTCR(21, 0xe6050015), /* PORT21CR */
3654 PORTCR(22, 0xe6050016), /* PORT22CR */
3655 PORTCR(23, 0xe6050017), /* PORT23CR */
3656 PORTCR(24, 0xe6050018), /* PORT24CR */
3657 PORTCR(25, 0xe6050019), /* PORT25CR */
3658 PORTCR(26, 0xe605001a), /* PORT26CR */
3659 PORTCR(27, 0xe605001b), /* PORT27CR */
3660 PORTCR(28, 0xe605001c), /* PORT28CR */
3661 PORTCR(29, 0xe605001d), /* PORT29CR */
3662
3663 PORTCR(30, 0xe605001e), /* PORT30CR */
3664 PORTCR(31, 0xe605001f), /* PORT31CR */
3665 PORTCR(32, 0xe6051020), /* PORT32CR */
3666 PORTCR(33, 0xe6051021), /* PORT33CR */
3667 PORTCR(34, 0xe6051022), /* PORT34CR */
3668 PORTCR(35, 0xe6051023), /* PORT35CR */
3669 PORTCR(36, 0xe6051024), /* PORT36CR */
3670 PORTCR(37, 0xe6051025), /* PORT37CR */
3671 PORTCR(38, 0xe6051026), /* PORT38CR */
3672 PORTCR(39, 0xe6051027), /* PORT39CR */
3673
3674 PORTCR(40, 0xe6051028), /* PORT40CR */
3675 PORTCR(41, 0xe6051029), /* PORT41CR */
3676 PORTCR(42, 0xe605102a), /* PORT42CR */
3677 PORTCR(43, 0xe605102b), /* PORT43CR */
3678 PORTCR(44, 0xe605102c), /* PORT44CR */
3679 PORTCR(45, 0xe605102d), /* PORT45CR */
3680 PORTCR(46, 0xe605102e), /* PORT46CR */
3681 PORTCR(47, 0xe605102f), /* PORT47CR */
3682 PORTCR(48, 0xe6051030), /* PORT48CR */
3683 PORTCR(49, 0xe6051031), /* PORT49CR */
3684
3685 PORTCR(50, 0xe6051032), /* PORT50CR */
3686 PORTCR(51, 0xe6051033), /* PORT51CR */
3687 PORTCR(52, 0xe6051034), /* PORT52CR */
3688 PORTCR(53, 0xe6051035), /* PORT53CR */
3689 PORTCR(54, 0xe6051036), /* PORT54CR */
3690 PORTCR(55, 0xe6051037), /* PORT55CR */
3691 PORTCR(56, 0xe6051038), /* PORT56CR */
3692 PORTCR(57, 0xe6051039), /* PORT57CR */
3693 PORTCR(58, 0xe605103a), /* PORT58CR */
3694 PORTCR(59, 0xe605103b), /* PORT59CR */
3695
3696 PORTCR(60, 0xe605103c), /* PORT60CR */
3697 PORTCR(61, 0xe605103d), /* PORT61CR */
3698 PORTCR(62, 0xe605103e), /* PORT62CR */
3699 PORTCR(63, 0xe605103f), /* PORT63CR */
3700 PORTCR(64, 0xe6051040), /* PORT64CR */
3701 PORTCR(65, 0xe6051041), /* PORT65CR */
3702 PORTCR(66, 0xe6051042), /* PORT66CR */
3703 PORTCR(67, 0xe6051043), /* PORT67CR */
3704 PORTCR(68, 0xe6051044), /* PORT68CR */
3705 PORTCR(69, 0xe6051045), /* PORT69CR */
3706
3707 PORTCR(70, 0xe6051046), /* PORT70CR */
3708 PORTCR(71, 0xe6051047), /* PORT71CR */
3709 PORTCR(72, 0xe6051048), /* PORT72CR */
3710 PORTCR(73, 0xe6051049), /* PORT73CR */
3711 PORTCR(74, 0xe605104a), /* PORT74CR */
3712 PORTCR(75, 0xe605104b), /* PORT75CR */
3713 PORTCR(76, 0xe605104c), /* PORT76CR */
3714 PORTCR(77, 0xe605104d), /* PORT77CR */
3715 PORTCR(78, 0xe605104e), /* PORT78CR */
3716 PORTCR(79, 0xe605104f), /* PORT79CR */
3717
3718 PORTCR(80, 0xe6051050), /* PORT80CR */
3719 PORTCR(81, 0xe6051051), /* PORT81CR */
3720 PORTCR(82, 0xe6051052), /* PORT82CR */
3721 PORTCR(83, 0xe6051053), /* PORT83CR */
3722 PORTCR(84, 0xe6051054), /* PORT84CR */
3723 PORTCR(85, 0xe6051055), /* PORT85CR */
3724 PORTCR(86, 0xe6051056), /* PORT86CR */
3725 PORTCR(87, 0xe6051057), /* PORT87CR */
3726 PORTCR(88, 0xe6051058), /* PORT88CR */
3727 PORTCR(89, 0xe6051059), /* PORT89CR */
3728
3729 PORTCR(90, 0xe605105a), /* PORT90CR */
3730 PORTCR(91, 0xe605105b), /* PORT91CR */
3731 PORTCR(92, 0xe605105c), /* PORT92CR */
3732 PORTCR(93, 0xe605105d), /* PORT93CR */
3733 PORTCR(94, 0xe605105e), /* PORT94CR */
3734 PORTCR(95, 0xe605105f), /* PORT95CR */
3735 PORTCR(96, 0xe6052060), /* PORT96CR */
3736 PORTCR(97, 0xe6052061), /* PORT97CR */
3737 PORTCR(98, 0xe6052062), /* PORT98CR */
3738 PORTCR(99, 0xe6052063), /* PORT99CR */
3739
3740 PORTCR(100, 0xe6052064), /* PORT100CR */
3741 PORTCR(101, 0xe6052065), /* PORT101CR */
3742 PORTCR(102, 0xe6052066), /* PORT102CR */
3743 PORTCR(103, 0xe6052067), /* PORT103CR */
3744 PORTCR(104, 0xe6052068), /* PORT104CR */
3745 PORTCR(105, 0xe6052069), /* PORT105CR */
3746 PORTCR(106, 0xe605206a), /* PORT106CR */
3747 PORTCR(107, 0xe605206b), /* PORT107CR */
3748 PORTCR(108, 0xe605206c), /* PORT108CR */
3749 PORTCR(109, 0xe605206d), /* PORT109CR */
3750
3751 PORTCR(110, 0xe605206e), /* PORT110CR */
3752 PORTCR(111, 0xe605206f), /* PORT111CR */
3753 PORTCR(112, 0xe6052070), /* PORT112CR */
3754 PORTCR(113, 0xe6052071), /* PORT113CR */
3755 PORTCR(114, 0xe6052072), /* PORT114CR */
3756 PORTCR(115, 0xe6052073), /* PORT115CR */
3757 PORTCR(116, 0xe6052074), /* PORT116CR */
3758 PORTCR(117, 0xe6052075), /* PORT117CR */
3759 PORTCR(118, 0xe6052076), /* PORT118CR */
3760
3761 PORTCR(128, 0xe6052080), /* PORT128CR */
3762 PORTCR(129, 0xe6052081), /* PORT129CR */
3763
3764 PORTCR(130, 0xe6052082), /* PORT130CR */
3765 PORTCR(131, 0xe6052083), /* PORT131CR */
3766 PORTCR(132, 0xe6052084), /* PORT132CR */
3767 PORTCR(133, 0xe6052085), /* PORT133CR */
3768 PORTCR(134, 0xe6052086), /* PORT134CR */
3769 PORTCR(135, 0xe6052087), /* PORT135CR */
3770 PORTCR(136, 0xe6052088), /* PORT136CR */
3771 PORTCR(137, 0xe6052089), /* PORT137CR */
3772 PORTCR(138, 0xe605208a), /* PORT138CR */
3773 PORTCR(139, 0xe605208b), /* PORT139CR */
3774
3775 PORTCR(140, 0xe605208c), /* PORT140CR */
3776 PORTCR(141, 0xe605208d), /* PORT141CR */
3777 PORTCR(142, 0xe605208e), /* PORT142CR */
3778 PORTCR(143, 0xe605208f), /* PORT143CR */
3779 PORTCR(144, 0xe6052090), /* PORT144CR */
3780 PORTCR(145, 0xe6052091), /* PORT145CR */
3781 PORTCR(146, 0xe6052092), /* PORT146CR */
3782 PORTCR(147, 0xe6052093), /* PORT147CR */
3783 PORTCR(148, 0xe6052094), /* PORT148CR */
3784 PORTCR(149, 0xe6052095), /* PORT149CR */
3785
3786 PORTCR(150, 0xe6052096), /* PORT150CR */
3787 PORTCR(151, 0xe6052097), /* PORT151CR */
3788 PORTCR(152, 0xe6052098), /* PORT152CR */
3789 PORTCR(153, 0xe6052099), /* PORT153CR */
3790 PORTCR(154, 0xe605209a), /* PORT154CR */
3791 PORTCR(155, 0xe605209b), /* PORT155CR */
3792 PORTCR(156, 0xe605209c), /* PORT156CR */
3793 PORTCR(157, 0xe605209d), /* PORT157CR */
3794 PORTCR(158, 0xe605209e), /* PORT158CR */
3795 PORTCR(159, 0xe605209f), /* PORT159CR */
3796
3797 PORTCR(160, 0xe60520a0), /* PORT160CR */
3798 PORTCR(161, 0xe60520a1), /* PORT161CR */
3799 PORTCR(162, 0xe60520a2), /* PORT162CR */
3800 PORTCR(163, 0xe60520a3), /* PORT163CR */
3801 PORTCR(164, 0xe60520a4), /* PORT164CR */
3802
3803 PORTCR(192, 0xe60520c0), /* PORT192CR */
3804 PORTCR(193, 0xe60520c1), /* PORT193CR */
3805 PORTCR(194, 0xe60520c2), /* PORT194CR */
3806 PORTCR(195, 0xe60520c3), /* PORT195CR */
3807 PORTCR(196, 0xe60520c4), /* PORT196CR */
3808 PORTCR(197, 0xe60520c5), /* PORT197CR */
3809 PORTCR(198, 0xe60520c6), /* PORT198CR */
3810 PORTCR(199, 0xe60520c7), /* PORT199CR */
3811
3812 PORTCR(200, 0xe60520c8), /* PORT200CR */
3813 PORTCR(201, 0xe60520c9), /* PORT201CR */
3814 PORTCR(202, 0xe60520ca), /* PORT202CR */
3815 PORTCR(203, 0xe60520cb), /* PORT203CR */
3816 PORTCR(204, 0xe60520cc), /* PORT204CR */
3817 PORTCR(205, 0xe60520cd), /* PORT205CR */
3818 PORTCR(206, 0xe60520ce), /* PORT206CR */
3819 PORTCR(207, 0xe60520cf), /* PORT207CR */
3820 PORTCR(208, 0xe60520d0), /* PORT208CR */
3821 PORTCR(209, 0xe60520d1), /* PORT209CR */
3822
3823 PORTCR(210, 0xe60520d2), /* PORT210CR */
3824 PORTCR(211, 0xe60520d3), /* PORT211CR */
3825 PORTCR(212, 0xe60520d4), /* PORT212CR */
3826 PORTCR(213, 0xe60520d5), /* PORT213CR */
3827 PORTCR(214, 0xe60520d6), /* PORT214CR */
3828 PORTCR(215, 0xe60520d7), /* PORT215CR */
3829 PORTCR(216, 0xe60520d8), /* PORT216CR */
3830 PORTCR(217, 0xe60520d9), /* PORT217CR */
3831 PORTCR(218, 0xe60520da), /* PORT218CR */
3832 PORTCR(219, 0xe60520db), /* PORT219CR */
3833
3834 PORTCR(220, 0xe60520dc), /* PORT220CR */
3835 PORTCR(221, 0xe60520dd), /* PORT221CR */
3836 PORTCR(222, 0xe60520de), /* PORT222CR */
3837 PORTCR(223, 0xe60520df), /* PORT223CR */
3838 PORTCR(224, 0xe60530e0), /* PORT224CR */
3839 PORTCR(225, 0xe60530e1), /* PORT225CR */
3840 PORTCR(226, 0xe60530e2), /* PORT226CR */
3841 PORTCR(227, 0xe60530e3), /* PORT227CR */
3842 PORTCR(228, 0xe60530e4), /* PORT228CR */
3843 PORTCR(229, 0xe60530e5), /* PORT229CR */
3844
3845 PORTCR(230, 0xe60530e6), /* PORT230CR */
3846 PORTCR(231, 0xe60530e7), /* PORT231CR */
3847 PORTCR(232, 0xe60530e8), /* PORT232CR */
3848 PORTCR(233, 0xe60530e9), /* PORT233CR */
3849 PORTCR(234, 0xe60530ea), /* PORT234CR */
3850 PORTCR(235, 0xe60530eb), /* PORT235CR */
3851 PORTCR(236, 0xe60530ec), /* PORT236CR */
3852 PORTCR(237, 0xe60530ed), /* PORT237CR */
3853 PORTCR(238, 0xe60530ee), /* PORT238CR */
3854 PORTCR(239, 0xe60530ef), /* PORT239CR */
3855
3856 PORTCR(240, 0xe60530f0), /* PORT240CR */
3857 PORTCR(241, 0xe60530f1), /* PORT241CR */
3858 PORTCR(242, 0xe60530f2), /* PORT242CR */
3859 PORTCR(243, 0xe60530f3), /* PORT243CR */
3860 PORTCR(244, 0xe60530f4), /* PORT244CR */
3861 PORTCR(245, 0xe60530f5), /* PORT245CR */
3862 PORTCR(246, 0xe60530f6), /* PORT246CR */
3863 PORTCR(247, 0xe60530f7), /* PORT247CR */
3864 PORTCR(248, 0xe60530f8), /* PORT248CR */
3865 PORTCR(249, 0xe60530f9), /* PORT249CR */
3866
3867 PORTCR(250, 0xe60530fa), /* PORT250CR */
3868 PORTCR(251, 0xe60530fb), /* PORT251CR */
3869 PORTCR(252, 0xe60530fc), /* PORT252CR */
3870 PORTCR(253, 0xe60530fd), /* PORT253CR */
3871 PORTCR(254, 0xe60530fe), /* PORT254CR */
3872 PORTCR(255, 0xe60530ff), /* PORT255CR */
3873 PORTCR(256, 0xe6053100), /* PORT256CR */
3874 PORTCR(257, 0xe6053101), /* PORT257CR */
3875 PORTCR(258, 0xe6053102), /* PORT258CR */
3876 PORTCR(259, 0xe6053103), /* PORT259CR */
3877
3878 PORTCR(260, 0xe6053104), /* PORT260CR */
3879 PORTCR(261, 0xe6053105), /* PORT261CR */
3880 PORTCR(262, 0xe6053106), /* PORT262CR */
3881 PORTCR(263, 0xe6053107), /* PORT263CR */
3882 PORTCR(264, 0xe6053108), /* PORT264CR */
3883 PORTCR(265, 0xe6053109), /* PORT265CR */
3884 PORTCR(266, 0xe605310a), /* PORT266CR */
3885 PORTCR(267, 0xe605310b), /* PORT267CR */
3886 PORTCR(268, 0xe605310c), /* PORT268CR */
3887 PORTCR(269, 0xe605310d), /* PORT269CR */
3888
3889 PORTCR(270, 0xe605310e), /* PORT270CR */
3890 PORTCR(271, 0xe605310f), /* PORT271CR */
3891 PORTCR(272, 0xe6053110), /* PORT272CR */
3892 PORTCR(273, 0xe6053111), /* PORT273CR */
3893 PORTCR(274, 0xe6053112), /* PORT274CR */
3894 PORTCR(275, 0xe6053113), /* PORT275CR */
3895 PORTCR(276, 0xe6053114), /* PORT276CR */
3896 PORTCR(277, 0xe6053115), /* PORT277CR */
3897 PORTCR(278, 0xe6053116), /* PORT278CR */
3898 PORTCR(279, 0xe6053117), /* PORT279CR */
3899
3900 PORTCR(280, 0xe6053118), /* PORT280CR */
3901 PORTCR(281, 0xe6053119), /* PORT281CR */
3902 PORTCR(282, 0xe605311a), /* PORT282CR */
3903
3904 PORTCR(288, 0xe6052120), /* PORT288CR */
3905 PORTCR(289, 0xe6052121), /* PORT289CR */
3906
3907 PORTCR(290, 0xe6052122), /* PORT290CR */
3908 PORTCR(291, 0xe6052123), /* PORT291CR */
3909 PORTCR(292, 0xe6052124), /* PORT292CR */
3910 PORTCR(293, 0xe6052125), /* PORT293CR */
3911 PORTCR(294, 0xe6052126), /* PORT294CR */
3912 PORTCR(295, 0xe6052127), /* PORT295CR */
3913 PORTCR(296, 0xe6052128), /* PORT296CR */
3914 PORTCR(297, 0xe6052129), /* PORT297CR */
3915 PORTCR(298, 0xe605212a), /* PORT298CR */
3916 PORTCR(299, 0xe605212b), /* PORT299CR */
3917
3918 PORTCR(300, 0xe605212c), /* PORT300CR */
3919 PORTCR(301, 0xe605212d), /* PORT301CR */
3920 PORTCR(302, 0xe605212e), /* PORT302CR */
3921 PORTCR(303, 0xe605212f), /* PORT303CR */
3922 PORTCR(304, 0xe6052130), /* PORT304CR */
3923 PORTCR(305, 0xe6052131), /* PORT305CR */
3924 PORTCR(306, 0xe6052132), /* PORT306CR */
3925 PORTCR(307, 0xe6052133), /* PORT307CR */
3926 PORTCR(308, 0xe6052134), /* PORT308CR */
3927 PORTCR(309, 0xe6052135), /* PORT309CR */
3928
3929 { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
3930 0, 0,
3931 0, 0,
3932 0, 0,
3933 0, 0,
3934 0, 0,
3935 0, 0,
3936 0, 0,
3937 0, 0,
3938 0, 0,
3939 0, 0,
3940 0, 0,
3941 0, 0,
3942 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
3943 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
3944 MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
3945 MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
3946 0, 0,
3947 MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
3948 MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
3949 MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
3950 MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
3951 MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
3952 MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
3953 MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
3954 MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
3955 MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
3956 MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
3957 MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
3958 MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
3959 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
3960 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
3961 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
3962 }
3963 },
3964 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
3965 0, 0,
3966 0, 0,
3967 0, 0,
3968 MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
3969 0, 0,
3970 0, 0,
3971 0, 0,
3972 0, 0,
3973 0, 0,
3974 0, 0,
3975 0, 0,
3976 0, 0,
3977 0, 0,
3978 0, 0,
3979 0, 0,
3980 0, 0,
3981 MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
3982 0, 0,
3983 0, 0,
3984 0, 0,
3985 MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
3986 0, 0,
3987 MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
3988 0, 0,
3989 0, 0,
3990 MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
3991 0, 0,
3992 0, 0,
3993 0, 0,
3994 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
3995 0, 0,
3996 0, 0,
3997 }
3998 },
3999 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
4000 0, 0,
4001 0, 0,
4002 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
4003 0, 0,
4004 MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
4005 MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
4006 0, 0,
4007 0, 0,
4008 0, 0,
4009 MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
4010 MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
4011 MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
4012 MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
4013 0, 0,
4014 0, 0,
4015 0, 0,
4016 MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
4017 0, 0,
4018 MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
4019 MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
4020 MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
4021 MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
4022 MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
4023 MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
4024 MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
4025 0, 0,
4026 0, 0,
4027 MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
4028 0, 0,
4029 0, 0,
4030 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
4031 0, 0,
4032 }
4033 },
4034 { },
4035};
4036
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]4037static const struct pinmux_data_reg pinmux_data_regs[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4038 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
4039 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
4040 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
4041 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
4042 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
4043 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
4044 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
4045 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
4046 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
4047 },
4048 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
4049 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
4050 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
4051 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
4052 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
4053 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
4054 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
4055 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
4056 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
4057 },
4058 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
4059 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
4060 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
4061 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
4062 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
4063 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
4064 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
4065 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
4066 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
4067 },
4068 { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
4069 0, 0, 0, 0,
4070 0, 0, 0, 0,
4071 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
4072 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
4073 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
4074 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
4075 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
4076 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
4077 },
4078 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
4079 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
4080 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
4081 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
4082 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
4083 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
4084 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
4085 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
4086 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
4087 },
4088 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
4089 0, 0, 0, 0,
4090 0, 0, 0, 0,
4091 0, 0, 0, 0,
4092 0, 0, 0, 0,
4093 0, 0, 0, 0,
4094 0, 0, 0, 0,
4095 0, 0, 0, PORT164_DATA,
4096 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
4097 },
4098 { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
4099 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
4100 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
4101 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
4102 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
4103 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
4104 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
4105 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
4106 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
4107 },
4108 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
4109 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
4110 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
4111 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
4112 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
4113 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
4114 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
4115 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
4116 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
4117 },
4118 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
4119 0, 0, 0, 0,
4120 0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
4121 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
4122 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
4123 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
4124 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
4125 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
4126 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
4127 },
4128 { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
4129 0, 0, 0, 0,
4130 0, 0, 0, 0,
4131 0, 0, PORT309_DATA, PORT308_DATA,
4132 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
4133 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
4134 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
4135 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
4136 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
4137 },
4138 { },
4139};
4140
4141/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
4142#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
4143#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
4144
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]4145static const struct pinmux_irq pinmux_irqs[] = {
Guennadi Liakhovetskib58e5fa2013-02-12 16:50:02 +0100[diff] [blame]4146 PINMUX_IRQ(EXT_IRQ16H(19), 9),
4147 PINMUX_IRQ(EXT_IRQ16L(1), 10),
4148 PINMUX_IRQ(EXT_IRQ16L(0), 11),
4149 PINMUX_IRQ(EXT_IRQ16H(18), 13),
4150 PINMUX_IRQ(EXT_IRQ16H(20), 14),
4151 PINMUX_IRQ(EXT_IRQ16H(21), 15),
4152 PINMUX_IRQ(EXT_IRQ16H(31), 26),
4153 PINMUX_IRQ(EXT_IRQ16H(30), 27),
4154 PINMUX_IRQ(EXT_IRQ16H(29), 28),
4155 PINMUX_IRQ(EXT_IRQ16H(22), 40),
4156 PINMUX_IRQ(EXT_IRQ16H(23), 53),
4157 PINMUX_IRQ(EXT_IRQ16L(10), 54),
4158 PINMUX_IRQ(EXT_IRQ16L(9), 56),
4159 PINMUX_IRQ(EXT_IRQ16H(26), 115),
4160 PINMUX_IRQ(EXT_IRQ16H(27), 116),
4161 PINMUX_IRQ(EXT_IRQ16H(28), 117),
4162 PINMUX_IRQ(EXT_IRQ16H(24), 118),
4163 PINMUX_IRQ(EXT_IRQ16L(6), 147),
4164 PINMUX_IRQ(EXT_IRQ16L(2), 149),
4165 PINMUX_IRQ(EXT_IRQ16L(7), 150),
4166 PINMUX_IRQ(EXT_IRQ16L(12), 156),
4167 PINMUX_IRQ(EXT_IRQ16L(4), 159),
4168 PINMUX_IRQ(EXT_IRQ16H(25), 164),
4169 PINMUX_IRQ(EXT_IRQ16L(8), 223),
4170 PINMUX_IRQ(EXT_IRQ16L(3), 224),
4171 PINMUX_IRQ(EXT_IRQ16L(5), 227),
4172 PINMUX_IRQ(EXT_IRQ16H(17), 234),
4173 PINMUX_IRQ(EXT_IRQ16L(11), 238),
4174 PINMUX_IRQ(EXT_IRQ16L(13), 239),
4175 PINMUX_IRQ(EXT_IRQ16H(16), 249),
4176 PINMUX_IRQ(EXT_IRQ16L(14), 251),
4177 PINMUX_IRQ(EXT_IRQ16L(9), 308),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4178};
4179
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]4180#define PORTnCR_PULMD_OFF (0 << 6)
4181#define PORTnCR_PULMD_DOWN (2 << 6)
4182#define PORTnCR_PULMD_UP (3 << 6)
4183#define PORTnCR_PULMD_MASK (3 << 6)
4184
4185static const unsigned int sh73a0_portcr_offsets[] = {
4186 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
4187 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
4188};
4189
4190static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
4191{
4192 void __iomem *addr = pfc->window->virt
4193 + sh73a0_portcr_offsets[pin >> 5] + pin;
4194 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
4195
4196 switch (value) {
4197 case PORTnCR_PULMD_UP:
4198 return PIN_CONFIG_BIAS_PULL_UP;
4199 case PORTnCR_PULMD_DOWN:
4200 return PIN_CONFIG_BIAS_PULL_DOWN;
4201 case PORTnCR_PULMD_OFF:
4202 default:
4203 return PIN_CONFIG_BIAS_DISABLE;
4204 }
4205}
4206
4207static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4208 unsigned int bias)
4209{
4210 void __iomem *addr = pfc->window->virt
4211 + sh73a0_portcr_offsets[pin >> 5] + pin;
4212 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
4213
4214 switch (bias) {
4215 case PIN_CONFIG_BIAS_PULL_UP:
4216 value |= PORTnCR_PULMD_UP;
4217 break;
4218 case PIN_CONFIG_BIAS_PULL_DOWN:
4219 value |= PORTnCR_PULMD_DOWN;
4220 break;
4221 }
4222
4223 iowrite8(value, addr);
4224}
4225
4226static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
4227 .get_bias = sh73a0_pinmux_get_bias,
4228 .set_bias = sh73a0_pinmux_set_bias,
4229};
4230
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]4231const struct sh_pfc_soc_info sh73a0_pinmux_info = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4232 .name = "sh73a0_pfc",
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]4233 .ops = &sh73a0_pinmux_ops,
4234
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4235 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
4236 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
4237 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
4238 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4239 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4240
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]4241 .pins = pinmux_pins,
4242 .nr_pins = ARRAY_SIZE(pinmux_pins),
Guennadi Liakhovetskib58e5fa2013-02-12 16:50:02 +0100[diff] [blame]4243 .ranges = pinmux_ranges,
4244 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]4245 .groups = pinmux_groups,
4246 .nr_groups = ARRAY_SIZE(pinmux_groups),
4247 .functions = pinmux_functions,
4248 .nr_functions = ARRAY_SIZE(pinmux_functions),
4249
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]4250 .func_gpios = pinmux_func_gpios,
4251 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
Laurent Pinchartd7a7ca52012-11-28 17:51:00 +0100[diff] [blame]4252
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4253 .cfg_regs = pinmux_config_regs,
4254 .data_regs = pinmux_data_regs,
4255
4256 .gpio_data = pinmux_data,
4257 .gpio_data_size = ARRAY_SIZE(pinmux_data),
4258
4259 .gpio_irq = pinmux_irqs,
4260 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
4261};