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gerrit-public.fairphone.software / kernel / msm-4.9 / 8327eb65e795ba4f922bf7e531cd312875f0dc29 / . / include / linux / stmmac.h
blob: 4aef9baff12bd887f226640a7d0dd34e4ce1d3bb [file] [log] [blame]
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]1/*******************************************************************************
2
3 Header file for stmmac platform data
4
5 Copyright (C) 2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24*******************************************************************************/
25
26#ifndef __STMMAC_PLATFORM_DATA
27#define __STMMAC_PLATFORM_DATA
28
Viresh KUMAR57a503c2011-05-02 18:36:45 +0000[diff] [blame]29#include <linux/platform_device.h>
30
Deepak SIKRI55f9a4d2012-04-04 04:33:20 +0000[diff] [blame]31#define STMMAC_RX_COE_NONE 0
32#define STMMAC_RX_COE_TYPE1 1
33#define STMMAC_RX_COE_TYPE2 2
34
Deepak SIKRIfaeae3f2012-04-04 04:33:22 +0000[diff] [blame]35/* Define the macros for CSR clock range parameters to be passed by
36 * platform code.
37 * This could also be configured at run time using CPU freq framework. */
38
39/* MDC Clock Selection define*/
40#define STMMAC_CSR_60_100M 0 /* MDC = clk_scr_i/42 */
41#define STMMAC_CSR_100_150M 1 /* MDC = clk_scr_i/62 */
42#define STMMAC_CSR_20_35M 2 /* MDC = clk_scr_i/16 */
43#define STMMAC_CSR_35_60M 3 /* MDC = clk_scr_i/26 */
44#define STMMAC_CSR_150_250M 4 /* MDC = clk_scr_i/102 */
45#define STMMAC_CSR_250_300M 5 /* MDC = clk_scr_i/122 */
46
47/* FIXME: The MDC clock could be set higher than the IEEE 802.3
48 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
49 * of value different than the above defined values. The resultant MDIO
50 * clock frequency of 12.5 MHz is applicable for the interfacing chips
51 * supporting higher MDC clocks.
52 * The MDC clock selection macros need to be defined for MDC clock rate
53 * of 12.5 MHz, corresponding to the following selection.
54 * 1000 clk_csr_i/4
55 * 1001 clk_csr_i/6
56 * 1010 clk_csr_i/8
57 * 1011 clk_csr_i/10
58 * 1100 clk_csr_i/12
59 * 1101 clk_csr_i/14
60 * 1110 clk_csr_i/16
61 * 1111 clk_csr_i/18 */
62
Deepak SIKRI8327eb62012-04-04 04:33:23 +0000[diff] [blame^]63/* AXI DMA Burst length suported */
64#define DMA_AXI_BLEN_4 (1 << 1)
65#define DMA_AXI_BLEN_8 (1 << 2)
66#define DMA_AXI_BLEN_16 (1 << 3)
67#define DMA_AXI_BLEN_32 (1 << 4)
68#define DMA_AXI_BLEN_64 (1 << 5)
69#define DMA_AXI_BLEN_128 (1 << 6)
70#define DMA_AXI_BLEN_256 (1 << 7)
71#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
72 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
73 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
74
Giuseppe CAVALLARO36bcfe72011-07-20 00:05:23 +0000[diff] [blame]75/* Platfrom data for platform device structure's platform_data field */
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]76
Giuseppe CAVALLARO36bcfe72011-07-20 00:05:23 +0000[diff] [blame]77struct stmmac_mdio_bus_data {
78 int bus_id;
79 int (*phy_reset)(void *priv);
80 unsigned int phy_mask;
81 int *irqs;
82 int probed_phy_irq;
83};
84
Deepak SIKRI8327eb62012-04-04 04:33:23 +0000[diff] [blame^]85struct stmmac_dma_cfg {
86 int pbl;
87 int fixed_burst;
88 int burst_len;
89};
90
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]91struct plat_stmmacenet_data {
Srinivas Kandagatlaf142af22012-04-04 04:33:19 +0000[diff] [blame]92 char *phy_bus_name;
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]93 int bus_id;
Giuseppe CAVALLARO36bcfe72011-07-20 00:05:23 +0000[diff] [blame]94 int phy_addr;
95 int interface;
96 struct stmmac_mdio_bus_data *mdio_bus_data;
Deepak SIKRI8327eb62012-04-04 04:33:23 +0000[diff] [blame^]97 struct stmmac_dma_cfg *dma_cfg;
Giuseppe CAVALLAROdfb8fb92010-09-17 03:23:39 +0000[diff] [blame]98 int clk_csr;
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]99 int has_gmac;
Giuseppe CAVALLAROe326e852010-04-13 20:21:14 +0000[diff] [blame]100 int enh_desc;
Giuseppe CAVALLAROebbb2932010-09-17 03:23:40 +0000[diff] [blame]101 int tx_coe;
Deepak SIKRI55f9a4d2012-04-04 04:33:20 +0000[diff] [blame]102 int rx_coe;
Giuseppe CAVALLAROebbb2932010-09-17 03:23:40 +0000[diff] [blame]103 int bugged_jumbo;
Giuseppe Cavallaro543876c2010-09-24 21:27:41 -0700[diff] [blame]104 int pmt;
Srinivas Kandagatla61b80132011-07-17 20:54:09 +0000[diff] [blame]105 int force_sf_dma_mode;
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]106 void (*fix_mac_speed)(void *priv, unsigned int speed);
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000[diff] [blame]107 void (*bus_setup)(void __iomem *ioaddr);
Giuseppe CAVALLARO293bb1c2010-11-24 02:38:05 +0000[diff] [blame]108 int (*init)(struct platform_device *pdev);
109 void (*exit)(struct platform_device *pdev);
110 void *custom_cfg;
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]111 void *bsp_priv;
112};
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]113#endif