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viresh kumar986435e2010-04-01 12:30:49 +01001/*
2 * arch/arm/plat-spear/time.c
3 *
Shiraz Hashim5c881d92011-02-16 07:40:32 +01004 * Copyright (C) 2010 ST Microelectronics
viresh kumar986435e2010-04-01 12:30:49 +01005 * Shiraz Hashim<shiraz.hashim@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/clockchips.h>
14#include <linux/clocksource.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
Arnd Bergmann5019f0b2012-04-11 17:30:11 +000018#include <linux/ioport.h>
viresh kumar986435e2010-04-01 12:30:49 +010019#include <linux/io.h>
20#include <linux/kernel.h>
Viresh Kumar30551c02012-04-21 13:15:37 +053021#include <linux/of_irq.h>
22#include <linux/of_address.h>
viresh kumar986435e2010-04-01 12:30:49 +010023#include <linux/time.h>
24#include <linux/irq.h>
25#include <asm/mach/time.h>
viresh kumar986435e2010-04-01 12:30:49 +010026#include <mach/generic.h>
27
28/*
29 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
30 * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
31 * they share same functional clock. Any change in one's functional clock will
32 * also affect other timer.
33 */
34
35#define CLKEVT 0 /* gpt0, channel0 as clockevent */
36#define CLKSRC 1 /* gpt0, channel1 as clocksource */
37
38/* Register offsets, x is channel number */
39#define CR(x) ((x) * 0x80 + 0x80)
40#define IR(x) ((x) * 0x80 + 0x84)
41#define LOAD(x) ((x) * 0x80 + 0x88)
42#define COUNT(x) ((x) * 0x80 + 0x8C)
43
44/* Reg bit definitions */
45#define CTRL_INT_ENABLE 0x0100
46#define CTRL_ENABLE 0x0020
47#define CTRL_ONE_SHOT 0x0010
48
49#define CTRL_PRESCALER1 0x0
50#define CTRL_PRESCALER2 0x1
51#define CTRL_PRESCALER4 0x2
52#define CTRL_PRESCALER8 0x3
53#define CTRL_PRESCALER16 0x4
54#define CTRL_PRESCALER32 0x5
55#define CTRL_PRESCALER64 0x6
56#define CTRL_PRESCALER128 0x7
57#define CTRL_PRESCALER256 0x8
58
59#define INT_STATUS 0x1
60
Linus Walleij4bd48942010-07-19 20:55:46 +010061/*
62 * Minimum clocksource/clockevent timer range in seconds
63 */
64#define SPEAR_MIN_RANGE 4
65
viresh kumar986435e2010-04-01 12:30:49 +010066static __iomem void *gpt_base;
67static struct clk *gpt_clk;
68
69static void clockevent_set_mode(enum clock_event_mode mode,
70 struct clock_event_device *clk_event_dev);
71static int clockevent_next_event(unsigned long evt,
72 struct clock_event_device *clk_event_dev);
73
viresh kumar986435e2010-04-01 12:30:49 +010074static void spear_clocksource_init(void)
75{
76 u32 tick_rate;
77 u16 val;
78
79 /* program the prescaler (/256)*/
80 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
81
82 /* find out actual clock driving Timer */
83 tick_rate = clk_get_rate(gpt_clk);
84 tick_rate >>= CTRL_PRESCALER256;
85
86 writew(0xFFFF, gpt_base + LOAD(CLKSRC));
87
88 val = readw(gpt_base + CR(CLKSRC));
89 val &= ~CTRL_ONE_SHOT; /* autoreload mode */
90 val |= CTRL_ENABLE ;
91 writew(val, gpt_base + CR(CLKSRC));
92
viresh kumar986435e2010-04-01 12:30:49 +010093 /* register the clocksource */
Russell Kingd6e15d72011-05-08 17:10:14 +010094 clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
95 200, 16, clocksource_mmio_readw_up);
viresh kumar986435e2010-04-01 12:30:49 +010096}
97
98static struct clock_event_device clkevt = {
99 .name = "tmr0",
100 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
101 .set_mode = clockevent_set_mode,
102 .set_next_event = clockevent_next_event,
103 .shift = 0, /* to be computed */
104};
105
106static void clockevent_set_mode(enum clock_event_mode mode,
107 struct clock_event_device *clk_event_dev)
108{
109 u32 period;
110 u16 val;
111
112 /* stop the timer */
113 val = readw(gpt_base + CR(CLKEVT));
114 val &= ~CTRL_ENABLE;
115 writew(val, gpt_base + CR(CLKEVT));
116
117 switch (mode) {
118 case CLOCK_EVT_MODE_PERIODIC:
119 period = clk_get_rate(gpt_clk) / HZ;
120 period >>= CTRL_PRESCALER16;
121 writew(period, gpt_base + LOAD(CLKEVT));
122
123 val = readw(gpt_base + CR(CLKEVT));
124 val &= ~CTRL_ONE_SHOT;
125 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
126 writew(val, gpt_base + CR(CLKEVT));
127
128 break;
129 case CLOCK_EVT_MODE_ONESHOT:
130 val = readw(gpt_base + CR(CLKEVT));
131 val |= CTRL_ONE_SHOT;
132 writew(val, gpt_base + CR(CLKEVT));
133
134 break;
135 case CLOCK_EVT_MODE_UNUSED:
136 case CLOCK_EVT_MODE_SHUTDOWN:
137 case CLOCK_EVT_MODE_RESUME:
138
139 break;
140 default:
141 pr_err("Invalid mode requested\n");
142 break;
143 }
144}
145
146static int clockevent_next_event(unsigned long cycles,
147 struct clock_event_device *clk_event_dev)
148{
Gilles Chanteperdrix12021372012-02-24 22:50:50 +0100149 u16 val = readw(gpt_base + CR(CLKEVT));
150
151 if (val & CTRL_ENABLE)
152 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
viresh kumar986435e2010-04-01 12:30:49 +0100153
154 writew(cycles, gpt_base + LOAD(CLKEVT));
155
viresh kumar986435e2010-04-01 12:30:49 +0100156 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
157 writew(val, gpt_base + CR(CLKEVT));
158
159 return 0;
160}
161
162static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
163{
164 struct clock_event_device *evt = &clkevt;
165
166 writew(INT_STATUS, gpt_base + IR(CLKEVT));
167
168 evt->event_handler(evt);
169
170 return IRQ_HANDLED;
171}
172
173static struct irqaction spear_timer_irq = {
174 .name = "timer",
175 .flags = IRQF_DISABLED | IRQF_TIMER,
176 .handler = spear_timer_interrupt
177};
178
Arnd Bergmann5019f0b2012-04-11 17:30:11 +0000179static void __init spear_clockevent_init(int irq)
viresh kumar986435e2010-04-01 12:30:49 +0100180{
181 u32 tick_rate;
182
183 /* program the prescaler */
184 writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
185
186 tick_rate = clk_get_rate(gpt_clk);
187 tick_rate >>= CTRL_PRESCALER16;
188
viresh kumar986435e2010-04-01 12:30:49 +0100189 clkevt.cpumask = cpumask_of(0);
190
Shawn Guo838a2ae2013-01-12 11:50:05 +0000191 clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
viresh kumar986435e2010-04-01 12:30:49 +0100192
Arnd Bergmann5019f0b2012-04-11 17:30:11 +0000193 setup_irq(irq, &spear_timer_irq);
viresh kumar986435e2010-04-01 12:30:49 +0100194}
195
Viresh Kumar30551c02012-04-21 13:15:37 +0530196const static struct of_device_id timer_of_match[] __initconst = {
197 { .compatible = "st,spear-timer", },
198 { },
199};
viresh kumar986435e2010-04-01 12:30:49 +0100200
Viresh Kumar30551c02012-04-21 13:15:37 +0530201void __init spear_setup_of_timer(void)
202{
203 struct device_node *np;
204 int irq, ret;
205
206 np = of_find_matching_node(NULL, timer_of_match);
207 if (!np) {
208 pr_err("%s: No timer passed via DT\n", __func__);
viresh kumar986435e2010-04-01 12:30:49 +0100209 return;
210 }
211
Viresh Kumar30551c02012-04-21 13:15:37 +0530212 irq = irq_of_parse_and_map(np, 0);
213 if (!irq) {
214 pr_err("%s: No irq passed for timer via DT\n", __func__);
215 return;
216 }
217
218 gpt_base = of_iomap(np, 0);
viresh kumar986435e2010-04-01 12:30:49 +0100219 if (!gpt_base) {
Viresh Kumar30551c02012-04-21 13:15:37 +0530220 pr_err("%s: of iomap failed\n", __func__);
221 return;
viresh kumar986435e2010-04-01 12:30:49 +0100222 }
223
224 gpt_clk = clk_get_sys("gpt0", NULL);
225 if (!gpt_clk) {
226 pr_err("%s:couldn't get clk for gpt\n", __func__);
227 goto err_iomap;
228 }
229
Viresh Kumarf8abc082012-04-16 13:56:18 +0530230 ret = clk_prepare_enable(gpt_clk);
Shiraz Hashim5c881d92011-02-16 07:40:32 +0100231 if (ret < 0) {
Viresh Kumarf8abc082012-04-16 13:56:18 +0530232 pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
233 goto err_prepare_enable_clk;
viresh kumar986435e2010-04-01 12:30:49 +0100234 }
235
Arnd Bergmann5019f0b2012-04-11 17:30:11 +0000236 spear_clockevent_init(irq);
viresh kumar986435e2010-04-01 12:30:49 +0100237 spear_clocksource_init();
238
239 return;
240
Viresh Kumarf8abc082012-04-16 13:56:18 +0530241err_prepare_enable_clk:
Shiraz Hashim5c881d92011-02-16 07:40:32 +0100242 clk_put(gpt_clk);
viresh kumar986435e2010-04-01 12:30:49 +0100243err_iomap:
244 iounmap(gpt_base);
viresh kumar986435e2010-04-01 12:30:49 +0100245}