Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <linux/string.h> |
| 29 | #include <linux/bitops.h> |
| 30 | #include <drm/drmP.h> |
| 31 | #include <drm/i915_drm.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
| 33 | |
| 34 | /** @file i915_gem_tiling.c |
| 35 | * |
| 36 | * Support for managing tiling state of buffer objects. |
| 37 | * |
| 38 | * The idea behind tiling is to increase cache hit rates by rearranging |
| 39 | * pixel data so that a group of pixel accesses are in the same cacheline. |
| 40 | * Performance improvement from doing this on the back/depth buffer are on |
| 41 | * the order of 30%. |
| 42 | * |
| 43 | * Intel architectures make this somewhat more complicated, though, by |
| 44 | * adjustments made to addressing of data when the memory is in interleaved |
| 45 | * mode (matched pairs of DIMMS) to improve memory bandwidth. |
| 46 | * For interleaved memory, the CPU sends every sequential 64 bytes |
| 47 | * to an alternate memory channel so it can get the bandwidth from both. |
| 48 | * |
| 49 | * The GPU also rearranges its accesses for increased bandwidth to interleaved |
| 50 | * memory, and it matches what the CPU does for non-tiled. However, when tiled |
| 51 | * it does it a little differently, since one walks addresses not just in the |
| 52 | * X direction but also Y. So, along with alternating channels when bit |
| 53 | * 6 of the address flips, it also alternates when other bits flip -- Bits 9 |
| 54 | * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) |
| 55 | * are common to both the 915 and 965-class hardware. |
| 56 | * |
| 57 | * The CPU also sometimes XORs in higher bits as well, to improve |
| 58 | * bandwidth doing strided access like we do so frequently in graphics. This |
| 59 | * is called "Channel XOR Randomization" in the MCH documentation. The result |
| 60 | * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address |
| 61 | * decode. |
| 62 | * |
| 63 | * All of this bit 6 XORing has an effect on our memory management, |
| 64 | * as we need to make sure that the 3d driver can correctly address object |
| 65 | * contents. |
| 66 | * |
| 67 | * If we don't have interleaved memory, all tiling is safe and no swizzling is |
| 68 | * required. |
| 69 | * |
| 70 | * When bit 17 is XORed in, we simply refuse to tile at all. Bit |
| 71 | * 17 is not just a page offset, so as we page an objet out and back in, |
| 72 | * individual pages in it will have different bit 17 addresses, resulting in |
| 73 | * each 64 bytes being swapped with its neighbor! |
| 74 | * |
| 75 | * Otherwise, if interleaved, we have to tell the 3d driver what the address |
| 76 | * swizzling it needs to do is, since it's writing with the CPU to the pages |
| 77 | * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the |
| 78 | * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling |
| 79 | * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order |
| 80 | * to match what the GPU expects. |
| 81 | */ |
| 82 | |
| 83 | /** |
| 84 | * Detects bit 6 swizzling of address lookup between IGD access and CPU |
| 85 | * access through main memory. |
| 86 | */ |
| 87 | void |
| 88 | i915_gem_detect_bit_6_swizzle(struct drm_device *dev) |
| 89 | { |
| 90 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 91 | uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 92 | uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 93 | |
Jesse Barnes | 7f66134 | 2012-10-02 17:43:46 -0500 | [diff] [blame] | 94 | if (IS_VALLEYVIEW(dev)) { |
| 95 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 96 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| 97 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 98 | uint32_t dimm_c0, dimm_c1; |
| 99 | dimm_c0 = I915_READ(MAD_DIMM_C0); |
| 100 | dimm_c1 = I915_READ(MAD_DIMM_C1); |
| 101 | dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; |
| 102 | dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; |
| 103 | /* Enable swizzling when the channels are populated with |
| 104 | * identically sized dimms. We don't need to check the 3rd |
| 105 | * channel because no cpu with gpu attached ships in that |
| 106 | * configuration. Also, swizzling only makes sense for 2 |
| 107 | * channels anyway. */ |
| 108 | if (dimm_c0 == dimm_c1) { |
| 109 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| 110 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
| 111 | } else { |
| 112 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 113 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| 114 | } |
Daniel Vetter | acc83eb | 2011-09-12 20:49:16 +0200 | [diff] [blame] | 115 | } else if (IS_GEN5(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 116 | /* On Ironlake whatever DRAM config, GPU always do |
Zhenyu Wang | 553bd14 | 2009-09-02 10:57:52 +0800 | [diff] [blame] | 117 | * same swizzling setup. |
| 118 | */ |
| 119 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| 120 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 121 | } else if (IS_GEN2(dev)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 122 | /* As far as we know, the 865 doesn't have these bit 6 |
| 123 | * swizzling issues. |
| 124 | */ |
| 125 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 126 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
Daniel Vetter | c9c4b6f | 2011-12-14 13:57:15 +0100 | [diff] [blame] | 127 | } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 128 | uint32_t dcc; |
| 129 | |
Daniel Vetter | c9c4b6f | 2011-12-14 13:57:15 +0100 | [diff] [blame] | 130 | /* On 9xx chipsets, channel interleave by the CPU is |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 131 | * determined by DCC. For single-channel, neither the CPU |
| 132 | * nor the GPU do swizzling. For dual channel interleaved, |
| 133 | * the GPU's interleave is bit 9 and 10 for X tiled, and bit |
| 134 | * 9 for Y tiled. The CPU's interleave is independent, and |
| 135 | * can be based on either bit 11 (haven't seen this yet) or |
| 136 | * bit 17 (common). |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 137 | */ |
| 138 | dcc = I915_READ(DCC); |
| 139 | switch (dcc & DCC_ADDRESSING_MODE_MASK) { |
| 140 | case DCC_ADDRESSING_MODE_SINGLE_CHANNEL: |
| 141 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC: |
| 142 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 143 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| 144 | break; |
| 145 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED: |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 146 | if (dcc & DCC_CHANNEL_XOR_DISABLE) { |
| 147 | /* This is the base swizzling by the GPU for |
| 148 | * tiled buffers. |
| 149 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 150 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| 151 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 152 | } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { |
| 153 | /* Bit 11 swizzling by the CPU in addition. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 154 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_11; |
| 155 | swizzle_y = I915_BIT_6_SWIZZLE_9_11; |
| 156 | } else { |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 157 | /* Bit 17 swizzling by the CPU in addition. */ |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 158 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; |
| 159 | swizzle_y = I915_BIT_6_SWIZZLE_9_17; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 160 | } |
| 161 | break; |
| 162 | } |
| 163 | if (dcc == 0xffffffff) { |
| 164 | DRM_ERROR("Couldn't read from MCHBAR. " |
| 165 | "Disabling tiling.\n"); |
| 166 | swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 167 | swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 168 | } |
| 169 | } else { |
| 170 | /* The 965, G33, and newer, have a very flexible memory |
| 171 | * configuration. It will enable dual-channel mode |
| 172 | * (interleaving) on as much memory as it can, and the GPU |
| 173 | * will additionally sometimes enable different bit 6 |
| 174 | * swizzling for tiled objects from the CPU. |
| 175 | * |
| 176 | * Here's what I found on the G965: |
| 177 | * slot fill memory size swizzling |
| 178 | * 0A 0B 1A 1B 1-ch 2-ch |
| 179 | * 512 0 0 0 512 0 O |
| 180 | * 512 0 512 0 16 1008 X |
| 181 | * 512 0 0 512 16 1008 X |
| 182 | * 0 512 0 512 16 1008 X |
| 183 | * 1024 1024 1024 0 2048 1024 O |
| 184 | * |
| 185 | * We could probably detect this based on either the DRB |
| 186 | * matching, which was the case for the swizzling required in |
| 187 | * the table above, or from the 1-ch value being less than |
| 188 | * the minimum size of a rank. |
| 189 | */ |
| 190 | if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) { |
| 191 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 192 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| 193 | } else { |
| 194 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| 195 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
| 196 | } |
| 197 | } |
| 198 | |
| 199 | dev_priv->mm.bit_6_swizzle_x = swizzle_x; |
| 200 | dev_priv->mm.bit_6_swizzle_y = swizzle_y; |
| 201 | } |
| 202 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 203 | /* Check pitch constriants for all chips & tiling formats */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 204 | static bool |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 205 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) |
| 206 | { |
Chris Wilson | 0ee537a | 2011-03-06 09:03:16 +0000 | [diff] [blame] | 207 | int tile_width; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 208 | |
| 209 | /* Linear is always fine */ |
| 210 | if (tiling_mode == I915_TILING_NONE) |
| 211 | return true; |
| 212 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 213 | if (IS_GEN2(dev) || |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 214 | (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 215 | tile_width = 128; |
| 216 | else |
| 217 | tile_width = 512; |
| 218 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 219 | /* check maximum stride & object size */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 220 | if (INTEL_INFO(dev)->gen >= 4) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 221 | /* i965 stores the end address of the gtt mapping in the fence |
| 222 | * reg, so dont bother to check the size */ |
| 223 | if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) |
| 224 | return false; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 225 | } else { |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 226 | if (stride > 8192) |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 227 | return false; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 228 | |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 229 | if (IS_GEN3(dev)) { |
| 230 | if (size > I830_FENCE_MAX_SIZE_VAL << 20) |
| 231 | return false; |
| 232 | } else { |
| 233 | if (size > I830_FENCE_MAX_SIZE_VAL << 19) |
| 234 | return false; |
| 235 | } |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 236 | } |
| 237 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 238 | /* 965+ just needs multiples of tile width */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 239 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 240 | if (stride & (tile_width - 1)) |
| 241 | return false; |
| 242 | return true; |
| 243 | } |
| 244 | |
| 245 | /* Pre-965 needs power of two tile widths */ |
| 246 | if (stride < tile_width) |
| 247 | return false; |
| 248 | |
| 249 | if (stride & (stride - 1)) |
| 250 | return false; |
| 251 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 252 | return true; |
| 253 | } |
| 254 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 255 | /* Is the current GTT allocation valid for the change in tiling? */ |
| 256 | static bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 257 | i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 258 | { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 259 | u32 size; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 260 | |
| 261 | if (tiling_mode == I915_TILING_NONE) |
| 262 | return true; |
| 263 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 264 | if (INTEL_INFO(obj->base.dev)->gen >= 4) |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 265 | return true; |
| 266 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 267 | if (INTEL_INFO(obj->base.dev)->gen == 3) { |
| 268 | if (obj->gtt_offset & ~I915_FENCE_START_MASK) |
Chris Wilson | df15315 | 2010-11-15 05:25:58 +0000 | [diff] [blame] | 269 | return false; |
| 270 | } else { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 271 | if (obj->gtt_offset & ~I830_FENCE_START_MASK) |
Chris Wilson | df15315 | 2010-11-15 05:25:58 +0000 | [diff] [blame] | 272 | return false; |
| 273 | } |
| 274 | |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 275 | size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 276 | if (obj->gtt_space->size != size) |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 277 | return false; |
| 278 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 279 | if (obj->gtt_offset & (size - 1)) |
Chris Wilson | df15315 | 2010-11-15 05:25:58 +0000 | [diff] [blame] | 280 | return false; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 281 | |
| 282 | return true; |
| 283 | } |
| 284 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 285 | /** |
| 286 | * Sets the tiling mode of an object, returning the required swizzling of |
| 287 | * bit 6 of addresses in the object. |
| 288 | */ |
| 289 | int |
| 290 | i915_gem_set_tiling(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 291 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 292 | { |
| 293 | struct drm_i915_gem_set_tiling *args = data; |
| 294 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 295 | struct drm_i915_gem_object *obj; |
Chris Wilson | 47ae63e | 2011-03-07 12:32:44 +0000 | [diff] [blame] | 296 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 297 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 298 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 299 | if (&obj->base == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 300 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 301 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 302 | if (!i915_tiling_ok(dev, |
| 303 | args->stride, obj->base.size, args->tiling_mode)) { |
| 304 | drm_gem_object_unreference_unlocked(&obj->base); |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 305 | return -EINVAL; |
Chris Wilson | 72daad4 | 2009-01-30 21:10:22 +0000 | [diff] [blame] | 306 | } |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 307 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 308 | if (obj->pin_count) { |
| 309 | drm_gem_object_unreference_unlocked(&obj->base); |
Daniel Vetter | 31770bd | 2010-04-23 23:01:01 +0200 | [diff] [blame] | 310 | return -EBUSY; |
| 311 | } |
| 312 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 313 | if (args->tiling_mode == I915_TILING_NONE) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 314 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 315 | args->stride = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 316 | } else { |
| 317 | if (args->tiling_mode == I915_TILING_X) |
| 318 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; |
| 319 | else |
| 320 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 321 | |
| 322 | /* Hide bit 17 swizzling from the user. This prevents old Mesa |
| 323 | * from aborting the application on sw fallbacks to bit 17, |
| 324 | * and we use the pread/pwrite bit17 paths to swizzle for it. |
| 325 | * If there was a user that was relying on the swizzle |
| 326 | * information for drm_intel_bo_map()ed reads/writes this would |
| 327 | * break it, but we don't have any of those. |
| 328 | */ |
| 329 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
| 330 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
| 331 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
| 332 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; |
| 333 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 334 | /* If we can't handle the swizzling, make it untiled. */ |
| 335 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { |
| 336 | args->tiling_mode = I915_TILING_NONE; |
| 337 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 338 | args->stride = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 339 | } |
| 340 | } |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 341 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 342 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 343 | if (args->tiling_mode != obj->tiling_mode || |
| 344 | args->stride != obj->stride) { |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 345 | /* We need to rebind the object if its current allocation |
| 346 | * no longer meets the alignment restrictions for its new |
| 347 | * tiling mode. Otherwise we can just leave it alone, but |
Chris Wilson | 1869b62 | 2012-04-21 16:23:24 +0100 | [diff] [blame] | 348 | * need to ensure that any fence register is updated before |
| 349 | * the next fenced (either through the GTT or by the BLT unit |
| 350 | * on older GPUs) access. |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 351 | * |
| 352 | * After updating the tiling parameters, we then flag whether |
| 353 | * we need to update an associated fence register. Note this |
| 354 | * has to also include the unfenced register the GPU uses |
| 355 | * whilst executing a fenced command for an untiled object. |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 356 | */ |
Daniel Vetter | fe30519 | 2010-03-18 09:22:12 +0100 | [diff] [blame] | 357 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 358 | obj->map_and_fenceable = |
| 359 | obj->gtt_space == NULL || |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 360 | (obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end && |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 361 | i915_gem_object_fence_ok(obj, args->tiling_mode)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 362 | |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 363 | /* Rebind if we need a change of alignment */ |
| 364 | if (!obj->map_and_fenceable) { |
| 365 | u32 unfenced_alignment = |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 366 | i915_gem_get_gtt_alignment(dev, obj->base.size, |
| 367 | args->tiling_mode, |
| 368 | false); |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 369 | if (obj->gtt_offset & (unfenced_alignment - 1)) |
| 370 | ret = i915_gem_object_unbind(obj); |
| 371 | } |
| 372 | |
| 373 | if (ret == 0) { |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 374 | obj->fence_dirty = |
| 375 | obj->fenced_gpu_access || |
| 376 | obj->fence_reg != I915_FENCE_REG_NONE; |
| 377 | |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 378 | obj->tiling_mode = args->tiling_mode; |
| 379 | obj->stride = args->stride; |
Chris Wilson | 1869b62 | 2012-04-21 16:23:24 +0100 | [diff] [blame] | 380 | |
| 381 | /* Force the fence to be reacquired for GTT access */ |
| 382 | i915_gem_release_mmap(obj); |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 383 | } |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 384 | } |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 385 | /* we have to maintain this existing ABI... */ |
| 386 | args->stride = obj->stride; |
| 387 | args->tiling_mode = obj->tiling_mode; |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 388 | |
| 389 | /* Try to preallocate memory required to save swizzling on put-pages */ |
| 390 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
| 391 | if (obj->bit_17 == NULL) { |
| 392 | obj->bit_17 = kmalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT) * |
| 393 | sizeof(long), GFP_KERNEL); |
| 394 | } |
| 395 | } else { |
| 396 | kfree(obj->bit_17); |
| 397 | obj->bit_17 = NULL; |
| 398 | } |
| 399 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 400 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | d687310 | 2009-02-08 19:07:51 +0000 | [diff] [blame] | 401 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 402 | |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 403 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | /** |
| 407 | * Returns the current tiling mode and required bit 6 swizzling for the object. |
| 408 | */ |
| 409 | int |
| 410 | i915_gem_get_tiling(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 411 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 412 | { |
| 413 | struct drm_i915_gem_get_tiling *args = data; |
| 414 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 415 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 416 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 417 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 418 | if (&obj->base == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 419 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 420 | |
| 421 | mutex_lock(&dev->struct_mutex); |
| 422 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 423 | args->tiling_mode = obj->tiling_mode; |
| 424 | switch (obj->tiling_mode) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 425 | case I915_TILING_X: |
| 426 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; |
| 427 | break; |
| 428 | case I915_TILING_Y: |
| 429 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; |
| 430 | break; |
| 431 | case I915_TILING_NONE: |
| 432 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
| 433 | break; |
| 434 | default: |
| 435 | DRM_ERROR("unknown tiling mode\n"); |
| 436 | } |
| 437 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 438 | /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ |
| 439 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
| 440 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
| 441 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
| 442 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; |
| 443 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 444 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | d687310 | 2009-02-08 19:07:51 +0000 | [diff] [blame] | 445 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 446 | |
| 447 | return 0; |
| 448 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 449 | |
| 450 | /** |
| 451 | * Swap every 64 bytes of this page around, to account for it having a new |
| 452 | * bit 17 of its physical address and therefore being interpreted differently |
| 453 | * by the GPU. |
| 454 | */ |
Chris Wilson | dd2575f | 2010-09-04 12:59:16 +0100 | [diff] [blame] | 455 | static void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 456 | i915_gem_swizzle_page(struct page *page) |
| 457 | { |
Chris Wilson | dd2575f | 2010-09-04 12:59:16 +0100 | [diff] [blame] | 458 | char temp[64]; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 459 | char *vaddr; |
| 460 | int i; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 461 | |
| 462 | vaddr = kmap(page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 463 | |
| 464 | for (i = 0; i < PAGE_SIZE; i += 128) { |
| 465 | memcpy(temp, &vaddr[i], 64); |
| 466 | memcpy(&vaddr[i], &vaddr[i + 64], 64); |
| 467 | memcpy(&vaddr[i + 64], temp, 64); |
| 468 | } |
| 469 | |
| 470 | kunmap(page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 471 | } |
| 472 | |
| 473 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 474 | i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 475 | { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 476 | struct scatterlist *sg; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 477 | int page_count = obj->base.size >> PAGE_SHIFT; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 478 | int i; |
| 479 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 480 | if (obj->bit_17 == NULL) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 481 | return; |
| 482 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 483 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
| 484 | struct page *page = sg_page(sg); |
| 485 | char new_bit_17 = page_to_phys(page) >> 17; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 486 | if ((new_bit_17 & 0x1) != |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 487 | (test_bit(i, obj->bit_17) != 0)) { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 488 | i915_gem_swizzle_page(page); |
| 489 | set_page_dirty(page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 490 | } |
| 491 | } |
| 492 | } |
| 493 | |
| 494 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 495 | i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 496 | { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 497 | struct scatterlist *sg; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 498 | int page_count = obj->base.size >> PAGE_SHIFT; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 499 | int i; |
| 500 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 501 | if (obj->bit_17 == NULL) { |
| 502 | obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) * |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 503 | sizeof(long), GFP_KERNEL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 504 | if (obj->bit_17 == NULL) { |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 505 | DRM_ERROR("Failed to allocate memory for bit 17 " |
| 506 | "record\n"); |
| 507 | return; |
| 508 | } |
| 509 | } |
| 510 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 511 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
| 512 | struct page *page = sg_page(sg); |
| 513 | if (page_to_phys(page) & (1 << 17)) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 514 | __set_bit(i, obj->bit_17); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 515 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 516 | __clear_bit(i, obj->bit_17); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 517 | } |
| 518 | } |