blob: c3cde1a2b6de6d71956043cbd72054b6f3052438 [file] [log] [blame]
Tony Lindgren046d6b22005-11-10 14:26:52 +00001/*
Paul Walmsley8c810e72011-02-25 13:56:40 -07002 * OMAP2420 clock data
Tony Lindgren046d6b22005-11-10 14:26:52 +00003 *
Paul Walmsley8c810e72011-02-25 13:56:40 -07004 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
Tony Lindgrena16e9702008-03-18 11:56:39 +02006 *
Paul Walmsley8c810e72011-02-25 13:56:40 -07007 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
Tony Lindgren046d6b22005-11-10 14:26:52 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
Paul Walmsleyd8a94452009-12-08 16:21:29 -070016#include <linux/kernel.h>
Tony Lindgren2c799ce2012-02-24 10:34:35 -080017#include <linux/io.h>
Paul Walmsleyd8a94452009-12-08 16:21:29 -070018#include <linux/clk.h>
Paul Walmsley93340a22010-02-22 22:09:12 -070019#include <linux/list.h>
Paul Walmsleyd8a94452009-12-08 16:21:29 -070020
21#include <plat/clkdev_omap.h>
Tony Lindgren046d6b22005-11-10 14:26:52 +000022
Tony Lindgrendbc04162012-08-31 10:59:07 -070023#include "soc.h"
Tony Lindgrenee0839c2012-02-24 10:34:35 -080024#include "iomap.h"
Paul Walmsley6b8858a2008-03-18 10:35:15 +020025#include "clock.h"
Paul Walmsleyd8a94452009-12-08 16:21:29 -070026#include "clock2xxx.h"
27#include "opp2xxx.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070028#include "cm2xxx_3xxx.h"
29#include "prm2xxx_3xxx.h"
Paul Walmsley6b8858a2008-03-18 10:35:15 +020030#include "prm-regbits-24xx.h"
31#include "cm-regbits-24xx.h"
32#include "sdrc.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060033#include "control.h"
Paul Walmsley6b8858a2008-03-18 10:35:15 +020034
Paul Walmsley81b34fb2010-02-22 22:09:22 -070035#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
36
37/*
38 * 2420 clock tree.
Tony Lindgren046d6b22005-11-10 14:26:52 +000039 *
Paul Walmsley8c810e72011-02-25 13:56:40 -070040 * NOTE:In many cases here we are assigning a 'default' parent. In
41 * many cases the parent is selectable. The set parent calls will
42 * also switch sources.
Tony Lindgren046d6b22005-11-10 14:26:52 +000043 *
44 * Several sources are given initial rates which may be wrong, this will
45 * be fixed up in the init func.
46 *
47 * Things are broadly separated below by clock domains. It is
Paul Walmsley8c810e72011-02-25 13:56:40 -070048 * noteworthy that most peripherals have dependencies on multiple clock
Tony Lindgren046d6b22005-11-10 14:26:52 +000049 * domains. Many get their interface clocks from the L4 domain, but get
50 * functional clocks from fixed sources or other core domain derived
51 * clocks.
Paul Walmsley81b34fb2010-02-22 22:09:22 -070052 */
Tony Lindgren046d6b22005-11-10 14:26:52 +000053
54/* Base external input clocks */
55static struct clk func_32k_ck = {
56 .name = "func_32k_ck",
Russell King897dcde2008-11-04 16:35:03 +000057 .ops = &clkops_null,
Paul Walmsley3f9cfd32011-02-16 15:38:38 -070058 .rate = 32768,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +030059 .clkdm_name = "wkup_clkdm",
Tony Lindgren046d6b22005-11-10 14:26:52 +000060};
Paul Walmsleye32744b2008-03-18 15:47:55 +020061
Paul Walmsleyf2480762009-04-23 21:11:10 -060062static struct clk secure_32k_ck = {
63 .name = "secure_32k_ck",
64 .ops = &clkops_null,
65 .rate = 32768,
Paul Walmsleyf2480762009-04-23 21:11:10 -060066 .clkdm_name = "wkup_clkdm",
67};
68
Tony Lindgren046d6b22005-11-10 14:26:52 +000069/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
70static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
71 .name = "osc_ck",
Russell King548d8492008-11-04 14:02:46 +000072 .ops = &clkops_oscck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +030073 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +020074 .recalc = &omap2_osc_clk_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +000075};
76
Paul Walmsleyd1b03f62008-08-19 11:08:44 +030077/* Without modem likely 12MHz, with modem likely 13MHz */
Tony Lindgren046d6b22005-11-10 14:26:52 +000078static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
79 .name = "sys_ck", /* ~ ref_clk also */
Russell King897dcde2008-11-04 16:35:03 +000080 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +000081 .parent = &osc_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +030082 .clkdm_name = "wkup_clkdm",
Paul Walmsley44da0a52010-01-26 20:13:08 -070083 .recalc = &omap2xxx_sys_clk_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +000084};
Paul Walmsleye32744b2008-03-18 15:47:55 +020085
Tony Lindgren046d6b22005-11-10 14:26:52 +000086static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
87 .name = "alt_ck",
Russell King897dcde2008-11-04 16:35:03 +000088 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +000089 .rate = 54000000,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +030090 .clkdm_name = "wkup_clkdm",
Tony Lindgren046d6b22005-11-10 14:26:52 +000091};
Paul Walmsleye32744b2008-03-18 15:47:55 +020092
Paul Walmsley1bccb342010-10-08 11:40:17 -060093/* Optional external clock input for McBSP CLKS */
94static struct clk mcbsp_clks = {
95 .name = "mcbsp_clks",
96 .ops = &clkops_null,
97};
98
Tony Lindgren046d6b22005-11-10 14:26:52 +000099/*
100 * Analog domain root source clocks
101 */
102
103/* dpll_ck, is broken out in to special cases through clksel */
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200104/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
105 * deal with this
106 */
107
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300108static struct dpll_data dpll_dd = {
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200109 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
110 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
111 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
Russell Kingc0bf3132009-02-19 13:29:22 +0000112 .clk_bypass = &sys_ck,
113 .clk_ref = &sys_ck,
114 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
115 .enable_mask = OMAP24XX_EN_DPLL_MASK,
Paul Walmsley93340a22010-02-22 22:09:12 -0700116 .max_multiplier = 1023,
Paul Walmsley95f538a2009-01-28 12:08:44 -0700117 .min_divider = 1,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300118 .max_divider = 16,
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200119};
120
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300121/*
122 * XXX Cannot add round_rate here yet, as this is still a composite clock,
123 * not just a DPLL
124 */
Tony Lindgren046d6b22005-11-10 14:26:52 +0000125static struct clk dpll_ck = {
126 .name = "dpll_ck",
Paul Walmsley0fd0c212011-02-25 15:49:53 -0700127 .ops = &clkops_omap2xxx_dpll_ops,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000128 .parent = &sys_ck, /* Can be func_32k also */
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200129 .dpll_data = &dpll_dd,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300130 .clkdm_name = "wkup_clkdm",
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300131 .recalc = &omap2_dpllcore_recalc,
132 .set_rate = &omap2_reprogram_dpllcore,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000133};
134
135static struct clk apll96_ck = {
136 .name = "apll96_ck",
Paul Walmsley06b16932009-12-08 16:18:46 -0700137 .ops = &clkops_apll96,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000138 .parent = &sys_ck,
139 .rate = 96000000,
Paul Walmsley51c19542010-02-22 22:09:26 -0700140 .flags = ENABLE_ON_INIT,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300141 .clkdm_name = "wkup_clkdm",
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200142 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
143 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000144};
145
146static struct clk apll54_ck = {
147 .name = "apll54_ck",
Paul Walmsley06b16932009-12-08 16:18:46 -0700148 .ops = &clkops_apll54,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000149 .parent = &sys_ck,
150 .rate = 54000000,
Paul Walmsley51c19542010-02-22 22:09:26 -0700151 .flags = ENABLE_ON_INIT,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300152 .clkdm_name = "wkup_clkdm",
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200153 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
154 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000155};
156
157/*
158 * PRCM digital base sources
159 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200160
161/* func_54m_ck */
162
163static const struct clksel_rate func_54m_apll54_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600164 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200165 { .div = 0 },
166};
167
168static const struct clksel_rate func_54m_alt_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600169 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200170 { .div = 0 },
171};
172
173static const struct clksel func_54m_clksel[] = {
174 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
175 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
176 { .parent = NULL },
177};
178
Tony Lindgren046d6b22005-11-10 14:26:52 +0000179static struct clk func_54m_ck = {
180 .name = "func_54m_ck",
Russell King57137182008-11-04 16:48:35 +0000181 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000182 .parent = &apll54_ck, /* can also be alt_clk */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300183 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200184 .init = &omap2_init_clksel_parent,
185 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Paul Walmsleyf38ca102010-05-20 12:31:04 -0600186 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200187 .clksel = func_54m_clksel,
188 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000189};
Paul Walmsleye32744b2008-03-18 15:47:55 +0200190
Tony Lindgren046d6b22005-11-10 14:26:52 +0000191static struct clk core_ck = {
192 .name = "core_ck",
Russell King897dcde2008-11-04 16:35:03 +0000193 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000194 .parent = &dpll_ck, /* can also be 32k */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300195 .clkdm_name = "wkup_clkdm",
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200196 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000197};
Paul Walmsleye32744b2008-03-18 15:47:55 +0200198
Tony Lindgren046d6b22005-11-10 14:26:52 +0000199static struct clk func_96m_ck = {
200 .name = "func_96m_ck",
Russell King57137182008-11-04 16:48:35 +0000201 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000202 .parent = &apll96_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300203 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700204 .recalc = &followparent_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200205};
206
207/* func_48m_ck */
208
209static const struct clksel_rate func_48m_apll96_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600210 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200211 { .div = 0 },
212};
213
214static const struct clksel_rate func_48m_alt_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600215 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200216 { .div = 0 },
217};
218
219static const struct clksel func_48m_clksel[] = {
220 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
221 { .parent = &alt_ck, .rates = func_48m_alt_rates },
222 { .parent = NULL }
Tony Lindgren046d6b22005-11-10 14:26:52 +0000223};
224
225static struct clk func_48m_ck = {
226 .name = "func_48m_ck",
Russell King57137182008-11-04 16:48:35 +0000227 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000228 .parent = &apll96_ck, /* 96M or Alt */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300229 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200230 .init = &omap2_init_clksel_parent,
231 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Paul Walmsleyf38ca102010-05-20 12:31:04 -0600232 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200233 .clksel = func_48m_clksel,
234 .recalc = &omap2_clksel_recalc,
235 .round_rate = &omap2_clksel_round_rate,
236 .set_rate = &omap2_clksel_set_rate
Tony Lindgren046d6b22005-11-10 14:26:52 +0000237};
238
239static struct clk func_12m_ck = {
240 .name = "func_12m_ck",
Russell King57137182008-11-04 16:48:35 +0000241 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000242 .parent = &func_48m_ck,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200243 .fixed_div = 4,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300244 .clkdm_name = "wkup_clkdm",
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700245 .recalc = &omap_fixed_divisor_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000246};
247
248/* Secure timer, only available in secure mode */
249static struct clk wdt1_osc_ck = {
250 .name = "ck_wdt1_osc",
Russell King897dcde2008-11-04 16:35:03 +0000251 .ops = &clkops_null, /* RMK: missing? */
Tony Lindgren046d6b22005-11-10 14:26:52 +0000252 .parent = &osc_ck,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200253 .recalc = &followparent_recalc,
254};
255
256/*
257 * The common_clkout* clksel_rate structs are common to
258 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
259 * sys_clkout2_* are 2420-only, so the
260 * clksel_rate flags fields are inaccurate for those clocks. This is
261 * harmless since access to those clocks are gated by the struct clk
262 * flags fields, which mark them as 2420-only.
263 */
264static const struct clksel_rate common_clkout_src_core_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600265 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200266 { .div = 0 }
267};
268
269static const struct clksel_rate common_clkout_src_sys_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600270 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200271 { .div = 0 }
272};
273
274static const struct clksel_rate common_clkout_src_96m_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600275 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200276 { .div = 0 }
277};
278
279static const struct clksel_rate common_clkout_src_54m_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600280 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200281 { .div = 0 }
282};
283
284static const struct clksel common_clkout_src_clksel[] = {
285 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
286 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
287 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
288 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
289 { .parent = NULL }
290};
291
292static struct clk sys_clkout_src = {
293 .name = "sys_clkout_src",
Russell Kingc1168dc2008-11-04 21:24:00 +0000294 .ops = &clkops_omap2_dflt,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200295 .parent = &func_54m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300296 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700297 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200298 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
299 .init = &omap2_init_clksel_parent,
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700300 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200301 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
302 .clksel = common_clkout_src_clksel,
303 .recalc = &omap2_clksel_recalc,
304 .round_rate = &omap2_clksel_round_rate,
305 .set_rate = &omap2_clksel_set_rate
306};
307
308static const struct clksel_rate common_clkout_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600309 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200310 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
311 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
312 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
313 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
314 { .div = 0 },
315};
316
317static const struct clksel sys_clkout_clksel[] = {
318 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
319 { .parent = NULL }
Tony Lindgren046d6b22005-11-10 14:26:52 +0000320};
321
322static struct clk sys_clkout = {
323 .name = "sys_clkout",
Russell King57137182008-11-04 16:48:35 +0000324 .ops = &clkops_null,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200325 .parent = &sys_clkout_src,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300326 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700327 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200328 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
329 .clksel = sys_clkout_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000330 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200331 .round_rate = &omap2_clksel_round_rate,
332 .set_rate = &omap2_clksel_set_rate
333};
334
335/* In 2430, new in 2420 ES2 */
336static struct clk sys_clkout2_src = {
337 .name = "sys_clkout2_src",
Russell Kingc1168dc2008-11-04 21:24:00 +0000338 .ops = &clkops_omap2_dflt,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200339 .parent = &func_54m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300340 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700341 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200342 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
343 .init = &omap2_init_clksel_parent,
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700344 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200345 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
346 .clksel = common_clkout_src_clksel,
347 .recalc = &omap2_clksel_recalc,
348 .round_rate = &omap2_clksel_round_rate,
349 .set_rate = &omap2_clksel_set_rate
350};
351
352static const struct clksel sys_clkout2_clksel[] = {
353 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
354 { .parent = NULL }
Tony Lindgren046d6b22005-11-10 14:26:52 +0000355};
356
357/* In 2430, new in 2420 ES2 */
358static struct clk sys_clkout2 = {
359 .name = "sys_clkout2",
Russell King57137182008-11-04 16:48:35 +0000360 .ops = &clkops_null,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200361 .parent = &sys_clkout2_src,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300362 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700363 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200364 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
365 .clksel = sys_clkout2_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000366 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200367 .round_rate = &omap2_clksel_round_rate,
368 .set_rate = &omap2_clksel_set_rate
Tony Lindgren046d6b22005-11-10 14:26:52 +0000369};
370
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100371static struct clk emul_ck = {
372 .name = "emul_ck",
Russell Kingc1168dc2008-11-04 21:24:00 +0000373 .ops = &clkops_omap2_dflt,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100374 .parent = &func_54m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300375 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700376 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200377 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
378 .recalc = &followparent_recalc,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100379
380};
Paul Walmsleye32744b2008-03-18 15:47:55 +0200381
Tony Lindgren046d6b22005-11-10 14:26:52 +0000382/*
383 * MPU clock domain
384 * Clocks:
385 * MPU_FCLK, MPU_ICLK
386 * INT_M_FCLK, INT_M_I_CLK
387 *
388 * - Individual clocks are hardware managed.
389 * - Base divider comes from: CM_CLKSEL_MPU
390 *
391 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200392static const struct clksel_rate mpu_core_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600393 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200394 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
395 { .div = 4, .val = 4, .flags = RATE_IN_242X },
396 { .div = 6, .val = 6, .flags = RATE_IN_242X },
397 { .div = 8, .val = 8, .flags = RATE_IN_242X },
398 { .div = 0 },
399};
400
401static const struct clksel mpu_clksel[] = {
402 { .parent = &core_ck, .rates = mpu_core_rates },
403 { .parent = NULL }
404};
405
Tony Lindgren046d6b22005-11-10 14:26:52 +0000406static struct clk mpu_ck = { /* Control cpu */
407 .name = "mpu_ck",
Russell King897dcde2008-11-04 16:35:03 +0000408 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000409 .parent = &core_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300410 .clkdm_name = "mpu_clkdm",
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200411 .init = &omap2_init_clksel_parent,
412 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
413 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200414 .clksel = mpu_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000415 .recalc = &omap2_clksel_recalc,
416};
Paul Walmsleye32744b2008-03-18 15:47:55 +0200417
Tony Lindgren046d6b22005-11-10 14:26:52 +0000418/*
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700419 * DSP (2420-UMA+IVA1) clock domain
Tony Lindgren046d6b22005-11-10 14:26:52 +0000420 * Clocks:
Tony Lindgren046d6b22005-11-10 14:26:52 +0000421 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
Paul Walmsleye32744b2008-03-18 15:47:55 +0200422 *
Tony Lindgren046d6b22005-11-10 14:26:52 +0000423 * Won't be too specific here. The core clock comes into this block
424 * it is divided then tee'ed. One branch goes directly to xyz enable
425 * controls. The other branch gets further divided by 2 then possibly
426 * routed into a synchronizer and out of clocks abc.
427 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200428static const struct clksel_rate dsp_fck_core_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600429 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200430 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
431 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
432 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
433 { .div = 6, .val = 6, .flags = RATE_IN_242X },
434 { .div = 8, .val = 8, .flags = RATE_IN_242X },
435 { .div = 12, .val = 12, .flags = RATE_IN_242X },
436 { .div = 0 },
437};
438
439static const struct clksel dsp_fck_clksel[] = {
440 { .parent = &core_ck, .rates = dsp_fck_core_rates },
441 { .parent = NULL }
442};
443
Tony Lindgren046d6b22005-11-10 14:26:52 +0000444static struct clk dsp_fck = {
445 .name = "dsp_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000446 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000447 .parent = &core_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300448 .clkdm_name = "dsp_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200449 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
450 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
451 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
452 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
453 .clksel = dsp_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000454 .recalc = &omap2_clksel_recalc,
455};
456
Paul Walmsley22411392011-02-25 15:52:04 -0700457static const struct clksel dsp_ick_clksel[] = {
458 { .parent = &dsp_fck, .rates = dsp_ick_rates },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200459 { .parent = NULL }
460};
461
Tony Lindgren046d6b22005-11-10 14:26:52 +0000462static struct clk dsp_ick = {
463 .name = "dsp_ick", /* apparently ipi and isp */
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700464 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley22411392011-02-25 15:52:04 -0700465 .parent = &dsp_fck,
466 .clkdm_name = "dsp_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200467 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
468 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
Paul Walmsley22411392011-02-25 15:52:04 -0700469 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
470 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
471 .clksel = dsp_ick_clksel,
472 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200473};
474
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300475/*
476 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
477 * the C54x, but which is contained in the DSP powerdomain. Does not
478 * exist on later OMAPs.
479 */
Tony Lindgren046d6b22005-11-10 14:26:52 +0000480static struct clk iva1_ifck = {
481 .name = "iva1_ifck",
Russell Kingb36ee722008-11-04 17:59:52 +0000482 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000483 .parent = &core_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300484 .clkdm_name = "iva1_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200485 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
486 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
487 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
488 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
489 .clksel = dsp_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000490 .recalc = &omap2_clksel_recalc,
491};
492
493/* IVA1 mpu/int/i/f clocks are /2 of parent */
494static struct clk iva1_mpu_int_ifck = {
495 .name = "iva1_mpu_int_ifck",
Russell Kingb36ee722008-11-04 17:59:52 +0000496 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000497 .parent = &iva1_ifck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300498 .clkdm_name = "iva1_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200499 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
500 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
501 .fixed_div = 2,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700502 .recalc = &omap_fixed_divisor_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000503};
504
505/*
506 * L3 clock domain
507 * L3 clocks are used for both interface and functional clocks to
508 * multiple entities. Some of these clocks are completely managed
509 * by hardware, and some others allow software control. Hardware
510 * managed ones general are based on directly CLK_REQ signals and
511 * various auto idle settings. The functional spec sets many of these
512 * as 'tie-high' for their enables.
513 *
514 * I-CLOCKS:
515 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
516 * CAM, HS-USB.
517 * F-CLOCK
518 * SSI.
519 *
520 * GPMC memories and SDRC have timing and clock sensitive registers which
521 * may very well need notification when the clock changes. Currently for low
522 * operating points, these are taken care of in sleep.S.
523 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200524static const struct clksel_rate core_l3_core_rates[] = {
525 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
526 { .div = 2, .val = 2, .flags = RATE_IN_242X },
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600527 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200528 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
529 { .div = 8, .val = 8, .flags = RATE_IN_242X },
530 { .div = 12, .val = 12, .flags = RATE_IN_242X },
531 { .div = 16, .val = 16, .flags = RATE_IN_242X },
532 { .div = 0 }
533};
534
535static const struct clksel core_l3_clksel[] = {
536 { .parent = &core_ck, .rates = core_l3_core_rates },
537 { .parent = NULL }
538};
539
Tony Lindgren046d6b22005-11-10 14:26:52 +0000540static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
541 .name = "core_l3_ck",
Russell King897dcde2008-11-04 16:35:03 +0000542 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000543 .parent = &core_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300544 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200545 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
546 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
547 .clksel = core_l3_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000548 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200549};
550
551/* usb_l4_ick */
552static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
553 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600554 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200555 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
556 { .div = 0 }
557};
558
559static const struct clksel usb_l4_ick_clksel[] = {
560 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
561 { .parent = NULL },
Tony Lindgren046d6b22005-11-10 14:26:52 +0000562};
563
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300564/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
Tony Lindgren046d6b22005-11-10 14:26:52 +0000565static struct clk usb_l4_ick = { /* FS-USB interface clock */
566 .name = "usb_l4_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700567 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgrenfde0fd42006-01-17 15:31:18 -0800568 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300569 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
571 .enable_bit = OMAP24XX_EN_USB_SHIFT,
572 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
573 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
574 .clksel = usb_l4_ick_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000575 .recalc = &omap2_clksel_recalc,
576};
577
578/*
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300579 * L4 clock management domain
580 *
581 * This domain contains lots of interface clocks from the L4 interface, some
582 * functional clocks. Fixed APLL functional source clocks are managed in
583 * this domain.
584 */
585static const struct clksel_rate l4_core_l3_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600586 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300587 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
588 { .div = 0 }
589};
590
591static const struct clksel l4_clksel[] = {
592 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
593 { .parent = NULL }
594};
595
596static struct clk l4_ck = { /* used both as an ick and fck */
597 .name = "l4_ck",
Russell King897dcde2008-11-04 16:35:03 +0000598 .ops = &clkops_null,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300599 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300600 .clkdm_name = "core_l4_clkdm",
601 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
602 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
603 .clksel = l4_clksel,
604 .recalc = &omap2_clksel_recalc,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300605};
606
607/*
Tony Lindgren046d6b22005-11-10 14:26:52 +0000608 * SSI is in L3 management domain, its direct parent is core not l3,
609 * many core power domain entities are grouped into the L3 clock
610 * domain.
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300611 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
Tony Lindgren046d6b22005-11-10 14:26:52 +0000612 *
613 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
614 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200615static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
616 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600617 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200618 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
619 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200620 { .div = 6, .val = 6, .flags = RATE_IN_242X },
621 { .div = 8, .val = 8, .flags = RATE_IN_242X },
622 { .div = 0 }
623};
624
625static const struct clksel ssi_ssr_sst_fck_clksel[] = {
626 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
627 { .parent = NULL }
628};
629
Tony Lindgren046d6b22005-11-10 14:26:52 +0000630static struct clk ssi_ssr_sst_fck = {
631 .name = "ssi_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000632 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000633 .parent = &core_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300634 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200635 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
636 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
637 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
638 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
639 .clksel = ssi_ssr_sst_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000640 .recalc = &omap2_clksel_recalc,
641};
642
Paul Walmsley9299fd82009-01-27 19:12:54 -0700643/*
644 * Presumably this is the same as SSI_ICLK.
645 * TRM contradicts itself on what clockdomain SSI_ICLK is in
646 */
647static struct clk ssi_l4_ick = {
648 .name = "ssi_l4_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700649 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley9299fd82009-01-27 19:12:54 -0700650 .parent = &l4_ck,
651 .clkdm_name = "core_l4_clkdm",
652 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
653 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
654 .recalc = &followparent_recalc,
655};
656
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300657
Tony Lindgren046d6b22005-11-10 14:26:52 +0000658/*
659 * GFX clock domain
660 * Clocks:
661 * GFX_FCLK, GFX_ICLK
662 * GFX_CG1(2d), GFX_CG2(3d)
663 *
664 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
665 * The 2d and 3d clocks run at a hardware determined
666 * divided value of fclk.
667 *
668 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200669
670/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
671static const struct clksel gfx_fck_clksel[] = {
672 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
673 { .parent = NULL },
674};
675
Tony Lindgren046d6b22005-11-10 14:26:52 +0000676static struct clk gfx_3d_fck = {
677 .name = "gfx_3d_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000678 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000679 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300680 .clkdm_name = "gfx_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200681 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
682 .enable_bit = OMAP24XX_EN_3D_SHIFT,
683 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
684 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
685 .clksel = gfx_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000686 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200687 .round_rate = &omap2_clksel_round_rate,
688 .set_rate = &omap2_clksel_set_rate
Tony Lindgren046d6b22005-11-10 14:26:52 +0000689};
690
691static struct clk gfx_2d_fck = {
692 .name = "gfx_2d_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000693 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000694 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300695 .clkdm_name = "gfx_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200696 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
697 .enable_bit = OMAP24XX_EN_2D_SHIFT,
698 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
699 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
700 .clksel = gfx_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000701 .recalc = &omap2_clksel_recalc,
702};
703
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700704/* This interface clock does not have a CM_AUTOIDLE bit */
Tony Lindgren046d6b22005-11-10 14:26:52 +0000705static struct clk gfx_ick = {
706 .name = "gfx_ick", /* From l3 */
Russell Kingb36ee722008-11-04 17:59:52 +0000707 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000708 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300709 .clkdm_name = "gfx_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200710 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
711 .enable_bit = OMAP_EN_GFX_SHIFT,
712 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000713};
714
715/*
Tony Lindgren046d6b22005-11-10 14:26:52 +0000716 * DSS clock domain
717 * CLOCKs:
718 * DSS_L4_ICLK, DSS_L3_ICLK,
719 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
720 *
721 * DSS is both initiator and target.
722 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200723/* XXX Add RATE_NOT_VALIDATED */
724
725static const struct clksel_rate dss1_fck_sys_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600726 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200727 { .div = 0 }
728};
729
730static const struct clksel_rate dss1_fck_core_rates[] = {
731 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
732 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
733 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
734 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
735 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
736 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
737 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
738 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
739 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600740 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200741 { .div = 0 }
742};
743
744static const struct clksel dss1_fck_clksel[] = {
745 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
746 { .parent = &core_ck, .rates = dss1_fck_core_rates },
747 { .parent = NULL },
748};
749
Tony Lindgren046d6b22005-11-10 14:26:52 +0000750static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
751 .name = "dss_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700752 .ops = &clkops_omap2_iclk_dflt,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000753 .parent = &l4_ck, /* really both l3 and l4 */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300754 .clkdm_name = "dss_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200755 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
756 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
757 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000758};
759
760static struct clk dss1_fck = {
761 .name = "dss1_fck",
Russell Kingbc51da42008-11-04 18:59:32 +0000762 .ops = &clkops_omap2_dflt,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000763 .parent = &core_ck, /* Core or sys */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300764 .clkdm_name = "dss_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
766 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
767 .init = &omap2_init_clksel_parent,
768 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
769 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
770 .clksel = dss1_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000771 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200772};
773
774static const struct clksel_rate dss2_fck_sys_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600775 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200776 { .div = 0 }
777};
778
779static const struct clksel_rate dss2_fck_48m_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600780 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200781 { .div = 0 }
782};
783
784static const struct clksel dss2_fck_clksel[] = {
785 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
786 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
787 { .parent = NULL }
Tony Lindgren046d6b22005-11-10 14:26:52 +0000788};
789
790static struct clk dss2_fck = { /* Alt clk used in power management */
791 .name = "dss2_fck",
Russell Kingbc51da42008-11-04 18:59:32 +0000792 .ops = &clkops_omap2_dflt,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000793 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300794 .clkdm_name = "dss_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200795 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
796 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
797 .init = &omap2_init_clksel_parent,
798 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
799 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
800 .clksel = dss2_fck_clksel,
Paul Walmsleyd4521f62010-12-21 21:08:14 -0700801 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000802};
803
804static struct clk dss_54m_fck = { /* Alt clk used in power management */
805 .name = "dss_54m_fck", /* 54m tv clk */
Russell Kingb36ee722008-11-04 17:59:52 +0000806 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000807 .parent = &func_54m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300808 .clkdm_name = "dss_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
810 .enable_bit = OMAP24XX_EN_TV_SHIFT,
811 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000812};
813
Paul Walmsley19c1c0c2011-02-16 15:38:38 -0700814static struct clk wu_l4_ick = {
815 .name = "wu_l4_ick",
816 .ops = &clkops_null,
817 .parent = &sys_ck,
818 .clkdm_name = "wkup_clkdm",
819 .recalc = &followparent_recalc,
820};
821
Tony Lindgren046d6b22005-11-10 14:26:52 +0000822/*
823 * CORE power domain ICLK & FCLK defines.
824 * Many of the these can have more than one possible parent. Entries
825 * here will likely have an L4 interface parent, and may have multiple
826 * functional clock parents.
827 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200828static const struct clksel_rate gpt_alt_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600829 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200830 { .div = 0 }
831};
832
833static const struct clksel omap24xx_gpt_clksel[] = {
834 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
835 { .parent = &sys_ck, .rates = gpt_sys_rates },
836 { .parent = &alt_ck, .rates = gpt_alt_rates },
837 { .parent = NULL },
838};
839
Tony Lindgren046d6b22005-11-10 14:26:52 +0000840static struct clk gpt1_ick = {
841 .name = "gpt1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700842 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -0700843 .parent = &wu_l4_ick,
844 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200845 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
846 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
847 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000848};
849
850static struct clk gpt1_fck = {
851 .name = "gpt1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000852 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000853 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300854 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200855 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
856 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
857 .init = &omap2_init_clksel_parent,
858 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
859 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
860 .clksel = omap24xx_gpt_clksel,
861 .recalc = &omap2_clksel_recalc,
862 .round_rate = &omap2_clksel_round_rate,
863 .set_rate = &omap2_clksel_set_rate
Tony Lindgren046d6b22005-11-10 14:26:52 +0000864};
865
866static struct clk gpt2_ick = {
867 .name = "gpt2_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700868 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000869 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300870 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
872 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
873 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000874};
875
876static struct clk gpt2_fck = {
877 .name = "gpt2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000878 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000879 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300880 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
882 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
883 .init = &omap2_init_clksel_parent,
884 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
885 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
886 .clksel = omap24xx_gpt_clksel,
887 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000888};
889
890static struct clk gpt3_ick = {
891 .name = "gpt3_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700892 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000893 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300894 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
896 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
897 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000898};
899
900static struct clk gpt3_fck = {
901 .name = "gpt3_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000902 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000903 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300904 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
906 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
907 .init = &omap2_init_clksel_parent,
908 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
909 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
910 .clksel = omap24xx_gpt_clksel,
911 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000912};
913
914static struct clk gpt4_ick = {
915 .name = "gpt4_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700916 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000917 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300918 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200919 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
920 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
921 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000922};
923
924static struct clk gpt4_fck = {
925 .name = "gpt4_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000926 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000927 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300928 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200929 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
930 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
931 .init = &omap2_init_clksel_parent,
932 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
933 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
934 .clksel = omap24xx_gpt_clksel,
935 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000936};
937
938static struct clk gpt5_ick = {
939 .name = "gpt5_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700940 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000941 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300942 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200943 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
944 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
945 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000946};
947
948static struct clk gpt5_fck = {
949 .name = "gpt5_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000950 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000951 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300952 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200953 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
954 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
955 .init = &omap2_init_clksel_parent,
956 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
957 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
958 .clksel = omap24xx_gpt_clksel,
959 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000960};
961
962static struct clk gpt6_ick = {
963 .name = "gpt6_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700964 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000965 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300966 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200967 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
968 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
969 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000970};
971
972static struct clk gpt6_fck = {
973 .name = "gpt6_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000974 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000975 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300976 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
978 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
979 .init = &omap2_init_clksel_parent,
980 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
981 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
982 .clksel = omap24xx_gpt_clksel,
983 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000984};
985
986static struct clk gpt7_ick = {
987 .name = "gpt7_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700988 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000989 .parent = &l4_ck,
Paul Walmsleya4fc9272011-02-25 14:53:40 -0700990 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
992 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
993 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000994};
995
996static struct clk gpt7_fck = {
997 .name = "gpt7_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000998 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000999 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001000 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1002 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1003 .init = &omap2_init_clksel_parent,
1004 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1005 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1006 .clksel = omap24xx_gpt_clksel,
1007 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001008};
1009
1010static struct clk gpt8_ick = {
1011 .name = "gpt8_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001012 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001013 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001014 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1016 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1017 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001018};
1019
1020static struct clk gpt8_fck = {
1021 .name = "gpt8_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001022 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001023 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001024 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001025 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1026 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1027 .init = &omap2_init_clksel_parent,
1028 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1029 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1030 .clksel = omap24xx_gpt_clksel,
1031 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001032};
1033
1034static struct clk gpt9_ick = {
1035 .name = "gpt9_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001036 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001037 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001038 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1040 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1041 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001042};
1043
1044static struct clk gpt9_fck = {
1045 .name = "gpt9_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001046 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001047 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001048 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001049 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1050 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1051 .init = &omap2_init_clksel_parent,
1052 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1053 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1054 .clksel = omap24xx_gpt_clksel,
1055 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001056};
1057
1058static struct clk gpt10_ick = {
1059 .name = "gpt10_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001060 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001061 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001062 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001063 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1064 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1065 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001066};
1067
1068static struct clk gpt10_fck = {
1069 .name = "gpt10_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001070 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001071 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001072 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001073 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1074 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1075 .init = &omap2_init_clksel_parent,
1076 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1077 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1078 .clksel = omap24xx_gpt_clksel,
1079 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001080};
1081
1082static struct clk gpt11_ick = {
1083 .name = "gpt11_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001084 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001085 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001086 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001087 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1088 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1089 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001090};
1091
1092static struct clk gpt11_fck = {
1093 .name = "gpt11_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001094 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001095 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001096 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001097 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1098 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1099 .init = &omap2_init_clksel_parent,
1100 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1101 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1102 .clksel = omap24xx_gpt_clksel,
1103 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001104};
1105
1106static struct clk gpt12_ick = {
1107 .name = "gpt12_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001108 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001109 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001110 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001111 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1112 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1113 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001114};
1115
1116static struct clk gpt12_fck = {
1117 .name = "gpt12_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001118 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyf2480762009-04-23 21:11:10 -06001119 .parent = &secure_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001120 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001121 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1122 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1123 .init = &omap2_init_clksel_parent,
1124 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1125 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1126 .clksel = omap24xx_gpt_clksel,
1127 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001128};
1129
1130static struct clk mcbsp1_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001131 .name = "mcbsp1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001132 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001133 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001134 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001135 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1136 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1137 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001138};
1139
Paul Walmsley1bccb342010-10-08 11:40:17 -06001140static const struct clksel_rate common_mcbsp_96m_rates[] = {
1141 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1142 { .div = 0 }
1143};
1144
1145static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1146 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1147 { .div = 0 }
1148};
1149
1150static const struct clksel mcbsp_fck_clksel[] = {
1151 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1152 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1153 { .parent = NULL }
1154};
1155
Tony Lindgren046d6b22005-11-10 14:26:52 +00001156static struct clk mcbsp1_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001157 .name = "mcbsp1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001158 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001159 .parent = &func_96m_ck,
Paul Walmsley1bccb342010-10-08 11:40:17 -06001160 .init = &omap2_init_clksel_parent,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001161 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001162 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1163 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
Paul Walmsley1bccb342010-10-08 11:40:17 -06001164 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1165 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1166 .clksel = mcbsp_fck_clksel,
1167 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001168};
1169
1170static struct clk mcbsp2_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001171 .name = "mcbsp2_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001172 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001173 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001174 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001175 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1176 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1177 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001178};
1179
1180static struct clk mcbsp2_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001181 .name = "mcbsp2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001182 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001183 .parent = &func_96m_ck,
Paul Walmsley1bccb342010-10-08 11:40:17 -06001184 .init = &omap2_init_clksel_parent,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001185 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1187 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
Paul Walmsley1bccb342010-10-08 11:40:17 -06001188 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1189 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1190 .clksel = mcbsp_fck_clksel,
1191 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001192};
1193
Tony Lindgren046d6b22005-11-10 14:26:52 +00001194static struct clk mcspi1_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001195 .name = "mcspi1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001196 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001197 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001198 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001199 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1200 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1201 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001202};
1203
1204static struct clk mcspi1_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001205 .name = "mcspi1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001206 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001207 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001208 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001209 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1210 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1211 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001212};
1213
1214static struct clk mcspi2_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001215 .name = "mcspi2_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001216 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001217 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001218 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001219 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1220 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1221 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001222};
1223
1224static struct clk mcspi2_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001225 .name = "mcspi2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001226 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001227 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001228 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001229 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1230 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1231 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001232};
1233
Tony Lindgren046d6b22005-11-10 14:26:52 +00001234static struct clk uart1_ick = {
1235 .name = "uart1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001236 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001237 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001238 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001239 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1240 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1241 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001242};
1243
1244static struct clk uart1_fck = {
1245 .name = "uart1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001246 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001247 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001248 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001249 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1250 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1251 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001252};
1253
1254static struct clk uart2_ick = {
1255 .name = "uart2_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001256 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001257 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001258 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001259 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1260 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1261 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001262};
1263
1264static struct clk uart2_fck = {
1265 .name = "uart2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001266 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001267 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001268 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001269 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1270 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1271 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001272};
1273
1274static struct clk uart3_ick = {
1275 .name = "uart3_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001276 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001277 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001278 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001279 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1280 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1281 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001282};
1283
1284static struct clk uart3_fck = {
1285 .name = "uart3_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001286 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001287 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001288 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001289 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1290 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1291 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001292};
1293
1294static struct clk gpios_ick = {
1295 .name = "gpios_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001296 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001297 .parent = &wu_l4_ick,
1298 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001299 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1300 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1301 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001302};
1303
1304static struct clk gpios_fck = {
1305 .name = "gpios_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001306 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001307 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001308 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001309 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1310 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1311 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001312};
1313
1314static struct clk mpu_wdt_ick = {
1315 .name = "mpu_wdt_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001316 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001317 .parent = &wu_l4_ick,
1318 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001319 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1320 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1321 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001322};
1323
1324static struct clk mpu_wdt_fck = {
1325 .name = "mpu_wdt_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001326 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001327 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001328 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001329 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1330 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1331 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001332};
1333
1334static struct clk sync_32k_ick = {
1335 .name = "sync_32k_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001336 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001337 .parent = &wu_l4_ick,
1338 .clkdm_name = "wkup_clkdm",
Russell King8ad8ff62009-01-19 15:27:29 +00001339 .flags = ENABLE_ON_INIT,
Paul Walmsleye32744b2008-03-18 15:47:55 +02001340 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1341 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1342 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001343};
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001344
Tony Lindgren046d6b22005-11-10 14:26:52 +00001345static struct clk wdt1_ick = {
1346 .name = "wdt1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001347 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001348 .parent = &wu_l4_ick,
1349 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001350 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1351 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1352 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001353};
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001354
Tony Lindgren046d6b22005-11-10 14:26:52 +00001355static struct clk omapctrl_ick = {
1356 .name = "omapctrl_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001357 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001358 .parent = &wu_l4_ick,
1359 .clkdm_name = "wkup_clkdm",
Russell King8ad8ff62009-01-19 15:27:29 +00001360 .flags = ENABLE_ON_INIT,
Paul Walmsleye32744b2008-03-18 15:47:55 +02001361 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1362 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1363 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001364};
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001365
Tony Lindgren046d6b22005-11-10 14:26:52 +00001366static struct clk cam_ick = {
1367 .name = "cam_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001368 .ops = &clkops_omap2_iclk_dflt,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001369 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001370 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1372 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1373 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001374};
1375
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001376/*
1377 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1378 * split into two separate clocks, since the parent clocks are different
1379 * and the clockdomains are also different.
1380 */
Tony Lindgren046d6b22005-11-10 14:26:52 +00001381static struct clk cam_fck = {
1382 .name = "cam_fck",
Russell Kingbc51da42008-11-04 18:59:32 +00001383 .ops = &clkops_omap2_dflt,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001384 .parent = &func_96m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001385 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001386 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1387 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1388 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001389};
1390
1391static struct clk mailboxes_ick = {
1392 .name = "mailboxes_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001393 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001394 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001395 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001396 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1397 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1398 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001399};
1400
1401static struct clk wdt4_ick = {
1402 .name = "wdt4_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001403 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001404 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001405 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001406 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1407 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1408 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001409};
1410
1411static struct clk wdt4_fck = {
1412 .name = "wdt4_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001413 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001414 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001415 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1418 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001419};
1420
1421static struct clk wdt3_ick = {
1422 .name = "wdt3_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001423 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001424 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001425 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001426 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1427 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1428 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001429};
1430
1431static struct clk wdt3_fck = {
1432 .name = "wdt3_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001433 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001434 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001435 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001436 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1437 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1438 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001439};
1440
1441static struct clk mspro_ick = {
1442 .name = "mspro_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001443 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001444 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001445 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001446 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1447 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1448 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001449};
1450
1451static struct clk mspro_fck = {
1452 .name = "mspro_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001453 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001454 .parent = &func_96m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001455 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001456 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1457 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1458 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001459};
1460
1461static struct clk mmc_ick = {
1462 .name = "mmc_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001463 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001464 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001465 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001466 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1467 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1468 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001469};
1470
1471static struct clk mmc_fck = {
1472 .name = "mmc_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001473 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001474 .parent = &func_96m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001475 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001476 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1477 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1478 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001479};
1480
1481static struct clk fac_ick = {
1482 .name = "fac_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001483 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001484 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001485 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001486 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1487 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1488 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001489};
1490
1491static struct clk fac_fck = {
1492 .name = "fac_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001493 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001494 .parent = &func_12m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001495 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1498 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001499};
1500
1501static struct clk eac_ick = {
1502 .name = "eac_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001503 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001504 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001505 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001506 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1507 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1508 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001509};
1510
1511static struct clk eac_fck = {
1512 .name = "eac_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001513 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001514 .parent = &func_96m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001515 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001516 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1517 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1518 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001519};
1520
1521static struct clk hdq_ick = {
1522 .name = "hdq_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001523 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001524 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001525 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001526 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1527 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1528 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001529};
1530
1531static struct clk hdq_fck = {
1532 .name = "hdq_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001533 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001534 .parent = &func_12m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001535 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001536 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1537 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1538 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001539};
1540
1541static struct clk i2c2_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001542 .name = "i2c2_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001543 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001544 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001545 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001546 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1547 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1548 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001549};
1550
1551static struct clk i2c2_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001552 .name = "i2c2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001553 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001554 .parent = &func_12m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001555 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001556 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1557 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1558 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001559};
1560
Tony Lindgren046d6b22005-11-10 14:26:52 +00001561static struct clk i2c1_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001562 .name = "i2c1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001563 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001564 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001565 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001566 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1567 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1568 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001569};
1570
1571static struct clk i2c1_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001572 .name = "i2c1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001573 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001574 .parent = &func_12m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001575 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1577 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1578 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001579};
1580
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001581/*
1582 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1583 * accesses derived from this data.
1584 */
Paul Walmsleye32744b2008-03-18 15:47:55 +02001585static struct clk gpmc_fck = {
1586 .name = "gpmc_fck",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001587 .ops = &clkops_omap2_iclk_idle_only,
Paul Walmsleye32744b2008-03-18 15:47:55 +02001588 .parent = &core_l3_ck,
Russell King8ad8ff62009-01-19 15:27:29 +00001589 .flags = ENABLE_ON_INIT,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001590 .clkdm_name = "core_l3_clkdm",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001591 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1592 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
Paul Walmsleye32744b2008-03-18 15:47:55 +02001593 .recalc = &followparent_recalc,
1594};
1595
1596static struct clk sdma_fck = {
1597 .name = "sdma_fck",
Russell King897dcde2008-11-04 16:35:03 +00001598 .ops = &clkops_null, /* RMK: missing? */
Paul Walmsleye32744b2008-03-18 15:47:55 +02001599 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001600 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001601 .recalc = &followparent_recalc,
1602};
1603
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001604/*
1605 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1606 * accesses derived from this data.
1607 */
Paul Walmsleye32744b2008-03-18 15:47:55 +02001608static struct clk sdma_ick = {
1609 .name = "sdma_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001610 .ops = &clkops_omap2_iclk_idle_only,
Paul Walmsleya1fed572011-02-25 15:51:02 -07001611 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001612 .clkdm_name = "core_l3_clkdm",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1614 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
Paul Walmsleye32744b2008-03-18 15:47:55 +02001615 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001616};
1617
Paul Walmsleya56d9ea2011-02-25 15:39:29 -07001618/*
1619 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1620 * accesses derived from this data.
1621 */
1622static struct clk sdrc_ick = {
1623 .name = "sdrc_ick",
1624 .ops = &clkops_omap2_iclk_idle_only,
1625 .parent = &core_l3_ck,
1626 .flags = ENABLE_ON_INIT,
1627 .clkdm_name = "core_l3_clkdm",
1628 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1629 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1630 .recalc = &followparent_recalc,
1631};
1632
Tony Lindgren046d6b22005-11-10 14:26:52 +00001633static struct clk vlynq_ick = {
1634 .name = "vlynq_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001635 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001636 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001637 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001638 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1639 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1640 .recalc = &followparent_recalc,
1641};
1642
1643static const struct clksel_rate vlynq_fck_96m_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -06001644 { .div = 1, .val = 0, .flags = RATE_IN_242X },
Paul Walmsleye32744b2008-03-18 15:47:55 +02001645 { .div = 0 }
1646};
1647
1648static const struct clksel_rate vlynq_fck_core_rates[] = {
1649 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1650 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1651 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1652 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1653 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1654 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1655 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1656 { .div = 12, .val = 12, .flags = RATE_IN_242X },
Paul Walmsleyd74b4942010-05-18 18:40:24 -06001657 { .div = 16, .val = 16, .flags = RATE_IN_242X },
Paul Walmsleye32744b2008-03-18 15:47:55 +02001658 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1659 { .div = 0 }
1660};
1661
1662static const struct clksel vlynq_fck_clksel[] = {
1663 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1664 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1665 { .parent = NULL }
Tony Lindgren046d6b22005-11-10 14:26:52 +00001666};
1667
1668static struct clk vlynq_fck = {
1669 .name = "vlynq_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001670 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001671 .parent = &func_96m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001672 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001673 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1674 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1675 .init = &omap2_init_clksel_parent,
1676 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1677 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
1678 .clksel = vlynq_fck_clksel,
1679 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001680};
1681
Tony Lindgren046d6b22005-11-10 14:26:52 +00001682static struct clk des_ick = {
1683 .name = "des_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001684 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001685 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001686 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001687 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1688 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1689 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001690};
1691
1692static struct clk sha_ick = {
1693 .name = "sha_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001694 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001695 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001696 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001697 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1698 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1699 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001700};
1701
1702static struct clk rng_ick = {
1703 .name = "rng_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001704 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001705 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001706 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001707 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1708 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1709 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001710};
1711
1712static struct clk aes_ick = {
1713 .name = "aes_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001714 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001715 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001716 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1718 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1719 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001720};
1721
1722static struct clk pka_ick = {
1723 .name = "pka_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001724 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001725 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001726 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1728 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1729 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001730};
1731
1732static struct clk usb_fck = {
1733 .name = "usb_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001734 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001735 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001736 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001737 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1738 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1739 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001740};
1741
Tony Lindgren046d6b22005-11-10 14:26:52 +00001742/*
1743 * This clock is a composite clock which does entire set changes then
1744 * forces a rebalance. It keys on the MPU speed, but it really could
1745 * be any key speed part of a set in the rate table.
1746 *
1747 * to really change a set, you need memory table sets which get changed
1748 * in sram, pre-notifiers & post notifiers, changing the top set, without
1749 * having low level display recalc's won't work... this is why dpm notifiers
1750 * work, isr's off, walk a list of clocks already _off_ and not messing with
1751 * the bus.
1752 *
1753 * This clock should have no parent. It embodies the entire upper level
1754 * active set. A parent will mess up some of the init also.
1755 */
1756static struct clk virt_prcm_set = {
1757 .name = "virt_prcm_set",
Russell King897dcde2008-11-04 16:35:03 +00001758 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001759 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
Paul Walmsleye32744b2008-03-18 15:47:55 +02001760 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
Tony Lindgren046d6b22005-11-10 14:26:52 +00001761 .set_rate = &omap2_select_table_rate,
1762 .round_rate = &omap2_round_to_table_rate,
1763};
Paul Walmsleye32744b2008-03-18 15:47:55 +02001764
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001765
1766/*
1767 * clkdev integration
1768 */
1769
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001770static struct omap_clk omap2420_clks[] = {
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001771 /* external root sources */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001772 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
1773 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
1774 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1775 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1776 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
Paul Walmsley1bccb342010-10-08 11:40:17 -06001777 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001778 /* internal analog sources */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001779 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
1780 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
1781 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001782 /* internal prcm root sources */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001783 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1784 CLK(NULL, "core_ck", &core_ck, CK_242X),
1785 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1786 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1787 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
1788 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
1789 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
1790 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001791 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1792 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
1793 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
1794 /* mpu domain clocks */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001795 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001796 /* dsp domain clocks */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001797 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001798 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001799 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
1800 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1801 /* GFX domain clocks */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001802 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
1803 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
1804 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001805 /* DSS domain clocks */
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +00001806 CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001807 CLK(NULL, "dss_ick", &dss_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001808 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
1809 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
1810 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001811 /* L3 domain clocks */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001812 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
1813 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
1814 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001815 /* L4 domain clocks */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001816 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1817 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001818 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001819 /* virtual meta-group clock */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001820 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001821 /* general l4 interface ck, multi-parent functional clk */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001822 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
1823 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
1824 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
1825 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
1826 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
1827 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
1828 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
1829 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
1830 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
1831 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
1832 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
1833 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
1834 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
1835 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
1836 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
1837 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
1838 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
1839 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
1840 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
1841 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
1842 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
1843 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
1844 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1845 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1846 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001847 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001848 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001849 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001850 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001851 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001852 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001853 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001854 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001855 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001856 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001857 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001858 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1859 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
1860 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
1861 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
1862 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
1863 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
1864 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1865 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1866 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001867 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001868 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001869 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1870 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1871 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
1872 CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001873 CLK(NULL, "cam_fck", &cam_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001874 CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001875 CLK(NULL, "cam_ick", &cam_ick, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001876 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
1877 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
1878 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001879 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
1880 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001881 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
1882 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001883 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001884 CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001885 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001886 CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001887 CLK(NULL, "fac_ick", &fac_ick, CK_242X),
1888 CLK(NULL, "fac_fck", &fac_fck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001889 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1890 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001891 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001892 CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001893 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001894 CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
Benoit Coussonf7bb0d92010-12-09 14:24:16 +00001895 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001896 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001897 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
Benoit Coussonf7bb0d92010-12-09 14:24:16 +00001898 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001899 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001900 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001901 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1902 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1903 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
Paul Walmsleya56d9ea2011-02-25 15:39:29 -07001904 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001905 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
1906 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001907 CLK(NULL, "des_ick", &des_ick, CK_242X),
Dmitry Kasatkinee5500c2010-05-03 11:10:03 +08001908 CLK("omap-sham", "ick", &sha_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001909 CLK(NULL, "sha_ick", &sha_ick, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001910 CLK("omap_rng", "ick", &rng_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001911 CLK(NULL, "rng_ick", &rng_ick, CK_242X),
Dmitry Kasatkin82a0c142010-08-20 13:44:46 +00001912 CLK("omap-aes", "ick", &aes_ick, CK_242X),
Rajendra Nayak6ea74cb2012-09-22 02:24:16 -06001913 CLK(NULL, "aes_ick", &aes_ick, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001914 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1915 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
Felipe Balbi05ac10d2010-12-02 08:49:26 +02001916 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
Jon Hunterf84c3782012-09-22 02:24:14 -06001917 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
1918 CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
1919 CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
Paul Walmsleyc810fde2012-09-22 02:24:14 -06001920 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001921};
1922
1923/*
1924 * init code
1925 */
1926
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001927int __init omap2420_clk_init(void)
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001928{
1929 const struct prcm_config *prcm;
1930 struct omap_clk *c;
1931 u32 clkrate;
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001932
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001933 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1934 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
1935 cpu_mask = RATE_IN_242X;
1936 rate_table = omap2420_rate_table;
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001937
1938 clk_init(&omap2_clk_functions);
1939
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001940 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1941 c++)
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001942 clk_preinit(c->lk.clk);
1943
1944 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1945 propagate_rate(&osc_ck);
Paul Walmsley44da0a52010-01-26 20:13:08 -07001946 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001947 propagate_rate(&sys_ck);
1948
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001949 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1950 c++) {
1951 clkdev_add(&c->lk);
1952 clk_register(c->lk.clk);
1953 omap2_init_clk_clkdm(c->lk.clk);
1954 }
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001955
Paul Walmsleyc6461f52011-02-25 15:49:53 -07001956 /* Disable autoidle on all clocks; let the PM code enable it later */
1957 omap_clk_disable_autoidle_all();
1958
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001959 /* Check the MPU rate set by bootloader */
1960 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
1961 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1962 if (!(prcm->flags & cpu_mask))
1963 continue;
1964 if (prcm->xtal_speed != sys_ck.rate)
1965 continue;
1966 if (prcm->dpll_speed <= clkrate)
1967 break;
1968 }
1969 curr_prcm_set = prcm;
1970
1971 recalculate_root_clocks();
1972
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001973 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1974 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1975 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001976
1977 /*
1978 * Only enable those clocks we will need, let the drivers
1979 * enable other clocks as necessary
1980 */
1981 clk_enable_init_clocks();
1982
1983 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1984 vclk = clk_get(NULL, "virt_prcm_set");
1985 sclk = clk_get(NULL, "sys_ck");
1986 dclk = clk_get(NULL, "dpll_ck");
1987
1988 return 0;
1989}
Paul Walmsley6b8858a2008-03-18 10:35:15 +02001990