Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 2 | * arch/arm/mach-omap2/control.h |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 3 | * |
Santosh Shilimkar | 4416907 | 2009-05-28 14:16:04 -0700 | [diff] [blame] | 4 | * OMAP2/3/4 System Control Module definitions |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 5 | * |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 6 | * Copyright (C) 2007-2010 Texas Instruments, Inc. |
| 7 | * Copyright (C) 2007-2008, 2010 Nokia Corporation |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 8 | * |
| 9 | * Written by Paul Walmsley |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation. |
| 14 | */ |
| 15 | |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H |
| 17 | #define __ARCH_ARM_MACH_OMAP2_CONTROL_H |
Tony Lindgren | 646e3ed | 2008-10-06 15:49:36 +0300 | [diff] [blame] | 18 | |
Tony Lindgren | 91e80ae | 2012-09-20 11:40:59 -0700 | [diff] [blame] | 19 | #include "ctrl_module_core_44xx.h" |
Tony Lindgren | 829ce59 | 2012-09-20 11:41:06 -0700 | [diff] [blame] | 20 | #include "ctrl_module_wkup_44xx.h" |
Tony Lindgren | e2e02be | 2012-09-20 11:41:01 -0700 | [diff] [blame] | 21 | #include "ctrl_module_pad_core_44xx.h" |
Tony Lindgren | 98ce572 | 2012-09-20 11:41:04 -0700 | [diff] [blame] | 22 | #include "ctrl_module_pad_wkup_44xx.h" |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 23 | |
Tony Lindgren | c49f34b | 2012-08-31 16:08:07 -0700 | [diff] [blame] | 24 | #include "am33xx.h" |
Vaibhav Hiremath | 2e113c6 | 2012-06-18 00:47:25 -0600 | [diff] [blame] | 25 | |
Tony Lindgren | 646e3ed | 2008-10-06 15:49:36 +0300 | [diff] [blame] | 26 | #ifndef __ASSEMBLY__ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | #define OMAP242X_CTRL_REGADDR(reg) \ |
Santosh Shilimkar | 233fd64 | 2009-10-19 15:25:31 -0700 | [diff] [blame] | 28 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 29 | #define OMAP243X_CTRL_REGADDR(reg) \ |
Santosh Shilimkar | 233fd64 | 2009-10-19 15:25:31 -0700 | [diff] [blame] | 30 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 31 | #define OMAP343X_CTRL_REGADDR(reg) \ |
Santosh Shilimkar | 233fd64 | 2009-10-19 15:25:31 -0700 | [diff] [blame] | 32 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
Vaibhav Hiremath | 2e113c6 | 2012-06-18 00:47:25 -0600 | [diff] [blame] | 33 | #define AM33XX_CTRL_REGADDR(reg) \ |
| 34 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) |
Tony Lindgren | 646e3ed | 2008-10-06 15:49:36 +0300 | [diff] [blame] | 35 | #else |
Santosh Shilimkar | 233fd64 | 2009-10-19 15:25:31 -0700 | [diff] [blame] | 36 | #define OMAP242X_CTRL_REGADDR(reg) \ |
| 37 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
| 38 | #define OMAP243X_CTRL_REGADDR(reg) \ |
| 39 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
| 40 | #define OMAP343X_CTRL_REGADDR(reg) \ |
| 41 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
Vaibhav Hiremath | 2e113c6 | 2012-06-18 00:47:25 -0600 | [diff] [blame] | 42 | #define AM33XX_CTRL_REGADDR(reg) \ |
| 43 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) |
Tony Lindgren | 646e3ed | 2008-10-06 15:49:36 +0300 | [diff] [blame] | 44 | #endif /* __ASSEMBLY__ */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 45 | |
| 46 | /* |
| 47 | * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for |
| 48 | * OMAP24XX and OMAP34XX. |
| 49 | */ |
| 50 | |
| 51 | /* Control submodule offsets */ |
| 52 | |
| 53 | #define OMAP2_CONTROL_INTERFACE 0x000 |
| 54 | #define OMAP2_CONTROL_PADCONFS 0x030 |
| 55 | #define OMAP2_CONTROL_GENERAL 0x270 |
| 56 | #define OMAP343X_CONTROL_MEM_WKUP 0x600 |
| 57 | #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 |
| 58 | #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 |
| 59 | |
Hemant Pedanekar | a920360 | 2011-12-13 10:46:44 -0800 | [diff] [blame] | 60 | /* TI81XX spefic control submodules */ |
| 61 | #define TI81XX_CONTROL_DEVCONF 0x600 |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 62 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 63 | /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ |
| 64 | |
| 65 | #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) |
| 66 | |
| 67 | /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ |
| 68 | #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) |
| 69 | #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) |
| 70 | #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) |
| 71 | #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) |
| 72 | #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) |
| 73 | #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) |
| 74 | #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) |
| 75 | #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) |
| 76 | #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) |
| 77 | #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) |
| 78 | #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) |
| 79 | #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) |
| 80 | |
| 81 | /* 242x-only CONTROL_GENERAL register offsets */ |
| 82 | #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ |
| 83 | #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) |
| 84 | |
| 85 | /* 243x-only CONTROL_GENERAL register offsets */ |
| 86 | /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ |
| 87 | #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) |
| 88 | #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) |
| 89 | #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) |
| 90 | #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) |
| 91 | #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) |
Tony Lindgren | 90c62bf | 2008-12-10 17:37:17 -0800 | [diff] [blame] | 92 | #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 93 | |
| 94 | /* 24xx-only CONTROL_GENERAL register offsets */ |
| 95 | #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) |
| 96 | #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) |
| 97 | #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) |
| 98 | #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) |
| 99 | #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) |
| 100 | #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) |
| 101 | #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) |
| 102 | #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) |
| 103 | #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) |
| 104 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) |
| 105 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) |
| 106 | #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) |
| 107 | #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) |
| 108 | #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) |
| 109 | #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) |
| 110 | #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) |
| 111 | #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) |
| 112 | #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) |
| 113 | #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) |
| 114 | #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) |
| 115 | #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) |
| 116 | #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) |
| 117 | #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) |
| 118 | #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) |
| 119 | #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) |
| 120 | #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) |
| 121 | #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) |
| 122 | #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) |
| 123 | #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) |
| 124 | #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) |
| 125 | #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) |
| 126 | |
Rajendra Nayak | c171a25 | 2008-09-26 17:48:31 +0530 | [diff] [blame] | 127 | #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) |
| 128 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 129 | /* 34xx-only CONTROL_GENERAL register offsets */ |
| 130 | #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) |
| 131 | #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) |
| 132 | #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) |
| 133 | #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) |
| 134 | #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) |
| 135 | #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) |
| 136 | #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) |
| 137 | #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) |
| 138 | #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) |
| 139 | #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) |
| 140 | #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) |
| 141 | #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) |
| 142 | #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) |
| 143 | #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) |
| 144 | #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) |
| 145 | #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) |
| 146 | #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) |
| 147 | #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) |
| 148 | #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) |
| 149 | #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) |
| 150 | #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) |
| 151 | #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) |
| 152 | #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) |
| 153 | #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) |
| 154 | #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) |
| 155 | #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) |
| 156 | #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) |
| 157 | #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) |
| 158 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) |
Thara Gopinath | 2f34ce8 | 2010-05-29 22:02:21 +0530 | [diff] [blame] | 159 | #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) |
| 160 | #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) |
| 161 | #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) |
| 162 | #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) |
| 163 | #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) |
| 164 | #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) |
| 165 | #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) |
| 166 | #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) |
| 167 | #define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 168 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) |
| 169 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) |
Rajendra Nayak | c96631e | 2008-09-26 17:49:02 +0530 | [diff] [blame] | 170 | #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ |
Roel Kluin | 83969bf | 2010-01-08 10:29:07 -0800 | [diff] [blame] | 171 | + ((i) >> 1) * 4 + (!((i) & 1)) * 2) |
Rajendra Nayak | c96631e | 2008-09-26 17:49:02 +0530 | [diff] [blame] | 172 | #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) |
| 173 | #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) |
| 174 | #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) |
| 175 | #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) |
| 176 | #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) |
| 177 | #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) |
| 178 | #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) |
| 179 | #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) |
| 180 | #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) |
| 181 | #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) |
| 182 | #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) |
| 183 | |
Thara Gopinath | 2f34ce8 | 2010-05-29 22:02:21 +0530 | [diff] [blame] | 184 | /* OMAP3630 only CONTROL_GENERAL register offsets */ |
| 185 | #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) |
| 186 | #define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) |
| 187 | #define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) |
| 188 | #define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) |
| 189 | #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) |
| 190 | #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) |
Sakari Ailus | f0d3d82 | 2012-07-04 04:54:13 -0600 | [diff] [blame] | 191 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL (OMAP2_CONTROL_GENERAL + 0x02f0) |
Thara Gopinath | 2f34ce8 | 2010-05-29 22:02:21 +0530 | [diff] [blame] | 192 | |
Thara Gopinath | bd38107 | 2010-12-10 23:15:23 +0530 | [diff] [blame] | 193 | /* OMAP44xx control efuse offsets */ |
| 194 | #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C |
| 195 | #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F |
| 196 | #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232 |
| 197 | #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235 |
| 198 | #define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240 |
| 199 | #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243 |
| 200 | #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246 |
| 201 | #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 |
| 202 | #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 |
| 203 | #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 |
| 204 | |
Ranjith Lohithakshan | 05842a3 | 2010-01-26 20:12:56 -0700 | [diff] [blame] | 205 | /* AM35XX only CONTROL_GENERAL register offsets */ |
| 206 | #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) |
| 207 | #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) |
| 208 | #define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) |
| 209 | #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) |
| 210 | #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) |
| 211 | #define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) |
| 212 | #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) |
Rajendra Nayak | c96631e | 2008-09-26 17:49:02 +0530 | [diff] [blame] | 213 | |
| 214 | /* 34xx PADCONF register offsets */ |
| 215 | #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ |
| 216 | (i)*2) |
| 217 | #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) |
| 218 | #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) |
| 219 | #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) |
| 220 | #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) |
| 221 | #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) |
| 222 | #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) |
| 223 | #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) |
| 224 | #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) |
| 225 | #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) |
| 226 | #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) |
| 227 | #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) |
| 228 | #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) |
| 229 | #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) |
| 230 | #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) |
| 231 | #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) |
| 232 | #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) |
| 233 | #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) |
| 234 | #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) |
| 235 | |
| 236 | /* 34xx GENERAL_WKUP regist offsets */ |
| 237 | #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ |
| 238 | 0x008 + (i)) |
| 239 | #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) |
| 240 | #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) |
| 241 | #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) |
| 242 | #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) |
| 243 | #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 244 | |
Justin P. Mattock | 70f23fd | 2011-05-10 10:16:21 +0200 | [diff] [blame] | 245 | /* 36xx-only RTA - Retention till Access control registers and bits */ |
Nishanth Menon | 458e999 | 2010-12-20 14:05:06 -0600 | [diff] [blame] | 246 | #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C |
| 247 | #define OMAP36XX_RTA_DISABLE 0x0 |
| 248 | |
Kevin Hilman | 8111b22 | 2009-04-28 15:27:44 -0700 | [diff] [blame] | 249 | /* 34xx D2D idle-related pins, handled by PM core */ |
| 250 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 |
| 251 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 |
| 252 | |
Hemant Pedanekar | a920360 | 2011-12-13 10:46:44 -0800 | [diff] [blame] | 253 | /* TI81XX CONTROL_DEVCONF register offsets */ |
| 254 | #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 255 | |
R Sricharan | b13e80a | 2012-04-19 17:42:19 +0530 | [diff] [blame] | 256 | /* OMAP54XX CONTROL STATUS register */ |
| 257 | #define OMAP5XXX_CONTROL_STATUS 0x134 |
| 258 | #define OMAP5_DEVICETYPE_MASK (0x7 << 6) |
| 259 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 260 | /* |
| 261 | * REVISIT: This list of registers is not comprehensive - there are more |
| 262 | * that should be added. |
| 263 | */ |
| 264 | |
| 265 | /* |
| 266 | * Control module register bit defines - these should eventually go into |
| 267 | * their own regbits file. Some of these will be complicated, depending |
| 268 | * on the device type (general-purpose, emulator, test, secure, bad, other) |
| 269 | * and the security mode (secure, non-secure, don't care) |
| 270 | */ |
| 271 | /* CONTROL_DEVCONF0 bits */ |
Tony Lindgren | 90c62bf | 2008-12-10 17:37:17 -0800 | [diff] [blame] | 272 | #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 273 | #define OMAP24XX_USBSTANDBYCTRL (1 << 15) |
| 274 | #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) |
Paul Walmsley | cf4c87a | 2010-10-08 11:40:19 -0600 | [diff] [blame] | 275 | #define OMAP2_MCBSP1_FSR_MASK (1 << 4) |
| 276 | #define OMAP2_MCBSP1_CLKR_MASK (1 << 3) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 277 | #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) |
| 278 | |
| 279 | /* CONTROL_DEVCONF1 bits */ |
Tony Lindgren | 90c62bf | 2008-12-10 17:37:17 -0800 | [diff] [blame] | 280 | #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) |
| 281 | #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 282 | #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ |
| 283 | #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ |
| 284 | #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ |
| 285 | |
| 286 | /* CONTROL_STATUS bits */ |
| 287 | #define OMAP2_DEVICETYPE_MASK (0x7 << 8) |
| 288 | #define OMAP2_SYSBOOT_5_MASK (1 << 5) |
| 289 | #define OMAP2_SYSBOOT_4_MASK (1 << 4) |
| 290 | #define OMAP2_SYSBOOT_3_MASK (1 << 3) |
| 291 | #define OMAP2_SYSBOOT_2_MASK (1 << 2) |
| 292 | #define OMAP2_SYSBOOT_1_MASK (1 << 1) |
| 293 | #define OMAP2_SYSBOOT_0_MASK (1 << 0) |
| 294 | |
Tony Lindgren | 90c62bf | 2008-12-10 17:37:17 -0800 | [diff] [blame] | 295 | /* CONTROL_PBIAS_LITE bits */ |
| 296 | #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) |
| 297 | #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) |
| 298 | #define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) |
| 299 | #define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) |
| 300 | #define OMAP343X_PBIASLITEVMODE1 (1 << 8) |
| 301 | #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) |
| 302 | #define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) |
| 303 | #define OMAP2_PBIASSPEEDCTRL0 (1 << 2) |
| 304 | #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) |
| 305 | #define OMAP2_PBIASLITEVMODE0 (1 << 0) |
| 306 | |
Madhu | 555d503 | 2009-11-22 10:11:08 -0800 | [diff] [blame] | 307 | /* CONTROL_PROG_IO1 bits */ |
| 308 | #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) |
| 309 | |
Kevin Hilman | 1155e42 | 2008-11-25 11:48:24 -0800 | [diff] [blame] | 310 | /* CONTROL_IVA2_BOOTMOD bits */ |
| 311 | #define OMAP3_IVA2_BOOTMOD_SHIFT 0 |
| 312 | #define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) |
| 313 | #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) |
| 314 | |
Kevin Hilman | 5a1a5ab | 2008-10-31 11:08:42 -0700 | [diff] [blame] | 315 | /* CONTROL_PADCONF_X bits */ |
| 316 | #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) |
| 317 | #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) |
| 318 | |
Rajendra Nayak | 8014078 | 2008-09-26 17:48:46 +0530 | [diff] [blame] | 319 | #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) |
| 320 | #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) |
| 321 | #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C |
Jean Pihet | fe360e1 | 2010-12-18 16:44:43 +0100 | [diff] [blame] | 322 | #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ |
| 323 | OMAP343X_SCRATCHPAD + reg) |
Rajendra Nayak | 8014078 | 2008-09-26 17:48:46 +0530 | [diff] [blame] | 324 | |
Ranjith Lohithakshan | 05842a3 | 2010-01-26 20:12:56 -0700 | [diff] [blame] | 325 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ |
Vaibhav Hiremath | 2e113c6 | 2012-06-18 00:47:25 -0600 | [diff] [blame] | 326 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 |
| 327 | #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 |
| 328 | #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 |
| 329 | #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 |
| 330 | #define AM35XX_USBOTG_FCLK_SHIFT 8 |
| 331 | #define AM35XX_CPGMAC_FCLK_SHIFT 9 |
| 332 | #define AM35XX_VPFE_FCLK_SHIFT 10 |
Ranjith Lohithakshan | 05842a3 | 2010-01-26 20:12:56 -0700 | [diff] [blame] | 333 | |
Vaibhav Hiremath | 2e113c6 | 2012-06-18 00:47:25 -0600 | [diff] [blame] | 334 | /* AM35XX CONTROL_LVL_INTR_CLEAR bits */ |
Vaibhav Hiremath | 07dcbd0 | 2010-02-15 10:03:35 -0800 | [diff] [blame] | 335 | #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) |
| 336 | #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) |
| 337 | #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) |
| 338 | #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) |
| 339 | #define AM35XX_USBOTGSS_INT_CLR BIT(4) |
| 340 | #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) |
| 341 | #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) |
| 342 | #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) |
| 343 | |
Vaibhav Hiremath | 2e113c6 | 2012-06-18 00:47:25 -0600 | [diff] [blame] | 344 | /* AM35XX CONTROL_IP_SW_RESET bits */ |
Vaibhav Hiremath | 07dcbd0 | 2010-02-15 10:03:35 -0800 | [diff] [blame] | 345 | #define AM35XX_USBOTGSS_SW_RST BIT(0) |
| 346 | #define AM35XX_CPGMACSS_SW_RST BIT(1) |
| 347 | #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) |
| 348 | #define AM35XX_HECC_SW_RST BIT(3) |
| 349 | #define AM35XX_VPFE_PCLK_SW_RST BIT(4) |
| 350 | |
Vaibhav Hiremath | 2e113c6 | 2012-06-18 00:47:25 -0600 | [diff] [blame] | 351 | /* AM33XX CONTROL_STATUS register */ |
Afzal Mohammed | fb3cfb1 | 2012-03-05 16:11:01 -0800 | [diff] [blame] | 352 | #define AM33XX_CONTROL_STATUS 0x040 |
Vaibhav Hiremath | 2e113c6 | 2012-06-18 00:47:25 -0600 | [diff] [blame] | 353 | #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc |
Afzal Mohammed | fb3cfb1 | 2012-03-05 16:11:01 -0800 | [diff] [blame] | 354 | |
Vaibhav Hiremath | 2e113c6 | 2012-06-18 00:47:25 -0600 | [diff] [blame] | 355 | /* AM33XX CONTROL_STATUS bitfields (partial) */ |
| 356 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 |
Vaibhav Hiremath | a86c0b9 | 2012-09-19 18:05:15 -0600 | [diff] [blame] | 357 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 |
Vaibhav Hiremath | 2e113c6 | 2012-06-18 00:47:25 -0600 | [diff] [blame] | 358 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) |
| 359 | |
| 360 | /* CONTROL OMAP STATUS register to identify OMAP3 features */ |
Sanjeev Premi | 8384ce0 | 2009-11-22 10:10:53 -0800 | [diff] [blame] | 361 | #define OMAP3_CONTROL_OMAP_STATUS 0x044c |
| 362 | |
| 363 | #define OMAP3_SGX_SHIFT 13 |
| 364 | #define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) |
| 365 | #define FEAT_SGX_FULL 0 |
| 366 | #define FEAT_SGX_HALF 1 |
| 367 | #define FEAT_SGX_NONE 2 |
| 368 | |
| 369 | #define OMAP3_IVA_SHIFT 12 |
Arno Steffen | 4e012e5 | 2010-12-22 18:14:36 +0000 | [diff] [blame] | 370 | #define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT) |
Sanjeev Premi | 8384ce0 | 2009-11-22 10:10:53 -0800 | [diff] [blame] | 371 | #define FEAT_IVA 0 |
| 372 | #define FEAT_IVA_NONE 1 |
| 373 | |
| 374 | #define OMAP3_L2CACHE_SHIFT 10 |
| 375 | #define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) |
| 376 | #define FEAT_L2CACHE_NONE 0 |
| 377 | #define FEAT_L2CACHE_64KB 1 |
| 378 | #define FEAT_L2CACHE_128KB 2 |
| 379 | #define FEAT_L2CACHE_256KB 3 |
| 380 | |
| 381 | #define OMAP3_ISP_SHIFT 5 |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 382 | #define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) |
Sanjeev Premi | 8384ce0 | 2009-11-22 10:10:53 -0800 | [diff] [blame] | 383 | #define FEAT_ISP 0 |
| 384 | #define FEAT_ISP_NONE 1 |
| 385 | |
| 386 | #define OMAP3_NEON_SHIFT 4 |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 387 | #define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) |
Sanjeev Premi | 8384ce0 | 2009-11-22 10:10:53 -0800 | [diff] [blame] | 388 | #define FEAT_NEON 0 |
| 389 | #define FEAT_NEON_NONE 1 |
| 390 | |
| 391 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 392 | #ifndef __ASSEMBLY__ |
Tony Lindgren | 140455f | 2010-02-12 12:26:48 -0800 | [diff] [blame] | 393 | #ifdef CONFIG_ARCH_OMAP2PLUS |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 394 | extern void __iomem *omap_ctrl_base_get(void); |
| 395 | extern u8 omap_ctrl_readb(u16 offset); |
| 396 | extern u16 omap_ctrl_readw(u16 offset); |
| 397 | extern u32 omap_ctrl_readl(u16 offset); |
Santosh Shilimkar | 70ba71a | 2010-09-27 14:02:57 -0600 | [diff] [blame] | 398 | extern u32 omap4_ctrl_pad_readl(u16 offset); |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 399 | extern void omap_ctrl_writeb(u8 val, u16 offset); |
| 400 | extern void omap_ctrl_writew(u16 val, u16 offset); |
| 401 | extern void omap_ctrl_writel(u32 val, u16 offset); |
Santosh Shilimkar | 70ba71a | 2010-09-27 14:02:57 -0600 | [diff] [blame] | 402 | extern void omap4_ctrl_pad_writel(u32 val, u16 offset); |
Rajendra Nayak | 8014078 | 2008-09-26 17:48:46 +0530 | [diff] [blame] | 403 | |
| 404 | extern void omap3_save_scratchpad_contents(void); |
| 405 | extern void omap3_clear_scratchpad_contents(void); |
Kevin Hilman | 14c79bb | 2011-06-23 17:16:14 -0700 | [diff] [blame] | 406 | extern void omap3_restore(void); |
| 407 | extern void omap3_restore_es3(void); |
| 408 | extern void omap3_restore_3630(void); |
Rajendra Nayak | 8014078 | 2008-09-26 17:48:46 +0530 | [diff] [blame] | 409 | extern u32 omap3_arm_context[128]; |
Rajendra Nayak | c96631e | 2008-09-26 17:49:02 +0530 | [diff] [blame] | 410 | extern void omap3_control_save_context(void); |
| 411 | extern void omap3_control_restore_context(void); |
Paul Walmsley | 166353b | 2010-12-21 20:01:21 -0700 | [diff] [blame] | 412 | extern void omap3_ctrl_write_boot_mode(u8 bootmode); |
Omar Ramirez Luna | 90f1380 | 2012-06-18 16:18:09 -0600 | [diff] [blame] | 413 | extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); |
| 414 | extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); |
Nishanth Menon | 458e999 | 2010-12-20 14:05:06 -0600 | [diff] [blame] | 415 | extern void omap3630_ctrl_disable_rta(void); |
Paul Walmsley | 596efe4 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 416 | extern int omap3_ctrl_save_padconf(void); |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 417 | #else |
| 418 | #define omap_ctrl_base_get() 0 |
| 419 | #define omap_ctrl_readb(x) 0 |
| 420 | #define omap_ctrl_readw(x) 0 |
| 421 | #define omap_ctrl_readl(x) 0 |
Santosh Shilimkar | 70ba71a | 2010-09-27 14:02:57 -0600 | [diff] [blame] | 422 | #define omap4_ctrl_pad_readl(x) 0 |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 423 | #define omap_ctrl_writeb(x, y) WARN_ON(1) |
| 424 | #define omap_ctrl_writew(x, y) WARN_ON(1) |
| 425 | #define omap_ctrl_writel(x, y) WARN_ON(1) |
Santosh Shilimkar | 70ba71a | 2010-09-27 14:02:57 -0600 | [diff] [blame] | 426 | #define omap4_ctrl_pad_writel(x, y) WARN_ON(1) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 427 | #endif |
| 428 | #endif /* __ASSEMBLY__ */ |
| 429 | |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 430 | #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 431 | |