Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 30 | #include <linux/export.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
| 32 | #include <drm/drm_crtc.h> |
| 33 | #include <drm/drm_crtc_helper.h> |
| 34 | #include <drm/drm_edid.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 35 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 36 | #include <drm/i915_drm.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 37 | #include "i915_drv.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 38 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 40 | |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 41 | struct dp_link_dpll { |
| 42 | int link_bw; |
| 43 | struct dpll dpll; |
| 44 | }; |
| 45 | |
| 46 | static const struct dp_link_dpll gen4_dpll[] = { |
| 47 | { DP_LINK_BW_1_62, |
| 48 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
| 49 | { DP_LINK_BW_2_7, |
| 50 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
| 51 | }; |
| 52 | |
| 53 | static const struct dp_link_dpll pch_dpll[] = { |
| 54 | { DP_LINK_BW_1_62, |
| 55 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
| 56 | { DP_LINK_BW_2_7, |
| 57 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
| 58 | }; |
| 59 | |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 60 | static const struct dp_link_dpll vlv_dpll[] = { |
| 61 | { DP_LINK_BW_1_62, |
Chon Ming Lee | 58f6e63 | 2013-09-25 15:47:51 +0800 | [diff] [blame] | 62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 63 | { DP_LINK_BW_2_7, |
| 64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| 65 | }; |
| 66 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 67 | /** |
| 68 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 69 | * @intel_dp: DP struct |
| 70 | * |
| 71 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 72 | * will return true, and false otherwise. |
| 73 | */ |
| 74 | static bool is_edp(struct intel_dp *intel_dp) |
| 75 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 76 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 77 | |
| 78 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 79 | } |
| 80 | |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 81 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 82 | { |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 83 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 84 | |
| 85 | return intel_dig_port->base.base.dev; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 86 | } |
| 87 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 88 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 89 | { |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 90 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 91 | } |
| 92 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 93 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 94 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 95 | |
| 96 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 97 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 98 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 99 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 100 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 101 | |
| 102 | switch (max_link_bw) { |
| 103 | case DP_LINK_BW_1_62: |
| 104 | case DP_LINK_BW_2_7: |
| 105 | break; |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 106 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 107 | if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && |
| 108 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) |
| 109 | max_link_bw = DP_LINK_BW_5_4; |
| 110 | else |
| 111 | max_link_bw = DP_LINK_BW_2_7; |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 112 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 113 | default: |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 114 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
| 115 | max_link_bw); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 116 | max_link_bw = DP_LINK_BW_1_62; |
| 117 | break; |
| 118 | } |
| 119 | return max_link_bw; |
| 120 | } |
| 121 | |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 122 | /* |
| 123 | * The units on the numbers in the next two are... bizarre. Examples will |
| 124 | * make it clearer; this one parallels an example in the eDP spec. |
| 125 | * |
| 126 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
| 127 | * |
| 128 | * 270000 * 1 * 8 / 10 == 216000 |
| 129 | * |
| 130 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
| 131 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
| 132 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
| 133 | * 119000. At 18bpp that's 2142000 kilobits per second. |
| 134 | * |
| 135 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
| 136 | * get the result in decakilobits instead of kilobits. |
| 137 | */ |
| 138 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 139 | static int |
Keith Packard | c898261 | 2012-01-25 08:16:25 -0800 | [diff] [blame] | 140 | intel_dp_link_required(int pixel_clock, int bpp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 141 | { |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 142 | return (pixel_clock * bpp + 9) / 10; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | static int |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 146 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 147 | { |
| 148 | return (max_link_clock * max_lanes * 8) / 10; |
| 149 | } |
| 150 | |
Damien Lespiau | c19de8e | 2013-11-28 15:29:18 +0000 | [diff] [blame] | 151 | static enum drm_mode_status |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 152 | intel_dp_mode_valid(struct drm_connector *connector, |
| 153 | struct drm_display_mode *mode) |
| 154 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 155 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 156 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 157 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 158 | int target_clock = mode->clock; |
| 159 | int max_rate, mode_rate, max_lanes, max_link_clock; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 160 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 161 | if (is_edp(intel_dp) && fixed_mode) { |
| 162 | if (mode->hdisplay > fixed_mode->hdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 163 | return MODE_PANEL; |
| 164 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 165 | if (mode->vdisplay > fixed_mode->vdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 166 | return MODE_PANEL; |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 167 | |
| 168 | target_clock = fixed_mode->clock; |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 169 | } |
| 170 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 171 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
| 172 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
| 173 | |
| 174 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 175 | mode_rate = intel_dp_link_required(target_clock, 18); |
| 176 | |
| 177 | if (mode_rate > max_rate) |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 178 | return MODE_CLOCK_HIGH; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 179 | |
| 180 | if (mode->clock < 10000) |
| 181 | return MODE_CLOCK_LOW; |
| 182 | |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 183 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 184 | return MODE_H_ILLEGAL; |
| 185 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 186 | return MODE_OK; |
| 187 | } |
| 188 | |
| 189 | static uint32_t |
| 190 | pack_aux(uint8_t *src, int src_bytes) |
| 191 | { |
| 192 | int i; |
| 193 | uint32_t v = 0; |
| 194 | |
| 195 | if (src_bytes > 4) |
| 196 | src_bytes = 4; |
| 197 | for (i = 0; i < src_bytes; i++) |
| 198 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 199 | return v; |
| 200 | } |
| 201 | |
| 202 | static void |
| 203 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
| 204 | { |
| 205 | int i; |
| 206 | if (dst_bytes > 4) |
| 207 | dst_bytes = 4; |
| 208 | for (i = 0; i < dst_bytes; i++) |
| 209 | dst[i] = src >> ((3-i) * 8); |
| 210 | } |
| 211 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 212 | /* hrawclock is 1/4 the FSB frequency */ |
| 213 | static int |
| 214 | intel_hrawclk(struct drm_device *dev) |
| 215 | { |
| 216 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 217 | uint32_t clkcfg; |
| 218 | |
Vijay Purushothaman | 9473c8f | 2012-09-27 19:13:01 +0530 | [diff] [blame] | 219 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
| 220 | if (IS_VALLEYVIEW(dev)) |
| 221 | return 200; |
| 222 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 223 | clkcfg = I915_READ(CLKCFG); |
| 224 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 225 | case CLKCFG_FSB_400: |
| 226 | return 100; |
| 227 | case CLKCFG_FSB_533: |
| 228 | return 133; |
| 229 | case CLKCFG_FSB_667: |
| 230 | return 166; |
| 231 | case CLKCFG_FSB_800: |
| 232 | return 200; |
| 233 | case CLKCFG_FSB_1067: |
| 234 | return 266; |
| 235 | case CLKCFG_FSB_1333: |
| 236 | return 333; |
| 237 | /* these two are just a guess; one of them might be right */ |
| 238 | case CLKCFG_FSB_1600: |
| 239 | case CLKCFG_FSB_1600_ALT: |
| 240 | return 400; |
| 241 | default: |
| 242 | return 133; |
| 243 | } |
| 244 | } |
| 245 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 246 | static void |
| 247 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
| 248 | struct intel_dp *intel_dp, |
| 249 | struct edp_power_seq *out); |
| 250 | static void |
| 251 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
| 252 | struct intel_dp *intel_dp, |
| 253 | struct edp_power_seq *out); |
| 254 | |
| 255 | static enum pipe |
| 256 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
| 257 | { |
| 258 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 259 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 260 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 261 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 262 | enum port port = intel_dig_port->port; |
| 263 | enum pipe pipe; |
| 264 | |
| 265 | /* modeset should have pipe */ |
| 266 | if (crtc) |
| 267 | return to_intel_crtc(crtc)->pipe; |
| 268 | |
| 269 | /* init time, try to find a pipe with this port selected */ |
| 270 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
| 271 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
| 272 | PANEL_PORT_SELECT_MASK; |
| 273 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) |
| 274 | return pipe; |
| 275 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) |
| 276 | return pipe; |
| 277 | } |
| 278 | |
| 279 | /* shrug */ |
| 280 | return PIPE_A; |
| 281 | } |
| 282 | |
| 283 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) |
| 284 | { |
| 285 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 286 | |
| 287 | if (HAS_PCH_SPLIT(dev)) |
| 288 | return PCH_PP_CONTROL; |
| 289 | else |
| 290 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
| 291 | } |
| 292 | |
| 293 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) |
| 294 | { |
| 295 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 296 | |
| 297 | if (HAS_PCH_SPLIT(dev)) |
| 298 | return PCH_PP_STATUS; |
| 299 | else |
| 300 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
| 301 | } |
| 302 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 303 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 304 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 305 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 306 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 307 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 308 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 309 | } |
| 310 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 311 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 312 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 313 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 314 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 315 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 316 | return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 317 | } |
| 318 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 319 | static void |
| 320 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 321 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 322 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 323 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 324 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 325 | if (!is_edp(intel_dp)) |
| 326 | return; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 327 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 328 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 329 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 330 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 331 | I915_READ(_pp_stat_reg(intel_dp)), |
| 332 | I915_READ(_pp_ctrl_reg(intel_dp))); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 333 | } |
| 334 | } |
| 335 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 336 | static uint32_t |
| 337 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
| 338 | { |
| 339 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 340 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 341 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 342 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 343 | uint32_t status; |
| 344 | bool done; |
| 345 | |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 346 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 347 | if (has_aux_irq) |
Paulo Zanoni | b18ac46 | 2013-02-18 19:00:24 -0300 | [diff] [blame] | 348 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
Imre Deak | 3598706 | 2013-05-21 20:03:20 +0300 | [diff] [blame] | 349 | msecs_to_jiffies_timeout(10)); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 350 | else |
| 351 | done = wait_for_atomic(C, 10) == 0; |
| 352 | if (!done) |
| 353 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
| 354 | has_aux_irq); |
| 355 | #undef C |
| 356 | |
| 357 | return status; |
| 358 | } |
| 359 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 360 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 361 | { |
| 362 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 363 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 364 | |
| 365 | /* |
| 366 | * The clock divider is based off the hrawclk, and would like to run at |
| 367 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
| 368 | */ |
| 369 | return index ? 0 : intel_hrawclk(dev) / 2; |
| 370 | } |
| 371 | |
| 372 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 373 | { |
| 374 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 375 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 376 | |
| 377 | if (index) |
| 378 | return 0; |
| 379 | |
| 380 | if (intel_dig_port->port == PORT_A) { |
| 381 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 382 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
| 383 | else |
| 384 | return 225; /* eDP input clock at 450Mhz */ |
| 385 | } else { |
| 386 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
| 387 | } |
| 388 | } |
| 389 | |
| 390 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 391 | { |
| 392 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 393 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 394 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 395 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 396 | if (intel_dig_port->port == PORT_A) { |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 397 | if (index) |
| 398 | return 0; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 399 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 400 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
| 401 | /* Workaround for non-ULT HSW */ |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 402 | switch (index) { |
| 403 | case 0: return 63; |
| 404 | case 1: return 72; |
| 405 | default: return 0; |
| 406 | } |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 407 | } else { |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 408 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 409 | } |
| 410 | } |
| 411 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 412 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 413 | { |
| 414 | return index ? 0 : 100; |
| 415 | } |
| 416 | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 417 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 418 | bool has_aux_irq, |
| 419 | int send_bytes, |
| 420 | uint32_t aux_clock_divider) |
| 421 | { |
| 422 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 423 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 424 | uint32_t precharge, timeout; |
| 425 | |
| 426 | if (IS_GEN6(dev)) |
| 427 | precharge = 3; |
| 428 | else |
| 429 | precharge = 5; |
| 430 | |
| 431 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) |
| 432 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
| 433 | else |
| 434 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
| 435 | |
| 436 | return DP_AUX_CH_CTL_SEND_BUSY | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 437 | DP_AUX_CH_CTL_DONE | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 438 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 439 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 440 | timeout | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 441 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 442 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 443 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 444 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 445 | } |
| 446 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 447 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 448 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 449 | uint8_t *send, int send_bytes, |
| 450 | uint8_t *recv, int recv_size) |
| 451 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 452 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 453 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 454 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 455 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 456 | uint32_t ch_data = ch_ctl + 4; |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 457 | uint32_t aux_clock_divider; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 458 | int i, ret, recv_bytes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 459 | uint32_t status; |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 460 | int try, clock = 0; |
Daniel Vetter | 4e6b788 | 2014-02-07 16:33:20 +0100 | [diff] [blame] | 461 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 462 | |
| 463 | /* dp aux is extremely sensitive to irq latency, hence request the |
| 464 | * lowest possible wakeup latency and so prevent the cpu from going into |
| 465 | * deep sleep states. |
| 466 | */ |
| 467 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 468 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 469 | intel_dp_check_edp(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 470 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 471 | intel_aux_display_runtime_get(dev_priv); |
| 472 | |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 473 | /* Try to wait for any previous AUX channel activity */ |
| 474 | for (try = 0; try < 3; try++) { |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 475 | status = I915_READ_NOTRACE(ch_ctl); |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 476 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 477 | break; |
| 478 | msleep(1); |
| 479 | } |
| 480 | |
| 481 | if (try == 3) { |
| 482 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 483 | I915_READ(ch_ctl)); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 484 | ret = -EBUSY; |
| 485 | goto out; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 486 | } |
| 487 | |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 488 | /* Only 5 data registers! */ |
| 489 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
| 490 | ret = -E2BIG; |
| 491 | goto out; |
| 492 | } |
| 493 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 494 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 495 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
| 496 | has_aux_irq, |
| 497 | send_bytes, |
| 498 | aux_clock_divider); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 499 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 500 | /* Must try at least 3 times according to DP spec */ |
| 501 | for (try = 0; try < 5; try++) { |
| 502 | /* Load the send data into the aux channel data registers */ |
| 503 | for (i = 0; i < send_bytes; i += 4) |
| 504 | I915_WRITE(ch_data + i, |
| 505 | pack_aux(send + i, send_bytes - i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 506 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 507 | /* Send the command and wait for it to complete */ |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 508 | I915_WRITE(ch_ctl, send_ctl); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 509 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 510 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 511 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 512 | /* Clear done status and any errors */ |
| 513 | I915_WRITE(ch_ctl, |
| 514 | status | |
| 515 | DP_AUX_CH_CTL_DONE | |
| 516 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 517 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Adam Jackson | d7e96fe | 2011-07-26 15:39:46 -0400 | [diff] [blame] | 518 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 519 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 520 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
| 521 | continue; |
| 522 | if (status & DP_AUX_CH_CTL_DONE) |
| 523 | break; |
| 524 | } |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 525 | if (status & DP_AUX_CH_CTL_DONE) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 526 | break; |
| 527 | } |
| 528 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 529 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 530 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 531 | ret = -EBUSY; |
| 532 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | /* Check for timeout or receive error. |
| 536 | * Timeouts occur when the sink is not connected |
| 537 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 538 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 539 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 540 | ret = -EIO; |
| 541 | goto out; |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 542 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 543 | |
| 544 | /* Timeouts occur when the device isn't connected, so they're |
| 545 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 546 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 547 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 548 | ret = -ETIMEDOUT; |
| 549 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 550 | } |
| 551 | |
| 552 | /* Unload any bytes sent back from the other side */ |
| 553 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 554 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 555 | if (recv_bytes > recv_size) |
| 556 | recv_bytes = recv_size; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 557 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 558 | for (i = 0; i < recv_bytes; i += 4) |
| 559 | unpack_aux(I915_READ(ch_data + i), |
| 560 | recv + i, recv_bytes - i); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 561 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 562 | ret = recv_bytes; |
| 563 | out: |
| 564 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 565 | intel_aux_display_runtime_put(dev_priv); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 566 | |
| 567 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 568 | } |
| 569 | |
| 570 | /* Write data to the aux channel in native mode */ |
| 571 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 572 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 573 | uint16_t address, uint8_t *send, int send_bytes) |
| 574 | { |
| 575 | int ret; |
| 576 | uint8_t msg[20]; |
| 577 | int msg_bytes; |
| 578 | uint8_t ack; |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 579 | int retry; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 580 | |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 581 | if (WARN_ON(send_bytes > 16)) |
| 582 | return -E2BIG; |
| 583 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 584 | intel_dp_check_edp(intel_dp); |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 585 | msg[0] = DP_AUX_NATIVE_WRITE << 4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 586 | msg[1] = address >> 8; |
Zhenyu Wang | eebc863 | 2009-07-24 01:00:30 +0800 | [diff] [blame] | 587 | msg[2] = address & 0xff; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 588 | msg[3] = send_bytes - 1; |
| 589 | memcpy(&msg[4], send, send_bytes); |
| 590 | msg_bytes = send_bytes + 4; |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 591 | for (retry = 0; retry < 7; retry++) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 592 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 593 | if (ret < 0) |
| 594 | return ret; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 595 | ack >>= 4; |
| 596 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 597 | return send_bytes; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 598 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
Jani Nikula | 04eada2 | 2014-02-11 11:52:04 +0200 | [diff] [blame] | 599 | usleep_range(400, 500); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 600 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 601 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 602 | } |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 603 | |
| 604 | DRM_ERROR("too many retries, giving up\n"); |
| 605 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 606 | } |
| 607 | |
| 608 | /* Write a single byte to the aux channel in native mode */ |
| 609 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 610 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 611 | uint16_t address, uint8_t byte) |
| 612 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 613 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 614 | } |
| 615 | |
| 616 | /* read bytes from a native aux channel */ |
| 617 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 618 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 619 | uint16_t address, uint8_t *recv, int recv_bytes) |
| 620 | { |
| 621 | uint8_t msg[4]; |
| 622 | int msg_bytes; |
| 623 | uint8_t reply[20]; |
| 624 | int reply_bytes; |
| 625 | uint8_t ack; |
| 626 | int ret; |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 627 | int retry; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 628 | |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 629 | if (WARN_ON(recv_bytes > 19)) |
| 630 | return -E2BIG; |
| 631 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 632 | intel_dp_check_edp(intel_dp); |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 633 | msg[0] = DP_AUX_NATIVE_READ << 4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 634 | msg[1] = address >> 8; |
| 635 | msg[2] = address & 0xff; |
| 636 | msg[3] = recv_bytes - 1; |
| 637 | |
| 638 | msg_bytes = 4; |
| 639 | reply_bytes = recv_bytes + 1; |
| 640 | |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 641 | for (retry = 0; retry < 7; retry++) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 642 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 643 | reply, reply_bytes); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 644 | if (ret == 0) |
| 645 | return -EPROTO; |
| 646 | if (ret < 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 647 | return ret; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 648 | ack = reply[0] >> 4; |
| 649 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 650 | memcpy(recv, reply + 1, ret - 1); |
| 651 | return ret - 1; |
| 652 | } |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 653 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
Jani Nikula | 04eada2 | 2014-02-11 11:52:04 +0200 | [diff] [blame] | 654 | usleep_range(400, 500); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 655 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 656 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 657 | } |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 658 | |
| 659 | DRM_ERROR("too many retries, giving up\n"); |
| 660 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 661 | } |
| 662 | |
| 663 | static int |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 664 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
| 665 | uint8_t write_byte, uint8_t *read_byte) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 666 | { |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 667 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 668 | struct intel_dp *intel_dp = container_of(adapter, |
| 669 | struct intel_dp, |
| 670 | adapter); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 671 | uint16_t address = algo_data->address; |
| 672 | uint8_t msg[5]; |
| 673 | uint8_t reply[2]; |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 674 | unsigned retry; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 675 | int msg_bytes; |
| 676 | int reply_bytes; |
| 677 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 678 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 679 | edp_panel_vdd_on(intel_dp); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 680 | intel_dp_check_edp(intel_dp); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 681 | /* Set up the command byte */ |
| 682 | if (mode & MODE_I2C_READ) |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 683 | msg[0] = DP_AUX_I2C_READ << 4; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 684 | else |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 685 | msg[0] = DP_AUX_I2C_WRITE << 4; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 686 | |
| 687 | if (!(mode & MODE_I2C_STOP)) |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 688 | msg[0] |= DP_AUX_I2C_MOT << 4; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 689 | |
| 690 | msg[1] = address >> 8; |
| 691 | msg[2] = address; |
| 692 | |
| 693 | switch (mode) { |
| 694 | case MODE_I2C_WRITE: |
| 695 | msg[3] = 0; |
| 696 | msg[4] = write_byte; |
| 697 | msg_bytes = 5; |
| 698 | reply_bytes = 1; |
| 699 | break; |
| 700 | case MODE_I2C_READ: |
| 701 | msg[3] = 0; |
| 702 | msg_bytes = 4; |
| 703 | reply_bytes = 2; |
| 704 | break; |
| 705 | default: |
| 706 | msg_bytes = 3; |
| 707 | reply_bytes = 1; |
| 708 | break; |
| 709 | } |
| 710 | |
Jani Nikula | 58c67ce | 2013-09-20 16:42:14 +0300 | [diff] [blame] | 711 | /* |
| 712 | * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is |
| 713 | * required to retry at least seven times upon receiving AUX_DEFER |
| 714 | * before giving up the AUX transaction. |
| 715 | */ |
| 716 | for (retry = 0; retry < 7; retry++) { |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 717 | ret = intel_dp_aux_ch(intel_dp, |
| 718 | msg, msg_bytes, |
| 719 | reply, reply_bytes); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 720 | if (ret < 0) { |
Dave Airlie | 3ff9916 | 2009-12-08 14:03:47 +1000 | [diff] [blame] | 721 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
Paulo Zanoni | 8a5e6aeb | 2013-10-30 19:50:26 -0200 | [diff] [blame] | 722 | goto out; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 723 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 724 | |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 725 | switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { |
| 726 | case DP_AUX_NATIVE_REPLY_ACK: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 727 | /* I2C-over-AUX Reply field is only valid |
| 728 | * when paired with AUX ACK. |
| 729 | */ |
| 730 | break; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 731 | case DP_AUX_NATIVE_REPLY_NACK: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 732 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
Paulo Zanoni | 8a5e6aeb | 2013-10-30 19:50:26 -0200 | [diff] [blame] | 733 | ret = -EREMOTEIO; |
| 734 | goto out; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 735 | case DP_AUX_NATIVE_REPLY_DEFER: |
Jani Nikula | 8d16f25 | 2013-09-20 16:42:15 +0300 | [diff] [blame] | 736 | /* |
| 737 | * For now, just give more slack to branch devices. We |
| 738 | * could check the DPCD for I2C bit rate capabilities, |
| 739 | * and if available, adjust the interval. We could also |
| 740 | * be more careful with DP-to-Legacy adapters where a |
| 741 | * long legacy cable may force very low I2C bit rates. |
| 742 | */ |
| 743 | if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 744 | DP_DWN_STRM_PORT_PRESENT) |
| 745 | usleep_range(500, 600); |
| 746 | else |
| 747 | usleep_range(300, 400); |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 748 | continue; |
| 749 | default: |
| 750 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
| 751 | reply[0]); |
Paulo Zanoni | 8a5e6aeb | 2013-10-30 19:50:26 -0200 | [diff] [blame] | 752 | ret = -EREMOTEIO; |
| 753 | goto out; |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 754 | } |
| 755 | |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 756 | switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { |
| 757 | case DP_AUX_I2C_REPLY_ACK: |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 758 | if (mode == MODE_I2C_READ) { |
| 759 | *read_byte = reply[1]; |
| 760 | } |
Paulo Zanoni | 8a5e6aeb | 2013-10-30 19:50:26 -0200 | [diff] [blame] | 761 | ret = reply_bytes - 1; |
| 762 | goto out; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 763 | case DP_AUX_I2C_REPLY_NACK: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 764 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
Paulo Zanoni | 8a5e6aeb | 2013-10-30 19:50:26 -0200 | [diff] [blame] | 765 | ret = -EREMOTEIO; |
| 766 | goto out; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 767 | case DP_AUX_I2C_REPLY_DEFER: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 768 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 769 | udelay(100); |
| 770 | break; |
| 771 | default: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 772 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
Paulo Zanoni | 8a5e6aeb | 2013-10-30 19:50:26 -0200 | [diff] [blame] | 773 | ret = -EREMOTEIO; |
| 774 | goto out; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 775 | } |
| 776 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 777 | |
| 778 | DRM_ERROR("too many retries, giving up\n"); |
Paulo Zanoni | 8a5e6aeb | 2013-10-30 19:50:26 -0200 | [diff] [blame] | 779 | ret = -EREMOTEIO; |
| 780 | |
| 781 | out: |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 782 | edp_panel_vdd_off(intel_dp, false); |
Paulo Zanoni | 8a5e6aeb | 2013-10-30 19:50:26 -0200 | [diff] [blame] | 783 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 784 | } |
| 785 | |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 786 | static void |
| 787 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
| 788 | { |
| 789 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
| 790 | |
| 791 | sysfs_remove_link(&intel_connector->base.kdev->kobj, |
| 792 | intel_dp->adapter.dev.kobj.name); |
| 793 | intel_connector_unregister(intel_connector); |
| 794 | } |
| 795 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 796 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 797 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 798 | struct intel_connector *intel_connector, const char *name) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 799 | { |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 800 | int ret; |
| 801 | |
Zhenyu Wang | d54e9d2 | 2009-10-19 15:43:51 +0800 | [diff] [blame] | 802 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 803 | intel_dp->algo.running = false; |
| 804 | intel_dp->algo.address = 0; |
| 805 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 806 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 807 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 808 | intel_dp->adapter.owner = THIS_MODULE; |
| 809 | intel_dp->adapter.class = I2C_CLASS_DDC; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 810 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 811 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
| 812 | intel_dp->adapter.algo_data = &intel_dp->algo; |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 813 | intel_dp->adapter.dev.parent = intel_connector->base.dev->dev; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 814 | |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 815 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 816 | if (ret < 0) |
| 817 | return ret; |
| 818 | |
| 819 | ret = sysfs_create_link(&intel_connector->base.kdev->kobj, |
| 820 | &intel_dp->adapter.dev.kobj, |
| 821 | intel_dp->adapter.dev.kobj.name); |
| 822 | |
| 823 | if (ret < 0) |
| 824 | i2c_del_adapter(&intel_dp->adapter); |
| 825 | |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 826 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 827 | } |
| 828 | |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 829 | static void |
| 830 | intel_dp_set_clock(struct intel_encoder *encoder, |
| 831 | struct intel_crtc_config *pipe_config, int link_bw) |
| 832 | { |
| 833 | struct drm_device *dev = encoder->base.dev; |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 834 | const struct dp_link_dpll *divisor = NULL; |
| 835 | int i, count = 0; |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 836 | |
| 837 | if (IS_G4X(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 838 | divisor = gen4_dpll; |
| 839 | count = ARRAY_SIZE(gen4_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 840 | } else if (IS_HASWELL(dev)) { |
| 841 | /* Haswell has special-purpose DP DDI clocks. */ |
| 842 | } else if (HAS_PCH_SPLIT(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 843 | divisor = pch_dpll; |
| 844 | count = ARRAY_SIZE(pch_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 845 | } else if (IS_VALLEYVIEW(dev)) { |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 846 | divisor = vlv_dpll; |
| 847 | count = ARRAY_SIZE(vlv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 848 | } |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 849 | |
| 850 | if (divisor && count) { |
| 851 | for (i = 0; i < count; i++) { |
| 852 | if (link_bw == divisor[i].link_bw) { |
| 853 | pipe_config->dpll = divisor[i].dpll; |
| 854 | pipe_config->clock_set = true; |
| 855 | break; |
| 856 | } |
| 857 | } |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 858 | } |
| 859 | } |
| 860 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 861 | bool |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 862 | intel_dp_compute_config(struct intel_encoder *encoder, |
| 863 | struct intel_crtc_config *pipe_config) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 864 | { |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 865 | struct drm_device *dev = encoder->base.dev; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 866 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 867 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 868 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 869 | enum port port = dp_to_dig_port(intel_dp)->port; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 870 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 871 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 872 | int lane_count, clock; |
Daniel Vetter | 397fe15 | 2012-10-22 22:56:43 +0200 | [diff] [blame] | 873 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 874 | /* Conveniently, the link BW constants become indices with a shift...*/ |
| 875 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 876 | int bpp, mode_rate; |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 877 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 878 | int link_avail, link_clock; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 879 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 880 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 881 | pipe_config->has_pch_encoder = true; |
| 882 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 883 | pipe_config->has_dp_encoder = true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 884 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 885 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 886 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 887 | adjusted_mode); |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 888 | if (!HAS_PCH_SPLIT(dev)) |
| 889 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
| 890 | intel_connector->panel.fitting_mode); |
| 891 | else |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 892 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
| 893 | intel_connector->panel.fitting_mode); |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 894 | } |
| 895 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 896 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 897 | return false; |
| 898 | |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 899 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
| 900 | "max bw %02x pixel clock %iKHz\n", |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 901 | max_lane_count, bws[max_clock], |
| 902 | adjusted_mode->crtc_clock); |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 903 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 904 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
| 905 | * bpc in between. */ |
Daniel Vetter | 3e7ca98 | 2013-06-01 19:45:56 +0200 | [diff] [blame] | 906 | bpp = pipe_config->pipe_bpp; |
Jani Nikula | 6da7f10 | 2013-10-16 17:06:17 +0300 | [diff] [blame] | 907 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
| 908 | dev_priv->vbt.edp_bpp < bpp) { |
Imre Deak | 7984211 | 2013-07-18 17:44:13 +0300 | [diff] [blame] | 909 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
| 910 | dev_priv->vbt.edp_bpp); |
Jani Nikula | 6da7f10 | 2013-10-16 17:06:17 +0300 | [diff] [blame] | 911 | bpp = dev_priv->vbt.edp_bpp; |
Imre Deak | 7984211 | 2013-07-18 17:44:13 +0300 | [diff] [blame] | 912 | } |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 913 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 914 | for (; bpp >= 6*3; bpp -= 2*3) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 915 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
| 916 | bpp); |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 917 | |
Daniel Vetter | 38aecea | 2014-03-03 11:18:10 +0100 | [diff] [blame] | 918 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
| 919 | for (clock = 0; clock <= max_clock; clock++) { |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 920 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
| 921 | link_avail = intel_dp_max_data_rate(link_clock, |
| 922 | lane_count); |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 923 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 924 | if (mode_rate <= link_avail) { |
| 925 | goto found; |
| 926 | } |
| 927 | } |
| 928 | } |
| 929 | } |
| 930 | |
| 931 | return false; |
| 932 | |
| 933 | found: |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 934 | if (intel_dp->color_range_auto) { |
| 935 | /* |
| 936 | * See: |
| 937 | * CEA-861-E - 5.1 Default Encoding Parameters |
| 938 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| 939 | */ |
Thierry Reding | 18316c8 | 2012-12-20 15:41:44 +0100 | [diff] [blame] | 940 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 941 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
| 942 | else |
| 943 | intel_dp->color_range = 0; |
| 944 | } |
| 945 | |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 946 | if (intel_dp->color_range) |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 947 | pipe_config->limited_color_range = true; |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 948 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 949 | intel_dp->link_bw = bws[clock]; |
| 950 | intel_dp->lane_count = lane_count; |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 951 | pipe_config->pipe_bpp = bpp; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 952 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 953 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 954 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
| 955 | intel_dp->link_bw, intel_dp->lane_count, |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 956 | pipe_config->port_clock, bpp); |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 957 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
| 958 | mode_rate, link_avail); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 959 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 960 | intel_link_compute_m_n(bpp, lane_count, |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 961 | adjusted_mode->crtc_clock, |
| 962 | pipe_config->port_clock, |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 963 | &pipe_config->dp_m_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 964 | |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 965 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
| 966 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 967 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 968 | } |
| 969 | |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 970 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 971 | { |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 972 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 973 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 974 | struct drm_device *dev = crtc->base.dev; |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 975 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 976 | u32 dpa_ctl; |
| 977 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 978 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 979 | dpa_ctl = I915_READ(DP_A); |
| 980 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
| 981 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 982 | if (crtc->config.port_clock == 162000) { |
Daniel Vetter | 1ce1703 | 2012-11-29 15:59:32 +0100 | [diff] [blame] | 983 | /* For a long time we've carried around a ILK-DevA w/a for the |
| 984 | * 160MHz clock. If we're really unlucky, it's still required. |
| 985 | */ |
| 986 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 987 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 988 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 989 | } else { |
| 990 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 991 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 992 | } |
Daniel Vetter | 1ce1703 | 2012-11-29 15:59:32 +0100 | [diff] [blame] | 993 | |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 994 | I915_WRITE(DP_A, dpa_ctl); |
| 995 | |
| 996 | POSTING_READ(DP_A); |
| 997 | udelay(500); |
| 998 | } |
| 999 | |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1000 | static void intel_dp_mode_set(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1001 | { |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1002 | struct drm_device *dev = encoder->base.dev; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1003 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1004 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1005 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1006 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 1007 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1008 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1009 | /* |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1010 | * There are four kinds of DP registers: |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1011 | * |
| 1012 | * IBX PCH |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1013 | * SNB CPU |
| 1014 | * IVB CPU |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1015 | * CPT PCH |
| 1016 | * |
| 1017 | * IBX PCH and CPU are the same for almost everything, |
| 1018 | * except that the CPU DP PLL is configured in this |
| 1019 | * register |
| 1020 | * |
| 1021 | * CPT PCH is quite different, having many bits moved |
| 1022 | * to the TRANS_DP_CTL register instead. That |
| 1023 | * configuration happens (oddly) in ironlake_pch_enable |
| 1024 | */ |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 1025 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1026 | /* Preserve the BIOS-computed detected bit. This is |
| 1027 | * supposed to be read-only. |
| 1028 | */ |
| 1029 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1030 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1031 | /* Handle DP bits in common between all three register formats */ |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1032 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
Daniel Vetter | 17aa6be | 2013-04-30 14:01:40 +0200 | [diff] [blame] | 1033 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1034 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 1035 | if (intel_dp->has_audio) { |
| 1036 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 1037 | pipe_name(crtc->pipe)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1038 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1039 | intel_write_eld(&encoder->base, adjusted_mode); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 1040 | } |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 1041 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1042 | /* Split out the IBX/CPU vs CPT settings */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1043 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1044 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1045 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1046 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1047 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1048 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1049 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 1050 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 1051 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1052 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1053 | |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 1054 | intel_dp->DP |= crtc->pipe << 29; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1055 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 1056 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 1057 | intel_dp->DP |= intel_dp->color_range; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1058 | |
| 1059 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1060 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1061 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1062 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1063 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| 1064 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 1065 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1066 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1067 | |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 1068 | if (crtc->pipe == 1) |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1069 | intel_dp->DP |= DP_PIPEB_SELECT; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1070 | } else { |
| 1071 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1072 | } |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 1073 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1074 | if (port == PORT_A && !IS_VALLEYVIEW(dev)) |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 1075 | ironlake_set_pll_cpu_edp(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1076 | } |
| 1077 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1078 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 1079 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1080 | |
Paulo Zanoni | 1a5ef5b | 2013-12-19 14:29:43 -0200 | [diff] [blame] | 1081 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
| 1082 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1083 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1084 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| 1085 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1086 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1087 | static void wait_panel_status(struct intel_dp *intel_dp, |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1088 | u32 mask, |
| 1089 | u32 value) |
| 1090 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1091 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1092 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1093 | u32 pp_stat_reg, pp_ctrl_reg; |
| 1094 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1095 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1096 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1097 | |
| 1098 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1099 | mask, value, |
| 1100 | I915_READ(pp_stat_reg), |
| 1101 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1102 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1103 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1104 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1105 | I915_READ(pp_stat_reg), |
| 1106 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1107 | } |
Chris Wilson | 54c136d | 2013-12-02 09:57:16 +0000 | [diff] [blame] | 1108 | |
| 1109 | DRM_DEBUG_KMS("Wait complete\n"); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1110 | } |
| 1111 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1112 | static void wait_panel_on(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1113 | { |
| 1114 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1115 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1116 | } |
| 1117 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1118 | static void wait_panel_off(struct intel_dp *intel_dp) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1119 | { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1120 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1121 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1122 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1123 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1124 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1125 | { |
| 1126 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1127 | |
| 1128 | /* When we disable the VDD override bit last we have to do the manual |
| 1129 | * wait. */ |
| 1130 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
| 1131 | intel_dp->panel_power_cycle_delay); |
| 1132 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1133 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1134 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1135 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1136 | static void wait_backlight_on(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1137 | { |
| 1138 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
| 1139 | intel_dp->backlight_on_delay); |
| 1140 | } |
| 1141 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1142 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1143 | { |
| 1144 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
| 1145 | intel_dp->backlight_off_delay); |
| 1146 | } |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1147 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1148 | /* Read the current pp_control value, unlocking the register if it |
| 1149 | * is locked |
| 1150 | */ |
| 1151 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1152 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1153 | { |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1154 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1155 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1156 | u32 control; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1157 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1158 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1159 | control &= ~PANEL_UNLOCK_MASK; |
| 1160 | control |= PANEL_UNLOCK_REGS; |
| 1161 | return control; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1162 | } |
| 1163 | |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame^] | 1164 | void edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1165 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1166 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1167 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1168 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1169 | u32 pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1170 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1171 | if (!is_edp(intel_dp)) |
| 1172 | return; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1173 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1174 | WARN(intel_dp->want_panel_vdd, |
| 1175 | "eDP VDD already requested on\n"); |
| 1176 | |
| 1177 | intel_dp->want_panel_vdd = true; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1178 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1179 | if (edp_have_panel_vdd(intel_dp)) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1180 | return; |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1181 | |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1182 | intel_runtime_pm_get(dev_priv); |
| 1183 | |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1184 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1185 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1186 | if (!edp_have_panel_power(intel_dp)) |
| 1187 | wait_panel_power_cycle(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1188 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1189 | pp = ironlake_get_pp_control(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1190 | pp |= EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1191 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1192 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1193 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1194 | |
| 1195 | I915_WRITE(pp_ctrl_reg, pp); |
| 1196 | POSTING_READ(pp_ctrl_reg); |
| 1197 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1198 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1199 | /* |
| 1200 | * If the panel wasn't on, delay before accessing aux channel |
| 1201 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1202 | if (!edp_have_panel_power(intel_dp)) { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1203 | DRM_DEBUG_KMS("eDP was not running\n"); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1204 | msleep(intel_dp->panel_power_up_delay); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1205 | } |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1206 | } |
| 1207 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1208 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1209 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1210 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1211 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1212 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1213 | u32 pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1214 | |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1215 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
| 1216 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1217 | if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1218 | DRM_DEBUG_KMS("Turning eDP VDD off\n"); |
| 1219 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1220 | pp = ironlake_get_pp_control(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1221 | pp &= ~EDP_FORCE_VDD; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1222 | |
Paulo Zanoni | 9f08ef5 | 2013-10-31 12:44:21 -0200 | [diff] [blame] | 1223 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1224 | pp_stat_reg = _pp_stat_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1225 | |
| 1226 | I915_WRITE(pp_ctrl_reg, pp); |
| 1227 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1228 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1229 | /* Make sure sequencer is idle before allowing subsequent activity */ |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1230 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1231 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Paulo Zanoni | 90791a5 | 2013-12-06 17:32:42 -0200 | [diff] [blame] | 1232 | |
| 1233 | if ((pp & POWER_TARGET_ON) == 0) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1234 | intel_dp->last_power_cycle = jiffies; |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1235 | |
| 1236 | intel_runtime_pm_put(dev_priv); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1237 | } |
| 1238 | } |
| 1239 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1240 | static void edp_panel_vdd_work(struct work_struct *__work) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1241 | { |
| 1242 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 1243 | struct intel_dp, panel_vdd_work); |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1244 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1245 | |
Keith Packard | 627f767 | 2011-10-31 11:30:10 -0700 | [diff] [blame] | 1246 | mutex_lock(&dev->mode_config.mutex); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1247 | edp_panel_vdd_off_sync(intel_dp); |
Keith Packard | 627f767 | 2011-10-31 11:30:10 -0700 | [diff] [blame] | 1248 | mutex_unlock(&dev->mode_config.mutex); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1249 | } |
| 1250 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1251 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1252 | { |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1253 | if (!is_edp(intel_dp)) |
| 1254 | return; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1255 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1256 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
Keith Packard | f2e8b18 | 2011-11-01 20:01:35 -0700 | [diff] [blame] | 1257 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1258 | intel_dp->want_panel_vdd = false; |
| 1259 | |
| 1260 | if (sync) { |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1261 | edp_panel_vdd_off_sync(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1262 | } else { |
| 1263 | /* |
| 1264 | * Queue the timer to fire a long |
| 1265 | * time from now (relative to the power down delay) |
| 1266 | * to keep the panel power up across a sequence of operations |
| 1267 | */ |
| 1268 | schedule_delayed_work(&intel_dp->panel_vdd_work, |
| 1269 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
| 1270 | } |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1271 | } |
| 1272 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1273 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1274 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1275 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1276 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1277 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1278 | u32 pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1279 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1280 | if (!is_edp(intel_dp)) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1281 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1282 | |
| 1283 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
| 1284 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1285 | if (edp_have_panel_power(intel_dp)) { |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1286 | DRM_DEBUG_KMS("eDP power already on\n"); |
Keith Packard | 7d639f3 | 2011-09-29 16:05:34 -0700 | [diff] [blame] | 1287 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1288 | } |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1289 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1290 | wait_panel_power_cycle(intel_dp); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1291 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1292 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1293 | pp = ironlake_get_pp_control(intel_dp); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1294 | if (IS_GEN5(dev)) { |
| 1295 | /* ILK workaround: disable reset around power sequence */ |
| 1296 | pp &= ~PANEL_POWER_RESET; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1297 | I915_WRITE(pp_ctrl_reg, pp); |
| 1298 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1299 | } |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1300 | |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 1301 | pp |= POWER_TARGET_ON; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1302 | if (!IS_GEN5(dev)) |
| 1303 | pp |= PANEL_POWER_RESET; |
| 1304 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1305 | I915_WRITE(pp_ctrl_reg, pp); |
| 1306 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1307 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1308 | wait_panel_on(intel_dp); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1309 | intel_dp->last_power_on = jiffies; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1310 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1311 | if (IS_GEN5(dev)) { |
| 1312 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1313 | I915_WRITE(pp_ctrl_reg, pp); |
| 1314 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1315 | } |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1316 | } |
| 1317 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1318 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1319 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1320 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1321 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1322 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1323 | u32 pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1324 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1325 | if (!is_edp(intel_dp)) |
| 1326 | return; |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1327 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1328 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1329 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1330 | edp_wait_backlight_off(intel_dp); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1331 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1332 | pp = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 1333 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 1334 | * panels get very unhappy and cease to work. */ |
Patrik Jakobsson | b306415 | 2014-03-04 00:42:44 +0100 | [diff] [blame] | 1335 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
| 1336 | EDP_BLC_ENABLE); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1337 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1338 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1339 | |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame^] | 1340 | intel_dp->want_panel_vdd = false; |
| 1341 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1342 | I915_WRITE(pp_ctrl_reg, pp); |
| 1343 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1344 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1345 | intel_dp->last_power_cycle = jiffies; |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1346 | wait_panel_off(intel_dp); |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame^] | 1347 | |
| 1348 | /* We got a reference when we enabled the VDD. */ |
| 1349 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1350 | } |
| 1351 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1352 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1353 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 1354 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1355 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1356 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1357 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1358 | u32 pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1359 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1360 | if (!is_edp(intel_dp)) |
| 1361 | return; |
| 1362 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1363 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1364 | /* |
| 1365 | * If we enable the backlight right away following a panel power |
| 1366 | * on, we may see slight flicker as the panel syncs with the eDP |
| 1367 | * link. So delay a bit to make sure the image is solid before |
| 1368 | * allowing it to appear. |
| 1369 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1370 | wait_backlight_on(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1371 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1372 | pp |= EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1373 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1374 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1375 | |
| 1376 | I915_WRITE(pp_ctrl_reg, pp); |
| 1377 | POSTING_READ(pp_ctrl_reg); |
Daniel Vetter | 035aa3d | 2012-10-20 20:57:42 +0200 | [diff] [blame] | 1378 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 1379 | intel_panel_enable_backlight(intel_dp->attached_connector); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1380 | } |
| 1381 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1382 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1383 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1384 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1385 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1386 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1387 | u32 pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1388 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1389 | if (!is_edp(intel_dp)) |
| 1390 | return; |
| 1391 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 1392 | intel_panel_disable_backlight(intel_dp->attached_connector); |
Daniel Vetter | 035aa3d | 2012-10-20 20:57:42 +0200 | [diff] [blame] | 1393 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1394 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1395 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1396 | pp &= ~EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1397 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1398 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1399 | |
| 1400 | I915_WRITE(pp_ctrl_reg, pp); |
| 1401 | POSTING_READ(pp_ctrl_reg); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1402 | intel_dp->last_backlight_off = jiffies; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1403 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1404 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1405 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1406 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 1407 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1408 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 1409 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1410 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1411 | u32 dpa_ctl; |
| 1412 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1413 | assert_pipe_disabled(dev_priv, |
| 1414 | to_intel_crtc(crtc)->pipe); |
| 1415 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1416 | DRM_DEBUG_KMS("\n"); |
| 1417 | dpa_ctl = I915_READ(DP_A); |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 1418 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
| 1419 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
| 1420 | |
| 1421 | /* We don't adjust intel_dp->DP while tearing down the link, to |
| 1422 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
| 1423 | * enable bits here to ensure that we don't enable too much. */ |
| 1424 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
| 1425 | intel_dp->DP |= DP_PLL_ENABLE; |
| 1426 | I915_WRITE(DP_A, intel_dp->DP); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1427 | POSTING_READ(DP_A); |
| 1428 | udelay(200); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1429 | } |
| 1430 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1431 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1432 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 1433 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1434 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 1435 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1436 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1437 | u32 dpa_ctl; |
| 1438 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1439 | assert_pipe_disabled(dev_priv, |
| 1440 | to_intel_crtc(crtc)->pipe); |
| 1441 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1442 | dpa_ctl = I915_READ(DP_A); |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 1443 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
| 1444 | "dp pll off, should be on\n"); |
| 1445 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
| 1446 | |
| 1447 | /* We can't rely on the value tracked for the DP register in |
| 1448 | * intel_dp->DP because link_down must not change that (otherwise link |
| 1449 | * re-training will fail. */ |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1450 | dpa_ctl &= ~DP_PLL_ENABLE; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1451 | I915_WRITE(DP_A, dpa_ctl); |
Chris Wilson | 1af5fa1 | 2010-09-08 21:07:28 +0100 | [diff] [blame] | 1452 | POSTING_READ(DP_A); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1453 | udelay(200); |
| 1454 | } |
| 1455 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1456 | /* If the sink supports it, try to set the power state appropriately */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1457 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1458 | { |
| 1459 | int ret, i; |
| 1460 | |
| 1461 | /* Should have a valid DPCD by this point */ |
| 1462 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 1463 | return; |
| 1464 | |
| 1465 | if (mode != DRM_MODE_DPMS_ON) { |
| 1466 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, |
| 1467 | DP_SET_POWER_D3); |
| 1468 | if (ret != 1) |
| 1469 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
| 1470 | } else { |
| 1471 | /* |
| 1472 | * When turning on, we need to retry for 1ms to give the sink |
| 1473 | * time to wake up. |
| 1474 | */ |
| 1475 | for (i = 0; i < 3; i++) { |
| 1476 | ret = intel_dp_aux_native_write_1(intel_dp, |
| 1477 | DP_SET_POWER, |
| 1478 | DP_SET_POWER_D0); |
| 1479 | if (ret == 1) |
| 1480 | break; |
| 1481 | msleep(1); |
| 1482 | } |
| 1483 | } |
| 1484 | } |
| 1485 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1486 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 1487 | enum pipe *pipe) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1488 | { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1489 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1490 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1491 | struct drm_device *dev = encoder->base.dev; |
| 1492 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 1493 | enum intel_display_power_domain power_domain; |
| 1494 | u32 tmp; |
| 1495 | |
| 1496 | power_domain = intel_display_port_power_domain(encoder); |
| 1497 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
| 1498 | return false; |
| 1499 | |
| 1500 | tmp = I915_READ(intel_dp->output_reg); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1501 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1502 | if (!(tmp & DP_PORT_EN)) |
| 1503 | return false; |
| 1504 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1505 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1506 | *pipe = PORT_TO_PIPE_CPT(tmp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1507 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1508 | *pipe = PORT_TO_PIPE(tmp); |
| 1509 | } else { |
| 1510 | u32 trans_sel; |
| 1511 | u32 trans_dp; |
| 1512 | int i; |
| 1513 | |
| 1514 | switch (intel_dp->output_reg) { |
| 1515 | case PCH_DP_B: |
| 1516 | trans_sel = TRANS_DP_PORT_SEL_B; |
| 1517 | break; |
| 1518 | case PCH_DP_C: |
| 1519 | trans_sel = TRANS_DP_PORT_SEL_C; |
| 1520 | break; |
| 1521 | case PCH_DP_D: |
| 1522 | trans_sel = TRANS_DP_PORT_SEL_D; |
| 1523 | break; |
| 1524 | default: |
| 1525 | return true; |
| 1526 | } |
| 1527 | |
| 1528 | for_each_pipe(i) { |
| 1529 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
| 1530 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
| 1531 | *pipe = i; |
| 1532 | return true; |
| 1533 | } |
| 1534 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1535 | |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 1536 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
| 1537 | intel_dp->output_reg); |
| 1538 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1539 | |
| 1540 | return true; |
| 1541 | } |
| 1542 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1543 | static void intel_dp_get_config(struct intel_encoder *encoder, |
| 1544 | struct intel_crtc_config *pipe_config) |
| 1545 | { |
| 1546 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1547 | u32 tmp, flags = 0; |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 1548 | struct drm_device *dev = encoder->base.dev; |
| 1549 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1550 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1551 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 1552 | int dotclock; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1553 | |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 1554 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
| 1555 | tmp = I915_READ(intel_dp->output_reg); |
| 1556 | if (tmp & DP_SYNC_HS_HIGH) |
| 1557 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 1558 | else |
| 1559 | flags |= DRM_MODE_FLAG_NHSYNC; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1560 | |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 1561 | if (tmp & DP_SYNC_VS_HIGH) |
| 1562 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 1563 | else |
| 1564 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 1565 | } else { |
| 1566 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 1567 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
| 1568 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 1569 | else |
| 1570 | flags |= DRM_MODE_FLAG_NHSYNC; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1571 | |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 1572 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
| 1573 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 1574 | else |
| 1575 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 1576 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1577 | |
| 1578 | pipe_config->adjusted_mode.flags |= flags; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 1579 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 1580 | pipe_config->has_dp_encoder = true; |
| 1581 | |
| 1582 | intel_dp_get_m_n(crtc, pipe_config); |
| 1583 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 1584 | if (port == PORT_A) { |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 1585 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
| 1586 | pipe_config->port_clock = 162000; |
| 1587 | else |
| 1588 | pipe_config->port_clock = 270000; |
| 1589 | } |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 1590 | |
| 1591 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
| 1592 | &pipe_config->dp_m_n); |
| 1593 | |
| 1594 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
| 1595 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
| 1596 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1597 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
Daniel Vetter | 7f16e5c | 2013-11-04 16:28:47 +0100 | [diff] [blame] | 1598 | |
Jani Nikula | c6cd2ee | 2013-10-21 10:52:07 +0300 | [diff] [blame] | 1599 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
| 1600 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
| 1601 | /* |
| 1602 | * This is a big fat ugly hack. |
| 1603 | * |
| 1604 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 1605 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 1606 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 1607 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 1608 | * max, not what it tells us to use. |
| 1609 | * |
| 1610 | * Note: This will still be broken if the eDP panel is not lit |
| 1611 | * up by the BIOS, and thus we can't get the mode at module |
| 1612 | * load. |
| 1613 | */ |
| 1614 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
| 1615 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
| 1616 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
| 1617 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1618 | } |
| 1619 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1620 | static bool is_edp_psr(struct drm_device *dev) |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 1621 | { |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1622 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1623 | |
| 1624 | return dev_priv->psr.sink_support; |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 1625 | } |
| 1626 | |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1627 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
| 1628 | { |
| 1629 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1630 | |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1631 | if (!HAS_PSR(dev)) |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1632 | return false; |
| 1633 | |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1634 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1635 | } |
| 1636 | |
| 1637 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, |
| 1638 | struct edp_vsc_psr *vsc_psr) |
| 1639 | { |
| 1640 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1641 | struct drm_device *dev = dig_port->base.base.dev; |
| 1642 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1643 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 1644 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); |
| 1645 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); |
| 1646 | uint32_t *data = (uint32_t *) vsc_psr; |
| 1647 | unsigned int i; |
| 1648 | |
| 1649 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable |
| 1650 | the video DIP being updated before program video DIP data buffer |
| 1651 | registers for DIP being updated. */ |
| 1652 | I915_WRITE(ctl_reg, 0); |
| 1653 | POSTING_READ(ctl_reg); |
| 1654 | |
| 1655 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { |
| 1656 | if (i < sizeof(struct edp_vsc_psr)) |
| 1657 | I915_WRITE(data_reg + i, *data++); |
| 1658 | else |
| 1659 | I915_WRITE(data_reg + i, 0); |
| 1660 | } |
| 1661 | |
| 1662 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); |
| 1663 | POSTING_READ(ctl_reg); |
| 1664 | } |
| 1665 | |
| 1666 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) |
| 1667 | { |
| 1668 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1669 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1670 | struct edp_vsc_psr psr_vsc; |
| 1671 | |
| 1672 | if (intel_dp->psr_setup_done) |
| 1673 | return; |
| 1674 | |
| 1675 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
| 1676 | memset(&psr_vsc, 0, sizeof(psr_vsc)); |
| 1677 | psr_vsc.sdp_header.HB0 = 0; |
| 1678 | psr_vsc.sdp_header.HB1 = 0x7; |
| 1679 | psr_vsc.sdp_header.HB2 = 0x2; |
| 1680 | psr_vsc.sdp_header.HB3 = 0x8; |
| 1681 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); |
| 1682 | |
| 1683 | /* Avoid continuous PSR exit by masking memup and hpd */ |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1684 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
Rodrigo Vivi | 0cc4b69 | 2013-10-03 13:31:26 -0300 | [diff] [blame] | 1685 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1686 | |
| 1687 | intel_dp->psr_setup_done = true; |
| 1688 | } |
| 1689 | |
| 1690 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) |
| 1691 | { |
| 1692 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1693 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 1694 | uint32_t aux_clock_divider; |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1695 | int precharge = 0x3; |
| 1696 | int msg_size = 5; /* Header(4) + Message(1) */ |
| 1697 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 1698 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
| 1699 | |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1700 | /* Enable PSR in sink */ |
| 1701 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) |
| 1702 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, |
| 1703 | DP_PSR_ENABLE & |
| 1704 | ~DP_PSR_MAIN_LINK_ACTIVE); |
| 1705 | else |
| 1706 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, |
| 1707 | DP_PSR_ENABLE | |
| 1708 | DP_PSR_MAIN_LINK_ACTIVE); |
| 1709 | |
| 1710 | /* Setup AUX registers */ |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1711 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
| 1712 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); |
| 1713 | I915_WRITE(EDP_PSR_AUX_CTL(dev), |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1714 | DP_AUX_CH_CTL_TIME_OUT_400us | |
| 1715 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 1716 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 1717 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
| 1718 | } |
| 1719 | |
| 1720 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) |
| 1721 | { |
| 1722 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1723 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1724 | uint32_t max_sleep_time = 0x1f; |
| 1725 | uint32_t idle_frames = 1; |
| 1726 | uint32_t val = 0x0; |
Ben Widawsky | ed8546a | 2013-11-04 22:45:05 -0800 | [diff] [blame] | 1727 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1728 | |
| 1729 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { |
| 1730 | val |= EDP_PSR_LINK_STANDBY; |
| 1731 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
| 1732 | val |= EDP_PSR_TP1_TIME_0us; |
| 1733 | val |= EDP_PSR_SKIP_AUX_EXIT; |
| 1734 | } else |
| 1735 | val |= EDP_PSR_LINK_DISABLE; |
| 1736 | |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1737 | I915_WRITE(EDP_PSR_CTL(dev), val | |
Ben Widawsky | ed8546a | 2013-11-04 22:45:05 -0800 | [diff] [blame] | 1738 | IS_BROADWELL(dev) ? 0 : link_entry_time | |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1739 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
| 1740 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | |
| 1741 | EDP_PSR_ENABLE); |
| 1742 | } |
| 1743 | |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1744 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
| 1745 | { |
| 1746 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1747 | struct drm_device *dev = dig_port->base.base.dev; |
| 1748 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1749 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 1750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1751 | struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; |
| 1752 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
| 1753 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1754 | dev_priv->psr.source_ok = false; |
| 1755 | |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1756 | if (!HAS_PSR(dev)) { |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1757 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1758 | return false; |
| 1759 | } |
| 1760 | |
| 1761 | if ((intel_encoder->type != INTEL_OUTPUT_EDP) || |
| 1762 | (dig_port->port != PORT_A)) { |
| 1763 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1764 | return false; |
| 1765 | } |
| 1766 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 1767 | if (!i915.enable_psr) { |
Rodrigo Vivi | 105b7c1 | 2013-07-11 18:45:02 -0300 | [diff] [blame] | 1768 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
Rodrigo Vivi | 105b7c1 | 2013-07-11 18:45:02 -0300 | [diff] [blame] | 1769 | return false; |
| 1770 | } |
| 1771 | |
Chris Wilson | cd234b0 | 2013-08-02 20:39:49 +0100 | [diff] [blame] | 1772 | crtc = dig_port->base.base.crtc; |
| 1773 | if (crtc == NULL) { |
| 1774 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
Chris Wilson | cd234b0 | 2013-08-02 20:39:49 +0100 | [diff] [blame] | 1775 | return false; |
| 1776 | } |
| 1777 | |
| 1778 | intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1779 | if (!intel_crtc_active(crtc)) { |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1780 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1781 | return false; |
| 1782 | } |
| 1783 | |
Chris Wilson | cd234b0 | 2013-08-02 20:39:49 +0100 | [diff] [blame] | 1784 | obj = to_intel_framebuffer(crtc->fb)->obj; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1785 | if (obj->tiling_mode != I915_TILING_X || |
| 1786 | obj->fence_reg == I915_FENCE_REG_NONE) { |
| 1787 | DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1788 | return false; |
| 1789 | } |
| 1790 | |
| 1791 | if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { |
| 1792 | DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1793 | return false; |
| 1794 | } |
| 1795 | |
| 1796 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & |
| 1797 | S3D_ENABLE) { |
| 1798 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1799 | return false; |
| 1800 | } |
| 1801 | |
Ville Syrjälä | ca73b4f | 2013-09-04 18:25:24 +0300 | [diff] [blame] | 1802 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1803 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1804 | return false; |
| 1805 | } |
| 1806 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1807 | dev_priv->psr.source_ok = true; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1808 | return true; |
| 1809 | } |
| 1810 | |
Rodrigo Vivi | 3d739d9 | 2013-07-11 18:45:01 -0300 | [diff] [blame] | 1811 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1812 | { |
| 1813 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1814 | |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1815 | if (!intel_edp_psr_match_conditions(intel_dp) || |
| 1816 | intel_edp_is_psr_enabled(dev)) |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1817 | return; |
| 1818 | |
| 1819 | /* Setup PSR once */ |
| 1820 | intel_edp_psr_setup(intel_dp); |
| 1821 | |
| 1822 | /* Enable PSR on the panel */ |
| 1823 | intel_edp_psr_enable_sink(intel_dp); |
| 1824 | |
| 1825 | /* Enable PSR on the host */ |
| 1826 | intel_edp_psr_enable_source(intel_dp); |
| 1827 | } |
| 1828 | |
Rodrigo Vivi | 3d739d9 | 2013-07-11 18:45:01 -0300 | [diff] [blame] | 1829 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
| 1830 | { |
| 1831 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1832 | |
| 1833 | if (intel_edp_psr_match_conditions(intel_dp) && |
| 1834 | !intel_edp_is_psr_enabled(dev)) |
| 1835 | intel_edp_psr_do_enable(intel_dp); |
| 1836 | } |
| 1837 | |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1838 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
| 1839 | { |
| 1840 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1841 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1842 | |
| 1843 | if (!intel_edp_is_psr_enabled(dev)) |
| 1844 | return; |
| 1845 | |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1846 | I915_WRITE(EDP_PSR_CTL(dev), |
| 1847 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1848 | |
| 1849 | /* Wait till PSR is idle */ |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1850 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1851 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
| 1852 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
| 1853 | } |
| 1854 | |
Rodrigo Vivi | 3d739d9 | 2013-07-11 18:45:01 -0300 | [diff] [blame] | 1855 | void intel_edp_psr_update(struct drm_device *dev) |
| 1856 | { |
| 1857 | struct intel_encoder *encoder; |
| 1858 | struct intel_dp *intel_dp = NULL; |
| 1859 | |
| 1860 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) |
| 1861 | if (encoder->type == INTEL_OUTPUT_EDP) { |
| 1862 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 1863 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1864 | if (!is_edp_psr(dev)) |
Rodrigo Vivi | 3d739d9 | 2013-07-11 18:45:01 -0300 | [diff] [blame] | 1865 | return; |
| 1866 | |
| 1867 | if (!intel_edp_psr_match_conditions(intel_dp)) |
| 1868 | intel_edp_psr_disable(intel_dp); |
| 1869 | else |
| 1870 | if (!intel_edp_is_psr_enabled(dev)) |
| 1871 | intel_edp_psr_do_enable(intel_dp); |
| 1872 | } |
| 1873 | } |
| 1874 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1875 | static void intel_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1876 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1877 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1878 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1879 | struct drm_device *dev = encoder->base.dev; |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 1880 | |
| 1881 | /* Make sure the panel is off before trying to change the mode. But also |
| 1882 | * ensure that we have vdd while we switch off the panel. */ |
Patrik Jakobsson | b306415 | 2014-03-04 00:42:44 +0100 | [diff] [blame] | 1883 | edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1884 | intel_edp_backlight_off(intel_dp); |
Jani Nikula | fdbc3b1 | 2013-11-12 17:10:13 +0200 | [diff] [blame] | 1885 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1886 | intel_edp_panel_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1887 | |
| 1888 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1889 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1890 | intel_dp_link_down(intel_dp); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1891 | } |
| 1892 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1893 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1894 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1895 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1896 | enum port port = dp_to_dig_port(intel_dp)->port; |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 1897 | struct drm_device *dev = encoder->base.dev; |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1898 | |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1899 | if (port == PORT_A || IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1900 | intel_dp_link_down(intel_dp); |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 1901 | if (!IS_VALLEYVIEW(dev)) |
| 1902 | ironlake_edp_pll_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1903 | } |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1904 | } |
| 1905 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1906 | static void intel_enable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1907 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1908 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1909 | struct drm_device *dev = encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1910 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1911 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1912 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 1913 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
| 1914 | return; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1915 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1916 | edp_panel_vdd_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1917 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 1918 | intel_dp_start_link_train(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1919 | intel_edp_panel_on(intel_dp); |
| 1920 | edp_panel_vdd_off(intel_dp, true); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1921 | intel_dp_complete_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 1922 | intel_dp_stop_link_train(intel_dp); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1923 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1924 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 1925 | static void g4x_enable_dp(struct intel_encoder *encoder) |
| 1926 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 1927 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1928 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 1929 | intel_enable_dp(encoder); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1930 | intel_edp_backlight_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1931 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1932 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1933 | static void vlv_enable_dp(struct intel_encoder *encoder) |
| 1934 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 1935 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1936 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1937 | intel_edp_backlight_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1938 | } |
| 1939 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 1940 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1941 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1942 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1943 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1944 | |
| 1945 | if (dport->port == PORT_A) |
| 1946 | ironlake_edp_pll_on(intel_dp); |
| 1947 | } |
| 1948 | |
| 1949 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
| 1950 | { |
| 1951 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1952 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 1953 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1954 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1955 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1956 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1957 | int pipe = intel_crtc->pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1958 | struct edp_power_seq power_seq; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1959 | u32 val; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1960 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1961 | mutex_lock(&dev_priv->dpio_lock); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1962 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 1963 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1964 | val = 0; |
| 1965 | if (pipe) |
| 1966 | val |= (1<<21); |
| 1967 | else |
| 1968 | val &= ~(1<<21); |
| 1969 | val |= 0x001000c4; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 1970 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
| 1971 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
| 1972 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1973 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1974 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1975 | |
Imre Deak | 2cac613 | 2014-01-30 16:50:42 +0200 | [diff] [blame] | 1976 | if (is_edp(intel_dp)) { |
| 1977 | /* init power sequencer on this pipe and port */ |
| 1978 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
| 1979 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
| 1980 | &power_seq); |
| 1981 | } |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1982 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1983 | intel_enable_dp(encoder); |
| 1984 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1985 | vlv_wait_port_ready(dev_priv, dport); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1986 | } |
| 1987 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 1988 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1989 | { |
| 1990 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 1991 | struct drm_device *dev = encoder->base.dev; |
| 1992 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1993 | struct intel_crtc *intel_crtc = |
| 1994 | to_intel_crtc(encoder->base.crtc); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1995 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1996 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1997 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1998 | /* Program Tx lane resets to default */ |
Chris Wilson | 0980a60 | 2013-07-26 19:57:35 +0100 | [diff] [blame] | 1999 | mutex_lock(&dev_priv->dpio_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2000 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2001 | DPIO_PCS_TX_LANE2_RESET | |
| 2002 | DPIO_PCS_TX_LANE1_RESET); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2003 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2004 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
| 2005 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
| 2006 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | |
| 2007 | DPIO_PCS_CLK_SOFT_RESET); |
| 2008 | |
| 2009 | /* Fix up inter-pair skew failure */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2010 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
| 2011 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
| 2012 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
Chris Wilson | 0980a60 | 2013-07-26 19:57:35 +0100 | [diff] [blame] | 2013 | mutex_unlock(&dev_priv->dpio_lock); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2014 | } |
| 2015 | |
| 2016 | /* |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 2017 | * Native read with retry for link status and receiver capability reads for |
| 2018 | * cases where the sink may still be asleep. |
| 2019 | */ |
| 2020 | static bool |
| 2021 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
| 2022 | uint8_t *recv, int recv_bytes) |
| 2023 | { |
| 2024 | int ret, i; |
| 2025 | |
| 2026 | /* |
| 2027 | * Sinks are *supposed* to come up within 1ms from an off state, |
| 2028 | * but we're also supposed to retry 3 times per the spec. |
| 2029 | */ |
| 2030 | for (i = 0; i < 3; i++) { |
| 2031 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
| 2032 | recv_bytes); |
| 2033 | if (ret == recv_bytes) |
| 2034 | return true; |
| 2035 | msleep(1); |
| 2036 | } |
| 2037 | |
| 2038 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2039 | } |
| 2040 | |
| 2041 | /* |
| 2042 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 2043 | * link status information |
| 2044 | */ |
| 2045 | static bool |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2046 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2047 | { |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 2048 | return intel_dp_aux_native_read_retry(intel_dp, |
| 2049 | DP_LANE0_1_STATUS, |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2050 | link_status, |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 2051 | DP_LINK_STATUS_SIZE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2052 | } |
| 2053 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2054 | /* |
| 2055 | * These are source-specific values; current Intel hardware supports |
| 2056 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
| 2057 | */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2058 | |
| 2059 | static uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2060 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2061 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2062 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2063 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2064 | |
Paulo Zanoni | 8f93f4f | 2013-11-02 21:07:43 -0700 | [diff] [blame] | 2065 | if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2066 | return DP_TRAIN_VOLTAGE_SWING_1200; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2067 | else if (IS_GEN7(dev) && port == PORT_A) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2068 | return DP_TRAIN_VOLTAGE_SWING_800; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2069 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2070 | return DP_TRAIN_VOLTAGE_SWING_1200; |
| 2071 | else |
| 2072 | return DP_TRAIN_VOLTAGE_SWING_800; |
| 2073 | } |
| 2074 | |
| 2075 | static uint8_t |
| 2076 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
| 2077 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2078 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2079 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2080 | |
Paulo Zanoni | 8f93f4f | 2013-11-02 21:07:43 -0700 | [diff] [blame] | 2081 | if (IS_BROADWELL(dev)) { |
| 2082 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2083 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2084 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2085 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2086 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2087 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 2088 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2089 | default: |
| 2090 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 2091 | } |
| 2092 | } else if (IS_HASWELL(dev)) { |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2093 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2094 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2095 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
| 2096 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2097 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2098 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2099 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 2100 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2101 | default: |
| 2102 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 2103 | } |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2104 | } else if (IS_VALLEYVIEW(dev)) { |
| 2105 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2106 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2107 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
| 2108 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2109 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2110 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2111 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 2112 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2113 | default: |
| 2114 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 2115 | } |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2116 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2117 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2118 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2119 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2120 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2121 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2122 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 2123 | default: |
| 2124 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 2125 | } |
| 2126 | } else { |
| 2127 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2128 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2129 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2130 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2131 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2132 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2133 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 2134 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2135 | default: |
| 2136 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 2137 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2138 | } |
| 2139 | } |
| 2140 | |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2141 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
| 2142 | { |
| 2143 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2144 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2145 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2146 | struct intel_crtc *intel_crtc = |
| 2147 | to_intel_crtc(dport->base.base.crtc); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2148 | unsigned long demph_reg_value, preemph_reg_value, |
| 2149 | uniqtranscale_reg_value; |
| 2150 | uint8_t train_set = intel_dp->train_set[0]; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 2151 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2152 | int pipe = intel_crtc->pipe; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2153 | |
| 2154 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 2155 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 2156 | preemph_reg_value = 0x0004000; |
| 2157 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2158 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2159 | demph_reg_value = 0x2B405555; |
| 2160 | uniqtranscale_reg_value = 0x552AB83A; |
| 2161 | break; |
| 2162 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2163 | demph_reg_value = 0x2B404040; |
| 2164 | uniqtranscale_reg_value = 0x5548B83A; |
| 2165 | break; |
| 2166 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2167 | demph_reg_value = 0x2B245555; |
| 2168 | uniqtranscale_reg_value = 0x5560B83A; |
| 2169 | break; |
| 2170 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2171 | demph_reg_value = 0x2B405555; |
| 2172 | uniqtranscale_reg_value = 0x5598DA3A; |
| 2173 | break; |
| 2174 | default: |
| 2175 | return 0; |
| 2176 | } |
| 2177 | break; |
| 2178 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2179 | preemph_reg_value = 0x0002000; |
| 2180 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2181 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2182 | demph_reg_value = 0x2B404040; |
| 2183 | uniqtranscale_reg_value = 0x5552B83A; |
| 2184 | break; |
| 2185 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2186 | demph_reg_value = 0x2B404848; |
| 2187 | uniqtranscale_reg_value = 0x5580B83A; |
| 2188 | break; |
| 2189 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2190 | demph_reg_value = 0x2B404040; |
| 2191 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 2192 | break; |
| 2193 | default: |
| 2194 | return 0; |
| 2195 | } |
| 2196 | break; |
| 2197 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 2198 | preemph_reg_value = 0x0000000; |
| 2199 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2200 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2201 | demph_reg_value = 0x2B305555; |
| 2202 | uniqtranscale_reg_value = 0x5570B83A; |
| 2203 | break; |
| 2204 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2205 | demph_reg_value = 0x2B2B4040; |
| 2206 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 2207 | break; |
| 2208 | default: |
| 2209 | return 0; |
| 2210 | } |
| 2211 | break; |
| 2212 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 2213 | preemph_reg_value = 0x0006000; |
| 2214 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2215 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2216 | demph_reg_value = 0x1B405555; |
| 2217 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 2218 | break; |
| 2219 | default: |
| 2220 | return 0; |
| 2221 | } |
| 2222 | break; |
| 2223 | default: |
| 2224 | return 0; |
| 2225 | } |
| 2226 | |
Chris Wilson | 0980a60 | 2013-07-26 19:57:35 +0100 | [diff] [blame] | 2227 | mutex_lock(&dev_priv->dpio_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2228 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
| 2229 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
| 2230 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2231 | uniqtranscale_reg_value); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2232 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
| 2233 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
| 2234 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
| 2235 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
Chris Wilson | 0980a60 | 2013-07-26 19:57:35 +0100 | [diff] [blame] | 2236 | mutex_unlock(&dev_priv->dpio_lock); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2237 | |
| 2238 | return 0; |
| 2239 | } |
| 2240 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2241 | static void |
Jani Nikula | 0301b3a | 2013-10-15 09:36:08 +0300 | [diff] [blame] | 2242 | intel_get_adjust_train(struct intel_dp *intel_dp, |
| 2243 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2244 | { |
| 2245 | uint8_t v = 0; |
| 2246 | uint8_t p = 0; |
| 2247 | int lane; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2248 | uint8_t voltage_max; |
| 2249 | uint8_t preemph_max; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2250 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2251 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
Daniel Vetter | 0f037bd | 2012-10-18 10:15:27 +0200 | [diff] [blame] | 2252 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
| 2253 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2254 | |
| 2255 | if (this_v > v) |
| 2256 | v = this_v; |
| 2257 | if (this_p > p) |
| 2258 | p = this_p; |
| 2259 | } |
| 2260 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2261 | voltage_max = intel_dp_voltage_max(intel_dp); |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 2262 | if (v >= voltage_max) |
| 2263 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2264 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2265 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
| 2266 | if (p >= preemph_max) |
| 2267 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2268 | |
| 2269 | for (lane = 0; lane < 4; lane++) |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2270 | intel_dp->train_set[lane] = v | p; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2271 | } |
| 2272 | |
| 2273 | static uint32_t |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2274 | intel_gen4_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2275 | { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2276 | uint32_t signal_levels = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2277 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2278 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2279 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2280 | default: |
| 2281 | signal_levels |= DP_VOLTAGE_0_4; |
| 2282 | break; |
| 2283 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2284 | signal_levels |= DP_VOLTAGE_0_6; |
| 2285 | break; |
| 2286 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2287 | signal_levels |= DP_VOLTAGE_0_8; |
| 2288 | break; |
| 2289 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2290 | signal_levels |= DP_VOLTAGE_1_2; |
| 2291 | break; |
| 2292 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2293 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2294 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 2295 | default: |
| 2296 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 2297 | break; |
| 2298 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2299 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 2300 | break; |
| 2301 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 2302 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 2303 | break; |
| 2304 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 2305 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 2306 | break; |
| 2307 | } |
| 2308 | return signal_levels; |
| 2309 | } |
| 2310 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2311 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 2312 | static uint32_t |
| 2313 | intel_gen6_edp_signal_levels(uint8_t train_set) |
| 2314 | { |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2315 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 2316 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 2317 | switch (signal_levels) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2318 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2319 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2320 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
| 2321 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2322 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2323 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2324 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2325 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2326 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2327 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2328 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2329 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2330 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2331 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2332 | default: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2333 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 2334 | "0x%x\n", signal_levels); |
| 2335 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2336 | } |
| 2337 | } |
| 2338 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2339 | /* Gen7's DP voltage swing and pre-emphasis control */ |
| 2340 | static uint32_t |
| 2341 | intel_gen7_edp_signal_levels(uint8_t train_set) |
| 2342 | { |
| 2343 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 2344 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 2345 | switch (signal_levels) { |
| 2346 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2347 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
| 2348 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2349 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
| 2350 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2351 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
| 2352 | |
| 2353 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2354 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
| 2355 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2356 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
| 2357 | |
| 2358 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2359 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
| 2360 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2361 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
| 2362 | |
| 2363 | default: |
| 2364 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 2365 | "0x%x\n", signal_levels); |
| 2366 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
| 2367 | } |
| 2368 | } |
| 2369 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2370 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
| 2371 | static uint32_t |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2372 | intel_hsw_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2373 | { |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2374 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 2375 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 2376 | switch (signal_levels) { |
| 2377 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2378 | return DDI_BUF_EMP_400MV_0DB_HSW; |
| 2379 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2380 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
| 2381 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2382 | return DDI_BUF_EMP_400MV_6DB_HSW; |
| 2383 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
| 2384 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2385 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2386 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2387 | return DDI_BUF_EMP_600MV_0DB_HSW; |
| 2388 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2389 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
| 2390 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2391 | return DDI_BUF_EMP_600MV_6DB_HSW; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2392 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2393 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2394 | return DDI_BUF_EMP_800MV_0DB_HSW; |
| 2395 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2396 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
| 2397 | default: |
| 2398 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 2399 | "0x%x\n", signal_levels); |
| 2400 | return DDI_BUF_EMP_400MV_0DB_HSW; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2401 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2402 | } |
| 2403 | |
Paulo Zanoni | 8f93f4f | 2013-11-02 21:07:43 -0700 | [diff] [blame] | 2404 | static uint32_t |
| 2405 | intel_bdw_signal_levels(uint8_t train_set) |
| 2406 | { |
| 2407 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 2408 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 2409 | switch (signal_levels) { |
| 2410 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2411 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ |
| 2412 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2413 | return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ |
| 2414 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2415 | return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ |
| 2416 | |
| 2417 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2418 | return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ |
| 2419 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2420 | return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ |
| 2421 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2422 | return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ |
| 2423 | |
| 2424 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2425 | return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ |
| 2426 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2427 | return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ |
| 2428 | |
| 2429 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2430 | return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ |
| 2431 | |
| 2432 | default: |
| 2433 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 2434 | "0x%x\n", signal_levels); |
| 2435 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ |
| 2436 | } |
| 2437 | } |
| 2438 | |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2439 | /* Properly updates "DP" with the correct signal levels. */ |
| 2440 | static void |
| 2441 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
| 2442 | { |
| 2443 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2444 | enum port port = intel_dig_port->port; |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2445 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2446 | uint32_t signal_levels, mask; |
| 2447 | uint8_t train_set = intel_dp->train_set[0]; |
| 2448 | |
Paulo Zanoni | 8f93f4f | 2013-11-02 21:07:43 -0700 | [diff] [blame] | 2449 | if (IS_BROADWELL(dev)) { |
| 2450 | signal_levels = intel_bdw_signal_levels(train_set); |
| 2451 | mask = DDI_BUF_EMP_MASK; |
| 2452 | } else if (IS_HASWELL(dev)) { |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2453 | signal_levels = intel_hsw_signal_levels(train_set); |
| 2454 | mask = DDI_BUF_EMP_MASK; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2455 | } else if (IS_VALLEYVIEW(dev)) { |
| 2456 | signal_levels = intel_vlv_signal_levels(intel_dp); |
| 2457 | mask = 0; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2458 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2459 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
| 2460 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2461 | } else if (IS_GEN6(dev) && port == PORT_A) { |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2462 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
| 2463 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
| 2464 | } else { |
| 2465 | signal_levels = intel_gen4_signal_levels(train_set); |
| 2466 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
| 2467 | } |
| 2468 | |
| 2469 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
| 2470 | |
| 2471 | *DP = (*DP & ~mask) | signal_levels; |
| 2472 | } |
| 2473 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2474 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2475 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2476 | uint32_t *DP, |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 2477 | uint8_t dp_train_pat) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2478 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 2479 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2480 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2481 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 2482 | enum port port = intel_dig_port->port; |
Jani Nikula | 2cdfe6c | 2013-10-04 15:08:48 +0300 | [diff] [blame] | 2483 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
| 2484 | int ret, len; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2485 | |
Paulo Zanoni | 22b8bf1 | 2013-02-18 19:00:23 -0300 | [diff] [blame] | 2486 | if (HAS_DDI(dev)) { |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2487 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2488 | |
| 2489 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
| 2490 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2491 | else |
| 2492 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2493 | |
| 2494 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2495 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2496 | case DP_TRAINING_PATTERN_DISABLE: |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2497 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
| 2498 | |
| 2499 | break; |
| 2500 | case DP_TRAINING_PATTERN_1: |
| 2501 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2502 | break; |
| 2503 | case DP_TRAINING_PATTERN_2: |
| 2504 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
| 2505 | break; |
| 2506 | case DP_TRAINING_PATTERN_3: |
| 2507 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
| 2508 | break; |
| 2509 | } |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 2510 | I915_WRITE(DP_TP_CTL(port), temp); |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2511 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2512 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2513 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2514 | |
| 2515 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2516 | case DP_TRAINING_PATTERN_DISABLE: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2517 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2518 | break; |
| 2519 | case DP_TRAINING_PATTERN_1: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2520 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2521 | break; |
| 2522 | case DP_TRAINING_PATTERN_2: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2523 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2524 | break; |
| 2525 | case DP_TRAINING_PATTERN_3: |
| 2526 | DRM_ERROR("DP training pattern 3 not supported\n"); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2527 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2528 | break; |
| 2529 | } |
| 2530 | |
| 2531 | } else { |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2532 | *DP &= ~DP_LINK_TRAIN_MASK; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2533 | |
| 2534 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2535 | case DP_TRAINING_PATTERN_DISABLE: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2536 | *DP |= DP_LINK_TRAIN_OFF; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2537 | break; |
| 2538 | case DP_TRAINING_PATTERN_1: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2539 | *DP |= DP_LINK_TRAIN_PAT_1; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2540 | break; |
| 2541 | case DP_TRAINING_PATTERN_2: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2542 | *DP |= DP_LINK_TRAIN_PAT_2; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2543 | break; |
| 2544 | case DP_TRAINING_PATTERN_3: |
| 2545 | DRM_ERROR("DP training pattern 3 not supported\n"); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2546 | *DP |= DP_LINK_TRAIN_PAT_2; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2547 | break; |
| 2548 | } |
| 2549 | } |
| 2550 | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2551 | I915_WRITE(intel_dp->output_reg, *DP); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2552 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2553 | |
Jani Nikula | 2cdfe6c | 2013-10-04 15:08:48 +0300 | [diff] [blame] | 2554 | buf[0] = dp_train_pat; |
| 2555 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2556 | DP_TRAINING_PATTERN_DISABLE) { |
Jani Nikula | 2cdfe6c | 2013-10-04 15:08:48 +0300 | [diff] [blame] | 2557 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
| 2558 | len = 1; |
| 2559 | } else { |
| 2560 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
| 2561 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
| 2562 | len = intel_dp->lane_count + 1; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2563 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2564 | |
Jani Nikula | 2cdfe6c | 2013-10-04 15:08:48 +0300 | [diff] [blame] | 2565 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, |
| 2566 | buf, len); |
| 2567 | |
| 2568 | return ret == len; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2569 | } |
| 2570 | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2571 | static bool |
| 2572 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
| 2573 | uint8_t dp_train_pat) |
| 2574 | { |
Jani Nikula | 953d22e | 2013-10-04 15:08:47 +0300 | [diff] [blame] | 2575 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2576 | intel_dp_set_signal_levels(intel_dp, DP); |
| 2577 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
| 2578 | } |
| 2579 | |
| 2580 | static bool |
| 2581 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
Jani Nikula | 0301b3a | 2013-10-15 09:36:08 +0300 | [diff] [blame] | 2582 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2583 | { |
| 2584 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2585 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2586 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2587 | int ret; |
| 2588 | |
| 2589 | intel_get_adjust_train(intel_dp, link_status); |
| 2590 | intel_dp_set_signal_levels(intel_dp, DP); |
| 2591 | |
| 2592 | I915_WRITE(intel_dp->output_reg, *DP); |
| 2593 | POSTING_READ(intel_dp->output_reg); |
| 2594 | |
| 2595 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, |
| 2596 | intel_dp->train_set, |
| 2597 | intel_dp->lane_count); |
| 2598 | |
| 2599 | return ret == intel_dp->lane_count; |
| 2600 | } |
| 2601 | |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2602 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
| 2603 | { |
| 2604 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2605 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2606 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2607 | enum port port = intel_dig_port->port; |
| 2608 | uint32_t val; |
| 2609 | |
| 2610 | if (!HAS_DDI(dev)) |
| 2611 | return; |
| 2612 | |
| 2613 | val = I915_READ(DP_TP_CTL(port)); |
| 2614 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2615 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
| 2616 | I915_WRITE(DP_TP_CTL(port), val); |
| 2617 | |
| 2618 | /* |
| 2619 | * On PORT_A we can have only eDP in SST mode. There the only reason |
| 2620 | * we need to set idle transmission mode is to work around a HW issue |
| 2621 | * where we enable the pipe while not in idle link-training mode. |
| 2622 | * In this case there is requirement to wait for a minimum number of |
| 2623 | * idle patterns to be sent. |
| 2624 | */ |
| 2625 | if (port == PORT_A) |
| 2626 | return; |
| 2627 | |
| 2628 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
| 2629 | 1)) |
| 2630 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
| 2631 | } |
| 2632 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2633 | /* Enable corresponding port and start training pattern 1 */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2634 | void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2635 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2636 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2637 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2638 | struct drm_device *dev = encoder->dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2639 | int i; |
| 2640 | uint8_t voltage; |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2641 | int voltage_tries, loop_tries; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2642 | uint32_t DP = intel_dp->DP; |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 2643 | uint8_t link_config[2]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2644 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 2645 | if (HAS_DDI(dev)) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2646 | intel_ddi_prepare_link_retrain(encoder); |
| 2647 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2648 | /* Write the link configuration data */ |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 2649 | link_config[0] = intel_dp->link_bw; |
| 2650 | link_config[1] = intel_dp->lane_count; |
| 2651 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 2652 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 2653 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); |
| 2654 | |
| 2655 | link_config[0] = 0; |
| 2656 | link_config[1] = DP_SET_ANSI_8B10B; |
| 2657 | intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2658 | |
| 2659 | DP |= DP_PORT_EN; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2660 | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2661 | /* clock recovery */ |
| 2662 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
| 2663 | DP_TRAINING_PATTERN_1 | |
| 2664 | DP_LINK_SCRAMBLING_DISABLE)) { |
| 2665 | DRM_ERROR("failed to enable link training\n"); |
| 2666 | return; |
| 2667 | } |
| 2668 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2669 | voltage = 0xff; |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2670 | voltage_tries = 0; |
| 2671 | loop_tries = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2672 | for (;;) { |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2673 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2674 | |
Daniel Vetter | a7c9655 | 2012-10-18 10:15:30 +0200 | [diff] [blame] | 2675 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2676 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 2677 | DRM_ERROR("failed to get link status\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2678 | break; |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2679 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2680 | |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 2681 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2682 | DRM_DEBUG_KMS("clock recovery OK\n"); |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2683 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2684 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2685 | |
| 2686 | /* Check to see if we've tried the max voltage */ |
| 2687 | for (i = 0; i < intel_dp->lane_count; i++) |
| 2688 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 2689 | break; |
Takashi Iwai | 3b4f819 | 2013-03-11 18:40:16 +0100 | [diff] [blame] | 2690 | if (i == intel_dp->lane_count) { |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2691 | ++loop_tries; |
| 2692 | if (loop_tries == 5) { |
Jani Nikula | 3def84b | 2013-10-05 16:13:56 +0300 | [diff] [blame] | 2693 | DRM_ERROR("too many full retries, give up\n"); |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2694 | break; |
| 2695 | } |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2696 | intel_dp_reset_link_train(intel_dp, &DP, |
| 2697 | DP_TRAINING_PATTERN_1 | |
| 2698 | DP_LINK_SCRAMBLING_DISABLE); |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2699 | voltage_tries = 0; |
| 2700 | continue; |
| 2701 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2702 | |
| 2703 | /* Check to see if we've tried the same voltage 5 times */ |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2704 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
Chris Wilson | 2477367 | 2012-09-26 16:48:30 +0100 | [diff] [blame] | 2705 | ++voltage_tries; |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2706 | if (voltage_tries == 5) { |
Jani Nikula | 3def84b | 2013-10-05 16:13:56 +0300 | [diff] [blame] | 2707 | DRM_ERROR("too many voltage retries, give up\n"); |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2708 | break; |
| 2709 | } |
| 2710 | } else |
| 2711 | voltage_tries = 0; |
| 2712 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2713 | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2714 | /* Update training set as requested by target */ |
| 2715 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
| 2716 | DRM_ERROR("failed to update link training\n"); |
| 2717 | break; |
| 2718 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2719 | } |
| 2720 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2721 | intel_dp->DP = DP; |
| 2722 | } |
| 2723 | |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2724 | void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2725 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
| 2726 | { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2727 | bool channel_eq = false; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2728 | int tries, cr_tries; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2729 | uint32_t DP = intel_dp->DP; |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 2730 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
| 2731 | |
| 2732 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ |
| 2733 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) |
| 2734 | training_pattern = DP_TRAINING_PATTERN_3; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2735 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2736 | /* channel equalization */ |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2737 | if (!intel_dp_set_link_train(intel_dp, &DP, |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 2738 | training_pattern | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2739 | DP_LINK_SCRAMBLING_DISABLE)) { |
| 2740 | DRM_ERROR("failed to start channel equalization\n"); |
| 2741 | return; |
| 2742 | } |
| 2743 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2744 | tries = 0; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2745 | cr_tries = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2746 | channel_eq = false; |
| 2747 | for (;;) { |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2748 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2749 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2750 | if (cr_tries > 5) { |
| 2751 | DRM_ERROR("failed to train DP, aborting\n"); |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2752 | break; |
| 2753 | } |
| 2754 | |
Daniel Vetter | a7c9655 | 2012-10-18 10:15:30 +0200 | [diff] [blame] | 2755 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2756 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 2757 | DRM_ERROR("failed to get link status\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2758 | break; |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2759 | } |
Jesse Barnes | 869184a | 2010-10-07 16:01:22 -0700 | [diff] [blame] | 2760 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2761 | /* Make sure clock is still ok */ |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 2762 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2763 | intel_dp_start_link_train(intel_dp); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2764 | intel_dp_set_link_train(intel_dp, &DP, |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 2765 | training_pattern | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2766 | DP_LINK_SCRAMBLING_DISABLE); |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2767 | cr_tries++; |
| 2768 | continue; |
| 2769 | } |
| 2770 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 2771 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2772 | channel_eq = true; |
| 2773 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2774 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2775 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2776 | /* Try 5 times, then try clock recovery if that fails */ |
| 2777 | if (tries > 5) { |
| 2778 | intel_dp_link_down(intel_dp); |
| 2779 | intel_dp_start_link_train(intel_dp); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2780 | intel_dp_set_link_train(intel_dp, &DP, |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 2781 | training_pattern | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2782 | DP_LINK_SCRAMBLING_DISABLE); |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2783 | tries = 0; |
| 2784 | cr_tries++; |
| 2785 | continue; |
| 2786 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2787 | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2788 | /* Update training set as requested by target */ |
| 2789 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
| 2790 | DRM_ERROR("failed to update link training\n"); |
| 2791 | break; |
| 2792 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2793 | ++tries; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2794 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2795 | |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2796 | intel_dp_set_idle_link_train(intel_dp); |
| 2797 | |
| 2798 | intel_dp->DP = DP; |
| 2799 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2800 | if (channel_eq) |
Masanari Iida | 07f4225 | 2013-03-20 11:00:34 +0900 | [diff] [blame] | 2801 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2802 | |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2803 | } |
| 2804 | |
| 2805 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
| 2806 | { |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2807 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2808 | DP_TRAINING_PATTERN_DISABLE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2809 | } |
| 2810 | |
| 2811 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2812 | intel_dp_link_down(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2813 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2814 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2815 | enum port port = intel_dig_port->port; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2816 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2817 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | ab527ef | 2012-11-29 15:59:33 +0100 | [diff] [blame] | 2818 | struct intel_crtc *intel_crtc = |
| 2819 | to_intel_crtc(intel_dig_port->base.base.crtc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2820 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2821 | |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2822 | /* |
| 2823 | * DDI code has a strict mode set sequence and we should try to respect |
| 2824 | * it, otherwise we might hang the machine in many different ways. So we |
| 2825 | * really should be disabling the port only on a complete crtc_disable |
| 2826 | * sequence. This function is just called under two conditions on DDI |
| 2827 | * code: |
| 2828 | * - Link train failed while doing crtc_enable, and on this case we |
| 2829 | * really should respect the mode set sequence and wait for a |
| 2830 | * crtc_disable. |
| 2831 | * - Someone turned the monitor off and intel_dp_check_link_status |
| 2832 | * called us. We don't need to disable the whole port on this case, so |
| 2833 | * when someone turns the monitor on again, |
| 2834 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
| 2835 | * train. |
| 2836 | */ |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 2837 | if (HAS_DDI(dev)) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2838 | return; |
| 2839 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 2840 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 2841 | return; |
| 2842 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2843 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2844 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2845 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2846 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2847 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2848 | } else { |
| 2849 | DP &= ~DP_LINK_TRAIN_MASK; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2850 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2851 | } |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 2852 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2853 | |
Daniel Vetter | ab527ef | 2012-11-29 15:59:33 +0100 | [diff] [blame] | 2854 | /* We don't really know why we're doing this */ |
| 2855 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2856 | |
Daniel Vetter | 493a708 | 2012-05-30 12:31:56 +0200 | [diff] [blame] | 2857 | if (HAS_PCH_IBX(dev) && |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 2858 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2859 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 2860 | |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 2861 | /* Hardware workaround: leaving our transcoder select |
| 2862 | * set to transcoder B while it's off will prevent the |
| 2863 | * corresponding HDMI output on transcoder A. |
| 2864 | * |
| 2865 | * Combine this with another hardware workaround: |
| 2866 | * transcoder select bit can only be cleared while the |
| 2867 | * port is enabled. |
| 2868 | */ |
| 2869 | DP &= ~DP_PIPEB_SELECT; |
| 2870 | I915_WRITE(intel_dp->output_reg, DP); |
| 2871 | |
| 2872 | /* Changes to enable or select take place the vblank |
| 2873 | * after being written. |
| 2874 | */ |
Daniel Vetter | ff50afe | 2012-11-29 15:59:34 +0100 | [diff] [blame] | 2875 | if (WARN_ON(crtc == NULL)) { |
| 2876 | /* We should never try to disable a port without a crtc |
| 2877 | * attached. For paranoia keep the code around for a |
| 2878 | * bit. */ |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 2879 | POSTING_READ(intel_dp->output_reg); |
| 2880 | msleep(50); |
| 2881 | } else |
Daniel Vetter | ab527ef | 2012-11-29 15:59:33 +0100 | [diff] [blame] | 2882 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 2883 | } |
| 2884 | |
Wu Fengguang | 832afda | 2011-12-09 20:42:21 +0800 | [diff] [blame] | 2885 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2886 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 2887 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2888 | msleep(intel_dp->panel_power_down_delay); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2889 | } |
| 2890 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2891 | static bool |
| 2892 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2893 | { |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2894 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2895 | struct drm_device *dev = dig_port->base.base.dev; |
| 2896 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2897 | |
Damien Lespiau | 577c7a5 | 2012-12-13 16:09:02 +0000 | [diff] [blame] | 2898 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
| 2899 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2900 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 2901 | sizeof(intel_dp->dpcd)) == 0) |
| 2902 | return false; /* aux transfer failed */ |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2903 | |
Damien Lespiau | 577c7a5 | 2012-12-13 16:09:02 +0000 | [diff] [blame] | 2904 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
| 2905 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
| 2906 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
| 2907 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 2908 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
| 2909 | return false; /* DPCD not present */ |
| 2910 | |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 2911 | /* Check if the panel supports PSR */ |
| 2912 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 2913 | if (is_edp(intel_dp)) { |
| 2914 | intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, |
| 2915 | intel_dp->psr_dpcd, |
| 2916 | sizeof(intel_dp->psr_dpcd)); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2917 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
| 2918 | dev_priv->psr.sink_support = true; |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 2919 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2920 | } |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 2921 | } |
| 2922 | |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 2923 | /* Training Pattern 3 support */ |
| 2924 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && |
| 2925 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { |
| 2926 | intel_dp->use_tps3 = true; |
| 2927 | DRM_DEBUG_KMS("Displayport TPS3 supported"); |
| 2928 | } else |
| 2929 | intel_dp->use_tps3 = false; |
| 2930 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 2931 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 2932 | DP_DWN_STRM_PORT_PRESENT)) |
| 2933 | return true; /* native DP sink */ |
| 2934 | |
| 2935 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
| 2936 | return true; /* no per-port downstream info */ |
| 2937 | |
| 2938 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, |
| 2939 | intel_dp->downstream_ports, |
| 2940 | DP_MAX_DOWNSTREAM_PORTS) == 0) |
| 2941 | return false; /* downstream port status fetch failed */ |
| 2942 | |
| 2943 | return true; |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2944 | } |
| 2945 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2946 | static void |
| 2947 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
| 2948 | { |
| 2949 | u8 buf[3]; |
| 2950 | |
| 2951 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 2952 | return; |
| 2953 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2954 | edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 351cfc3 | 2012-06-12 13:20:47 +0200 | [diff] [blame] | 2955 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2956 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
| 2957 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 2958 | buf[0], buf[1], buf[2]); |
| 2959 | |
| 2960 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) |
| 2961 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 2962 | buf[0], buf[1], buf[2]); |
Daniel Vetter | 351cfc3 | 2012-06-12 13:20:47 +0200 | [diff] [blame] | 2963 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2964 | edp_panel_vdd_off(intel_dp, false); |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2965 | } |
| 2966 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 2967 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
| 2968 | { |
| 2969 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2970 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2971 | struct intel_crtc *intel_crtc = |
| 2972 | to_intel_crtc(intel_dig_port->base.base.crtc); |
| 2973 | u8 buf[1]; |
| 2974 | |
| 2975 | if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1)) |
| 2976 | return -EAGAIN; |
| 2977 | |
| 2978 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) |
| 2979 | return -ENOTTY; |
| 2980 | |
| 2981 | if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, |
| 2982 | DP_TEST_SINK_START)) |
| 2983 | return -EAGAIN; |
| 2984 | |
| 2985 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ |
| 2986 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 2987 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 2988 | |
| 2989 | if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6)) |
| 2990 | return -EAGAIN; |
| 2991 | |
| 2992 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0); |
| 2993 | return 0; |
| 2994 | } |
| 2995 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2996 | static bool |
| 2997 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 2998 | { |
| 2999 | int ret; |
| 3000 | |
| 3001 | ret = intel_dp_aux_native_read_retry(intel_dp, |
| 3002 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 3003 | sink_irq_vector, 1); |
| 3004 | if (!ret) |
| 3005 | return false; |
| 3006 | |
| 3007 | return true; |
| 3008 | } |
| 3009 | |
| 3010 | static void |
| 3011 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
| 3012 | { |
| 3013 | /* NAK by default */ |
Daniel Vetter | 9324cf7 | 2012-10-20 21:13:05 +0200 | [diff] [blame] | 3014 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3015 | } |
| 3016 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3017 | /* |
| 3018 | * According to DP spec |
| 3019 | * 5.1.2: |
| 3020 | * 1. Read DPCD |
| 3021 | * 2. Configure link according to Receiver Capabilities |
| 3022 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 3023 | * 4. Check link status on receipt of hot-plug interrupt |
| 3024 | */ |
| 3025 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 3026 | void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3027 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3028 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3029 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3030 | u8 sink_irq_vector; |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 3031 | u8 link_status[DP_LINK_STATUS_SIZE]; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3032 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3033 | if (!intel_encoder->connectors_active) |
Keith Packard | d2b996a | 2011-07-25 22:37:51 -0700 | [diff] [blame] | 3034 | return; |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 3035 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3036 | if (WARN_ON(!intel_encoder->base.crtc)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3037 | return; |
| 3038 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3039 | /* Try to read receiver status if the link appears to be up */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 3040 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3041 | return; |
| 3042 | } |
| 3043 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3044 | /* Now read the DPCD to see if it's actually running */ |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3045 | if (!intel_dp_get_dpcd(intel_dp)) { |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 3046 | return; |
| 3047 | } |
| 3048 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3049 | /* Try to read the source of the interrupt */ |
| 3050 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 3051 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 3052 | /* Clear interrupt source */ |
| 3053 | intel_dp_aux_native_write_1(intel_dp, |
| 3054 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 3055 | sink_irq_vector); |
| 3056 | |
| 3057 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 3058 | intel_dp_handle_test_request(intel_dp); |
| 3059 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 3060 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 3061 | } |
| 3062 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 3063 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3064 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3065 | drm_get_encoder_name(&intel_encoder->base)); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 3066 | intel_dp_start_link_train(intel_dp); |
| 3067 | intel_dp_complete_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 3068 | intel_dp_stop_link_train(intel_dp); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 3069 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3070 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3071 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3072 | /* XXX this is probably wrong for multiple downstream ports */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3073 | static enum drm_connector_status |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3074 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 3075 | { |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3076 | uint8_t *dpcd = intel_dp->dpcd; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3077 | uint8_t type; |
| 3078 | |
| 3079 | if (!intel_dp_get_dpcd(intel_dp)) |
| 3080 | return connector_status_disconnected; |
| 3081 | |
| 3082 | /* if there's no downstream port, we're done */ |
| 3083 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3084 | return connector_status_connected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3085 | |
| 3086 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 3087 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 3088 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
Adam Jackson | 2323517 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 3089 | uint8_t reg; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3090 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
Adam Jackson | 2323517 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 3091 | ®, 1)) |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3092 | return connector_status_unknown; |
Adam Jackson | 2323517 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 3093 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
| 3094 | : connector_status_disconnected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3095 | } |
| 3096 | |
| 3097 | /* If no HPD, poke DDC gently */ |
| 3098 | if (drm_probe_ddc(&intel_dp->adapter)) |
| 3099 | return connector_status_connected; |
| 3100 | |
| 3101 | /* Well we tried, say unknown for unreliable port types */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 3102 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
| 3103 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 3104 | if (type == DP_DS_PORT_TYPE_VGA || |
| 3105 | type == DP_DS_PORT_TYPE_NON_EDID) |
| 3106 | return connector_status_unknown; |
| 3107 | } else { |
| 3108 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 3109 | DP_DWN_STRM_PORT_TYPE_MASK; |
| 3110 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
| 3111 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
| 3112 | return connector_status_unknown; |
| 3113 | } |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3114 | |
| 3115 | /* Anything else is out of spec, warn and ignore */ |
| 3116 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3117 | return connector_status_disconnected; |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 3118 | } |
| 3119 | |
| 3120 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3121 | ironlake_dp_detect(struct intel_dp *intel_dp) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3122 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 3123 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Damien Lespiau | 1b46963 | 2012-12-13 16:09:01 +0000 | [diff] [blame] | 3124 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3125 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3126 | enum drm_connector_status status; |
| 3127 | |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 3128 | /* Can't disconnect eDP, but you can close the lid... */ |
| 3129 | if (is_edp(intel_dp)) { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 3130 | status = intel_panel_detect(dev); |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 3131 | if (status == connector_status_unknown) |
| 3132 | status = connector_status_connected; |
| 3133 | return status; |
| 3134 | } |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 3135 | |
Damien Lespiau | 1b46963 | 2012-12-13 16:09:01 +0000 | [diff] [blame] | 3136 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
| 3137 | return connector_status_disconnected; |
| 3138 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3139 | return intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3140 | } |
| 3141 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3142 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3143 | g4x_dp_detect(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3144 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 3145 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3146 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 34f2be4 | 2013-01-24 15:29:27 +0200 | [diff] [blame] | 3147 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 3148 | uint32_t bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3149 | |
Jesse Barnes | 35aad75 | 2013-03-01 13:14:31 -0800 | [diff] [blame] | 3150 | /* Can't disconnect eDP, but you can close the lid... */ |
| 3151 | if (is_edp(intel_dp)) { |
| 3152 | enum drm_connector_status status; |
| 3153 | |
| 3154 | status = intel_panel_detect(dev); |
| 3155 | if (status == connector_status_unknown) |
| 3156 | status = connector_status_connected; |
| 3157 | return status; |
| 3158 | } |
| 3159 | |
Todd Previte | 232a6ee | 2014-01-23 00:13:41 -0700 | [diff] [blame] | 3160 | if (IS_VALLEYVIEW(dev)) { |
| 3161 | switch (intel_dig_port->port) { |
| 3162 | case PORT_B: |
| 3163 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; |
| 3164 | break; |
| 3165 | case PORT_C: |
| 3166 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; |
| 3167 | break; |
| 3168 | case PORT_D: |
| 3169 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
| 3170 | break; |
| 3171 | default: |
| 3172 | return connector_status_unknown; |
| 3173 | } |
| 3174 | } else { |
| 3175 | switch (intel_dig_port->port) { |
| 3176 | case PORT_B: |
| 3177 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
| 3178 | break; |
| 3179 | case PORT_C: |
| 3180 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
| 3181 | break; |
| 3182 | case PORT_D: |
| 3183 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
| 3184 | break; |
| 3185 | default: |
| 3186 | return connector_status_unknown; |
| 3187 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3188 | } |
| 3189 | |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 3190 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3191 | return connector_status_disconnected; |
| 3192 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3193 | return intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3194 | } |
| 3195 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3196 | static struct edid * |
| 3197 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
| 3198 | { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3199 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3200 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3201 | /* use cached edid if we have one */ |
| 3202 | if (intel_connector->edid) { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3203 | /* invalid edid */ |
| 3204 | if (IS_ERR(intel_connector->edid)) |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 3205 | return NULL; |
| 3206 | |
Jani Nikula | 55e9ede | 2013-10-01 10:38:54 +0300 | [diff] [blame] | 3207 | return drm_edid_duplicate(intel_connector->edid); |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 3208 | } |
| 3209 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3210 | return drm_get_edid(connector, adapter); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3211 | } |
| 3212 | |
| 3213 | static int |
| 3214 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
| 3215 | { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3216 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3217 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3218 | /* use cached edid if we have one */ |
| 3219 | if (intel_connector->edid) { |
| 3220 | /* invalid edid */ |
| 3221 | if (IS_ERR(intel_connector->edid)) |
| 3222 | return 0; |
| 3223 | |
| 3224 | return intel_connector_update_modes(connector, |
| 3225 | intel_connector->edid); |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 3226 | } |
| 3227 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3228 | return intel_ddc_get_modes(connector, adapter); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3229 | } |
| 3230 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3231 | static enum drm_connector_status |
| 3232 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 3233 | { |
| 3234 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 3235 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3236 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3237 | struct drm_device *dev = connector->dev; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3238 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3239 | enum drm_connector_status status; |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3240 | enum intel_display_power_domain power_domain; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3241 | struct edid *edid = NULL; |
| 3242 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3243 | intel_runtime_pm_get(dev_priv); |
| 3244 | |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3245 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 3246 | intel_display_power_get(dev_priv, power_domain); |
| 3247 | |
Chris Wilson | 164c859 | 2013-07-20 20:27:08 +0100 | [diff] [blame] | 3248 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 3249 | connector->base.id, drm_get_connector_name(connector)); |
| 3250 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3251 | intel_dp->has_audio = false; |
| 3252 | |
| 3253 | if (HAS_PCH_SPLIT(dev)) |
| 3254 | status = ironlake_dp_detect(intel_dp); |
| 3255 | else |
| 3256 | status = g4x_dp_detect(intel_dp); |
Adam Jackson | 1b9be9d | 2011-07-12 17:38:01 -0400 | [diff] [blame] | 3257 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3258 | if (status != connector_status_connected) |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3259 | goto out; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3260 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3261 | intel_dp_probe_oui(intel_dp); |
| 3262 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 3263 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
| 3264 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3265 | } else { |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3266 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3267 | if (edid) { |
| 3268 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3269 | kfree(edid); |
| 3270 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3271 | } |
| 3272 | |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 3273 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 3274 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3275 | status = connector_status_connected; |
| 3276 | |
| 3277 | out: |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3278 | intel_display_power_put(dev_priv, power_domain); |
| 3279 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3280 | intel_runtime_pm_put(dev_priv); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3281 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3282 | return status; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3283 | } |
| 3284 | |
| 3285 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 3286 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 3287 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3288 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3289 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 3290 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3291 | struct drm_device *dev = connector->dev; |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3292 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3293 | enum intel_display_power_domain power_domain; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3294 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3295 | |
| 3296 | /* We should parse the EDID data and find out if it has an audio sink |
| 3297 | */ |
| 3298 | |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3299 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 3300 | intel_display_power_get(dev_priv, power_domain); |
| 3301 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3302 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3303 | intel_display_power_put(dev_priv, power_domain); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3304 | if (ret) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3305 | return ret; |
| 3306 | |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3307 | /* if eDP has no EDID, fall back to fixed mode */ |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 3308 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3309 | struct drm_display_mode *mode; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 3310 | mode = drm_mode_duplicate(dev, |
| 3311 | intel_connector->panel.fixed_mode); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3312 | if (mode) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3313 | drm_mode_probed_add(connector, mode); |
| 3314 | return 1; |
| 3315 | } |
| 3316 | } |
| 3317 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3318 | } |
| 3319 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3320 | static bool |
| 3321 | intel_dp_detect_audio(struct drm_connector *connector) |
| 3322 | { |
| 3323 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3324 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3325 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 3326 | struct drm_device *dev = connector->dev; |
| 3327 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3328 | enum intel_display_power_domain power_domain; |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3329 | struct edid *edid; |
| 3330 | bool has_audio = false; |
| 3331 | |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3332 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 3333 | intel_display_power_get(dev_priv, power_domain); |
| 3334 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3335 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3336 | if (edid) { |
| 3337 | has_audio = drm_detect_monitor_audio(edid); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3338 | kfree(edid); |
| 3339 | } |
| 3340 | |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3341 | intel_display_power_put(dev_priv, power_domain); |
| 3342 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3343 | return has_audio; |
| 3344 | } |
| 3345 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3346 | static int |
| 3347 | intel_dp_set_property(struct drm_connector *connector, |
| 3348 | struct drm_property *property, |
| 3349 | uint64_t val) |
| 3350 | { |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 3351 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3352 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3353 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
| 3354 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3355 | int ret; |
| 3356 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 3357 | ret = drm_object_property_set_value(&connector->base, property, val); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3358 | if (ret) |
| 3359 | return ret; |
| 3360 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 3361 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3362 | int i = val; |
| 3363 | bool has_audio; |
| 3364 | |
| 3365 | if (i == intel_dp->force_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3366 | return 0; |
| 3367 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3368 | intel_dp->force_audio = i; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3369 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 3370 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3371 | has_audio = intel_dp_detect_audio(connector); |
| 3372 | else |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 3373 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3374 | |
| 3375 | if (has_audio == intel_dp->has_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3376 | return 0; |
| 3377 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3378 | intel_dp->has_audio = has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3379 | goto done; |
| 3380 | } |
| 3381 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 3382 | if (property == dev_priv->broadcast_rgb_property) { |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 3383 | bool old_auto = intel_dp->color_range_auto; |
| 3384 | uint32_t old_range = intel_dp->color_range; |
| 3385 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 3386 | switch (val) { |
| 3387 | case INTEL_BROADCAST_RGB_AUTO: |
| 3388 | intel_dp->color_range_auto = true; |
| 3389 | break; |
| 3390 | case INTEL_BROADCAST_RGB_FULL: |
| 3391 | intel_dp->color_range_auto = false; |
| 3392 | intel_dp->color_range = 0; |
| 3393 | break; |
| 3394 | case INTEL_BROADCAST_RGB_LIMITED: |
| 3395 | intel_dp->color_range_auto = false; |
| 3396 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
| 3397 | break; |
| 3398 | default: |
| 3399 | return -EINVAL; |
| 3400 | } |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 3401 | |
| 3402 | if (old_auto == intel_dp->color_range_auto && |
| 3403 | old_range == intel_dp->color_range) |
| 3404 | return 0; |
| 3405 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 3406 | goto done; |
| 3407 | } |
| 3408 | |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3409 | if (is_edp(intel_dp) && |
| 3410 | property == connector->dev->mode_config.scaling_mode_property) { |
| 3411 | if (val == DRM_MODE_SCALE_NONE) { |
| 3412 | DRM_DEBUG_KMS("no scaling not supported\n"); |
| 3413 | return -EINVAL; |
| 3414 | } |
| 3415 | |
| 3416 | if (intel_connector->panel.fitting_mode == val) { |
| 3417 | /* the eDP scaling property is not changed */ |
| 3418 | return 0; |
| 3419 | } |
| 3420 | intel_connector->panel.fitting_mode = val; |
| 3421 | |
| 3422 | goto done; |
| 3423 | } |
| 3424 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3425 | return -EINVAL; |
| 3426 | |
| 3427 | done: |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 3428 | if (intel_encoder->base.crtc) |
| 3429 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3430 | |
| 3431 | return 0; |
| 3432 | } |
| 3433 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3434 | static void |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 3435 | intel_dp_connector_destroy(struct drm_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3436 | { |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 3437 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 3438 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3439 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
| 3440 | kfree(intel_connector->edid); |
| 3441 | |
Paulo Zanoni | acd8db10 | 2013-06-12 17:27:23 -0300 | [diff] [blame] | 3442 | /* Can't call is_edp() since the encoder may have been destroyed |
| 3443 | * already. */ |
| 3444 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 3445 | intel_panel_fini(&intel_connector->panel); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 3446 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3447 | drm_connector_cleanup(connector); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 3448 | kfree(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3449 | } |
| 3450 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 3451 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 3452 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3453 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
| 3454 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Daniel Vetter | bd17381 | 2013-03-25 11:24:10 +0100 | [diff] [blame] | 3455 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 3456 | |
| 3457 | i2c_del_adapter(&intel_dp->adapter); |
| 3458 | drm_encoder_cleanup(encoder); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 3459 | if (is_edp(intel_dp)) { |
| 3460 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Daniel Vetter | bd17381 | 2013-03-25 11:24:10 +0100 | [diff] [blame] | 3461 | mutex_lock(&dev->mode_config.mutex); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 3462 | edp_panel_vdd_off_sync(intel_dp); |
Daniel Vetter | bd17381 | 2013-03-25 11:24:10 +0100 | [diff] [blame] | 3463 | mutex_unlock(&dev->mode_config.mutex); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 3464 | } |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3465 | kfree(intel_dig_port); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 3466 | } |
| 3467 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3468 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 3469 | .dpms = intel_connector_dpms, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3470 | .detect = intel_dp_detect, |
| 3471 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3472 | .set_property = intel_dp_set_property, |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 3473 | .destroy = intel_dp_connector_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3474 | }; |
| 3475 | |
| 3476 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 3477 | .get_modes = intel_dp_get_modes, |
| 3478 | .mode_valid = intel_dp_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 3479 | .best_encoder = intel_best_encoder, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3480 | }; |
| 3481 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3482 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 3483 | .destroy = intel_dp_encoder_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3484 | }; |
| 3485 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3486 | static void |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 3487 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 3488 | { |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3489 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 3490 | |
Jesse Barnes | 885a501 | 2011-07-07 11:11:01 -0700 | [diff] [blame] | 3491 | intel_dp_check_link_status(intel_dp); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 3492 | } |
| 3493 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3494 | /* Return which DP Port should be selected for Transcoder DP control */ |
| 3495 | int |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3496 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3497 | { |
| 3498 | struct drm_device *dev = crtc->dev; |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3499 | struct intel_encoder *intel_encoder; |
| 3500 | struct intel_dp *intel_dp; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3501 | |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3502 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
| 3503 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3504 | |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3505 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 3506 | intel_encoder->type == INTEL_OUTPUT_EDP) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3507 | return intel_dp->output_reg; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3508 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3509 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3510 | return -1; |
| 3511 | } |
| 3512 | |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3513 | /* check the VBT to see whether the eDP is on DP-D port */ |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 3514 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3515 | { |
| 3516 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 3517 | union child_device_config *p_child; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3518 | int i; |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 3519 | static const short port_mapping[] = { |
| 3520 | [PORT_B] = PORT_IDPB, |
| 3521 | [PORT_C] = PORT_IDPC, |
| 3522 | [PORT_D] = PORT_IDPD, |
| 3523 | }; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3524 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 3525 | if (port == PORT_A) |
| 3526 | return true; |
| 3527 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 3528 | if (!dev_priv->vbt.child_dev_num) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3529 | return false; |
| 3530 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 3531 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
| 3532 | p_child = dev_priv->vbt.child_dev + i; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3533 | |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 3534 | if (p_child->common.dvo_port == port_mapping[port] && |
Ville Syrjälä | f02586d | 2013-11-01 20:32:08 +0200 | [diff] [blame] | 3535 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
| 3536 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3537 | return true; |
| 3538 | } |
| 3539 | return false; |
| 3540 | } |
| 3541 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3542 | static void |
| 3543 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 3544 | { |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3545 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 3546 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 3547 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 3548 | intel_attach_broadcast_rgb_property(connector); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 3549 | intel_dp->color_range_auto = true; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3550 | |
| 3551 | if (is_edp(intel_dp)) { |
| 3552 | drm_mode_create_scaling_mode_property(connector->dev); |
Rob Clark | 6de6d84 | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 3553 | drm_object_attach_property( |
| 3554 | &connector->base, |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3555 | connector->dev->mode_config.scaling_mode_property, |
Yuly Novikov | 8e740cd | 2012-10-26 12:04:01 +0300 | [diff] [blame] | 3556 | DRM_MODE_SCALE_ASPECT); |
| 3557 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3558 | } |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3559 | } |
| 3560 | |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 3561 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
| 3562 | { |
| 3563 | intel_dp->last_power_cycle = jiffies; |
| 3564 | intel_dp->last_power_on = jiffies; |
| 3565 | intel_dp->last_backlight_off = jiffies; |
| 3566 | } |
| 3567 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3568 | static void |
| 3569 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3570 | struct intel_dp *intel_dp, |
| 3571 | struct edp_power_seq *out) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3572 | { |
| 3573 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3574 | struct edp_power_seq cur, vbt, spec, final; |
| 3575 | u32 pp_on, pp_off, pp_div, pp; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3576 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3577 | |
| 3578 | if (HAS_PCH_SPLIT(dev)) { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3579 | pp_ctrl_reg = PCH_PP_CONTROL; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3580 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 3581 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 3582 | pp_div_reg = PCH_PP_DIVISOR; |
| 3583 | } else { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3584 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 3585 | |
| 3586 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 3587 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 3588 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 3589 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3590 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3591 | |
| 3592 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
| 3593 | * the very first thing. */ |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3594 | pp = ironlake_get_pp_control(intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3595 | I915_WRITE(pp_ctrl_reg, pp); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3596 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3597 | pp_on = I915_READ(pp_on_reg); |
| 3598 | pp_off = I915_READ(pp_off_reg); |
| 3599 | pp_div = I915_READ(pp_div_reg); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3600 | |
| 3601 | /* Pull timing values out of registers */ |
| 3602 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 3603 | PANEL_POWER_UP_DELAY_SHIFT; |
| 3604 | |
| 3605 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 3606 | PANEL_LIGHT_ON_DELAY_SHIFT; |
| 3607 | |
| 3608 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 3609 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
| 3610 | |
| 3611 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 3612 | PANEL_POWER_DOWN_DELAY_SHIFT; |
| 3613 | |
| 3614 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
| 3615 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
| 3616 | |
| 3617 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 3618 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
| 3619 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 3620 | vbt = dev_priv->vbt.edp_pps; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3621 | |
| 3622 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
| 3623 | * our hw here, which are all in 100usec. */ |
| 3624 | spec.t1_t3 = 210 * 10; |
| 3625 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
| 3626 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
| 3627 | spec.t10 = 500 * 10; |
| 3628 | /* This one is special and actually in units of 100ms, but zero |
| 3629 | * based in the hw (so we need to add 100 ms). But the sw vbt |
| 3630 | * table multiplies it with 1000 to make it in units of 100usec, |
| 3631 | * too. */ |
| 3632 | spec.t11_t12 = (510 + 100) * 10; |
| 3633 | |
| 3634 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 3635 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
| 3636 | |
| 3637 | /* Use the max of the register settings and vbt. If both are |
| 3638 | * unset, fall back to the spec limits. */ |
| 3639 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
| 3640 | spec.field : \ |
| 3641 | max(cur.field, vbt.field)) |
| 3642 | assign_final(t1_t3); |
| 3643 | assign_final(t8); |
| 3644 | assign_final(t9); |
| 3645 | assign_final(t10); |
| 3646 | assign_final(t11_t12); |
| 3647 | #undef assign_final |
| 3648 | |
| 3649 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
| 3650 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 3651 | intel_dp->backlight_on_delay = get_delay(t8); |
| 3652 | intel_dp->backlight_off_delay = get_delay(t9); |
| 3653 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 3654 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 3655 | #undef get_delay |
| 3656 | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3657 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 3658 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 3659 | intel_dp->panel_power_cycle_delay); |
| 3660 | |
| 3661 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 3662 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
| 3663 | |
| 3664 | if (out) |
| 3665 | *out = final; |
| 3666 | } |
| 3667 | |
| 3668 | static void |
| 3669 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
| 3670 | struct intel_dp *intel_dp, |
| 3671 | struct edp_power_seq *seq) |
| 3672 | { |
| 3673 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3674 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
| 3675 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
| 3676 | int pp_on_reg, pp_off_reg, pp_div_reg; |
| 3677 | |
| 3678 | if (HAS_PCH_SPLIT(dev)) { |
| 3679 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 3680 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 3681 | pp_div_reg = PCH_PP_DIVISOR; |
| 3682 | } else { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3683 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 3684 | |
| 3685 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 3686 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 3687 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3688 | } |
| 3689 | |
Paulo Zanoni | b2f19d1 | 2013-12-19 14:29:44 -0200 | [diff] [blame] | 3690 | /* |
| 3691 | * And finally store the new values in the power sequencer. The |
| 3692 | * backlight delays are set to 1 because we do manual waits on them. For |
| 3693 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
| 3694 | * we'll end up waiting for the backlight off delay twice: once when we |
| 3695 | * do the manual sleep, and once when we disable the panel and wait for |
| 3696 | * the PP_STATUS bit to become zero. |
| 3697 | */ |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3698 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
Paulo Zanoni | b2f19d1 | 2013-12-19 14:29:44 -0200 | [diff] [blame] | 3699 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
| 3700 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3701 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3702 | /* Compute the divisor for the pp clock, simply match the Bspec |
| 3703 | * formula. */ |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3704 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3705 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3706 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
| 3707 | |
| 3708 | /* Haswell doesn't have any port selection bits for the panel |
| 3709 | * power sequencer any more. */ |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3710 | if (IS_VALLEYVIEW(dev)) { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3711 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
| 3712 | port_sel = PANEL_PORT_SELECT_DPB_VLV; |
| 3713 | else |
| 3714 | port_sel = PANEL_PORT_SELECT_DPC_VLV; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3715 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
| 3716 | if (dp_to_dig_port(intel_dp)->port == PORT_A) |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 3717 | port_sel = PANEL_PORT_SELECT_DPA; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3718 | else |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 3719 | port_sel = PANEL_PORT_SELECT_DPD; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3720 | } |
| 3721 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3722 | pp_on |= port_sel; |
| 3723 | |
| 3724 | I915_WRITE(pp_on_reg, pp_on); |
| 3725 | I915_WRITE(pp_off_reg, pp_off); |
| 3726 | I915_WRITE(pp_div_reg, pp_div); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3727 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3728 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3729 | I915_READ(pp_on_reg), |
| 3730 | I915_READ(pp_off_reg), |
| 3731 | I915_READ(pp_div_reg)); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 3732 | } |
| 3733 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 3734 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 3735 | struct intel_connector *intel_connector, |
| 3736 | struct edp_power_seq *power_seq) |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 3737 | { |
| 3738 | struct drm_connector *connector = &intel_connector->base; |
| 3739 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3740 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3741 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3742 | struct drm_display_mode *fixed_mode = NULL; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 3743 | bool has_dpcd; |
| 3744 | struct drm_display_mode *scan; |
| 3745 | struct edid *edid; |
| 3746 | |
| 3747 | if (!is_edp(intel_dp)) |
| 3748 | return true; |
| 3749 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 3750 | /* Cache DPCD and EDID for edp. */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 3751 | edp_panel_vdd_on(intel_dp); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 3752 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 3753 | edp_panel_vdd_off(intel_dp, false); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 3754 | |
| 3755 | if (has_dpcd) { |
| 3756 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 3757 | dev_priv->no_aux_handshake = |
| 3758 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
| 3759 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 3760 | } else { |
| 3761 | /* if this fails, presume the device is a ghost */ |
| 3762 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 3763 | return false; |
| 3764 | } |
| 3765 | |
| 3766 | /* We now know it's not a ghost, init power sequence regs. */ |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 3767 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 3768 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 3769 | edid = drm_get_edid(connector, &intel_dp->adapter); |
| 3770 | if (edid) { |
| 3771 | if (drm_add_edid_modes(connector, edid)) { |
| 3772 | drm_mode_connector_update_edid_property(connector, |
| 3773 | edid); |
| 3774 | drm_edid_to_eld(connector, edid); |
| 3775 | } else { |
| 3776 | kfree(edid); |
| 3777 | edid = ERR_PTR(-EINVAL); |
| 3778 | } |
| 3779 | } else { |
| 3780 | edid = ERR_PTR(-ENOENT); |
| 3781 | } |
| 3782 | intel_connector->edid = edid; |
| 3783 | |
| 3784 | /* prefer fixed mode from EDID if available */ |
| 3785 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 3786 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 3787 | fixed_mode = drm_mode_duplicate(dev, scan); |
| 3788 | break; |
| 3789 | } |
| 3790 | } |
| 3791 | |
| 3792 | /* fallback to VBT if available for eDP */ |
| 3793 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
| 3794 | fixed_mode = drm_mode_duplicate(dev, |
| 3795 | dev_priv->vbt.lfp_lvds_vbt_mode); |
| 3796 | if (fixed_mode) |
| 3797 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 3798 | } |
| 3799 | |
Vandana Kannan | 4b6ed68 | 2014-02-11 14:26:36 +0530 | [diff] [blame] | 3800 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 3801 | intel_panel_setup_backlight(connector); |
| 3802 | |
| 3803 | return true; |
| 3804 | } |
| 3805 | |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 3806 | bool |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3807 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 3808 | struct intel_connector *intel_connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3809 | { |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3810 | struct drm_connector *connector = &intel_connector->base; |
| 3811 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 3812 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 3813 | struct drm_device *dev = intel_encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3814 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 3815 | enum port port = intel_dig_port->port; |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 3816 | struct edp_power_seq power_seq = { 0 }; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3817 | const char *name = NULL; |
Paulo Zanoni | b2a1475 | 2013-06-12 17:27:28 -0300 | [diff] [blame] | 3818 | int type, error; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3819 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 3820 | /* intel_dp vfuncs */ |
| 3821 | if (IS_VALLEYVIEW(dev)) |
| 3822 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
| 3823 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 3824 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
| 3825 | else if (HAS_PCH_SPLIT(dev)) |
| 3826 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
| 3827 | else |
| 3828 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
| 3829 | |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 3830 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
| 3831 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 3832 | /* Preserve the current hw state. */ |
| 3833 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 3834 | intel_dp->attached_connector = intel_connector; |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 3835 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 3836 | if (intel_dp_is_edp(dev, port)) |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 3837 | type = DRM_MODE_CONNECTOR_eDP; |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 3838 | else |
| 3839 | type = DRM_MODE_CONNECTOR_DisplayPort; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 3840 | |
Imre Deak | f7d2490 | 2013-05-08 13:14:05 +0300 | [diff] [blame] | 3841 | /* |
| 3842 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
| 3843 | * for DP the encoder type can be set by the caller to |
| 3844 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
| 3845 | */ |
| 3846 | if (type == DRM_MODE_CONNECTOR_eDP) |
| 3847 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 3848 | |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 3849 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
| 3850 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
| 3851 | port_name(port)); |
| 3852 | |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 3853 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3854 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 3855 | |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3856 | connector->interlace_allowed = true; |
| 3857 | connector->doublescan_allowed = 0; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 3858 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 3859 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 3860 | edp_panel_vdd_work); |
Zhenyu Wang | 6251ec0 | 2010-01-12 05:38:32 +0800 | [diff] [blame] | 3861 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 3862 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3863 | drm_sysfs_connector_add(connector); |
| 3864 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 3865 | if (HAS_DDI(dev)) |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 3866 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
| 3867 | else |
| 3868 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 3869 | intel_connector->unregister = intel_dp_connector_unregister; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 3870 | |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 3871 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
| 3872 | if (HAS_DDI(dev)) { |
| 3873 | switch (intel_dig_port->port) { |
| 3874 | case PORT_A: |
| 3875 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
| 3876 | break; |
| 3877 | case PORT_B: |
| 3878 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
| 3879 | break; |
| 3880 | case PORT_C: |
| 3881 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
| 3882 | break; |
| 3883 | case PORT_D: |
| 3884 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
| 3885 | break; |
| 3886 | default: |
| 3887 | BUG(); |
| 3888 | } |
| 3889 | } |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 3890 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3891 | /* Set up the DDC bus. */ |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 3892 | switch (port) { |
| 3893 | case PORT_A: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 3894 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 3895 | name = "DPDDC-A"; |
| 3896 | break; |
| 3897 | case PORT_B: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 3898 | intel_encoder->hpd_pin = HPD_PORT_B; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 3899 | name = "DPDDC-B"; |
| 3900 | break; |
| 3901 | case PORT_C: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 3902 | intel_encoder->hpd_pin = HPD_PORT_C; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 3903 | name = "DPDDC-C"; |
| 3904 | break; |
| 3905 | case PORT_D: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 3906 | intel_encoder->hpd_pin = HPD_PORT_D; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 3907 | name = "DPDDC-D"; |
| 3908 | break; |
| 3909 | default: |
Damien Lespiau | ad1c0b1 | 2013-03-07 15:30:28 +0000 | [diff] [blame] | 3910 | BUG(); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3911 | } |
| 3912 | |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 3913 | if (is_edp(intel_dp)) { |
| 3914 | intel_dp_init_panel_power_timestamps(intel_dp); |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 3915 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 3916 | } |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 3917 | |
Paulo Zanoni | b2a1475 | 2013-06-12 17:27:28 -0300 | [diff] [blame] | 3918 | error = intel_dp_i2c_init(intel_dp, intel_connector, name); |
| 3919 | WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", |
| 3920 | error, port_name(port)); |
Dave Airlie | c1f0526 | 2012-08-30 11:06:18 +1000 | [diff] [blame] | 3921 | |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 3922 | intel_dp->psr_setup_done = false; |
| 3923 | |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 3924 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
Paulo Zanoni | 15b1d17 | 2013-06-12 17:27:27 -0300 | [diff] [blame] | 3925 | i2c_del_adapter(&intel_dp->adapter); |
| 3926 | if (is_edp(intel_dp)) { |
| 3927 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 3928 | mutex_lock(&dev->mode_config.mutex); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 3929 | edp_panel_vdd_off_sync(intel_dp); |
Paulo Zanoni | 15b1d17 | 2013-06-12 17:27:27 -0300 | [diff] [blame] | 3930 | mutex_unlock(&dev->mode_config.mutex); |
| 3931 | } |
Paulo Zanoni | b2f246a | 2013-06-12 17:27:26 -0300 | [diff] [blame] | 3932 | drm_sysfs_connector_remove(connector); |
| 3933 | drm_connector_cleanup(connector); |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 3934 | return false; |
Paulo Zanoni | b2f246a | 2013-06-12 17:27:26 -0300 | [diff] [blame] | 3935 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3936 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3937 | intel_dp_add_properties(intel_dp, connector); |
| 3938 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3939 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 3940 | * 0xd. Failure to do so will result in spurious interrupts being |
| 3941 | * generated on the port when a cable is not attached. |
| 3942 | */ |
| 3943 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 3944 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 3945 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 3946 | } |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 3947 | |
| 3948 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3949 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3950 | |
| 3951 | void |
| 3952 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
| 3953 | { |
| 3954 | struct intel_digital_port *intel_dig_port; |
| 3955 | struct intel_encoder *intel_encoder; |
| 3956 | struct drm_encoder *encoder; |
| 3957 | struct intel_connector *intel_connector; |
| 3958 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 3959 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3960 | if (!intel_dig_port) |
| 3961 | return; |
| 3962 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 3963 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3964 | if (!intel_connector) { |
| 3965 | kfree(intel_dig_port); |
| 3966 | return; |
| 3967 | } |
| 3968 | |
| 3969 | intel_encoder = &intel_dig_port->base; |
| 3970 | encoder = &intel_encoder->base; |
| 3971 | |
| 3972 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
| 3973 | DRM_MODE_ENCODER_TMDS); |
| 3974 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 3975 | intel_encoder->compute_config = intel_dp_compute_config; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 3976 | intel_encoder->mode_set = intel_dp_mode_set; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 3977 | intel_encoder->disable = intel_disable_dp; |
| 3978 | intel_encoder->post_disable = intel_post_disable_dp; |
| 3979 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 3980 | intel_encoder->get_config = intel_dp_get_config; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 3981 | if (IS_VALLEYVIEW(dev)) { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 3982 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 3983 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
| 3984 | intel_encoder->enable = vlv_enable_dp; |
| 3985 | } else { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 3986 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
| 3987 | intel_encoder->enable = g4x_enable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 3988 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3989 | |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 3990 | intel_dig_port->port = port; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3991 | intel_dig_port->dp.output_reg = output_reg; |
| 3992 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 3993 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3994 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 3995 | intel_encoder->cloneable = 0; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3996 | intel_encoder->hot_plug = intel_dp_hot_plug; |
| 3997 | |
Paulo Zanoni | 15b1d17 | 2013-06-12 17:27:27 -0300 | [diff] [blame] | 3998 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
| 3999 | drm_encoder_cleanup(encoder); |
| 4000 | kfree(intel_dig_port); |
Paulo Zanoni | b2f246a | 2013-06-12 17:27:26 -0300 | [diff] [blame] | 4001 | kfree(intel_connector); |
Paulo Zanoni | 15b1d17 | 2013-06-12 17:27:27 -0300 | [diff] [blame] | 4002 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4003 | } |