Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include "drmP.h" |
Ben Skeggs | b01f060 | 2010-07-23 11:39:03 +1000 | [diff] [blame] | 26 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 27 | #include "nouveau_drv.h" |
| 28 | #include "nouveau_i2c.h" |
Ben Skeggs | b01f060 | 2010-07-23 11:39:03 +1000 | [diff] [blame] | 29 | #include "nouveau_connector.h" |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 30 | #include "nouveau_encoder.h" |
| 31 | |
| 32 | static int |
| 33 | auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size) |
| 34 | { |
| 35 | struct drm_device *dev = encoder->dev; |
| 36 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 37 | struct nouveau_i2c_chan *auxch; |
| 38 | int ret; |
| 39 | |
| 40 | auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); |
| 41 | if (!auxch) |
| 42 | return -ENODEV; |
| 43 | |
| 44 | ret = nouveau_dp_auxch(auxch, 9, address, buf, size); |
| 45 | if (ret) |
| 46 | return ret; |
| 47 | |
| 48 | return 0; |
| 49 | } |
| 50 | |
| 51 | static int |
| 52 | auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size) |
| 53 | { |
| 54 | struct drm_device *dev = encoder->dev; |
| 55 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 56 | struct nouveau_i2c_chan *auxch; |
| 57 | int ret; |
| 58 | |
| 59 | auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); |
| 60 | if (!auxch) |
| 61 | return -ENODEV; |
| 62 | |
| 63 | ret = nouveau_dp_auxch(auxch, 8, address, buf, size); |
| 64 | return ret; |
| 65 | } |
| 66 | |
| 67 | static int |
| 68 | nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd) |
| 69 | { |
| 70 | struct drm_device *dev = encoder->dev; |
| 71 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 72 | uint32_t tmp; |
| 73 | int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1); |
| 74 | |
| 75 | tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); |
| 76 | tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED | |
| 77 | NV50_SOR_DP_CTRL_LANE_MASK); |
| 78 | tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16; |
| 79 | if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
| 80 | tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED; |
| 81 | nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp); |
| 82 | |
| 83 | return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1); |
| 84 | } |
| 85 | |
| 86 | static int |
| 87 | nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd) |
| 88 | { |
| 89 | struct drm_device *dev = encoder->dev; |
| 90 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 91 | uint32_t tmp; |
| 92 | int reg = 0x614300 + (nv_encoder->or * 0x800); |
| 93 | |
| 94 | tmp = nv_rd32(dev, reg); |
| 95 | tmp &= 0xfff3ffff; |
| 96 | if (cmd == DP_LINK_BW_2_7) |
| 97 | tmp |= 0x00040000; |
| 98 | nv_wr32(dev, reg, tmp); |
| 99 | |
| 100 | return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1); |
| 101 | } |
| 102 | |
| 103 | static int |
| 104 | nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern) |
| 105 | { |
| 106 | struct drm_device *dev = encoder->dev; |
| 107 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 108 | uint32_t tmp; |
| 109 | uint8_t cmd; |
| 110 | int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1); |
| 111 | int ret; |
| 112 | |
| 113 | tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); |
| 114 | tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN; |
| 115 | tmp |= (pattern << 24); |
| 116 | nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp); |
| 117 | |
| 118 | ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1); |
| 119 | if (ret) |
| 120 | return ret; |
| 121 | cmd &= ~DP_TRAINING_PATTERN_MASK; |
| 122 | cmd |= (pattern & DP_TRAINING_PATTERN_MASK); |
| 123 | return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1); |
| 124 | } |
| 125 | |
| 126 | static int |
| 127 | nouveau_dp_max_voltage_swing(struct drm_encoder *encoder) |
| 128 | { |
| 129 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 130 | struct drm_device *dev = encoder->dev; |
| 131 | struct bit_displayport_encoder_table_entry *dpse; |
| 132 | struct bit_displayport_encoder_table *dpe; |
| 133 | int i, dpe_headerlen, max_vs = 0; |
| 134 | |
| 135 | dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); |
| 136 | if (!dpe) |
| 137 | return false; |
| 138 | dpse = (void *)((char *)dpe + dpe_headerlen); |
| 139 | |
| 140 | for (i = 0; i < dpe_headerlen; i++, dpse++) { |
| 141 | if (dpse->vs_level > max_vs) |
| 142 | max_vs = dpse->vs_level; |
| 143 | } |
| 144 | |
| 145 | return max_vs; |
| 146 | } |
| 147 | |
| 148 | static int |
| 149 | nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs) |
| 150 | { |
| 151 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 152 | struct drm_device *dev = encoder->dev; |
| 153 | struct bit_displayport_encoder_table_entry *dpse; |
| 154 | struct bit_displayport_encoder_table *dpe; |
| 155 | int i, dpe_headerlen, max_pre = 0; |
| 156 | |
| 157 | dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); |
| 158 | if (!dpe) |
| 159 | return false; |
| 160 | dpse = (void *)((char *)dpe + dpe_headerlen); |
| 161 | |
| 162 | for (i = 0; i < dpe_headerlen; i++, dpse++) { |
| 163 | if (dpse->vs_level != vs) |
| 164 | continue; |
| 165 | |
| 166 | if (dpse->pre_level > max_pre) |
| 167 | max_pre = dpse->pre_level; |
| 168 | } |
| 169 | |
| 170 | return max_pre; |
| 171 | } |
| 172 | |
| 173 | static bool |
| 174 | nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config) |
| 175 | { |
| 176 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 177 | struct drm_device *dev = encoder->dev; |
| 178 | struct bit_displayport_encoder_table_entry *dpse; |
| 179 | struct bit_displayport_encoder_table *dpe; |
| 180 | int ret, i, dpe_headerlen, vs = 0, pre = 0; |
| 181 | uint8_t request[2]; |
| 182 | |
| 183 | dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); |
| 184 | if (!dpe) |
| 185 | return false; |
| 186 | dpse = (void *)((char *)dpe + dpe_headerlen); |
| 187 | |
| 188 | ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2); |
| 189 | if (ret) |
| 190 | return false; |
| 191 | |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 192 | NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 193 | |
| 194 | /* Keep all lanes at the same level.. */ |
| 195 | for (i = 0; i < nv_encoder->dp.link_nr; i++) { |
| 196 | int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf; |
| 197 | int lane_vs = lane_req & 3; |
| 198 | int lane_pre = (lane_req >> 2) & 3; |
| 199 | |
| 200 | if (lane_vs > vs) |
| 201 | vs = lane_vs; |
| 202 | if (lane_pre > pre) |
| 203 | pre = lane_pre; |
| 204 | } |
| 205 | |
| 206 | if (vs >= nouveau_dp_max_voltage_swing(encoder)) { |
| 207 | vs = nouveau_dp_max_voltage_swing(encoder); |
| 208 | vs |= 4; |
| 209 | } |
| 210 | |
| 211 | if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) { |
| 212 | pre = nouveau_dp_max_pre_emphasis(encoder, vs & 3); |
| 213 | pre |= 4; |
| 214 | } |
| 215 | |
| 216 | /* Update the configuration for all lanes.. */ |
| 217 | for (i = 0; i < nv_encoder->dp.link_nr; i++) |
| 218 | config[i] = (pre << 3) | vs; |
| 219 | |
| 220 | return true; |
| 221 | } |
| 222 | |
| 223 | static bool |
| 224 | nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config) |
| 225 | { |
| 226 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 227 | struct drm_device *dev = encoder->dev; |
| 228 | struct bit_displayport_encoder_table_entry *dpse; |
| 229 | struct bit_displayport_encoder_table *dpe; |
| 230 | int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1); |
| 231 | int dpe_headerlen, ret, i; |
| 232 | |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 233 | NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n", |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 234 | config[0], config[1], config[2], config[3]); |
| 235 | |
| 236 | dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); |
| 237 | if (!dpe) |
| 238 | return false; |
| 239 | dpse = (void *)((char *)dpe + dpe_headerlen); |
| 240 | |
| 241 | for (i = 0; i < dpe->record_nr; i++, dpse++) { |
| 242 | if (dpse->vs_level == (config[0] & 3) && |
| 243 | dpse->pre_level == ((config[0] >> 3) & 3)) |
| 244 | break; |
| 245 | } |
| 246 | BUG_ON(i == dpe->record_nr); |
| 247 | |
| 248 | for (i = 0; i < nv_encoder->dp.link_nr; i++) { |
| 249 | const int shift[4] = { 16, 8, 0, 24 }; |
| 250 | uint32_t mask = 0xff << shift[i]; |
| 251 | uint32_t reg0, reg1, reg2; |
| 252 | |
| 253 | reg0 = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask; |
| 254 | reg0 |= (dpse->reg0 << shift[i]); |
| 255 | reg1 = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask; |
| 256 | reg1 |= (dpse->reg1 << shift[i]); |
| 257 | reg2 = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff; |
| 258 | reg2 |= (dpse->reg2 << 8); |
| 259 | nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0); |
| 260 | nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1); |
| 261 | nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2); |
| 262 | } |
| 263 | |
| 264 | ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4); |
| 265 | if (ret) |
| 266 | return false; |
| 267 | |
| 268 | return true; |
| 269 | } |
| 270 | |
| 271 | bool |
| 272 | nouveau_dp_link_train(struct drm_encoder *encoder) |
| 273 | { |
| 274 | struct drm_device *dev = encoder->dev; |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 275 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 276 | struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 277 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | b01f060 | 2010-07-23 11:39:03 +1000 | [diff] [blame] | 278 | struct nouveau_connector *nv_connector; |
Ben Skeggs | ea4718d | 2010-07-06 11:00:42 +1000 | [diff] [blame] | 279 | struct bit_displayport_encoder_table *dpe; |
| 280 | int dpe_headerlen; |
| 281 | uint8_t config[4], status[3]; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 282 | bool cr_done, cr_max_vs, eq_done; |
| 283 | int ret = 0, i, tries, voltage; |
| 284 | |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 285 | NV_DEBUG_KMS(dev, "link training!!\n"); |
Ben Skeggs | ea4718d | 2010-07-06 11:00:42 +1000 | [diff] [blame] | 286 | |
Ben Skeggs | b01f060 | 2010-07-23 11:39:03 +1000 | [diff] [blame] | 287 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 288 | if (!nv_connector) |
| 289 | return false; |
| 290 | |
Ben Skeggs | ea4718d | 2010-07-06 11:00:42 +1000 | [diff] [blame] | 291 | dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); |
| 292 | if (!dpe) { |
| 293 | NV_ERROR(dev, "SOR-%d: no DP encoder table!\n", nv_encoder->or); |
| 294 | return false; |
| 295 | } |
| 296 | |
Ben Skeggs | b01f060 | 2010-07-23 11:39:03 +1000 | [diff] [blame] | 297 | /* disable hotplug detect, this flips around on some panels during |
| 298 | * link training. |
| 299 | */ |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 300 | pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false); |
Ben Skeggs | b01f060 | 2010-07-23 11:39:03 +1000 | [diff] [blame] | 301 | |
Ben Skeggs | ea4718d | 2010-07-06 11:00:42 +1000 | [diff] [blame] | 302 | if (dpe->script0) { |
| 303 | NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or); |
| 304 | nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0), |
| 305 | nv_encoder->dcb); |
| 306 | } |
| 307 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 308 | train: |
| 309 | cr_done = eq_done = false; |
| 310 | |
| 311 | /* set link configuration */ |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 312 | NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n", |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 313 | nv_encoder->dp.link_bw, nv_encoder->dp.link_nr); |
| 314 | |
| 315 | ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw); |
| 316 | if (ret) |
| 317 | return false; |
| 318 | |
| 319 | config[0] = nv_encoder->dp.link_nr; |
Ben Skeggs | fe224bb | 2010-09-27 08:29:33 +1000 | [diff] [blame] | 320 | if (nv_encoder->dp.dpcd_version >= 0x11 && |
| 321 | nv_encoder->dp.enhanced_frame) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 322 | config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 323 | |
| 324 | ret = nouveau_dp_lane_count_set(encoder, config[0]); |
| 325 | if (ret) |
| 326 | return false; |
| 327 | |
| 328 | /* clock recovery */ |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 329 | NV_DEBUG_KMS(dev, "\tbegin cr\n"); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 330 | ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1); |
| 331 | if (ret) |
| 332 | goto stop; |
| 333 | |
| 334 | tries = 0; |
| 335 | voltage = -1; |
| 336 | memset(config, 0x00, sizeof(config)); |
| 337 | for (;;) { |
| 338 | if (!nouveau_dp_link_train_commit(encoder, config)) |
| 339 | break; |
| 340 | |
| 341 | udelay(100); |
| 342 | |
| 343 | ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2); |
| 344 | if (ret) |
| 345 | break; |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 346 | NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n", |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 347 | status[0], status[1]); |
| 348 | |
| 349 | cr_done = true; |
| 350 | cr_max_vs = false; |
| 351 | for (i = 0; i < nv_encoder->dp.link_nr; i++) { |
| 352 | int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf; |
| 353 | |
| 354 | if (!(lane & DP_LANE_CR_DONE)) { |
| 355 | cr_done = false; |
| 356 | if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED) |
| 357 | cr_max_vs = true; |
| 358 | break; |
| 359 | } |
| 360 | } |
| 361 | |
| 362 | if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) { |
| 363 | voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
| 364 | tries = 0; |
| 365 | } |
| 366 | |
| 367 | if (cr_done || cr_max_vs || (++tries == 5)) |
| 368 | break; |
| 369 | |
| 370 | if (!nouveau_dp_link_train_adjust(encoder, config)) |
| 371 | break; |
| 372 | } |
| 373 | |
| 374 | if (!cr_done) |
| 375 | goto stop; |
| 376 | |
| 377 | /* channel equalisation */ |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 378 | NV_DEBUG_KMS(dev, "\tbegin eq\n"); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 379 | ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2); |
| 380 | if (ret) |
| 381 | goto stop; |
| 382 | |
| 383 | for (tries = 0; tries <= 5; tries++) { |
| 384 | udelay(400); |
| 385 | |
| 386 | ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3); |
| 387 | if (ret) |
| 388 | break; |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 389 | NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n", |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 390 | status[0], status[1]); |
| 391 | |
| 392 | eq_done = true; |
| 393 | if (!(status[2] & DP_INTERLANE_ALIGN_DONE)) |
| 394 | eq_done = false; |
| 395 | |
| 396 | for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) { |
| 397 | int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf; |
| 398 | |
| 399 | if (!(lane & DP_LANE_CR_DONE)) { |
| 400 | cr_done = false; |
| 401 | break; |
| 402 | } |
| 403 | |
| 404 | if (!(lane & DP_LANE_CHANNEL_EQ_DONE) || |
| 405 | !(lane & DP_LANE_SYMBOL_LOCKED)) { |
| 406 | eq_done = false; |
| 407 | break; |
| 408 | } |
| 409 | } |
| 410 | |
| 411 | if (eq_done || !cr_done) |
| 412 | break; |
| 413 | |
| 414 | if (!nouveau_dp_link_train_adjust(encoder, config) || |
| 415 | !nouveau_dp_link_train_commit(encoder, config)) |
| 416 | break; |
| 417 | } |
| 418 | |
| 419 | stop: |
| 420 | /* end link training */ |
| 421 | ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE); |
| 422 | if (ret) |
| 423 | return false; |
| 424 | |
| 425 | /* retry at a lower setting, if possible */ |
| 426 | if (!ret && !(eq_done && cr_done)) { |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 427 | NV_DEBUG_KMS(dev, "\twe failed\n"); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 428 | if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) { |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 429 | NV_DEBUG_KMS(dev, "retry link training at low rate\n"); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 430 | nv_encoder->dp.link_bw = DP_LINK_BW_1_62; |
| 431 | goto train; |
| 432 | } |
| 433 | } |
| 434 | |
Ben Skeggs | ea4718d | 2010-07-06 11:00:42 +1000 | [diff] [blame] | 435 | if (dpe->script1) { |
| 436 | NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or); |
| 437 | nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1), |
| 438 | nv_encoder->dcb); |
| 439 | } |
| 440 | |
Ben Skeggs | b01f060 | 2010-07-23 11:39:03 +1000 | [diff] [blame] | 441 | /* re-enable hotplug detect */ |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 442 | pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, true); |
Ben Skeggs | b01f060 | 2010-07-23 11:39:03 +1000 | [diff] [blame] | 443 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 444 | return eq_done; |
| 445 | } |
| 446 | |
| 447 | bool |
| 448 | nouveau_dp_detect(struct drm_encoder *encoder) |
| 449 | { |
| 450 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 451 | struct drm_device *dev = encoder->dev; |
| 452 | uint8_t dpcd[4]; |
| 453 | int ret; |
| 454 | |
| 455 | ret = auxch_rd(encoder, 0x0000, dpcd, 4); |
| 456 | if (ret) |
| 457 | return false; |
| 458 | |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 459 | NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n" |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 460 | "display: link_bw %d, link_nr %d version 0x%02x\n", |
| 461 | nv_encoder->dcb->dpconf.link_bw, |
| 462 | nv_encoder->dcb->dpconf.link_nr, |
| 463 | dpcd[1], dpcd[2] & 0x0f, dpcd[0]); |
| 464 | |
| 465 | nv_encoder->dp.dpcd_version = dpcd[0]; |
| 466 | |
| 467 | nv_encoder->dp.link_bw = dpcd[1]; |
| 468 | if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62 && |
| 469 | !nv_encoder->dcb->dpconf.link_bw) |
| 470 | nv_encoder->dp.link_bw = DP_LINK_BW_1_62; |
| 471 | |
Ben Skeggs | 85341f2 | 2010-09-28 10:03:57 +1000 | [diff] [blame^] | 472 | nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 473 | if (nv_encoder->dp.link_nr > nv_encoder->dcb->dpconf.link_nr) |
| 474 | nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr; |
| 475 | |
Ben Skeggs | fe224bb | 2010-09-27 08:29:33 +1000 | [diff] [blame] | 476 | nv_encoder->dp.enhanced_frame = (dpcd[2] & DP_ENHANCED_FRAME_CAP); |
| 477 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 478 | return true; |
| 479 | } |
| 480 | |
| 481 | int |
| 482 | nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, |
| 483 | uint8_t *data, int data_nr) |
| 484 | { |
| 485 | struct drm_device *dev = auxch->dev; |
| 486 | uint32_t tmp, ctrl, stat = 0, data32[4] = {}; |
| 487 | int ret = 0, i, index = auxch->rd; |
| 488 | |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 489 | NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 490 | |
| 491 | tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); |
| 492 | nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000); |
| 493 | tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); |
| 494 | if (!(tmp & 0x01000000)) { |
| 495 | NV_ERROR(dev, "expected bit 24 == 1, got 0x%08x\n", tmp); |
| 496 | ret = -EIO; |
| 497 | goto out; |
| 498 | } |
| 499 | |
| 500 | for (i = 0; i < 3; i++) { |
| 501 | tmp = nv_rd32(dev, NV50_AUXCH_STAT(auxch->rd)); |
| 502 | if (tmp & NV50_AUXCH_STAT_STATE_READY) |
| 503 | break; |
| 504 | udelay(100); |
| 505 | } |
| 506 | |
| 507 | if (i == 3) { |
| 508 | ret = -EBUSY; |
| 509 | goto out; |
| 510 | } |
| 511 | |
| 512 | if (!(cmd & 1)) { |
| 513 | memcpy(data32, data, data_nr); |
| 514 | for (i = 0; i < 4; i++) { |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 515 | NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 516 | nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]); |
| 517 | } |
| 518 | } |
| 519 | |
| 520 | nv_wr32(dev, NV50_AUXCH_ADDR(index), addr); |
| 521 | ctrl = nv_rd32(dev, NV50_AUXCH_CTRL(index)); |
| 522 | ctrl &= ~(NV50_AUXCH_CTRL_CMD | NV50_AUXCH_CTRL_LEN); |
| 523 | ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT); |
| 524 | ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT); |
| 525 | |
Ben Skeggs | 8e024f1 | 2010-03-16 08:45:07 +1000 | [diff] [blame] | 526 | for (i = 0; i < 16; i++) { |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 527 | nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000); |
| 528 | nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl); |
| 529 | nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000); |
Francisco Jerez | 4b5c152 | 2010-09-07 17:34:44 +0200 | [diff] [blame] | 530 | if (!nv_wait(dev, NV50_AUXCH_CTRL(index), |
| 531 | 0x00010000, 0x00000000)) { |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 532 | NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n", |
| 533 | nv_rd32(dev, NV50_AUXCH_CTRL(index))); |
Ben Skeggs | 0107bae | 2010-01-22 09:10:05 +1000 | [diff] [blame] | 534 | ret = -EBUSY; |
| 535 | goto out; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 536 | } |
| 537 | |
| 538 | udelay(400); |
| 539 | |
| 540 | stat = nv_rd32(dev, NV50_AUXCH_STAT(index)); |
| 541 | if ((stat & NV50_AUXCH_STAT_REPLY_AUX) != |
| 542 | NV50_AUXCH_STAT_REPLY_AUX_DEFER) |
| 543 | break; |
| 544 | } |
| 545 | |
Ben Skeggs | 8e024f1 | 2010-03-16 08:45:07 +1000 | [diff] [blame] | 546 | if (i == 16) { |
| 547 | NV_ERROR(dev, "auxch DEFER too many times, bailing\n"); |
| 548 | ret = -EREMOTEIO; |
| 549 | goto out; |
| 550 | } |
| 551 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 552 | if (cmd & 1) { |
Ben Skeggs | 1ee7698 | 2010-02-09 10:08:34 +1000 | [diff] [blame] | 553 | if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) { |
| 554 | ret = -EREMOTEIO; |
| 555 | goto out; |
| 556 | } |
| 557 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 558 | for (i = 0; i < 4; i++) { |
| 559 | data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i)); |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 560 | NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 561 | } |
| 562 | memcpy(data, data32, data_nr); |
| 563 | } |
| 564 | |
| 565 | out: |
| 566 | tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); |
| 567 | nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp & ~0x00100000); |
| 568 | tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); |
| 569 | if (tmp & 0x01000000) { |
| 570 | NV_ERROR(dev, "expected bit 24 == 0, got 0x%08x\n", tmp); |
| 571 | ret = -EIO; |
| 572 | } |
| 573 | |
| 574 | udelay(400); |
| 575 | |
| 576 | return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY); |
| 577 | } |
| 578 | |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 579 | static int |
| 580 | nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 581 | { |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 582 | struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 583 | struct drm_device *dev = auxch->dev; |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 584 | struct i2c_msg *msg = msgs; |
| 585 | int ret, mcnt = num; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 586 | |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 587 | while (mcnt--) { |
| 588 | u8 remaining = msg->len; |
| 589 | u8 *ptr = msg->buf; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 590 | |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 591 | while (remaining) { |
| 592 | u8 cnt = (remaining > 16) ? 16 : remaining; |
| 593 | u8 cmd; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 594 | |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 595 | if (msg->flags & I2C_M_RD) |
| 596 | cmd = AUX_I2C_READ; |
| 597 | else |
| 598 | cmd = AUX_I2C_WRITE; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 599 | |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 600 | if (mcnt || remaining > 16) |
| 601 | cmd |= AUX_I2C_MOT; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 602 | |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 603 | ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt); |
| 604 | if (ret < 0) |
| 605 | return ret; |
| 606 | |
| 607 | switch (ret & NV50_AUXCH_STAT_REPLY_I2C) { |
| 608 | case NV50_AUXCH_STAT_REPLY_I2C_ACK: |
| 609 | break; |
| 610 | case NV50_AUXCH_STAT_REPLY_I2C_NACK: |
| 611 | return -EREMOTEIO; |
| 612 | case NV50_AUXCH_STAT_REPLY_I2C_DEFER: |
| 613 | udelay(100); |
| 614 | continue; |
| 615 | default: |
| 616 | NV_ERROR(dev, "bad auxch reply: 0x%08x\n", ret); |
| 617 | return -EREMOTEIO; |
| 618 | } |
| 619 | |
| 620 | ptr += cnt; |
| 621 | remaining -= cnt; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 622 | } |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 623 | |
| 624 | msg++; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 625 | } |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 626 | |
| 627 | return num; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 628 | } |
| 629 | |
Ben Skeggs | c020c9a | 2010-07-29 21:01:45 +1000 | [diff] [blame] | 630 | static u32 |
| 631 | nouveau_dp_i2c_func(struct i2c_adapter *adap) |
| 632 | { |
| 633 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
| 634 | } |
| 635 | |
| 636 | const struct i2c_algorithm nouveau_dp_i2c_algo = { |
| 637 | .master_xfer = nouveau_dp_i2c_xfer, |
| 638 | .functionality = nouveau_dp_i2c_func |
| 639 | }; |