blob: e418b9035caceb3be77a4927896df424daf39245 [file] [log] [blame]
Francois Romieu1202d6f2007-09-17 17:13:55 -07001/*
2 *
3 * ipg.h
4 *
5 * Include file for Gigabit Ethernet device driver for Network
6 * Interface Cards (NICs) utilizing the Tamarack Microelectronics
7 * Inc. IPG Gigabit or Triple Speed Ethernet Media Access
8 * Controller.
9 *
10 * Craig Rich
11 * Sundance Technology, Inc.
12 * 1485 Saratoga Avenue
13 * Suite 200
14 * San Jose, CA 95129
15 * 408 873 4117
16 * www.sundanceti.com
17 * craig_rich@sundanceti.com
18 */
19#ifndef __LINUX_IPG_H
20#define __LINUX_IPG_H
21
22#include <linux/version.h>
23#include <linux/module.h>
24
25#include <linux/kernel.h>
26#include <linux/pci.h>
27#include <linux/ioport.h>
28#include <linux/errno.h>
29#include <asm/io.h>
30#include <linux/delay.h>
31#include <linux/types.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/skbuff.h>
36#include <linux/version.h>
37#include <asm/bitops.h>
38/*#include <asm/spinlock.h>*/
39
40#define DrvVer "2.09d"
41
42#define IPG_DEV_KFREE_SKB(skb) dev_kfree_skb_irq(skb)
43
44/*
45 * Constants
46 */
47
48/* GMII based PHY IDs */
49#define NS 0x2000
50#define MARVELL 0x0141
51#define ICPLUS_PHY 0x243
52
53/* NIC Physical Layer Device MII register fields. */
54#define MII_PHY_SELECTOR_IEEE8023 0x0001
55#define MII_PHY_TECHABILITYFIELD 0x1FE0
56
57/* GMII_PHY_1000 need to set to prefer master */
58#define GMII_PHY_1000BASETCONTROL_PreferMaster 0x0400
59
60/* NIC Physical Layer Device GMII constants. */
61#define GMII_PREAMBLE 0xFFFFFFFF
62#define GMII_ST 0x1
63#define GMII_READ 0x2
64#define GMII_WRITE 0x1
65#define GMII_TA_READ_MASK 0x1
66#define GMII_TA_WRITE 0x2
67
68/* I/O register offsets. */
69enum ipg_regs {
70 DMA_CTRL = 0x00,
71 RX_DMA_STATUS = 0x08, // Unused + reserved
72 TFD_LIST_PTR_0 = 0x10,
73 TFD_LIST_PTR_1 = 0x14,
74 TX_DMA_BURST_THRESH = 0x18,
75 TX_DMA_URGENT_THRESH = 0x19,
76 TX_DMA_POLL_PERIOD = 0x1a,
77 RFD_LIST_PTR_0 = 0x1c,
78 RFD_LIST_PTR_1 = 0x20,
79 RX_DMA_BURST_THRESH = 0x24,
80 RX_DMA_URGENT_THRESH = 0x25,
81 RX_DMA_POLL_PERIOD = 0x26,
82 DEBUG_CTRL = 0x2c,
83 ASIC_CTRL = 0x30,
84 FIFO_CTRL = 0x38, // Unused
85 FLOW_OFF_THRESH = 0x3c,
86 FLOW_ON_THRESH = 0x3e,
87 EEPROM_DATA = 0x48,
88 EEPROM_CTRL = 0x4a,
89 EXPROM_ADDR = 0x4c, // Unused
90 EXPROM_DATA = 0x50, // Unused
91 WAKE_EVENT = 0x51, // Unused
92 COUNTDOWN = 0x54, // Unused
93 INT_STATUS_ACK = 0x5a,
94 INT_ENABLE = 0x5c,
95 INT_STATUS = 0x5e, // Unused
96 TX_STATUS = 0x60,
97 MAC_CTRL = 0x6c,
98 VLAN_TAG = 0x70, // Unused
99 PHY_SET = 0x75, // JES20040127EEPROM
100 PHY_CTRL = 0x76,
101 STATION_ADDRESS_0 = 0x78,
102 STATION_ADDRESS_1 = 0x7a,
103 STATION_ADDRESS_2 = 0x7c,
104 MAX_FRAME_SIZE = 0x86,
105 RECEIVE_MODE = 0x88,
106 HASHTABLE_0 = 0x8c,
107 HASHTABLE_1 = 0x90,
108 RMON_STATISTICS_MASK = 0x98,
109 STATISTICS_MASK = 0x9c,
110 RX_JUMBO_FRAMES = 0xbc, // Unused
111 TCP_CHECKSUM_ERRORS = 0xc0, // Unused
112 IP_CHECKSUM_ERRORS = 0xc2, // Unused
113 UDP_CHECKSUM_ERRORS = 0xc4, // Unused
114 TX_JUMBO_FRAMES = 0xf4 // Unused
115};
116
117/* Ethernet MIB statistic register offsets. */
118#define IPG_OCTETRCVOK 0xA8
119#define IPG_MCSTOCTETRCVDOK 0xAC
120#define IPG_BCSTOCTETRCVOK 0xB0
121#define IPG_FRAMESRCVDOK 0xB4
122#define IPG_MCSTFRAMESRCVDOK 0xB8
123#define IPG_BCSTFRAMESRCVDOK 0xBE
124#define IPG_MACCONTROLFRAMESRCVD 0xC6
125#define IPG_FRAMETOOLONGERRRORS 0xC8
126#define IPG_INRANGELENGTHERRORS 0xCA
127#define IPG_FRAMECHECKSEQERRORS 0xCC
128#define IPG_FRAMESLOSTRXERRORS 0xCE
129#define IPG_OCTETXMTOK 0xD0
130#define IPG_MCSTOCTETXMTOK 0xD4
131#define IPG_BCSTOCTETXMTOK 0xD8
132#define IPG_FRAMESXMTDOK 0xDC
133#define IPG_MCSTFRAMESXMTDOK 0xE0
134#define IPG_FRAMESWDEFERREDXMT 0xE4
135#define IPG_LATECOLLISIONS 0xE8
136#define IPG_MULTICOLFRAMES 0xEC
137#define IPG_SINGLECOLFRAMES 0xF0
138#define IPG_BCSTFRAMESXMTDOK 0xF6
139#define IPG_CARRIERSENSEERRORS 0xF8
140#define IPG_MACCONTROLFRAMESXMTDOK 0xFA
141#define IPG_FRAMESABORTXSCOLLS 0xFC
142#define IPG_FRAMESWEXDEFERRAL 0xFE
143
144/* RMON statistic register offsets. */
145#define IPG_ETHERSTATSCOLLISIONS 0x100
146#define IPG_ETHERSTATSOCTETSTRANSMIT 0x104
147#define IPG_ETHERSTATSPKTSTRANSMIT 0x108
148#define IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT 0x10C
149#define IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT 0x110
150#define IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT 0x114
151#define IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT 0x118
152#define IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT 0x11C
153#define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT 0x120
154#define IPG_ETHERSTATSCRCALIGNERRORS 0x124
155#define IPG_ETHERSTATSUNDERSIZEPKTS 0x128
156#define IPG_ETHERSTATSFRAGMENTS 0x12C
157#define IPG_ETHERSTATSJABBERS 0x130
158#define IPG_ETHERSTATSOCTETS 0x134
159#define IPG_ETHERSTATSPKTS 0x138
160#define IPG_ETHERSTATSPKTS64OCTESTS 0x13C
161#define IPG_ETHERSTATSPKTS65TO127OCTESTS 0x140
162#define IPG_ETHERSTATSPKTS128TO255OCTESTS 0x144
163#define IPG_ETHERSTATSPKTS256TO511OCTESTS 0x148
164#define IPG_ETHERSTATSPKTS512TO1023OCTESTS 0x14C
165#define IPG_ETHERSTATSPKTS1024TO1518OCTESTS 0x150
166
167/* RMON statistic register equivalents. */
168#define IPG_ETHERSTATSMULTICASTPKTSTRANSMIT 0xE0
169#define IPG_ETHERSTATSBROADCASTPKTSTRANSMIT 0xF6
170#define IPG_ETHERSTATSMULTICASTPKTS 0xB8
171#define IPG_ETHERSTATSBROADCASTPKTS 0xBE
172#define IPG_ETHERSTATSOVERSIZEPKTS 0xC8
173#define IPG_ETHERSTATSDROPEVENTS 0xCE
174
175/* Serial EEPROM offsets */
176#define IPG_EEPROM_CONFIGPARAM 0x00
177#define IPG_EEPROM_ASICCTRL 0x01
178#define IPG_EEPROM_SUBSYSTEMVENDORID 0x02
179#define IPG_EEPROM_SUBSYSTEMID 0x03
180#define IPG_EEPROM_STATIONADDRESS0 0x10
181#define IPG_EEPROM_STATIONADDRESS1 0x11
182#define IPG_EEPROM_STATIONADDRESS2 0x12
183
184/* Register & data structure bit masks */
185
186/* PCI register masks. */
187
188/* IOBaseAddress */
189#define IPG_PIB_RSVD_MASK 0xFFFFFE01
190#define IPG_PIB_IOBASEADDRESS 0xFFFFFF00
191#define IPG_PIB_IOBASEADDRIND 0x00000001
192
193/* MemBaseAddress */
194#define IPG_PMB_RSVD_MASK 0xFFFFFE07
195#define IPG_PMB_MEMBASEADDRIND 0x00000001
196#define IPG_PMB_MEMMAPTYPE 0x00000006
197#define IPG_PMB_MEMMAPTYPE0 0x00000002
198#define IPG_PMB_MEMMAPTYPE1 0x00000004
199#define IPG_PMB_MEMBASEADDRESS 0xFFFFFE00
200
201/* ConfigStatus */
202#define IPG_CS_RSVD_MASK 0xFFB0
203#define IPG_CS_CAPABILITIES 0x0010
204#define IPG_CS_66MHZCAPABLE 0x0020
205#define IPG_CS_FASTBACK2BACK 0x0080
206#define IPG_CS_DATAPARITYREPORTED 0x0100
207#define IPG_CS_DEVSELTIMING 0x0600
208#define IPG_CS_SIGNALEDTARGETABORT 0x0800
209#define IPG_CS_RECEIVEDTARGETABORT 0x1000
210#define IPG_CS_RECEIVEDMASTERABORT 0x2000
211#define IPG_CS_SIGNALEDSYSTEMERROR 0x4000
212#define IPG_CS_DETECTEDPARITYERROR 0x8000
213
214/* TFD data structure masks. */
215
216/* TFDList, TFC */
217#define IPG_TFC_RSVD_MASK 0x0000FFFF9FFFFFFF
218#define IPG_TFC_FRAMEID 0x000000000000FFFF
219#define IPG_TFC_WORDALIGN 0x0000000000030000
220#define IPG_TFC_WORDALIGNTODWORD 0x0000000000000000
221#define IPG_TFC_WORDALIGNTOWORD 0x0000000000020000
222#define IPG_TFC_WORDALIGNDISABLED 0x0000000000030000
223#define IPG_TFC_TCPCHECKSUMENABLE 0x0000000000040000
224#define IPG_TFC_UDPCHECKSUMENABLE 0x0000000000080000
225#define IPG_TFC_IPCHECKSUMENABLE 0x0000000000100000
226#define IPG_TFC_FCSAPPENDDISABLE 0x0000000000200000
227#define IPG_TFC_TXINDICATE 0x0000000000400000
228#define IPG_TFC_TXDMAINDICATE 0x0000000000800000
229#define IPG_TFC_FRAGCOUNT 0x000000000F000000
230#define IPG_TFC_VLANTAGINSERT 0x0000000010000000
231#define IPG_TFC_TFDDONE 0x0000000080000000
232#define IPG_TFC_VID 0x00000FFF00000000
233#define IPG_TFC_CFI 0x0000100000000000
234#define IPG_TFC_USERPRIORITY 0x0000E00000000000
235
236/* TFDList, FragInfo */
237#define IPG_TFI_RSVD_MASK 0xFFFF00FFFFFFFFFF
238#define IPG_TFI_FRAGADDR 0x000000FFFFFFFFFF
239#define IPG_TFI_FRAGLEN 0xFFFF000000000000LL
240
241/* RFD data structure masks. */
242
243/* RFDList, RFS */
244#define IPG_RFS_RSVD_MASK 0x0000FFFFFFFFFFFF
245#define IPG_RFS_RXFRAMELEN 0x000000000000FFFF
246#define IPG_RFS_RXFIFOOVERRUN 0x0000000000010000
247#define IPG_RFS_RXRUNTFRAME 0x0000000000020000
248#define IPG_RFS_RXALIGNMENTERROR 0x0000000000040000
249#define IPG_RFS_RXFCSERROR 0x0000000000080000
250#define IPG_RFS_RXOVERSIZEDFRAME 0x0000000000100000
251#define IPG_RFS_RXLENGTHERROR 0x0000000000200000
252#define IPG_RFS_VLANDETECTED 0x0000000000400000
253#define IPG_RFS_TCPDETECTED 0x0000000000800000
254#define IPG_RFS_TCPERROR 0x0000000001000000
255#define IPG_RFS_UDPDETECTED 0x0000000002000000
256#define IPG_RFS_UDPERROR 0x0000000004000000
257#define IPG_RFS_IPDETECTED 0x0000000008000000
258#define IPG_RFS_IPERROR 0x0000000010000000
259#define IPG_RFS_FRAMESTART 0x0000000020000000
260#define IPG_RFS_FRAMEEND 0x0000000040000000
261#define IPG_RFS_RFDDONE 0x0000000080000000
262#define IPG_RFS_TCI 0x0000FFFF00000000
263
264/* RFDList, FragInfo */
265#define IPG_RFI_RSVD_MASK 0xFFFF00FFFFFFFFFF
266#define IPG_RFI_FRAGADDR 0x000000FFFFFFFFFF
267#define IPG_RFI_FRAGLEN 0xFFFF000000000000LL
268
269/* I/O Register masks. */
270
271/* RMON Statistics Mask */
272#define IPG_RZ_ALL 0x0FFFFFFF
273
274/* Statistics Mask */
275#define IPG_SM_ALL 0x0FFFFFFF
276#define IPG_SM_OCTETRCVOK_FRAMESRCVDOK 0x00000001
277#define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002
278#define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004
279#define IPG_SM_RXJUMBOFRAMES 0x00000008
280#define IPG_SM_TCPCHECKSUMERRORS 0x00000010
281#define IPG_SM_IPCHECKSUMERRORS 0x00000020
282#define IPG_SM_UDPCHECKSUMERRORS 0x00000040
283#define IPG_SM_MACCONTROLFRAMESRCVD 0x00000080
284#define IPG_SM_FRAMESTOOLONGERRORS 0x00000100
285#define IPG_SM_INRANGELENGTHERRORS 0x00000200
286#define IPG_SM_FRAMECHECKSEQERRORS 0x00000400
287#define IPG_SM_FRAMESLOSTRXERRORS 0x00000800
288#define IPG_SM_OCTETXMTOK_FRAMESXMTOK 0x00001000
289#define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK 0x00002000
290#define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK 0x00004000
291#define IPG_SM_FRAMESWDEFERREDXMT 0x00008000
292#define IPG_SM_LATECOLLISIONS 0x00010000
293#define IPG_SM_MULTICOLFRAMES 0x00020000
294#define IPG_SM_SINGLECOLFRAMES 0x00040000
295#define IPG_SM_TXJUMBOFRAMES 0x00080000
296#define IPG_SM_CARRIERSENSEERRORS 0x00100000
297#define IPG_SM_MACCONTROLFRAMESXMTD 0x00200000
298#define IPG_SM_FRAMESABORTXSCOLLS 0x00400000
299#define IPG_SM_FRAMESWEXDEFERAL 0x00800000
300
301/* Countdown */
302#define IPG_CD_RSVD_MASK 0x0700FFFF
303#define IPG_CD_COUNT 0x0000FFFF
304#define IPG_CD_COUNTDOWNSPEED 0x01000000
305#define IPG_CD_COUNTDOWNMODE 0x02000000
306#define IPG_CD_COUNTINTENABLED 0x04000000
307
308/* TxDMABurstThresh */
309#define IPG_TB_RSVD_MASK 0xFF
310
311/* TxDMAUrgentThresh */
312#define IPG_TU_RSVD_MASK 0xFF
313
314/* TxDMAPollPeriod */
315#define IPG_TP_RSVD_MASK 0xFF
316
317/* RxDMAUrgentThresh */
318#define IPG_RU_RSVD_MASK 0xFF
319
320/* RxDMAPollPeriod */
321#define IPG_RP_RSVD_MASK 0xFF
322
323/* ReceiveMode */
324#define IPG_RM_RSVD_MASK 0x3F
325#define IPG_RM_RECEIVEUNICAST 0x01
326#define IPG_RM_RECEIVEMULTICAST 0x02
327#define IPG_RM_RECEIVEBROADCAST 0x04
328#define IPG_RM_RECEIVEALLFRAMES 0x08
329#define IPG_RM_RECEIVEMULTICASTHASH 0x10
330#define IPG_RM_RECEIVEIPMULTICAST 0x20
331
332/* PhySet JES20040127EEPROM*/
333#define IPG_PS_MEM_LENB9B 0x01
334#define IPG_PS_MEM_LEN9 0x02
335#define IPG_PS_NON_COMPDET 0x04
336
337/* PhyCtrl */
338#define IPG_PC_RSVD_MASK 0xFF
339#define IPG_PC_MGMTCLK_LO 0x00
340#define IPG_PC_MGMTCLK_HI 0x01
341#define IPG_PC_MGMTCLK 0x01
342#define IPG_PC_MGMTDATA 0x02
343#define IPG_PC_MGMTDIR 0x04
344#define IPG_PC_DUPLEX_POLARITY 0x08
345#define IPG_PC_DUPLEX_STATUS 0x10
346#define IPG_PC_LINK_POLARITY 0x20
347#define IPG_PC_LINK_SPEED 0xC0
348#define IPG_PC_LINK_SPEED_10MBPS 0x40
349#define IPG_PC_LINK_SPEED_100MBPS 0x80
350#define IPG_PC_LINK_SPEED_1000MBPS 0xC0
351
352/* DMACtrl */
353#define IPG_DC_RSVD_MASK 0xC07D9818
354#define IPG_DC_RX_DMA_COMPLETE 0x00000008
355#define IPG_DC_RX_DMA_POLL_NOW 0x00000010
356#define IPG_DC_TX_DMA_COMPLETE 0x00000800
357#define IPG_DC_TX_DMA_POLL_NOW 0x00001000
358#define IPG_DC_TX_DMA_IN_PROG 0x00008000
359#define IPG_DC_RX_EARLY_DISABLE 0x00010000
360#define IPG_DC_MWI_DISABLE 0x00040000
361#define IPG_DC_TX_WRITE_BACK_DISABLE 0x00080000
362#define IPG_DC_TX_BURST_LIMIT 0x00700000
363#define IPG_DC_TARGET_ABORT 0x40000000
364#define IPG_DC_MASTER_ABORT 0x80000000
365
366/* ASICCtrl */
367#define IPG_AC_RSVD_MASK 0x07FFEFF2
368#define IPG_AC_EXP_ROM_SIZE 0x00000002
369#define IPG_AC_PHY_SPEED10 0x00000010
370#define IPG_AC_PHY_SPEED100 0x00000020
371#define IPG_AC_PHY_SPEED1000 0x00000040
372#define IPG_AC_PHY_MEDIA 0x00000080
373#define IPG_AC_FORCED_CFG 0x00000700
374#define IPG_AC_D3RESETDISABLE 0x00000800
375#define IPG_AC_SPEED_UP_MODE 0x00002000
376#define IPG_AC_LED_MODE 0x00004000
377#define IPG_AC_RST_OUT_POLARITY 0x00008000
378#define IPG_AC_GLOBAL_RESET 0x00010000
379#define IPG_AC_RX_RESET 0x00020000
380#define IPG_AC_TX_RESET 0x00040000
381#define IPG_AC_DMA 0x00080000
382#define IPG_AC_FIFO 0x00100000
383#define IPG_AC_NETWORK 0x00200000
384#define IPG_AC_HOST 0x00400000
385#define IPG_AC_AUTO_INIT 0x00800000
386#define IPG_AC_RST_OUT 0x01000000
387#define IPG_AC_INT_REQUEST 0x02000000
388#define IPG_AC_RESET_BUSY 0x04000000
389#define IPG_AC_LED_SPEED 0x08000000 //JES20040127EEPROM
390#define IPG_AC_LED_MODE_BIT_1 0x20000000 //JES20040127EEPROM
391
392/* EepromCtrl */
393#define IPG_EC_RSVD_MASK 0x83FF
394#define IPG_EC_EEPROM_ADDR 0x00FF
395#define IPG_EC_EEPROM_OPCODE 0x0300
396#define IPG_EC_EEPROM_SUBCOMMAD 0x0000
397#define IPG_EC_EEPROM_WRITEOPCODE 0x0100
398#define IPG_EC_EEPROM_READOPCODE 0x0200
399#define IPG_EC_EEPROM_ERASEOPCODE 0x0300
400#define IPG_EC_EEPROM_BUSY 0x8000
401
402/* FIFOCtrl */
403#define IPG_FC_RSVD_MASK 0xC001
404#define IPG_FC_RAM_TEST_MODE 0x0001
405#define IPG_FC_TRANSMITTING 0x4000
406#define IPG_FC_RECEIVING 0x8000
407
408/* TxStatus */
409#define IPG_TS_RSVD_MASK 0xFFFF00DD
410#define IPG_TS_TX_ERROR 0x00000001
411#define IPG_TS_LATE_COLLISION 0x00000004
412#define IPG_TS_TX_MAX_COLL 0x00000008
413#define IPG_TS_TX_UNDERRUN 0x00000010
414#define IPG_TS_TX_IND_REQD 0x00000040
415#define IPG_TS_TX_COMPLETE 0x00000080
416#define IPG_TS_TX_FRAMEID 0xFFFF0000
417
418/* WakeEvent */
419#define IPG_WE_WAKE_PKT_ENABLE 0x01
420#define IPG_WE_MAGIC_PKT_ENABLE 0x02
421#define IPG_WE_LINK_EVT_ENABLE 0x04
422#define IPG_WE_WAKE_POLARITY 0x08
423#define IPG_WE_WAKE_PKT_EVT 0x10
424#define IPG_WE_MAGIC_PKT_EVT 0x20
425#define IPG_WE_LINK_EVT 0x40
426#define IPG_WE_WOL_ENABLE 0x80
427
428/* IntEnable */
429#define IPG_IE_RSVD_MASK 0x1FFE
430#define IPG_IE_HOST_ERROR 0x0002
431#define IPG_IE_TX_COMPLETE 0x0004
432#define IPG_IE_MAC_CTRL_FRAME 0x0008
433#define IPG_IE_RX_COMPLETE 0x0010
434#define IPG_IE_RX_EARLY 0x0020
435#define IPG_IE_INT_REQUESTED 0x0040
436#define IPG_IE_UPDATE_STATS 0x0080
437#define IPG_IE_LINK_EVENT 0x0100
438#define IPG_IE_TX_DMA_COMPLETE 0x0200
439#define IPG_IE_RX_DMA_COMPLETE 0x0400
440#define IPG_IE_RFD_LIST_END 0x0800
441#define IPG_IE_RX_DMA_PRIORITY 0x1000
442
443/* IntStatus */
444#define IPG_IS_RSVD_MASK 0x1FFF
445#define IPG_IS_INTERRUPT_STATUS 0x0001
446#define IPG_IS_HOST_ERROR 0x0002
447#define IPG_IS_TX_COMPLETE 0x0004
448#define IPG_IS_MAC_CTRL_FRAME 0x0008
449#define IPG_IS_RX_COMPLETE 0x0010
450#define IPG_IS_RX_EARLY 0x0020
451#define IPG_IS_INT_REQUESTED 0x0040
452#define IPG_IS_UPDATE_STATS 0x0080
453#define IPG_IS_LINK_EVENT 0x0100
454#define IPG_IS_TX_DMA_COMPLETE 0x0200
455#define IPG_IS_RX_DMA_COMPLETE 0x0400
456#define IPG_IS_RFD_LIST_END 0x0800
457#define IPG_IS_RX_DMA_PRIORITY 0x1000
458
459/* MACCtrl */
460#define IPG_MC_RSVD_MASK 0x7FE33FA3
461#define IPG_MC_IFS_SELECT 0x00000003
462#define IPG_MC_IFS_4352BIT 0x00000003
463#define IPG_MC_IFS_1792BIT 0x00000002
464#define IPG_MC_IFS_1024BIT 0x00000001
465#define IPG_MC_IFS_96BIT 0x00000000
466#define IPG_MC_DUPLEX_SELECT 0x00000020
467#define IPG_MC_DUPLEX_SELECT_FD 0x00000020
468#define IPG_MC_DUPLEX_SELECT_HD 0x00000000
469#define IPG_MC_TX_FLOW_CONTROL_ENABLE 0x00000080
470#define IPG_MC_RX_FLOW_CONTROL_ENABLE 0x00000100
471#define IPG_MC_RCV_FCS 0x00000200
472#define IPG_MC_FIFO_LOOPBACK 0x00000400
473#define IPG_MC_MAC_LOOPBACK 0x00000800
474#define IPG_MC_AUTO_VLAN_TAGGING 0x00001000
475#define IPG_MC_AUTO_VLAN_UNTAGGING 0x00002000
476#define IPG_MC_COLLISION_DETECT 0x00010000
477#define IPG_MC_CARRIER_SENSE 0x00020000
478#define IPG_MC_STATISTICS_ENABLE 0x00200000
479#define IPG_MC_STATISTICS_DISABLE 0x00400000
480#define IPG_MC_STATISTICS_ENABLED 0x00800000
481#define IPG_MC_TX_ENABLE 0x01000000
482#define IPG_MC_TX_DISABLE 0x02000000
483#define IPG_MC_TX_ENABLED 0x04000000
484#define IPG_MC_RX_ENABLE 0x08000000
485#define IPG_MC_RX_DISABLE 0x10000000
486#define IPG_MC_RX_ENABLED 0x20000000
487#define IPG_MC_PAUSED 0x40000000
488
489/*
490 * Tune
491 */
492
493/* Miscellaneous Constants. */
494#define TRUE 1
495#define FALSE 0
496
497/* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS append on TX. */
498#define IPG_APPEND_FCS_ON_TX TRUE
499
500/* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS strip on RX. */
501#define IPG_STRIP_FCS_ON_RX TRUE
502
503/* Assign IPG_DROP_ON_RX_ETH_ERRORS > 0 to drop RX frames with
504 * Ethernet errors.
505 */
506#define IPG_DROP_ON_RX_ETH_ERRORS TRUE
507
508/* Assign IPG_INSERT_MANUAL_VLAN_TAG > 0 to insert VLAN tags manually
509 * (via TFC).
510 */
511#define IPG_INSERT_MANUAL_VLAN_TAG FALSE
512
513/* Assign IPG_ADD_IPCHECKSUM_ON_TX > 0 for auto IP checksum on TX. */
514#define IPG_ADD_IPCHECKSUM_ON_TX FALSE
515
516/* Assign IPG_ADD_TCPCHECKSUM_ON_TX > 0 for auto TCP checksum on TX.
517 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
518 */
519#define IPG_ADD_TCPCHECKSUM_ON_TX FALSE
520
521/* Assign IPG_ADD_UDPCHECKSUM_ON_TX > 0 for auto UDP checksum on TX.
522 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
523 */
524#define IPG_ADD_UDPCHECKSUM_ON_TX FALSE
525
526/* If inserting VLAN tags manually, assign the IPG_MANUAL_VLAN_xx
527 * constants as desired.
528 */
529#define IPG_MANUAL_VLAN_VID 0xABC
530#define IPG_MANUAL_VLAN_CFI 0x1
531#define IPG_MANUAL_VLAN_USERPRIORITY 0x5
532
533#define IPG_IO_REG_RANGE 0xFF
534#define IPG_MEM_REG_RANGE 0x154
535#define IPG_DRIVER_NAME "Sundance Technology IPG Triple-Speed Ethernet"
536#define IPG_NIC_PHY_ADDRESS 0x01
537#define IPG_DMALIST_ALIGN_PAD 0x07
538#define IPG_MULTICAST_HASHTABLE_SIZE 0x40
539
540/* Number of miliseconds to wait after issuing a software reset.
541 * 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
542 */
543#define IPG_AC_RESETWAIT 0x05
544
545/* Number of IPG_AC_RESETWAIT timeperiods before declaring timeout. */
546#define IPG_AC_RESET_TIMEOUT 0x0A
547
548/* Minimum number of nanoseconds used to toggle MDC clock during
549 * MII/GMII register access.
550 */
551#define IPG_PC_PHYCTRLWAIT_NS 200
552
553#define IPG_TFDLIST_LENGTH 0x100
554
555/* Number of frames between TxDMAComplete interrupt.
556 * 0 < IPG_FRAMESBETWEENTXDMACOMPLETES <= IPG_TFDLIST_LENGTH
557 */
558#define IPG_FRAMESBETWEENTXDMACOMPLETES 0x1
559
560#ifdef JUMBO_FRAME
561
562# ifdef JUMBO_FRAME_SIZE_2K
563# define JUMBO_FRAME_SIZE 2048
564# define __IPG_RXFRAG_SIZE 2048
565# else
566# ifdef JUMBO_FRAME_SIZE_3K
567# define JUMBO_FRAME_SIZE 3072
568# define __IPG_RXFRAG_SIZE 3072
569# else
570# ifdef JUMBO_FRAME_SIZE_4K
571# define JUMBO_FRAME_SIZE 4096
572# define __IPG_RXFRAG_SIZE 4088
573# else
574# ifdef JUMBO_FRAME_SIZE_5K
575# define JUMBO_FRAME_SIZE 5120
576# define __IPG_RXFRAG_SIZE 4088
577# else
578# ifdef JUMBO_FRAME_SIZE_6K
579# define JUMBO_FRAME_SIZE 6144
580# define __IPG_RXFRAG_SIZE 4088
581# else
582# ifdef JUMBO_FRAME_SIZE_7K
583# define JUMBO_FRAME_SIZE 7168
584# define __IPG_RXFRAG_SIZE 4088
585# else
586# ifdef JUMBO_FRAME_SIZE_8K
587# define JUMBO_FRAME_SIZE 8192
588# define __IPG_RXFRAG_SIZE 4088
589# else
590# ifdef JUMBO_FRAME_SIZE_9K
591# define JUMBO_FRAME_SIZE 9216
592# define __IPG_RXFRAG_SIZE 4088
593# else
594# ifdef JUMBO_FRAME_SIZE_10K
595# define JUMBO_FRAME_SIZE 10240
596# define __IPG_RXFRAG_SIZE 4088
597# else
598# define JUMBO_FRAME_SIZE 4096
599# endif
600# endif
601# endif
602# endif
603# endif
604# endif
605# endif
606# endif
607# endif
608#endif
609
610/* Size of allocated received buffers. Nominally 0x0600.
611 * Define larger if expecting jumbo frames.
612 */
613#ifdef JUMBO_FRAME
614//IPG_TXFRAG_SIZE must <= 0x2b00, or TX will crash
615#define IPG_TXFRAG_SIZE JUMBO_FRAME_SIZE
616#endif
617
618/* Size of allocated received buffers. Nominally 0x0600.
619 * Define larger if expecting jumbo frames.
620 */
621#ifdef JUMBO_FRAME
622//4088=4096-8
623#define IPG_RXFRAG_SIZE __IPG_RXFRAG_SIZE
624#define IPG_RXSUPPORT_SIZE IPG_MAX_RXFRAME_SIZE
625#else
626#define IPG_RXFRAG_SIZE 0x0600
627#define IPG_RXSUPPORT_SIZE IPG_RXFRAG_SIZE
628#endif
629
630/* IPG_MAX_RXFRAME_SIZE <= IPG_RXFRAG_SIZE */
631#ifdef JUMBO_FRAME
632#define IPG_MAX_RXFRAME_SIZE JUMBO_FRAME_SIZE
633#else
634#define IPG_MAX_RXFRAME_SIZE 0x0600
635#endif
636
637#define IPG_RFDLIST_LENGTH 0x100
638
639/* Maximum number of RFDs to process per interrupt.
640 * 1 < IPG_MAXRFDPROCESS_COUNT < IPG_RFDLIST_LENGTH
641 */
642#define IPG_MAXRFDPROCESS_COUNT 0x80
643
644/* Minimum margin between last freed RFD, and current RFD.
645 * 1 < IPG_MINUSEDRFDSTOFREE < IPG_RFDLIST_LENGTH
646 */
647#define IPG_MINUSEDRFDSTOFREE 0x80
648
649/* specify the jumbo frame maximum size
650 * per unit is 0x600 (the RxBuffer size that one RFD can carry)
651 */
652#define MAX_JUMBOSIZE 0x8 // max is 12K
653
654/* Key register values loaded at driver start up. */
655
656/* TXDMAPollPeriod is specified in 320ns increments.
657 *
658 * Value Time
659 * ---------------------
660 * 0x00-0x01 320ns
661 * 0x03 ~1us
662 * 0x1F ~10us
663 * 0xFF ~82us
664 */
665#define IPG_TXDMAPOLLPERIOD_VALUE 0x26
666
667/* TxDMAUrgentThresh specifies the minimum amount of
668 * data in the transmit FIFO before asserting an
669 * urgent transmit DMA request.
670 *
671 * Value Min TxFIFO occupied space before urgent TX request
672 * ---------------------------------------------------------------
673 * 0x00-0x04 128 bytes (1024 bits)
674 * 0x27 1248 bytes (~10000 bits)
675 * 0x30 1536 bytes (12288 bits)
676 * 0xFF 8192 bytes (65535 bits)
677 */
678#define IPG_TXDMAURGENTTHRESH_VALUE 0x04
679
680/* TxDMABurstThresh specifies the minimum amount of
681 * free space in the transmit FIFO before asserting an
682 * transmit DMA request.
683 *
684 * Value Min TxFIFO free space before TX request
685 * ----------------------------------------------------
686 * 0x00-0x08 256 bytes
687 * 0x30 1536 bytes
688 * 0xFF 8192 bytes
689 */
690#define IPG_TXDMABURSTTHRESH_VALUE 0x30
691
692/* RXDMAPollPeriod is specified in 320ns increments.
693 *
694 * Value Time
695 * ---------------------
696 * 0x00-0x01 320ns
697 * 0x03 ~1us
698 * 0x1F ~10us
699 * 0xFF ~82us
700 */
701#define IPG_RXDMAPOLLPERIOD_VALUE 0x01
702
703/* RxDMAUrgentThresh specifies the minimum amount of
704 * free space within the receive FIFO before asserting
705 * a urgent receive DMA request.
706 *
707 * Value Min RxFIFO free space before urgent RX request
708 * ---------------------------------------------------------------
709 * 0x00-0x04 128 bytes (1024 bits)
710 * 0x27 1248 bytes (~10000 bits)
711 * 0x30 1536 bytes (12288 bits)
712 * 0xFF 8192 bytes (65535 bits)
713 */
714#define IPG_RXDMAURGENTTHRESH_VALUE 0x30
715
716/* RxDMABurstThresh specifies the minimum amount of
717 * occupied space within the receive FIFO before asserting
718 * a receive DMA request.
719 *
720 * Value Min TxFIFO free space before TX request
721 * ----------------------------------------------------
722 * 0x00-0x08 256 bytes
723 * 0x30 1536 bytes
724 * 0xFF 8192 bytes
725 */
726#define IPG_RXDMABURSTTHRESH_VALUE 0x30
727
728/* FlowOnThresh specifies the maximum amount of occupied
729 * space in the receive FIFO before a PAUSE frame with
730 * maximum pause time transmitted.
731 *
732 * Value Max RxFIFO occupied space before PAUSE
733 * ---------------------------------------------------
734 * 0x0000 0 bytes
735 * 0x0740 29,696 bytes
736 * 0x07FF 32,752 bytes
737 */
738#define IPG_FLOWONTHRESH_VALUE 0x0740
739
740/* FlowOffThresh specifies the minimum amount of occupied
741 * space in the receive FIFO before a PAUSE frame with
742 * zero pause time is transmitted.
743 *
744 * Value Max RxFIFO occupied space before PAUSE
745 * ---------------------------------------------------
746 * 0x0000 0 bytes
747 * 0x00BF 3056 bytes
748 * 0x07FF 32,752 bytes
749 */
750#define IPG_FLOWOFFTHRESH_VALUE 0x00BF
751
752/*
753 * Miscellaneous macros.
754 */
755
756/* Marco for printing debug statements.
757# define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " ## args) */
758#ifdef IPG_DEBUG
759# define IPG_DEBUG_MSG(args...)
760# define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " args)
761# define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args)
762# define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args)
763#else
764# define IPG_DEBUG_MSG(args...)
765# define IPG_DDEBUG_MSG(args...)
766# define IPG_DUMPRFDLIST(args)
767# define IPG_DUMPTFDLIST(args)
768#endif
769
770/*
771 * End miscellaneous macros.
772 */
773
774/* Transmit Frame Descriptor. The IPG supports 15 fragments,
775 * however Linux requires only a single fragment. Note, each
776 * TFD field is 64 bits wide.
777 */
778struct ipg_tx {
Al Viro857e37d2007-10-14 19:41:19 +0100779 __le64 next_desc;
780 __le64 tfc;
781 __le64 frag_info;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700782};
783
784/* Receive Frame Descriptor. Note, each RFD field is 64 bits wide.
785 */
786struct ipg_rx {
Al Viro857e37d2007-10-14 19:41:19 +0100787 __le64 next_desc;
788 __le64 rfs;
789 __le64 frag_info;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700790};
791
792struct SJumbo {
793 int FoundStart;
794 int CurrentSize;
795 struct sk_buff *skb;
796};
797/* Structure of IPG NIC specific data. */
798struct ipg_nic_private {
799 void __iomem *ioaddr;
800 struct ipg_tx *txd;
801 struct ipg_rx *rxd;
802 dma_addr_t txd_map;
803 dma_addr_t rxd_map;
804 struct sk_buff *TxBuff[IPG_TFDLIST_LENGTH];
805 struct sk_buff *RxBuff[IPG_RFDLIST_LENGTH];
806 unsigned int tx_current;
807 unsigned int tx_dirty;
808 unsigned int rx_current;
809 unsigned int rx_dirty;
810// Add by Grace 2005/05/19
811#ifdef JUMBO_FRAME
812 struct SJumbo Jumbo;
813#endif
814 unsigned int rx_buf_sz;
815 struct pci_dev *pdev;
816 struct net_device *dev;
817 struct net_device_stats stats;
818 spinlock_t lock;
819 int tenmbpsmode;
820
821 /*Jesse20040128EEPROM_VALUE */
822 u16 LED_Mode;
823 u16 station_addr[3]; /* Station Address in EEPROM Reg 0x10..0x12 */
824
825 struct mutex mii_mutex;
826 struct mii_if_info mii_if;
827 int ResetCurrentTFD;
828#ifdef IPG_DEBUG
829 int RFDlistendCount;
830 int RFDListCheckedCount;
831 int EmptyRFDListCount;
832#endif
833 struct delayed_work task;
834};
835
836//variable record -- index by leading revision/length
837//Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
838unsigned short DefaultPhyParam[] = {
839 // 11/12/03 IP1000A v1-3 rev=0x40
840 /*--------------------------------------------------------------------------
841 (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
842 27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
843 31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7, 9, 0x0700,
844 --------------------------------------------------------------------------*/
845 // 12/17/03 IP1000A v1-4 rev=0x40
846 (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
847 0x0000,
848 30, 0x005e, 9, 0x0700,
849 // 01/09/04 IP1000A v1-5 rev=0x41
850 (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
851 0x0000,
852 30, 0x005e, 9, 0x0700,
853 0x0000
854};
855
856#endif /* __LINUX_IPG_H */