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Mark Lordedea3ab2005-10-10 17:53:58 -04001/*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Mark Lord
7 *
Jeff Garzik68399bb2005-10-11 01:44:14 -04008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
Mark Lordedea3ab2005-10-10 17:53:58 -040012 *
Jeff Garzik68399bb2005-10-11 01:44:14 -040013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
Mark Lordedea3ab2005-10-10 17:53:58 -040026 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050042#include <linux/device.h>
Mark Lordedea3ab2005-10-10 17:53:58 -040043#include <scsi/scsi_host.h>
Mark Lordedea3ab2005-10-10 17:53:58 -040044#include <linux/libata.h>
45
46#define DRV_NAME "pdc_adma"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040047#define DRV_VERSION "1.0"
Mark Lordedea3ab2005-10-10 17:53:58 -040048
49/* macro to calculate base address for ATA regs */
50#define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40))
51
52/* macro to calculate base address for ADMA regs */
Tejun Heo0d5ff562007-02-01 15:06:36 +090053#define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20))
54
Tejun Heo5d728822007-04-17 23:44:08 +090055/* macro to obtain addresses from ata_port */
56#define ADMA_PORT_REGS(ap) \
57 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
Mark Lordedea3ab2005-10-10 17:53:58 -040058
59enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090060 ADMA_MMIO_BAR = 4,
61
Mark Lordedea3ab2005-10-10 17:53:58 -040062 ADMA_PORTS = 2,
63 ADMA_CPB_BYTES = 40,
64 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
65 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
66
67 ADMA_DMA_BOUNDARY = 0xffffffff,
68
69 /* global register offsets */
70 ADMA_MODE_LOCK = 0x00c7,
71
72 /* per-channel register offsets */
73 ADMA_CONTROL = 0x0000, /* ADMA control */
74 ADMA_STATUS = 0x0002, /* ADMA status */
75 ADMA_CPB_COUNT = 0x0004, /* CPB count */
76 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
77 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
78 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
79 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
80 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
81
82 /* ADMA_CONTROL register bits */
83 aNIEN = (1 << 8), /* irq mask: 1==masked */
84 aGO = (1 << 7), /* packet trigger ("Go!") */
85 aRSTADM = (1 << 5), /* ADMA logic reset */
Mark Lordedea3ab2005-10-10 17:53:58 -040086 aPIOMD4 = 0x0003, /* PIO mode 4 */
87
88 /* ADMA_STATUS register bits */
89 aPSD = (1 << 6),
90 aUIRQ = (1 << 4),
91 aPERR = (1 << 0),
92
93 /* CPB bits */
94 cDONE = (1 << 0),
Jeff Garzik640fdb52007-08-03 11:10:07 -040095 cATERR = (1 << 3),
96
Mark Lordedea3ab2005-10-10 17:53:58 -040097 cVLD = (1 << 0),
98 cDAT = (1 << 2),
99 cIEN = (1 << 3),
100
101 /* PRD bits */
102 pORD = (1 << 4),
103 pDIRO = (1 << 5),
104 pEND = (1 << 7),
105
106 /* ATA register flags */
107 rIGN = (1 << 5),
108 rEND = (1 << 7),
109
110 /* ATA register addresses */
111 ADMA_REGS_CONTROL = 0x0e,
112 ADMA_REGS_SECTOR_COUNT = 0x12,
113 ADMA_REGS_LBA_LOW = 0x13,
114 ADMA_REGS_LBA_MID = 0x14,
115 ADMA_REGS_LBA_HIGH = 0x15,
116 ADMA_REGS_DEVICE = 0x16,
117 ADMA_REGS_COMMAND = 0x17,
118
119 /* PCI device IDs */
120 board_1841_idx = 0, /* ADMA 2-port controller */
121};
122
123typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
124
125struct adma_port_priv {
126 u8 *pkt;
127 dma_addr_t pkt_dma;
128 adma_state_t state;
129};
130
131static int adma_ata_init_one (struct pci_dev *pdev,
132 const struct pci_device_id *ent);
Mark Lordedea3ab2005-10-10 17:53:58 -0400133static int adma_port_start(struct ata_port *ap);
Jeff Garzikcca39742006-08-24 03:19:22 -0400134static void adma_host_stop(struct ata_host *host);
Mark Lordedea3ab2005-10-10 17:53:58 -0400135static void adma_port_stop(struct ata_port *ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400136static void adma_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900137static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
Mark Lordedea3ab2005-10-10 17:53:58 -0400138static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
139static void adma_bmdma_stop(struct ata_queued_cmd *qc);
140static u8 adma_bmdma_status(struct ata_port *ap);
141static void adma_irq_clear(struct ata_port *ap);
Jeff Garzik640fdb52007-08-03 11:10:07 -0400142static void adma_freeze(struct ata_port *ap);
143static void adma_thaw(struct ata_port *ap);
144static void adma_error_handler(struct ata_port *ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400145
Jeff Garzik193515d2005-11-07 00:59:37 -0500146static struct scsi_host_template adma_ata_sht = {
Mark Lordedea3ab2005-10-10 17:53:58 -0400147 .module = THIS_MODULE,
148 .name = DRV_NAME,
149 .ioctl = ata_scsi_ioctl,
150 .queuecommand = ata_scsi_queuecmd,
Mark Lordedea3ab2005-10-10 17:53:58 -0400151 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900152 .slave_destroy = ata_scsi_slave_destroy,
Mark Lordedea3ab2005-10-10 17:53:58 -0400153 .bios_param = ata_std_bios_param,
Jeff Garzik49de0ac2007-05-26 18:20:51 -0400154 .proc_name = DRV_NAME,
155 .can_queue = ATA_DEF_QUEUE,
156 .this_id = ATA_SHT_THIS_ID,
157 .sg_tablesize = LIBATA_MAX_PRD,
158 .dma_boundary = ADMA_DMA_BOUNDARY,
159 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
160 .use_clustering = ENABLE_CLUSTERING,
161 .emulated = ATA_SHT_EMULATED,
Mark Lordedea3ab2005-10-10 17:53:58 -0400162};
163
Jeff Garzik057ace52005-10-22 14:27:05 -0400164static const struct ata_port_operations adma_ata_ops = {
Mark Lordedea3ab2005-10-10 17:53:58 -0400165 .tf_load = ata_tf_load,
166 .tf_read = ata_tf_read,
Mark Lordedea3ab2005-10-10 17:53:58 -0400167 .exec_command = ata_exec_command,
Jeff Garzik49de0ac2007-05-26 18:20:51 -0400168 .check_status = ata_check_status,
Mark Lordedea3ab2005-10-10 17:53:58 -0400169 .dev_select = ata_std_dev_select,
Jeff Garzik49de0ac2007-05-26 18:20:51 -0400170 .check_atapi_dma = adma_check_atapi_dma,
171 .data_xfer = ata_data_xfer,
Mark Lordedea3ab2005-10-10 17:53:58 -0400172 .qc_prep = adma_qc_prep,
173 .qc_issue = adma_qc_issue,
Jeff Garzik640fdb52007-08-03 11:10:07 -0400174 .freeze = adma_freeze,
175 .thaw = adma_thaw,
176 .error_handler = adma_error_handler,
Mark Lordedea3ab2005-10-10 17:53:58 -0400177 .irq_clear = adma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900178 .irq_on = ata_irq_on,
Mark Lordedea3ab2005-10-10 17:53:58 -0400179 .port_start = adma_port_start,
180 .port_stop = adma_port_stop,
181 .host_stop = adma_host_stop,
182 .bmdma_stop = adma_bmdma_stop,
183 .bmdma_status = adma_bmdma_status,
184};
185
186static struct ata_port_info adma_port_info[] = {
187 /* board_1841_idx */
188 {
Jeff Garzik640fdb52007-08-03 11:10:07 -0400189 .flags = ATA_FLAG_SLAVE_POSS |
Albert Lee51704c62006-08-09 18:36:22 +0800190 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
191 ATA_FLAG_PIO_POLLING,
Mark Lordedea3ab2005-10-10 17:53:58 -0400192 .pio_mask = 0x10, /* pio4 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400193 .udma_mask = ATA_UDMA4,
Mark Lordedea3ab2005-10-10 17:53:58 -0400194 .port_ops = &adma_ata_ops,
195 },
196};
197
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500198static const struct pci_device_id adma_ata_pci_tbl[] = {
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400199 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
Mark Lordedea3ab2005-10-10 17:53:58 -0400200
201 { } /* terminate list */
202};
203
204static struct pci_driver adma_ata_pci_driver = {
205 .name = DRV_NAME,
206 .id_table = adma_ata_pci_tbl,
207 .probe = adma_ata_init_one,
208 .remove = ata_pci_remove_one,
209};
210
211static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
212{
213 return 1; /* ATAPI DMA not yet supported */
214}
215
216static void adma_bmdma_stop(struct ata_queued_cmd *qc)
217{
218 /* nothing */
219}
220
221static u8 adma_bmdma_status(struct ata_port *ap)
222{
223 return 0;
224}
225
226static void adma_irq_clear(struct ata_port *ap)
227{
228 /* nothing */
229}
230
Tejun Heo5d728822007-04-17 23:44:08 +0900231static void adma_reset_engine(struct ata_port *ap)
Mark Lordedea3ab2005-10-10 17:53:58 -0400232{
Tejun Heo5d728822007-04-17 23:44:08 +0900233 void __iomem *chan = ADMA_PORT_REGS(ap);
234
Mark Lordedea3ab2005-10-10 17:53:58 -0400235 /* reset ADMA to idle state */
236 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
237 udelay(2);
238 writew(aPIOMD4, chan + ADMA_CONTROL);
239 udelay(2);
240}
241
242static void adma_reinit_engine(struct ata_port *ap)
243{
244 struct adma_port_priv *pp = ap->private_data;
Tejun Heo5d728822007-04-17 23:44:08 +0900245 void __iomem *chan = ADMA_PORT_REGS(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400246
247 /* mask/clear ATA interrupts */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900248 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
Mark Lordedea3ab2005-10-10 17:53:58 -0400249 ata_check_status(ap);
250
251 /* reset the ADMA engine */
Tejun Heo5d728822007-04-17 23:44:08 +0900252 adma_reset_engine(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400253
254 /* set in-FIFO threshold to 0x100 */
255 writew(0x100, chan + ADMA_FIFO_IN);
256
257 /* set CPB pointer */
258 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
259
260 /* set out-FIFO threshold to 0x100 */
261 writew(0x100, chan + ADMA_FIFO_OUT);
262
263 /* set CPB count */
264 writew(1, chan + ADMA_CPB_COUNT);
265
266 /* read/discard ADMA status */
267 readb(chan + ADMA_STATUS);
268}
269
270static inline void adma_enter_reg_mode(struct ata_port *ap)
271{
Tejun Heo5d728822007-04-17 23:44:08 +0900272 void __iomem *chan = ADMA_PORT_REGS(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400273
274 writew(aPIOMD4, chan + ADMA_CONTROL);
275 readb(chan + ADMA_STATUS); /* flush */
276}
277
Jeff Garzik640fdb52007-08-03 11:10:07 -0400278static void adma_freeze(struct ata_port *ap)
Mark Lordedea3ab2005-10-10 17:53:58 -0400279{
Jeff Garzik640fdb52007-08-03 11:10:07 -0400280 void __iomem *chan = ADMA_PORT_REGS(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400281
Jeff Garzik640fdb52007-08-03 11:10:07 -0400282 /* mask/clear ATA interrupts */
283 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
284 ata_check_status(ap);
285
286 /* reset ADMA to idle state */
287 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
288 udelay(2);
289 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
290 udelay(2);
Mark Lordedea3ab2005-10-10 17:53:58 -0400291}
292
Jeff Garzik640fdb52007-08-03 11:10:07 -0400293static void adma_thaw(struct ata_port *ap)
294{
295 adma_reinit_engine(ap);
296}
297
Tejun Heo02607312007-08-06 18:36:23 +0900298static int adma_prereset(struct ata_link *link, unsigned long deadline)
Mark Lordedea3ab2005-10-10 17:53:58 -0400299{
Tejun Heo02607312007-08-06 18:36:23 +0900300 struct ata_port *ap = link->ap;
Mark Lordedea3ab2005-10-10 17:53:58 -0400301 struct adma_port_priv *pp = ap->private_data;
302
303 if (pp->state != adma_state_idle) /* healthy paranoia */
304 pp->state = adma_state_mmio;
305 adma_reinit_engine(ap);
Jeff Garzik640fdb52007-08-03 11:10:07 -0400306
Tejun Heo02607312007-08-06 18:36:23 +0900307 return ata_std_prereset(link, deadline);
Jeff Garzik640fdb52007-08-03 11:10:07 -0400308}
309
310static void adma_error_handler(struct ata_port *ap)
311{
312 ata_do_eh(ap, adma_prereset, ata_std_softreset, NULL,
313 ata_std_postreset);
Mark Lordedea3ab2005-10-10 17:53:58 -0400314}
315
316static int adma_fill_sg(struct ata_queued_cmd *qc)
317{
Jeff Garzik972c26b2005-10-18 22:14:54 -0400318 struct scatterlist *sg;
Mark Lordedea3ab2005-10-10 17:53:58 -0400319 struct ata_port *ap = qc->ap;
320 struct adma_port_priv *pp = ap->private_data;
321 u8 *buf = pp->pkt;
Jeff Garzik972c26b2005-10-18 22:14:54 -0400322 int i = (2 + buf[3]) * 8;
Mark Lordedea3ab2005-10-10 17:53:58 -0400323 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
324
Jeff Garzik972c26b2005-10-18 22:14:54 -0400325 ata_for_each_sg(sg, qc) {
Mark Lordedea3ab2005-10-10 17:53:58 -0400326 u32 addr;
327 u32 len;
328
329 addr = (u32)sg_dma_address(sg);
330 *(__le32 *)(buf + i) = cpu_to_le32(addr);
331 i += 4;
332
333 len = sg_dma_len(sg) >> 3;
334 *(__le32 *)(buf + i) = cpu_to_le32(len);
335 i += 4;
336
Jeff Garzik972c26b2005-10-18 22:14:54 -0400337 if (ata_sg_is_last(sg, qc))
Mark Lordedea3ab2005-10-10 17:53:58 -0400338 pFLAGS |= pEND;
339 buf[i++] = pFLAGS;
340 buf[i++] = qc->dev->dma_mode & 0xf;
341 buf[i++] = 0; /* pPKLW */
342 buf[i++] = 0; /* reserved */
343
344 *(__le32 *)(buf + i)
345 = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
346 i += 4;
347
Alan Coxdb7f44d2006-03-21 15:54:24 +0000348 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
Mark Lordedea3ab2005-10-10 17:53:58 -0400349 (unsigned long)addr, len);
350 }
351 return i;
352}
353
354static void adma_qc_prep(struct ata_queued_cmd *qc)
355{
356 struct adma_port_priv *pp = qc->ap->private_data;
357 u8 *buf = pp->pkt;
358 u32 pkt_dma = (u32)pp->pkt_dma;
359 int i = 0;
360
361 VPRINTK("ENTER\n");
362
363 adma_enter_reg_mode(qc->ap);
364 if (qc->tf.protocol != ATA_PROT_DMA) {
365 ata_qc_prep(qc);
366 return;
367 }
368
369 buf[i++] = 0; /* Response flags */
370 buf[i++] = 0; /* reserved */
371 buf[i++] = cVLD | cDAT | cIEN;
372 i++; /* cLEN, gets filled in below */
373
374 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
375 i += 4; /* cNCPB */
376 i += 4; /* cPRD, gets filled in below */
377
378 buf[i++] = 0; /* reserved */
379 buf[i++] = 0; /* reserved */
380 buf[i++] = 0; /* reserved */
381 buf[i++] = 0; /* reserved */
382
383 /* ATA registers; must be a multiple of 4 */
384 buf[i++] = qc->tf.device;
385 buf[i++] = ADMA_REGS_DEVICE;
386 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
387 buf[i++] = qc->tf.hob_nsect;
388 buf[i++] = ADMA_REGS_SECTOR_COUNT;
389 buf[i++] = qc->tf.hob_lbal;
390 buf[i++] = ADMA_REGS_LBA_LOW;
391 buf[i++] = qc->tf.hob_lbam;
392 buf[i++] = ADMA_REGS_LBA_MID;
393 buf[i++] = qc->tf.hob_lbah;
394 buf[i++] = ADMA_REGS_LBA_HIGH;
395 }
396 buf[i++] = qc->tf.nsect;
397 buf[i++] = ADMA_REGS_SECTOR_COUNT;
398 buf[i++] = qc->tf.lbal;
399 buf[i++] = ADMA_REGS_LBA_LOW;
400 buf[i++] = qc->tf.lbam;
401 buf[i++] = ADMA_REGS_LBA_MID;
402 buf[i++] = qc->tf.lbah;
403 buf[i++] = ADMA_REGS_LBA_HIGH;
404 buf[i++] = 0;
405 buf[i++] = ADMA_REGS_CONTROL;
406 buf[i++] = rIGN;
407 buf[i++] = 0;
408 buf[i++] = qc->tf.command;
409 buf[i++] = ADMA_REGS_COMMAND | rEND;
410
411 buf[3] = (i >> 3) - 2; /* cLEN */
412 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
413
414 i = adma_fill_sg(qc);
415 wmb(); /* flush PRDs and pkt to memory */
416#if 0
417 /* dump out CPB + PRDs for debug */
418 {
419 int j, len = 0;
420 static char obuf[2048];
421 for (j = 0; j < i; ++j) {
422 len += sprintf(obuf+len, "%02x ", buf[j]);
423 if ((j & 7) == 7) {
424 printk("%s\n", obuf);
425 len = 0;
426 }
427 }
428 if (len)
429 printk("%s\n", obuf);
430 }
431#endif
432}
433
434static inline void adma_packet_start(struct ata_queued_cmd *qc)
435{
436 struct ata_port *ap = qc->ap;
Tejun Heo5d728822007-04-17 23:44:08 +0900437 void __iomem *chan = ADMA_PORT_REGS(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400438
439 VPRINTK("ENTER, ap %p\n", ap);
440
441 /* fire up the ADMA engine */
Jeff Garzik68399bb2005-10-11 01:44:14 -0400442 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
Mark Lordedea3ab2005-10-10 17:53:58 -0400443}
444
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900445static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
Mark Lordedea3ab2005-10-10 17:53:58 -0400446{
447 struct adma_port_priv *pp = qc->ap->private_data;
448
449 switch (qc->tf.protocol) {
450 case ATA_PROT_DMA:
451 pp->state = adma_state_pkt;
452 adma_packet_start(qc);
453 return 0;
454
455 case ATA_PROT_ATAPI_DMA:
456 BUG();
457 break;
458
459 default:
460 break;
461 }
462
463 pp->state = adma_state_mmio;
464 return ata_qc_issue_prot(qc);
465}
466
Jeff Garzikcca39742006-08-24 03:19:22 -0400467static inline unsigned int adma_intr_pkt(struct ata_host *host)
Mark Lordedea3ab2005-10-10 17:53:58 -0400468{
469 unsigned int handled = 0, port_no;
Mark Lordedea3ab2005-10-10 17:53:58 -0400470
Jeff Garzikcca39742006-08-24 03:19:22 -0400471 for (port_no = 0; port_no < host->n_ports; ++port_no) {
472 struct ata_port *ap = host->ports[port_no];
Mark Lordedea3ab2005-10-10 17:53:58 -0400473 struct adma_port_priv *pp;
474 struct ata_queued_cmd *qc;
Tejun Heo5d728822007-04-17 23:44:08 +0900475 void __iomem *chan = ADMA_PORT_REGS(ap);
Jeff Garzika7dac442005-10-30 04:44:42 -0500476 u8 status = readb(chan + ADMA_STATUS);
Mark Lordedea3ab2005-10-10 17:53:58 -0400477
478 if (status == 0)
479 continue;
480 handled = 1;
481 adma_enter_reg_mode(ap);
Jeff Garzik029f5462006-04-02 10:30:40 -0400482 if (ap->flags & ATA_FLAG_DISABLED)
Mark Lordedea3ab2005-10-10 17:53:58 -0400483 continue;
484 pp = ap->private_data;
485 if (!pp || pp->state != adma_state_pkt)
486 continue;
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900487 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Jeff Garzik94ec1ef2005-10-30 02:15:08 -0500488 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
Jeff Garzik640fdb52007-08-03 11:10:07 -0400489 if (status & aPERR)
490 qc->err_mask |= AC_ERR_HOST_BUS;
491 else if ((status & (aPSD | aUIRQ)))
Albert Leea22e2eb2005-12-05 15:38:02 +0800492 qc->err_mask |= AC_ERR_OTHER;
Jeff Garzik640fdb52007-08-03 11:10:07 -0400493
494 if (pp->pkt[0] & cATERR)
495 qc->err_mask |= AC_ERR_DEV;
Jeff Garzika21a84a2005-10-28 15:43:16 -0400496 else if (pp->pkt[0] != cDONE)
Albert Leea22e2eb2005-12-05 15:38:02 +0800497 qc->err_mask |= AC_ERR_OTHER;
Jeff Garzika7dac442005-10-30 04:44:42 -0500498
Jeff Garzik640fdb52007-08-03 11:10:07 -0400499 if (!qc->err_mask)
500 ata_qc_complete(qc);
501 else {
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900502 struct ata_eh_info *ehi = &ap->link.eh_info;
Jeff Garzik640fdb52007-08-03 11:10:07 -0400503 ata_ehi_clear_desc(ehi);
504 ata_ehi_push_desc(ehi,
505 "ADMA-status 0x%02X", status);
506 ata_ehi_push_desc(ehi,
507 "pkt[0] 0x%02X", pp->pkt[0]);
508
509 if (qc->err_mask == AC_ERR_DEV)
510 ata_port_abort(ap);
511 else
512 ata_port_freeze(ap);
513 }
Jeff Garzika21a84a2005-10-28 15:43:16 -0400514 }
Mark Lordedea3ab2005-10-10 17:53:58 -0400515 }
516 return handled;
517}
518
Jeff Garzikcca39742006-08-24 03:19:22 -0400519static inline unsigned int adma_intr_mmio(struct ata_host *host)
Mark Lordedea3ab2005-10-10 17:53:58 -0400520{
521 unsigned int handled = 0, port_no;
522
Jeff Garzikcca39742006-08-24 03:19:22 -0400523 for (port_no = 0; port_no < host->n_ports; ++port_no) {
Mark Lordedea3ab2005-10-10 17:53:58 -0400524 struct ata_port *ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400525 ap = host->ports[port_no];
Jeff Garzik029f5462006-04-02 10:30:40 -0400526 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
Mark Lordedea3ab2005-10-10 17:53:58 -0400527 struct ata_queued_cmd *qc;
528 struct adma_port_priv *pp = ap->private_data;
529 if (!pp || pp->state != adma_state_mmio)
530 continue;
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900531 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Jeff Garzikbe697c32005-10-18 21:27:34 -0400532 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
Mark Lordedea3ab2005-10-10 17:53:58 -0400533
534 /* check main status, clearing INTRQ */
Jeff Garzikac19bff2005-10-29 13:58:21 -0400535 u8 status = ata_check_status(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400536 if ((status & ATA_BUSY))
537 continue;
538 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
Tejun Heo44877b42007-02-21 01:06:51 +0900539 ap->print_id, qc->tf.protocol, status);
Jeff Garzik9bec2e32006-08-31 00:02:15 -0400540
Mark Lordedea3ab2005-10-10 17:53:58 -0400541 /* complete taskfile transaction */
542 pp->state = adma_state_idle;
Albert Leea22e2eb2005-12-05 15:38:02 +0800543 qc->err_mask |= ac_err_mask(status);
Jeff Garzik640fdb52007-08-03 11:10:07 -0400544 if (!qc->err_mask)
545 ata_qc_complete(qc);
546 else {
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900547 struct ata_eh_info *ehi =
548 &ap->link.eh_info;
Jeff Garzik640fdb52007-08-03 11:10:07 -0400549 ata_ehi_clear_desc(ehi);
550 ata_ehi_push_desc(ehi,
551 "status 0x%02X", status);
552
553 if (qc->err_mask == AC_ERR_DEV)
554 ata_port_abort(ap);
555 else
556 ata_port_freeze(ap);
557 }
Mark Lordedea3ab2005-10-10 17:53:58 -0400558 handled = 1;
559 }
560 }
561 }
562 return handled;
563}
564
David Howells7d12e782006-10-05 14:55:46 +0100565static irqreturn_t adma_intr(int irq, void *dev_instance)
Mark Lordedea3ab2005-10-10 17:53:58 -0400566{
Jeff Garzikcca39742006-08-24 03:19:22 -0400567 struct ata_host *host = dev_instance;
Mark Lordedea3ab2005-10-10 17:53:58 -0400568 unsigned int handled = 0;
569
570 VPRINTK("ENTER\n");
571
Jeff Garzikcca39742006-08-24 03:19:22 -0400572 spin_lock(&host->lock);
573 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
574 spin_unlock(&host->lock);
Mark Lordedea3ab2005-10-10 17:53:58 -0400575
576 VPRINTK("EXIT\n");
577
578 return IRQ_RETVAL(handled);
579}
580
Tejun Heo0d5ff562007-02-01 15:06:36 +0900581static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
Mark Lordedea3ab2005-10-10 17:53:58 -0400582{
583 port->cmd_addr =
584 port->data_addr = base + 0x000;
585 port->error_addr =
586 port->feature_addr = base + 0x004;
587 port->nsect_addr = base + 0x008;
588 port->lbal_addr = base + 0x00c;
589 port->lbam_addr = base + 0x010;
590 port->lbah_addr = base + 0x014;
591 port->device_addr = base + 0x018;
592 port->status_addr =
593 port->command_addr = base + 0x01c;
594 port->altstatus_addr =
595 port->ctl_addr = base + 0x038;
596}
597
598static int adma_port_start(struct ata_port *ap)
599{
Jeff Garzikcca39742006-08-24 03:19:22 -0400600 struct device *dev = ap->host->dev;
Mark Lordedea3ab2005-10-10 17:53:58 -0400601 struct adma_port_priv *pp;
602 int rc;
603
604 rc = ata_port_start(ap);
605 if (rc)
606 return rc;
607 adma_enter_reg_mode(ap);
Tejun Heo24dc5f32007-01-20 16:00:28 +0900608 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Mark Lordedea3ab2005-10-10 17:53:58 -0400609 if (!pp)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900610 return -ENOMEM;
611 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
612 GFP_KERNEL);
Mark Lordedea3ab2005-10-10 17:53:58 -0400613 if (!pp->pkt)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900614 return -ENOMEM;
Mark Lordedea3ab2005-10-10 17:53:58 -0400615 /* paranoia? */
616 if ((pp->pkt_dma & 7) != 0) {
617 printk("bad alignment for pp->pkt_dma: %08x\n",
618 (u32)pp->pkt_dma);
Tejun Heo24dc5f32007-01-20 16:00:28 +0900619 return -ENOMEM;
Mark Lordedea3ab2005-10-10 17:53:58 -0400620 }
621 memset(pp->pkt, 0, ADMA_PKT_BYTES);
622 ap->private_data = pp;
623 adma_reinit_engine(ap);
624 return 0;
Mark Lordedea3ab2005-10-10 17:53:58 -0400625}
626
627static void adma_port_stop(struct ata_port *ap)
628{
Tejun Heo5d728822007-04-17 23:44:08 +0900629 adma_reset_engine(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400630}
631
Jeff Garzikcca39742006-08-24 03:19:22 -0400632static void adma_host_stop(struct ata_host *host)
Mark Lordedea3ab2005-10-10 17:53:58 -0400633{
634 unsigned int port_no;
635
636 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
Tejun Heo5d728822007-04-17 23:44:08 +0900637 adma_reset_engine(host->ports[port_no]);
Mark Lordedea3ab2005-10-10 17:53:58 -0400638}
639
Tejun Heo5d728822007-04-17 23:44:08 +0900640static void adma_host_init(struct ata_host *host, unsigned int chip_id)
Mark Lordedea3ab2005-10-10 17:53:58 -0400641{
642 unsigned int port_no;
Mark Lordedea3ab2005-10-10 17:53:58 -0400643
644 /* enable/lock aGO operation */
Tejun Heo5d728822007-04-17 23:44:08 +0900645 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
Mark Lordedea3ab2005-10-10 17:53:58 -0400646
647 /* reset the ADMA logic */
648 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
Tejun Heo5d728822007-04-17 23:44:08 +0900649 adma_reset_engine(host->ports[port_no]);
Mark Lordedea3ab2005-10-10 17:53:58 -0400650}
651
652static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
653{
654 int rc;
655
656 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
657 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500658 dev_printk(KERN_ERR, &pdev->dev,
659 "32-bit DMA enable failed\n");
Mark Lordedea3ab2005-10-10 17:53:58 -0400660 return rc;
661 }
662 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
663 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500664 dev_printk(KERN_ERR, &pdev->dev,
665 "32-bit consistent DMA enable failed\n");
Mark Lordedea3ab2005-10-10 17:53:58 -0400666 return rc;
667 }
668 return 0;
669}
670
671static int adma_ata_init_one(struct pci_dev *pdev,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900672 const struct pci_device_id *ent)
Mark Lordedea3ab2005-10-10 17:53:58 -0400673{
674 static int printed_version;
Mark Lordedea3ab2005-10-10 17:53:58 -0400675 unsigned int board_idx = (unsigned int) ent->driver_data;
Tejun Heo5d728822007-04-17 23:44:08 +0900676 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
677 struct ata_host *host;
678 void __iomem *mmio_base;
Mark Lordedea3ab2005-10-10 17:53:58 -0400679 int rc, port_no;
680
681 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500682 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Mark Lordedea3ab2005-10-10 17:53:58 -0400683
Tejun Heo5d728822007-04-17 23:44:08 +0900684 /* alloc host */
685 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
686 if (!host)
687 return -ENOMEM;
688
689 /* acquire resources and fill host */
Tejun Heo24dc5f32007-01-20 16:00:28 +0900690 rc = pcim_enable_device(pdev);
Mark Lordedea3ab2005-10-10 17:53:58 -0400691 if (rc)
692 return rc;
693
Tejun Heo24dc5f32007-01-20 16:00:28 +0900694 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
695 return -ENODEV;
Mark Lordedea3ab2005-10-10 17:53:58 -0400696
Tejun Heo0d5ff562007-02-01 15:06:36 +0900697 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
698 if (rc)
699 return rc;
Tejun Heo5d728822007-04-17 23:44:08 +0900700 host->iomap = pcim_iomap_table(pdev);
701 mmio_base = host->iomap[ADMA_MMIO_BAR];
Mark Lordedea3ab2005-10-10 17:53:58 -0400702
703 rc = adma_set_dma_masks(pdev, mmio_base);
704 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900705 return rc;
Mark Lordedea3ab2005-10-10 17:53:58 -0400706
Tejun Heocbcdd872007-08-18 13:14:55 +0900707 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
708 struct ata_port *ap = host->ports[port_no];
709 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
710 unsigned int offset = port_base - mmio_base;
711
712 adma_ata_setup_port(&ap->ioaddr, port_base);
713
714 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
715 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
716 }
Mark Lordedea3ab2005-10-10 17:53:58 -0400717
718 /* initialize adapter */
Tejun Heo5d728822007-04-17 23:44:08 +0900719 adma_host_init(host, board_idx);
Mark Lordedea3ab2005-10-10 17:53:58 -0400720
Tejun Heo5d728822007-04-17 23:44:08 +0900721 pci_set_master(pdev);
722 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
723 &adma_ata_sht);
Mark Lordedea3ab2005-10-10 17:53:58 -0400724}
725
726static int __init adma_ata_init(void)
727{
Pavel Roskinb7887192006-08-10 18:13:18 +0900728 return pci_register_driver(&adma_ata_pci_driver);
Mark Lordedea3ab2005-10-10 17:53:58 -0400729}
730
731static void __exit adma_ata_exit(void)
732{
733 pci_unregister_driver(&adma_ata_pci_driver);
734}
735
736MODULE_AUTHOR("Mark Lord");
737MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
738MODULE_LICENSE("GPL");
739MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
740MODULE_VERSION(DRV_VERSION);
741
742module_init(adma_ata_init);
743module_exit(adma_ata_exit);