Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 1 | # |
| 2 | # DMA engine configuration |
| 3 | # |
| 4 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 5 | menuconfig DMADEVICES |
Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 6 | bool "DMA Engine support" |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 7 | depends on HAS_DMA |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 8 | help |
Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 9 | DMA engines can do asynchronous data transfers without |
| 10 | involving the host CPU. Currently, this framework can be |
| 11 | used to offload memory copies in the network stack and |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 12 | RAID operations in the MD driver. This menu only presents |
| 13 | DMA Device drivers supported by the configured arch, it may |
| 14 | be empty in some cases. |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 15 | |
Linus Walleij | 6c664a8 | 2010-02-09 22:34:54 +0100 | [diff] [blame] | 16 | config DMADEVICES_DEBUG |
| 17 | bool "DMA Engine debugging" |
| 18 | depends on DMADEVICES != n |
| 19 | help |
| 20 | This is an option for use by developers; most people should |
| 21 | say N here. This enables DMA engine core and driver debugging. |
| 22 | |
| 23 | config DMADEVICES_VDEBUG |
| 24 | bool "DMA Engine verbose debugging" |
| 25 | depends on DMADEVICES_DEBUG != n |
| 26 | help |
| 27 | This is an option for use by developers; most people should |
| 28 | say N here. This enables deeper (more verbose) debugging of |
| 29 | the DMA engine core and drivers. |
| 30 | |
| 31 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 32 | if DMADEVICES |
Chris Leech | db21733 | 2006-06-17 21:24:58 -0700 | [diff] [blame] | 33 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 34 | comment "DMA Devices" |
| 35 | |
Dan Williams | 138f4c3 | 2009-09-08 17:42:51 -0700 | [diff] [blame] | 36 | config ASYNC_TX_DISABLE_CHANNEL_SWITCH |
| 37 | bool |
| 38 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 39 | config INTEL_IOATDMA |
| 40 | tristate "Intel I/OAT DMA support" |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 41 | depends on PCI && X86 |
| 42 | select DMA_ENGINE |
| 43 | select DCA |
Dan Williams | 138f4c3 | 2009-09-08 17:42:51 -0700 | [diff] [blame] | 44 | select ASYNC_TX_DISABLE_CHANNEL_SWITCH |
Dan Williams | 7b3cc2b | 2009-11-19 17:10:37 -0700 | [diff] [blame] | 45 | select ASYNC_TX_DISABLE_PQ_VAL_DMA |
| 46 | select ASYNC_TX_DISABLE_XOR_VAL_DMA |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 47 | help |
| 48 | Enable support for the Intel(R) I/OAT DMA engine present |
| 49 | in recent Intel Xeon chipsets. |
| 50 | |
| 51 | Say Y here if you have such a chipset. |
| 52 | |
| 53 | If unsure, say N. |
Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 54 | |
| 55 | config INTEL_IOP_ADMA |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 56 | tristate "Intel IOP ADMA support" |
| 57 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 58 | select DMA_ENGINE |
| 59 | help |
| 60 | Enable support for the Intel(R) IOP Series RAID engines. |
Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 61 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 62 | config DW_DMAC |
| 63 | tristate "Synopsys DesignWare AHB DMA support" |
| 64 | depends on AVR32 |
| 65 | select DMA_ENGINE |
| 66 | default y if CPU_AT32AP7000 |
| 67 | help |
| 68 | Support the Synopsys DesignWare AHB DMA controller. This |
| 69 | can be integrated in chips such as the Atmel AT32ap7000. |
| 70 | |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 71 | config AT_HDMAC |
| 72 | tristate "Atmel AHB DMA support" |
Yegor Yefremov | cd3abf9 | 2009-10-23 11:27:59 +0100 | [diff] [blame] | 73 | depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 74 | select DMA_ENGINE |
| 75 | help |
| 76 | Support the Atmel AHB DMA controller. This can be integrated in |
| 77 | chips such as the Atmel AT91SAM9RL. |
| 78 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 79 | config FSL_DMA |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 80 | tristate "Freescale Elo and Elo Plus DMA support" |
| 81 | depends on FSL_SOC |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 82 | select DMA_ENGINE |
| 83 | ---help--- |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 84 | Enable support for the Freescale Elo and Elo Plus DMA controllers. |
| 85 | The Elo is the DMA controller on some 82xx and 83xx parts, and the |
| 86 | Elo Plus is the DMA controller on 85xx and 86xx parts. |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 87 | |
Piotr Ziecik | 0fb6f73 | 2010-02-05 03:42:52 +0000 | [diff] [blame] | 88 | config MPC512X_DMA |
| 89 | tristate "Freescale MPC512x built-in DMA engine support" |
| 90 | depends on PPC_MPC512x |
| 91 | select DMA_ENGINE |
| 92 | ---help--- |
| 93 | Enable support for the Freescale MPC512x built-in DMA engine. |
| 94 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 95 | config MV_XOR |
| 96 | bool "Marvell XOR engine support" |
| 97 | depends on PLAT_ORION |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 98 | select DMA_ENGINE |
| 99 | ---help--- |
| 100 | Enable support for the Marvell XOR engine. |
| 101 | |
Guennadi Liakhovetski | 5296b56 | 2009-01-19 15:36:21 -0700 | [diff] [blame] | 102 | config MX3_IPU |
| 103 | bool "MX3x Image Processing Unit support" |
| 104 | depends on ARCH_MX3 |
| 105 | select DMA_ENGINE |
| 106 | default y |
| 107 | help |
| 108 | If you plan to use the Image Processing unit in the i.MX3x, say |
| 109 | Y here. If unsure, select Y. |
| 110 | |
| 111 | config MX3_IPU_IRQS |
| 112 | int "Number of dynamically mapped interrupts for IPU" |
| 113 | depends on MX3_IPU |
| 114 | range 2 137 |
| 115 | default 4 |
| 116 | help |
| 117 | Out of 137 interrupt sources on i.MX31 IPU only very few are used. |
| 118 | To avoid bloating the irq_desc[] array we allocate a sufficient |
| 119 | number of IRQ slots and map them dynamically to specific sources. |
| 120 | |
Atsushi Nemoto | ea76f0b | 2009-04-23 00:40:30 +0900 | [diff] [blame] | 121 | config TXX9_DMAC |
| 122 | tristate "Toshiba TXx9 SoC DMA support" |
| 123 | depends on MACH_TX49XX || MACH_TX39XX |
| 124 | select DMA_ENGINE |
| 125 | help |
| 126 | Support the TXx9 SoC internal DMA controller. This can be |
| 127 | integrated in chips such as the Toshiba TX4927/38/39. |
| 128 | |
Nobuhiro Iwamatsu | d8902ad | 2009-09-07 03:26:23 +0000 | [diff] [blame] | 129 | config SH_DMAE |
| 130 | tristate "Renesas SuperH DMAC support" |
| 131 | depends on SUPERH && SH_DMA |
| 132 | depends on !SH_DMA_API |
| 133 | select DMA_ENGINE |
| 134 | help |
| 135 | Enable support for the Renesas SuperH DMA controllers. |
| 136 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 137 | config COH901318 |
| 138 | bool "ST-Ericsson COH901318 DMA support" |
| 139 | select DMA_ENGINE |
| 140 | depends on ARCH_U300 |
| 141 | help |
| 142 | Enable support for ST-Ericsson COH 901 318 DMA. |
| 143 | |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 144 | config AMCC_PPC440SPE_ADMA |
| 145 | tristate "AMCC PPC440SPe ADMA support" |
| 146 | depends on 440SPe || 440SP |
| 147 | select DMA_ENGINE |
| 148 | select ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
| 149 | help |
| 150 | Enable support for the AMCC PPC440SPe RAID engines. |
| 151 | |
| 152 | config ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
| 153 | bool |
| 154 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 155 | config DMA_ENGINE |
| 156 | bool |
| 157 | |
| 158 | comment "DMA Clients" |
| 159 | depends on DMA_ENGINE |
| 160 | |
| 161 | config NET_DMA |
| 162 | bool "Network: TCP receive copy offload" |
| 163 | depends on DMA_ENGINE && NET |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 164 | default (INTEL_IOATDMA || FSL_DMA) |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 165 | help |
| 166 | This enables the use of DMA engines in the network stack to |
| 167 | offload receive copy-to-user operations, freeing CPU cycles. |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 168 | |
| 169 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise |
| 170 | say N. |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 171 | |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 172 | config ASYNC_TX_DMA |
| 173 | bool "Async_tx: Offload support for the async_tx api" |
Dan Williams | 9a8de63 | 2009-09-08 15:06:10 -0700 | [diff] [blame] | 174 | depends on DMA_ENGINE |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 175 | help |
| 176 | This allows the async_tx api to take advantage of offload engines for |
| 177 | memcpy, memset, xor, and raid6 p+q operations. If your platform has |
| 178 | a dma engine that can perform raid operations and you have enabled |
| 179 | MD_RAID456 say Y. |
| 180 | |
| 181 | If unsure, say N. |
| 182 | |
Haavard Skinnemoen | 4a776f0 | 2008-07-08 11:58:45 -0700 | [diff] [blame] | 183 | config DMATEST |
| 184 | tristate "DMA Test client" |
| 185 | depends on DMA_ENGINE |
| 186 | help |
| 187 | Simple DMA test client. Say N unless you're debugging a |
| 188 | DMA Device driver. |
| 189 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 190 | endif |