blob: 2733c6c1f027e4b33d3f04f990eb3fe50164756e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-integrator/pci_v3.c
3 *
4 * PCI functions for V3 host PCI bridge
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include <linux/kernel.h>
24#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/ioport.h>
26#include <linux/interrupt.h>
27#include <linux/spinlock.h>
28#include <linux/init.h>
Russell Kingfced80c2008-09-06 12:10:45 +010029#include <linux/io.h>
Linus Walleij86adc392013-02-02 23:16:57 +010030#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
Russell Kinga09e64f2008-08-05 16:14:15 +010032#include <mach/hardware.h>
Russell Kinga285edc2010-01-14 19:59:37 +000033#include <mach/platform.h>
Linus Walleij695436e2012-02-26 10:46:48 +010034#include <mach/irqs.h>
35
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040036#include <asm/signal.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include <asm/mach/pci.h>
Russell Kingc6af66b2007-05-17 10:16:55 +010038#include <asm/irq_regs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
40#include <asm/hardware/pci_v3.h>
41
42/*
43 * The V3 PCI interface chip in Integrator provides several windows from
44 * local bus memory into the PCI memory areas. Unfortunately, there
Rob Herring29d39602012-07-13 16:27:43 -050045 * are not really enough windows for our usage, therefore we reuse
Linus Torvalds1da177e2005-04-16 15:20:36 -070046 * one of the windows for access to PCI configuration space. The
47 * memory map is as follows:
Rob Herring29d39602012-07-13 16:27:43 -050048 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070049 * Local Bus Memory Usage
Rob Herring29d39602012-07-13 16:27:43 -050050 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
52 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
53 * 60000000 - 60FFFFFF PCI IO. 16M
54 * 61000000 - 61FFFFFF PCI Configuration. 16M
Rob Herring29d39602012-07-13 16:27:43 -050055 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 * There are three V3 windows, each described by a pair of V3 registers.
57 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
58 * Base0 and Base1 can be used for any type of PCI memory access. Base2
59 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
60 * uses this only for PCI IO space.
Rob Herring29d39602012-07-13 16:27:43 -050061 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 * Normally these spaces are mapped using the following base registers:
Rob Herring29d39602012-07-13 16:27:43 -050063 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070064 * Usage Local Bus Memory Base/Map registers used
Rob Herring29d39602012-07-13 16:27:43 -050065 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070066 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
67 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
68 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
69 * Cfg 61000000 - 61FFFFFF
Rob Herring29d39602012-07-13 16:27:43 -050070 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070071 * This means that I20 and PCI configuration space accesses will fail.
Rob Herring29d39602012-07-13 16:27:43 -050072 * When PCI configuration accesses are needed (via the uHAL PCI
Linus Torvalds1da177e2005-04-16 15:20:36 -070073 * configuration space primitives) we must remap the spaces as follows:
Rob Herring29d39602012-07-13 16:27:43 -050074 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 * Usage Local Bus Memory Base/Map registers used
Rob Herring29d39602012-07-13 16:27:43 -050076 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070077 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
78 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
79 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
80 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
Rob Herring29d39602012-07-13 16:27:43 -050081 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070082 * To make this work, the code depends on overlapping windows working.
Rob Herring29d39602012-07-13 16:27:43 -050083 * The V3 chip translates an address by checking its range within
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 * each of the BASE/MAP pairs in turn (in ascending register number
85 * order). It will use the first matching pair. So, for example,
86 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
Rob Herring29d39602012-07-13 16:27:43 -050087 * LB_BASE1/LB_MAP1, the V3 will use the translation from
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 * LB_BASE0/LB_MAP0.
Rob Herring29d39602012-07-13 16:27:43 -050089 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 * To allow PCI Configuration space access, the code enlarges the
91 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
92 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
93 * be remapped for use by configuration cycles.
Rob Herring29d39602012-07-13 16:27:43 -050094 *
95 * At the end of the PCI Configuration space accesses,
Linus Torvalds1da177e2005-04-16 15:20:36 -070096 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
97 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
98 * reveal the now restored LB_BASE1/LB_MAP1 window.
Rob Herring29d39602012-07-13 16:27:43 -050099 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100 * NOTE: We do not set up I2O mapping. I suspect that this is only
101 * for an intelligent (target) device. Using I2O disables most of
102 * the mappings into PCI memory.
103 */
104
105// V3 access routines
106#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
107#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
108
109#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
110#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
111
112#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
113#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
114
115/*============================================================================
116 *
117 * routine: uHALir_PCIMakeConfigAddress()
118 *
119 * parameters: bus = which bus
120 * device = which device
121 * function = which function
122 * offset = configuration space register we are interested in
123 *
124 * description: this routine will generate a platform dependent config
125 * address.
126 *
127 * calls: none
128 *
129 * returns: configuration address to play on the PCI bus
130 *
Rob Herring29d39602012-07-13 16:27:43 -0500131 * To generate the appropriate PCI configuration cycles in the PCI
132 * configuration address space, you present the V3 with the following pattern
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133 * (which is very nearly a type 1 (except that the lower two bits are 00 and
134 * not 01). In order for this mapping to work you need to set up one of
135 * the local to PCI aperatures to 16Mbytes in length translating to
136 * PCI configuration space starting at 0x0000.0000.
137 *
138 * PCI configuration cycles look like this:
139 *
140 * Type 0:
141 *
Rob Herring29d39602012-07-13 16:27:43 -0500142 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
144 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
145 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
146 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
147 *
148 * 31:11 Device select bit.
149 * 10:8 Function number
150 * 7:2 Register number
151 *
152 * Type 1:
153 *
Rob Herring29d39602012-07-13 16:27:43 -0500154 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
156 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
157 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
158 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
159 *
160 * 31:24 reserved
161 * 23:16 bus number (8 bits = 128 possible buses)
162 * 15:11 Device number (5 bits)
163 * 10:8 function number
164 * 7:2 register number
Rob Herring29d39602012-07-13 16:27:43 -0500165 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 */
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500167static DEFINE_RAW_SPINLOCK(v3_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168
169#define PCI_BUS_NONMEM_START 0x00000000
170#define PCI_BUS_NONMEM_SIZE SZ_256M
171
172#define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
173#define PCI_BUS_PREMEM_SIZE SZ_256M
174
175#if PCI_BUS_NONMEM_START & 0x000fffff
176#error PCI_BUS_NONMEM_START must be megabyte aligned
177#endif
178#if PCI_BUS_PREMEM_START & 0x000fffff
179#error PCI_BUS_PREMEM_START must be megabyte aligned
180#endif
181
182#undef V3_LB_BASE_PREFETCH
183#define V3_LB_BASE_PREFETCH 0
184
Arnd Bergmannb7a3f8d2012-09-14 20:16:39 +0000185static void __iomem *v3_open_config_window(struct pci_bus *bus,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186 unsigned int devfn, int offset)
187{
188 unsigned int address, mapaddress, busnr;
189
190 busnr = bus->number;
191
192 /*
193 * Trap out illegal values
194 */
Sasha Levinf7a9b362012-11-08 15:23:08 -0500195 BUG_ON(offset > 255);
196 BUG_ON(busnr > 255);
197 BUG_ON(devfn > 255);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198
199 if (busnr == 0) {
200 int slot = PCI_SLOT(devfn);
201
202 /*
203 * local bus segment so need a type 0 config cycle
204 *
205 * build the PCI configuration "address" with one-hot in
206 * A31-A11
207 *
208 * mapaddress:
209 * 3:1 = config cycle (101)
210 * 0 = PCI A1 & A0 are 0 (0)
211 */
212 address = PCI_FUNC(devfn) << 8;
213 mapaddress = V3_LB_MAP_TYPE_CONFIG;
214
215 if (slot > 12)
216 /*
217 * high order bits are handled by the MAP register
218 */
219 mapaddress |= 1 << (slot - 5);
220 else
221 /*
222 * low order bits handled directly in the address
223 */
224 address |= 1 << (slot + 11);
225 } else {
226 /*
227 * not the local bus segment so need a type 1 config cycle
228 *
229 * address:
230 * 23:16 = bus number
231 * 15:11 = slot number (7:3 of devfn)
232 * 10:8 = func number (2:0 of devfn)
233 *
234 * mapaddress:
235 * 3:1 = config cycle (101)
236 * 0 = PCI A1 & A0 from host bus (1)
237 */
238 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
239 address = (busnr << 16) | (devfn << 8);
240 }
241
242 /*
243 * Set up base0 to see all 512Mbytes of memory space (not
244 * prefetchable), this frees up base1 for re-use by
245 * configuration memory
246 */
247 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
248 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
249
250 /*
251 * Set up base1/map1 to point into configuration space.
252 */
253 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
254 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
255 v3_writew(V3_LB_MAP1, mapaddress);
256
257 return PCI_CONFIG_VADDR + address + offset;
258}
259
260static void v3_close_config_window(void)
261{
262 /*
263 * Reassign base1 for use by prefetchable PCI memory
264 */
265 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
266 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
267 V3_LB_BASE_ENABLE);
268 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
269 V3_LB_MAP_TYPE_MEM_MULTIPLE);
270
271 /*
272 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
273 */
274 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
275 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
276}
277
278static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
279 int size, u32 *val)
280{
Arnd Bergmannb7a3f8d2012-09-14 20:16:39 +0000281 void __iomem *addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 unsigned long flags;
283 u32 v;
284
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500285 raw_spin_lock_irqsave(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286 addr = v3_open_config_window(bus, devfn, where);
287
288 switch (size) {
289 case 1:
290 v = __raw_readb(addr);
291 break;
292
293 case 2:
294 v = __raw_readw(addr);
295 break;
296
297 default:
298 v = __raw_readl(addr);
299 break;
300 }
301
302 v3_close_config_window();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500303 raw_spin_unlock_irqrestore(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304
305 *val = v;
306 return PCIBIOS_SUCCESSFUL;
307}
308
309static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
310 int size, u32 val)
311{
Arnd Bergmannb7a3f8d2012-09-14 20:16:39 +0000312 void __iomem *addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313 unsigned long flags;
314
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500315 raw_spin_lock_irqsave(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316 addr = v3_open_config_window(bus, devfn, where);
317
318 switch (size) {
319 case 1:
320 __raw_writeb((u8)val, addr);
321 __raw_readb(addr);
322 break;
323
324 case 2:
325 __raw_writew((u16)val, addr);
326 __raw_readw(addr);
327 break;
328
329 case 4:
330 __raw_writel(val, addr);
331 __raw_readl(addr);
332 break;
333 }
334
335 v3_close_config_window();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500336 raw_spin_unlock_irqrestore(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337
338 return PCIBIOS_SUCCESSFUL;
339}
340
Linus Walleijf4bc4f02013-01-29 17:14:18 +0100341static struct pci_ops pci_v3_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342 .read = v3_read_config,
343 .write = v3_write_config,
344};
345
346static struct resource non_mem = {
347 .name = "PCI non-prefetchable",
348 .start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
349 .end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
350 .flags = IORESOURCE_MEM,
351};
352
353static struct resource pre_mem = {
354 .name = "PCI prefetchable",
355 .start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
356 .end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
357 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
358};
359
Bjorn Helgaas37d15902011-10-28 16:26:16 -0600360static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361{
362 if (request_resource(&iomem_resource, &non_mem)) {
363 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
364 "memory region\n");
365 return -EBUSY;
366 }
367 if (request_resource(&iomem_resource, &pre_mem)) {
368 release_resource(&non_mem);
369 printk(KERN_ERR "PCI: unable to allocate prefetchable "
370 "memory region\n");
371 return -EBUSY;
372 }
373
374 /*
Bjorn Helgaas37d15902011-10-28 16:26:16 -0600375 * the mem resource for this bus
376 * the prefetch mem resource for this bus
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 */
Bjorn Helgaas9f786d02012-02-23 20:19:01 -0700378 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
379 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380
381 return 1;
382}
383
384/*
385 * These don't seem to be implemented on the Integrator I have, which
386 * means I can't get additional information on the reason for the pm2fb
387 * problems. I suppose I'll just have to mind-meld with the machine. ;)
388 */
Linus Walleij379df272012-11-17 19:24:23 +0100389static void __iomem *ap_syscon_base;
390#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
391#define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
392#define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393
394static int
395v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
396{
397 unsigned long pc = instruction_pointer(regs);
398 unsigned long instr = *(unsigned long *)pc;
399#if 0
400 char buf[128];
401
402 sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
Linus Walleij379df272012-11-17 19:24:23 +0100403 addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404 v3_readb(V3_LB_ISTAT));
405 printk(KERN_DEBUG "%s", buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406#endif
407
408 v3_writeb(V3_LB_ISTAT, 0);
Linus Walleij379df272012-11-17 19:24:23 +0100409 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410
411 /*
412 * If the instruction being executed was a read,
413 * make it look like it read all-ones.
414 */
415 if ((instr & 0x0c100000) == 0x04100000) {
416 int reg = (instr >> 12) & 15;
417 unsigned long val;
418
419 if (instr & 0x00400000)
420 val = 255;
421 else
422 val = -1;
423
424 regs->uregs[reg] = val;
425 regs->ARM_pc += 4;
426 return 0;
427 }
428
429 if ((instr & 0x0e100090) == 0x00100090) {
430 int reg = (instr >> 12) & 15;
431
432 regs->uregs[reg] = -1;
433 regs->ARM_pc += 4;
434 return 0;
435 }
436
437 return 1;
438}
439
Jeff Garzike8f2af12007-10-26 05:40:25 -0400440static irqreturn_t v3_irq(int dummy, void *devid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441{
442#ifdef CONFIG_DEBUG_LL
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700443 struct pt_regs *regs = get_irq_regs();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 unsigned long pc = instruction_pointer(regs);
445 unsigned long instr = *(unsigned long *)pc;
446 char buf[128];
Russell King7c284722008-05-23 19:35:52 +0100447 extern void printascii(const char *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448
Jeff Garzike8f2af12007-10-26 05:40:25 -0400449 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
450 "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr,
Linus Walleij379df272012-11-17 19:24:23 +0100451 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET),
452 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453 v3_readb(V3_LB_ISTAT));
454 printascii(buf);
455#endif
456
457 v3_writew(V3_PCI_STAT, 0xf000);
458 v3_writeb(V3_LB_ISTAT, 0);
Linus Walleij379df272012-11-17 19:24:23 +0100459 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460
461#ifdef CONFIG_DEBUG_LL
462 /*
463 * If the instruction being executed was a read,
464 * make it look like it read all-ones.
465 */
466 if ((instr & 0x0c100000) == 0x04100000) {
467 int reg = (instr >> 16) & 15;
468 sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
469 printascii(buf);
470 }
471#endif
472 return IRQ_HANDLED;
473}
474
Linus Walleijf4bc4f02013-01-29 17:14:18 +0100475static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476{
477 int ret = 0;
478
Linus Walleij67c6b2e2013-01-10 10:18:49 +0100479 if (!ap_syscon_base)
480 return -EINVAL;
481
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482 if (nr == 0) {
483 sys->mem_offset = PHYS_PCI_MEM_BASE;
Bjorn Helgaas37d15902011-10-28 16:26:16 -0600484 ret = pci_v3_setup_resources(sys);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485 }
486
487 return ret;
488}
489
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490/*
491 * V3_LB_BASE? - local bus address
492 * V3_LB_MAP? - pci bus address
493 */
Linus Walleijf4bc4f02013-01-29 17:14:18 +0100494static void __init pci_v3_preinit(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495{
496 unsigned long flags;
497 unsigned int temp;
498 int ret;
499
Linus Walleij67c6b2e2013-01-10 10:18:49 +0100500 /* Remap the Integrator system controller */
501 ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
502 if (!ap_syscon_base) {
503 pr_err("unable to remap the AP syscon for PCIv3\n");
504 return;
505 }
506
Rob Herringc9d95fb2011-06-28 21:16:13 -0500507 pcibios_min_mem = 0x00100000;
508
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509 /*
510 * Hook in our fault handler for PCI errors
511 */
Kirill A. Shutemov6338a6a2010-07-22 13:18:19 +0100512 hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
513 hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
514 hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
515 hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500517 raw_spin_lock_irqsave(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518
519 /*
520 * Unlock V3 registers, but only if they were previously locked.
521 */
522 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
523 v3_writew(V3_SYSTEM, 0xa05f);
524
525 /*
526 * Setup window 0 - PCI non-prefetchable memory
527 * Local: 0x40000000 Bus: 0x00000000 Size: 256MB
528 */
529 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
530 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
531 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
532 V3_LB_MAP_TYPE_MEM);
533
534 /*
535 * Setup window 1 - PCI prefetchable memory
536 * Local: 0x50000000 Bus: 0x10000000 Size: 256MB
537 */
538 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
539 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
540 V3_LB_BASE_ENABLE);
541 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
542 V3_LB_MAP_TYPE_MEM_MULTIPLE);
543
544 /*
545 * Setup window 2 - PCI IO
546 */
547 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
548 V3_LB_BASE_ENABLE);
549 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
550
551 /*
552 * Disable PCI to host IO cycles
553 */
554 temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
555 temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
556 v3_writew(V3_PCI_CFG, temp);
557
558 printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
559 v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
560
561 /*
562 * Set the V3 FIFO such that writes have higher priority than
563 * reads, and local bus write causes local bus read fifo flush.
564 * Same for PCI.
565 */
566 v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
567
568 /*
569 * Re-lock the system register.
570 */
571 temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
572 v3_writew(V3_SYSTEM, temp);
573
574 /*
575 * Clear any error conditions, and enable write errors.
576 */
577 v3_writeb(V3_LB_ISTAT, 0);
578 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
579 v3_writeb(V3_LB_IMASK, 0x28);
Linus Walleij379df272012-11-17 19:24:23 +0100580 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581
582 /*
583 * Grab the PCI error interrupt.
584 */
585 ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
586 if (ret)
587 printk(KERN_ERR "PCI: unable to grab PCI error "
588 "interrupt: %d\n", ret);
589
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500590 raw_spin_unlock_irqrestore(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591}
592
Linus Walleijf4bc4f02013-01-29 17:14:18 +0100593static void __init pci_v3_postinit(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594{
595 unsigned int pci_cmd;
596
597 pci_cmd = PCI_COMMAND_MEMORY |
598 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
599
600 v3_writew(V3_PCI_CMD, pci_cmd);
601
602 v3_writeb(V3_LB_ISTAT, ~0x40);
603 v3_writeb(V3_LB_IMASK, 0x68);
604
605#if 0
606 ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
607 if (ret)
608 printk(KERN_ERR "PCI: unable to grab local bus timeout "
609 "interrupt: %d\n", ret);
610#endif
Russell King863dab42006-08-28 12:47:05 +0100611
612 register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700613}
Linus Walleijf4bc4f02013-01-29 17:14:18 +0100614
615/*
616 * A small note about bridges and interrupts. The DECchip 21050 (and
617 * later) adheres to the PCI-PCI bridge specification. This says that
618 * the interrupts on the other side of a bridge are swizzled in the
619 * following manner:
620 *
621 * Dev Interrupt Interrupt
622 * Pin on Pin on
623 * Device Connector
624 *
625 * 4 A A
626 * B B
627 * C C
628 * D D
629 *
630 * 5 A B
631 * B C
632 * C D
633 * D A
634 *
635 * 6 A C
636 * B D
637 * C A
638 * D B
639 *
640 * 7 A D
641 * B A
642 * C B
643 * D C
644 *
645 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
646 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
647 */
648
649/*
650 * This routine handles multiple bridges.
651 */
Linus Walleij86adc392013-02-02 23:16:57 +0100652static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
Linus Walleijf4bc4f02013-01-29 17:14:18 +0100653{
654 if (*pinp == 0)
655 *pinp = 1;
656
657 return pci_common_swizzle(dev, pinp);
658}
659
660static int irq_tab[4] __initdata = {
661 IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
662};
663
664/*
665 * map the specified device/slot/pin to an IRQ. This works out such
666 * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
667 */
Linus Walleij86adc392013-02-02 23:16:57 +0100668static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
Linus Walleijf4bc4f02013-01-29 17:14:18 +0100669{
670 int intnr = ((slot - 9) + (pin - 1)) & 3;
671
672 return irq_tab[intnr];
673}
674
Linus Walleij86adc392013-02-02 23:16:57 +0100675static struct hw_pci pci_v3 __initdata = {
676 .swizzle = pci_v3_swizzle,
677 .map_irq = pci_v3_map_irq,
Linus Walleijf4bc4f02013-01-29 17:14:18 +0100678 .setup = pci_v3_setup,
679 .nr_controllers = 1,
680 .ops = &pci_v3_ops,
681 .preinit = pci_v3_preinit,
682 .postinit = pci_v3_postinit,
683};
684
Linus Walleij86adc392013-02-02 23:16:57 +0100685static int __init pci_v3_probe(struct platform_device *pdev)
Linus Walleijf4bc4f02013-01-29 17:14:18 +0100686{
Linus Walleij86adc392013-02-02 23:16:57 +0100687 pci_common_init(&pci_v3);
Linus Walleijf4bc4f02013-01-29 17:14:18 +0100688 return 0;
689}
690
Linus Walleij86adc392013-02-02 23:16:57 +0100691static struct platform_driver pci_v3_driver = {
692 .driver = {
693 .name = "pci-v3",
694 },
695};
696
697static int __init pci_v3_init(void)
698{
699 return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
700}
701
702subsys_initcall(pci_v3_init);