Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel(R) Gigabit Ethernet Linux driver |
Alexander Duyck | 86d5d38 | 2009-02-06 23:23:12 +0000 | [diff] [blame^] | 4 | Copyright(c) 2007-2009 Intel Corporation. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | /* e1000_82575 |
| 29 | * e1000_82576 |
| 30 | */ |
| 31 | |
| 32 | #include <linux/types.h> |
| 33 | #include <linux/slab.h> |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 34 | #include <linux/if_ether.h> |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 35 | |
| 36 | #include "e1000_mac.h" |
| 37 | #include "e1000_82575.h" |
| 38 | |
| 39 | static s32 igb_get_invariants_82575(struct e1000_hw *); |
| 40 | static s32 igb_acquire_phy_82575(struct e1000_hw *); |
| 41 | static void igb_release_phy_82575(struct e1000_hw *); |
| 42 | static s32 igb_acquire_nvm_82575(struct e1000_hw *); |
| 43 | static void igb_release_nvm_82575(struct e1000_hw *); |
| 44 | static s32 igb_check_for_link_82575(struct e1000_hw *); |
| 45 | static s32 igb_get_cfg_done_82575(struct e1000_hw *); |
| 46 | static s32 igb_init_hw_82575(struct e1000_hw *); |
| 47 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); |
| 48 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 49 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
| 50 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); |
| 51 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); |
| 52 | static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *); |
| 53 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); |
| 54 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *); |
| 55 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); |
| 56 | static s32 igb_configure_pcs_link_82575(struct e1000_hw *); |
| 57 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, |
| 58 | u16 *); |
| 59 | static s32 igb_get_phy_id_82575(struct e1000_hw *); |
| 60 | static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); |
| 61 | static bool igb_sgmii_active_82575(struct e1000_hw *); |
| 62 | static s32 igb_reset_init_script_82575(struct e1000_hw *); |
| 63 | static s32 igb_read_mac_addr_82575(struct e1000_hw *); |
| 64 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 65 | static s32 igb_get_invariants_82575(struct e1000_hw *hw) |
| 66 | { |
| 67 | struct e1000_phy_info *phy = &hw->phy; |
| 68 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 69 | struct e1000_mac_info *mac = &hw->mac; |
Alexander Duyck | c1889bf | 2009-02-06 23:16:45 +0000 | [diff] [blame] | 70 | struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 71 | u32 eecd; |
| 72 | s32 ret_val; |
| 73 | u16 size; |
| 74 | u32 ctrl_ext = 0; |
| 75 | |
| 76 | switch (hw->device_id) { |
| 77 | case E1000_DEV_ID_82575EB_COPPER: |
| 78 | case E1000_DEV_ID_82575EB_FIBER_SERDES: |
| 79 | case E1000_DEV_ID_82575GB_QUAD_COPPER: |
| 80 | mac->type = e1000_82575; |
| 81 | break; |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 82 | case E1000_DEV_ID_82576: |
| 83 | case E1000_DEV_ID_82576_FIBER: |
| 84 | case E1000_DEV_ID_82576_SERDES: |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 85 | mac->type = e1000_82576; |
| 86 | break; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 87 | default: |
| 88 | return -E1000_ERR_MAC_INIT; |
| 89 | break; |
| 90 | } |
| 91 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 92 | /* Set media type */ |
| 93 | /* |
| 94 | * The 82575 uses bits 22:23 for link mode. The mode can be changed |
| 95 | * based on the EEPROM. We cannot rely upon device ID. There |
| 96 | * is no distinguishable difference between fiber and internal |
| 97 | * SerDes mode on the 82575. There can be an external PHY attached |
| 98 | * on the SGMII interface. For this, we'll set sgmii_active to true. |
| 99 | */ |
| 100 | phy->media_type = e1000_media_type_copper; |
| 101 | dev_spec->sgmii_active = false; |
| 102 | |
| 103 | ctrl_ext = rd32(E1000_CTRL_EXT); |
| 104 | if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == |
| 105 | E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { |
| 106 | hw->phy.media_type = e1000_media_type_internal_serdes; |
| 107 | ctrl_ext |= E1000_CTRL_I2C_ENA; |
| 108 | } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { |
| 109 | dev_spec->sgmii_active = true; |
| 110 | ctrl_ext |= E1000_CTRL_I2C_ENA; |
| 111 | } else { |
| 112 | ctrl_ext &= ~E1000_CTRL_I2C_ENA; |
| 113 | } |
| 114 | wr32(E1000_CTRL_EXT, ctrl_ext); |
| 115 | |
| 116 | /* Set mta register count */ |
| 117 | mac->mta_reg_count = 128; |
| 118 | /* Set rar entry count */ |
| 119 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 120 | if (mac->type == e1000_82576) |
| 121 | mac->rar_entry_count = E1000_RAR_ENTRIES_82576; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 122 | /* Set if part includes ASF firmware */ |
| 123 | mac->asf_firmware_present = true; |
| 124 | /* Set if manageability features are enabled. */ |
| 125 | mac->arc_subsystem_valid = |
| 126 | (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) |
| 127 | ? true : false; |
| 128 | |
| 129 | /* physical interface link setup */ |
| 130 | mac->ops.setup_physical_interface = |
| 131 | (hw->phy.media_type == e1000_media_type_copper) |
| 132 | ? igb_setup_copper_link_82575 |
| 133 | : igb_setup_fiber_serdes_link_82575; |
| 134 | |
| 135 | /* NVM initialization */ |
| 136 | eecd = rd32(E1000_EECD); |
| 137 | |
| 138 | nvm->opcode_bits = 8; |
| 139 | nvm->delay_usec = 1; |
| 140 | switch (nvm->override) { |
| 141 | case e1000_nvm_override_spi_large: |
| 142 | nvm->page_size = 32; |
| 143 | nvm->address_bits = 16; |
| 144 | break; |
| 145 | case e1000_nvm_override_spi_small: |
| 146 | nvm->page_size = 8; |
| 147 | nvm->address_bits = 8; |
| 148 | break; |
| 149 | default: |
| 150 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; |
| 151 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; |
| 152 | break; |
| 153 | } |
| 154 | |
| 155 | nvm->type = e1000_nvm_eeprom_spi; |
| 156 | |
| 157 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
| 158 | E1000_EECD_SIZE_EX_SHIFT); |
| 159 | |
| 160 | /* |
| 161 | * Added to a constant, "size" becomes the left-shift value |
| 162 | * for setting word_size. |
| 163 | */ |
| 164 | size += NVM_WORD_SIZE_BASE_SHIFT; |
Jeff Kirsher | 5c3cad7 | 2008-06-27 10:59:33 -0700 | [diff] [blame] | 165 | |
| 166 | /* EEPROM access above 16k is unsupported */ |
| 167 | if (size > 14) |
| 168 | size = 14; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 169 | nvm->word_size = 1 << size; |
| 170 | |
| 171 | /* setup PHY parameters */ |
| 172 | if (phy->media_type != e1000_media_type_copper) { |
| 173 | phy->type = e1000_phy_none; |
| 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
| 178 | phy->reset_delay_us = 100; |
| 179 | |
| 180 | /* PHY function pointers */ |
| 181 | if (igb_sgmii_active_82575(hw)) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 182 | phy->ops.reset = igb_phy_hw_reset_sgmii_82575; |
| 183 | phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; |
| 184 | phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 185 | } else { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 186 | phy->ops.reset = igb_phy_hw_reset; |
| 187 | phy->ops.read_reg = igb_read_phy_reg_igp; |
| 188 | phy->ops.write_reg = igb_write_phy_reg_igp; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 189 | } |
| 190 | |
| 191 | /* Set phy->phy_addr and phy->id. */ |
| 192 | ret_val = igb_get_phy_id_82575(hw); |
| 193 | if (ret_val) |
| 194 | return ret_val; |
| 195 | |
| 196 | /* Verify phy id and set remaining function pointers */ |
| 197 | switch (phy->id) { |
| 198 | case M88E1111_I_PHY_ID: |
| 199 | phy->type = e1000_phy_m88; |
| 200 | phy->ops.get_phy_info = igb_get_phy_info_m88; |
| 201 | phy->ops.get_cable_length = igb_get_cable_length_m88; |
| 202 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; |
| 203 | break; |
| 204 | case IGP03E1000_E_PHY_ID: |
| 205 | phy->type = e1000_phy_igp_3; |
| 206 | phy->ops.get_phy_info = igb_get_phy_info_igp; |
| 207 | phy->ops.get_cable_length = igb_get_cable_length_igp_2; |
| 208 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; |
| 209 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; |
| 210 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; |
| 211 | break; |
| 212 | default: |
| 213 | return -E1000_ERR_PHY; |
| 214 | } |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 220 | * igb_acquire_phy_82575 - Acquire rights to access PHY |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 221 | * @hw: pointer to the HW structure |
| 222 | * |
| 223 | * Acquire access rights to the correct PHY. This is a |
| 224 | * function pointer entry point called by the api module. |
| 225 | **/ |
| 226 | static s32 igb_acquire_phy_82575(struct e1000_hw *hw) |
| 227 | { |
| 228 | u16 mask; |
| 229 | |
| 230 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; |
| 231 | |
| 232 | return igb_acquire_swfw_sync_82575(hw, mask); |
| 233 | } |
| 234 | |
| 235 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 236 | * igb_release_phy_82575 - Release rights to access PHY |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 237 | * @hw: pointer to the HW structure |
| 238 | * |
| 239 | * A wrapper to release access rights to the correct PHY. This is a |
| 240 | * function pointer entry point called by the api module. |
| 241 | **/ |
| 242 | static void igb_release_phy_82575(struct e1000_hw *hw) |
| 243 | { |
| 244 | u16 mask; |
| 245 | |
| 246 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; |
| 247 | igb_release_swfw_sync_82575(hw, mask); |
| 248 | } |
| 249 | |
| 250 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 251 | * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 252 | * @hw: pointer to the HW structure |
| 253 | * @offset: register offset to be read |
| 254 | * @data: pointer to the read data |
| 255 | * |
| 256 | * Reads the PHY register at offset using the serial gigabit media independent |
| 257 | * interface and stores the retrieved information in data. |
| 258 | **/ |
| 259 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, |
| 260 | u16 *data) |
| 261 | { |
| 262 | struct e1000_phy_info *phy = &hw->phy; |
| 263 | u32 i, i2ccmd = 0; |
| 264 | |
| 265 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 266 | hw_dbg("PHY Address %u is out of range\n", offset); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 267 | return -E1000_ERR_PARAM; |
| 268 | } |
| 269 | |
| 270 | /* |
| 271 | * Set up Op-code, Phy Address, and register address in the I2CCMD |
| 272 | * register. The MAC will take care of interfacing with the |
| 273 | * PHY to retrieve the desired data. |
| 274 | */ |
| 275 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | |
| 276 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | |
| 277 | (E1000_I2CCMD_OPCODE_READ)); |
| 278 | |
| 279 | wr32(E1000_I2CCMD, i2ccmd); |
| 280 | |
| 281 | /* Poll the ready bit to see if the I2C read completed */ |
| 282 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { |
| 283 | udelay(50); |
| 284 | i2ccmd = rd32(E1000_I2CCMD); |
| 285 | if (i2ccmd & E1000_I2CCMD_READY) |
| 286 | break; |
| 287 | } |
| 288 | if (!(i2ccmd & E1000_I2CCMD_READY)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 289 | hw_dbg("I2CCMD Read did not complete\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 290 | return -E1000_ERR_PHY; |
| 291 | } |
| 292 | if (i2ccmd & E1000_I2CCMD_ERROR) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 293 | hw_dbg("I2CCMD Error bit set\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 294 | return -E1000_ERR_PHY; |
| 295 | } |
| 296 | |
| 297 | /* Need to byte-swap the 16-bit value. */ |
| 298 | *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); |
| 299 | |
| 300 | return 0; |
| 301 | } |
| 302 | |
| 303 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 304 | * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 305 | * @hw: pointer to the HW structure |
| 306 | * @offset: register offset to write to |
| 307 | * @data: data to write at register offset |
| 308 | * |
| 309 | * Writes the data to PHY register at the offset using the serial gigabit |
| 310 | * media independent interface. |
| 311 | **/ |
| 312 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, |
| 313 | u16 data) |
| 314 | { |
| 315 | struct e1000_phy_info *phy = &hw->phy; |
| 316 | u32 i, i2ccmd = 0; |
| 317 | u16 phy_data_swapped; |
| 318 | |
| 319 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 320 | hw_dbg("PHY Address %d is out of range\n", offset); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 321 | return -E1000_ERR_PARAM; |
| 322 | } |
| 323 | |
| 324 | /* Swap the data bytes for the I2C interface */ |
| 325 | phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); |
| 326 | |
| 327 | /* |
| 328 | * Set up Op-code, Phy Address, and register address in the I2CCMD |
| 329 | * register. The MAC will take care of interfacing with the |
| 330 | * PHY to retrieve the desired data. |
| 331 | */ |
| 332 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | |
| 333 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | |
| 334 | E1000_I2CCMD_OPCODE_WRITE | |
| 335 | phy_data_swapped); |
| 336 | |
| 337 | wr32(E1000_I2CCMD, i2ccmd); |
| 338 | |
| 339 | /* Poll the ready bit to see if the I2C read completed */ |
| 340 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { |
| 341 | udelay(50); |
| 342 | i2ccmd = rd32(E1000_I2CCMD); |
| 343 | if (i2ccmd & E1000_I2CCMD_READY) |
| 344 | break; |
| 345 | } |
| 346 | if (!(i2ccmd & E1000_I2CCMD_READY)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 347 | hw_dbg("I2CCMD Write did not complete\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 348 | return -E1000_ERR_PHY; |
| 349 | } |
| 350 | if (i2ccmd & E1000_I2CCMD_ERROR) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 351 | hw_dbg("I2CCMD Error bit set\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 352 | return -E1000_ERR_PHY; |
| 353 | } |
| 354 | |
| 355 | return 0; |
| 356 | } |
| 357 | |
| 358 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 359 | * igb_get_phy_id_82575 - Retrieve PHY addr and id |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 360 | * @hw: pointer to the HW structure |
| 361 | * |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 362 | * Retrieves the PHY address and ID for both PHY's which do and do not use |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 363 | * sgmi interface. |
| 364 | **/ |
| 365 | static s32 igb_get_phy_id_82575(struct e1000_hw *hw) |
| 366 | { |
| 367 | struct e1000_phy_info *phy = &hw->phy; |
| 368 | s32 ret_val = 0; |
| 369 | u16 phy_id; |
| 370 | |
| 371 | /* |
| 372 | * For SGMII PHYs, we try the list of possible addresses until |
| 373 | * we find one that works. For non-SGMII PHYs |
| 374 | * (e.g. integrated copper PHYs), an address of 1 should |
| 375 | * work. The result of this function should mean phy->phy_addr |
| 376 | * and phy->id are set correctly. |
| 377 | */ |
| 378 | if (!(igb_sgmii_active_82575(hw))) { |
| 379 | phy->addr = 1; |
| 380 | ret_val = igb_get_phy_id(hw); |
| 381 | goto out; |
| 382 | } |
| 383 | |
| 384 | /* |
| 385 | * The address field in the I2CCMD register is 3 bits and 0 is invalid. |
| 386 | * Therefore, we need to test 1-7 |
| 387 | */ |
| 388 | for (phy->addr = 1; phy->addr < 8; phy->addr++) { |
| 389 | ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); |
| 390 | if (ret_val == 0) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 391 | hw_dbg("Vendor ID 0x%08X read at address %u\n", |
| 392 | phy_id, phy->addr); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 393 | /* |
| 394 | * At the time of this writing, The M88 part is |
| 395 | * the only supported SGMII PHY product. |
| 396 | */ |
| 397 | if (phy_id == M88_VENDOR) |
| 398 | break; |
| 399 | } else { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 400 | hw_dbg("PHY address %u was unreadable\n", phy->addr); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 401 | } |
| 402 | } |
| 403 | |
| 404 | /* A valid PHY type couldn't be found. */ |
| 405 | if (phy->addr == 8) { |
| 406 | phy->addr = 0; |
| 407 | ret_val = -E1000_ERR_PHY; |
| 408 | goto out; |
| 409 | } |
| 410 | |
| 411 | ret_val = igb_get_phy_id(hw); |
| 412 | |
| 413 | out: |
| 414 | return ret_val; |
| 415 | } |
| 416 | |
| 417 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 418 | * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 419 | * @hw: pointer to the HW structure |
| 420 | * |
| 421 | * Resets the PHY using the serial gigabit media independent interface. |
| 422 | **/ |
| 423 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) |
| 424 | { |
| 425 | s32 ret_val; |
| 426 | |
| 427 | /* |
| 428 | * This isn't a true "hard" reset, but is the only reset |
| 429 | * available to us at this time. |
| 430 | */ |
| 431 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 432 | hw_dbg("Soft resetting SGMII attached PHY...\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 433 | |
| 434 | /* |
| 435 | * SFP documentation requires the following to configure the SPF module |
| 436 | * to work on SGMII. No further documentation is given. |
| 437 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 438 | ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 439 | if (ret_val) |
| 440 | goto out; |
| 441 | |
| 442 | ret_val = igb_phy_sw_reset(hw); |
| 443 | |
| 444 | out: |
| 445 | return ret_val; |
| 446 | } |
| 447 | |
| 448 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 449 | * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 450 | * @hw: pointer to the HW structure |
| 451 | * @active: true to enable LPLU, false to disable |
| 452 | * |
| 453 | * Sets the LPLU D0 state according to the active flag. When |
| 454 | * activating LPLU this function also disables smart speed |
| 455 | * and vice versa. LPLU will not be activated unless the |
| 456 | * device autonegotiation advertisement meets standards of |
| 457 | * either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 458 | * This is a function pointer entry point only called by |
| 459 | * PHY setup routines. |
| 460 | **/ |
| 461 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) |
| 462 | { |
| 463 | struct e1000_phy_info *phy = &hw->phy; |
| 464 | s32 ret_val; |
| 465 | u16 data; |
| 466 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 467 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 468 | if (ret_val) |
| 469 | goto out; |
| 470 | |
| 471 | if (active) { |
| 472 | data |= IGP02E1000_PM_D0_LPLU; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 473 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 474 | data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 475 | if (ret_val) |
| 476 | goto out; |
| 477 | |
| 478 | /* When LPLU is enabled, we should disable SmartSpeed */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 479 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 480 | &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 481 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 482 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 483 | data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 484 | if (ret_val) |
| 485 | goto out; |
| 486 | } else { |
| 487 | data &= ~IGP02E1000_PM_D0_LPLU; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 488 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 489 | data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 490 | /* |
| 491 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used |
| 492 | * during Dx states where the power conservation is most |
| 493 | * important. During driver activity we should enable |
| 494 | * SmartSpeed, so performance is maintained. |
| 495 | */ |
| 496 | if (phy->smart_speed == e1000_smart_speed_on) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 497 | ret_val = phy->ops.read_reg(hw, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 498 | IGP01E1000_PHY_PORT_CONFIG, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 499 | if (ret_val) |
| 500 | goto out; |
| 501 | |
| 502 | data |= IGP01E1000_PSCFR_SMART_SPEED; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 503 | ret_val = phy->ops.write_reg(hw, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 504 | IGP01E1000_PHY_PORT_CONFIG, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 505 | if (ret_val) |
| 506 | goto out; |
| 507 | } else if (phy->smart_speed == e1000_smart_speed_off) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 508 | ret_val = phy->ops.read_reg(hw, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 509 | IGP01E1000_PHY_PORT_CONFIG, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 510 | if (ret_val) |
| 511 | goto out; |
| 512 | |
| 513 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 514 | ret_val = phy->ops.write_reg(hw, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 515 | IGP01E1000_PHY_PORT_CONFIG, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 516 | if (ret_val) |
| 517 | goto out; |
| 518 | } |
| 519 | } |
| 520 | |
| 521 | out: |
| 522 | return ret_val; |
| 523 | } |
| 524 | |
| 525 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 526 | * igb_acquire_nvm_82575 - Request for access to EEPROM |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 527 | * @hw: pointer to the HW structure |
| 528 | * |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 529 | * Acquire the necessary semaphores for exclusive access to the EEPROM. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 530 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
| 531 | * Return successful if access grant bit set, else clear the request for |
| 532 | * EEPROM access and return -E1000_ERR_NVM (-1). |
| 533 | **/ |
| 534 | static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) |
| 535 | { |
| 536 | s32 ret_val; |
| 537 | |
| 538 | ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); |
| 539 | if (ret_val) |
| 540 | goto out; |
| 541 | |
| 542 | ret_val = igb_acquire_nvm(hw); |
| 543 | |
| 544 | if (ret_val) |
| 545 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); |
| 546 | |
| 547 | out: |
| 548 | return ret_val; |
| 549 | } |
| 550 | |
| 551 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 552 | * igb_release_nvm_82575 - Release exclusive access to EEPROM |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 553 | * @hw: pointer to the HW structure |
| 554 | * |
| 555 | * Stop any current commands to the EEPROM and clear the EEPROM request bit, |
| 556 | * then release the semaphores acquired. |
| 557 | **/ |
| 558 | static void igb_release_nvm_82575(struct e1000_hw *hw) |
| 559 | { |
| 560 | igb_release_nvm(hw); |
| 561 | igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); |
| 562 | } |
| 563 | |
| 564 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 565 | * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 566 | * @hw: pointer to the HW structure |
| 567 | * @mask: specifies which semaphore to acquire |
| 568 | * |
| 569 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask |
| 570 | * will also specify which port we're acquiring the lock for. |
| 571 | **/ |
| 572 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) |
| 573 | { |
| 574 | u32 swfw_sync; |
| 575 | u32 swmask = mask; |
| 576 | u32 fwmask = mask << 16; |
| 577 | s32 ret_val = 0; |
| 578 | s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ |
| 579 | |
| 580 | while (i < timeout) { |
| 581 | if (igb_get_hw_semaphore(hw)) { |
| 582 | ret_val = -E1000_ERR_SWFW_SYNC; |
| 583 | goto out; |
| 584 | } |
| 585 | |
| 586 | swfw_sync = rd32(E1000_SW_FW_SYNC); |
| 587 | if (!(swfw_sync & (fwmask | swmask))) |
| 588 | break; |
| 589 | |
| 590 | /* |
| 591 | * Firmware currently using resource (fwmask) |
| 592 | * or other software thread using resource (swmask) |
| 593 | */ |
| 594 | igb_put_hw_semaphore(hw); |
| 595 | mdelay(5); |
| 596 | i++; |
| 597 | } |
| 598 | |
| 599 | if (i == timeout) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 600 | hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 601 | ret_val = -E1000_ERR_SWFW_SYNC; |
| 602 | goto out; |
| 603 | } |
| 604 | |
| 605 | swfw_sync |= swmask; |
| 606 | wr32(E1000_SW_FW_SYNC, swfw_sync); |
| 607 | |
| 608 | igb_put_hw_semaphore(hw); |
| 609 | |
| 610 | out: |
| 611 | return ret_val; |
| 612 | } |
| 613 | |
| 614 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 615 | * igb_release_swfw_sync_82575 - Release SW/FW semaphore |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 616 | * @hw: pointer to the HW structure |
| 617 | * @mask: specifies which semaphore to acquire |
| 618 | * |
| 619 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask |
| 620 | * will also specify which port we're releasing the lock for. |
| 621 | **/ |
| 622 | static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) |
| 623 | { |
| 624 | u32 swfw_sync; |
| 625 | |
| 626 | while (igb_get_hw_semaphore(hw) != 0); |
| 627 | /* Empty */ |
| 628 | |
| 629 | swfw_sync = rd32(E1000_SW_FW_SYNC); |
| 630 | swfw_sync &= ~mask; |
| 631 | wr32(E1000_SW_FW_SYNC, swfw_sync); |
| 632 | |
| 633 | igb_put_hw_semaphore(hw); |
| 634 | } |
| 635 | |
| 636 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 637 | * igb_get_cfg_done_82575 - Read config done bit |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 638 | * @hw: pointer to the HW structure |
| 639 | * |
| 640 | * Read the management control register for the config done bit for |
| 641 | * completion status. NOTE: silicon which is EEPROM-less will fail trying |
| 642 | * to read the config done bit, so an error is *ONLY* logged and returns |
| 643 | * 0. If we were to return with error, EEPROM-less silicon |
| 644 | * would not be able to be reset or change link. |
| 645 | **/ |
| 646 | static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) |
| 647 | { |
| 648 | s32 timeout = PHY_CFG_TIMEOUT; |
| 649 | s32 ret_val = 0; |
| 650 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; |
| 651 | |
| 652 | if (hw->bus.func == 1) |
| 653 | mask = E1000_NVM_CFG_DONE_PORT_1; |
| 654 | |
| 655 | while (timeout) { |
| 656 | if (rd32(E1000_EEMNGCTL) & mask) |
| 657 | break; |
| 658 | msleep(1); |
| 659 | timeout--; |
| 660 | } |
| 661 | if (!timeout) |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 662 | hw_dbg("MNG configuration cycle has not completed.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 663 | |
| 664 | /* If EEPROM is not marked present, init the PHY manually */ |
| 665 | if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && |
| 666 | (hw->phy.type == e1000_phy_igp_3)) |
| 667 | igb_phy_init_script_igp3(hw); |
| 668 | |
| 669 | return ret_val; |
| 670 | } |
| 671 | |
| 672 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 673 | * igb_check_for_link_82575 - Check for link |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 674 | * @hw: pointer to the HW structure |
| 675 | * |
| 676 | * If sgmii is enabled, then use the pcs register to determine link, otherwise |
| 677 | * use the generic interface for determining link. |
| 678 | **/ |
| 679 | static s32 igb_check_for_link_82575(struct e1000_hw *hw) |
| 680 | { |
| 681 | s32 ret_val; |
| 682 | u16 speed, duplex; |
| 683 | |
| 684 | /* SGMII link check is done through the PCS register. */ |
| 685 | if ((hw->phy.media_type != e1000_media_type_copper) || |
Alexander Duyck | 5d0932a | 2009-01-31 00:53:18 -0800 | [diff] [blame] | 686 | (igb_sgmii_active_82575(hw))) { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 687 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 688 | &duplex); |
Alexander Duyck | 5d0932a | 2009-01-31 00:53:18 -0800 | [diff] [blame] | 689 | /* |
| 690 | * Use this flag to determine if link needs to be checked or |
| 691 | * not. If we have link clear the flag so that we do not |
| 692 | * continue to check for link. |
| 693 | */ |
| 694 | hw->mac.get_link_status = !hw->mac.serdes_has_link; |
| 695 | } else { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 696 | ret_val = igb_check_for_copper_link(hw); |
Alexander Duyck | 5d0932a | 2009-01-31 00:53:18 -0800 | [diff] [blame] | 697 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 698 | |
| 699 | return ret_val; |
| 700 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 701 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 702 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 703 | * @hw: pointer to the HW structure |
| 704 | * @speed: stores the current speed |
| 705 | * @duplex: stores the current duplex |
| 706 | * |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 707 | * Using the physical coding sub-layer (PCS), retrieve the current speed and |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 708 | * duplex, then store the values in the pointers provided. |
| 709 | **/ |
| 710 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, |
| 711 | u16 *duplex) |
| 712 | { |
| 713 | struct e1000_mac_info *mac = &hw->mac; |
| 714 | u32 pcs; |
| 715 | |
| 716 | /* Set up defaults for the return values of this function */ |
| 717 | mac->serdes_has_link = false; |
| 718 | *speed = 0; |
| 719 | *duplex = 0; |
| 720 | |
| 721 | /* |
| 722 | * Read the PCS Status register for link state. For non-copper mode, |
| 723 | * the status register is not accurate. The PCS status register is |
| 724 | * used instead. |
| 725 | */ |
| 726 | pcs = rd32(E1000_PCS_LSTAT); |
| 727 | |
| 728 | /* |
| 729 | * The link up bit determines when link is up on autoneg. The sync ok |
| 730 | * gets set once both sides sync up and agree upon link. Stable link |
| 731 | * can be determined by checking for both link up and link sync ok |
| 732 | */ |
| 733 | if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { |
| 734 | mac->serdes_has_link = true; |
| 735 | |
| 736 | /* Detect and store PCS speed */ |
| 737 | if (pcs & E1000_PCS_LSTS_SPEED_1000) { |
| 738 | *speed = SPEED_1000; |
| 739 | } else if (pcs & E1000_PCS_LSTS_SPEED_100) { |
| 740 | *speed = SPEED_100; |
| 741 | } else { |
| 742 | *speed = SPEED_10; |
| 743 | } |
| 744 | |
| 745 | /* Detect and store PCS duplex */ |
| 746 | if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { |
| 747 | *duplex = FULL_DUPLEX; |
| 748 | } else { |
| 749 | *duplex = HALF_DUPLEX; |
| 750 | } |
| 751 | } |
| 752 | |
| 753 | return 0; |
| 754 | } |
| 755 | |
| 756 | /** |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 757 | * igb_init_rx_addrs_82575 - Initialize receive address's |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 758 | * @hw: pointer to the HW structure |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 759 | * @rar_count: receive address registers |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 760 | * |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 761 | * Setups the receive address registers by setting the base receive address |
| 762 | * register to the devices MAC address and clearing all the other receive |
| 763 | * address registers to 0. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 764 | **/ |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 765 | static void igb_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 766 | { |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 767 | u32 i; |
| 768 | u8 addr[6] = {0,0,0,0,0,0}; |
| 769 | /* |
| 770 | * This function is essentially the same as that of |
| 771 | * e1000_init_rx_addrs_generic. However it also takes care |
| 772 | * of the special case where the register offset of the |
| 773 | * second set of RARs begins elsewhere. This is implicitly taken care by |
| 774 | * function e1000_rar_set_generic. |
| 775 | */ |
| 776 | |
| 777 | hw_dbg("e1000_init_rx_addrs_82575"); |
| 778 | |
| 779 | /* Setup the receive address */ |
| 780 | hw_dbg("Programming MAC Address into RAR[0]\n"); |
| 781 | hw->mac.ops.rar_set(hw, hw->mac.addr, 0); |
| 782 | |
| 783 | /* Zero out the other (rar_entry_count - 1) receive addresses */ |
| 784 | hw_dbg("Clearing RAR[1-%u]\n", rar_count-1); |
| 785 | for (i = 1; i < rar_count; i++) |
| 786 | hw->mac.ops.rar_set(hw, addr, i); |
| 787 | } |
| 788 | |
| 789 | /** |
Alexander Duyck | 8a90086 | 2009-02-06 23:20:10 +0000 | [diff] [blame] | 790 | * igb_update_mc_addr_list - Update Multicast addresses |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 791 | * @hw: pointer to the HW structure |
| 792 | * @mc_addr_list: array of multicast addresses to program |
| 793 | * @mc_addr_count: number of multicast addresses to program |
| 794 | * @rar_used_count: the first RAR register free to program |
| 795 | * @rar_count: total number of supported Receive Address Registers |
| 796 | * |
| 797 | * Updates the Receive Address Registers and Multicast Table Array. |
| 798 | * The caller must have a packed mc_addr_list of multicast addresses. |
| 799 | * The parameter rar_count will usually be hw->mac.rar_entry_count |
| 800 | * unless there are workarounds that change this. |
| 801 | **/ |
Alexander Duyck | 8a90086 | 2009-02-06 23:20:10 +0000 | [diff] [blame] | 802 | void igb_update_mc_addr_list(struct e1000_hw *hw, |
| 803 | u8 *mc_addr_list, u32 mc_addr_count, |
| 804 | u32 rar_used_count, u32 rar_count) |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 805 | { |
| 806 | u32 hash_value; |
| 807 | u32 i; |
| 808 | u8 addr[6] = {0,0,0,0,0,0}; |
| 809 | /* |
| 810 | * This function is essentially the same as that of |
| 811 | * igb_update_mc_addr_list_generic. However it also takes care |
| 812 | * of the special case where the register offset of the |
| 813 | * second set of RARs begins elsewhere. This is implicitly taken care by |
| 814 | * function e1000_rar_set_generic. |
| 815 | */ |
| 816 | |
| 817 | /* |
| 818 | * Load the first set of multicast addresses into the exact |
| 819 | * filters (RAR). If there are not enough to fill the RAR |
| 820 | * array, clear the filters. |
| 821 | */ |
| 822 | for (i = rar_used_count; i < rar_count; i++) { |
| 823 | if (mc_addr_count) { |
| 824 | igb_rar_set(hw, mc_addr_list, i); |
| 825 | mc_addr_count--; |
| 826 | mc_addr_list += ETH_ALEN; |
| 827 | } else { |
| 828 | igb_rar_set(hw, addr, i); |
| 829 | } |
| 830 | } |
| 831 | |
| 832 | /* Clear the old settings from the MTA */ |
| 833 | hw_dbg("Clearing MTA\n"); |
| 834 | for (i = 0; i < hw->mac.mta_reg_count; i++) { |
| 835 | array_wr32(E1000_MTA, i, 0); |
| 836 | wrfl(); |
| 837 | } |
| 838 | |
| 839 | /* Load any remaining multicast addresses into the hash table. */ |
| 840 | for (; mc_addr_count > 0; mc_addr_count--) { |
| 841 | hash_value = igb_hash_mc_addr(hw, mc_addr_list); |
| 842 | hw_dbg("Hash value = 0x%03X\n", hash_value); |
Alexander Duyck | 549bdd8 | 2008-08-04 15:00:06 -0700 | [diff] [blame] | 843 | igb_mta_set(hw, hash_value); |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 844 | mc_addr_list += ETH_ALEN; |
| 845 | } |
| 846 | } |
| 847 | |
| 848 | /** |
| 849 | * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down |
| 850 | * @hw: pointer to the HW structure |
| 851 | * |
| 852 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
| 853 | * when management pass thru is not enabled. |
| 854 | **/ |
| 855 | void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) |
| 856 | { |
| 857 | u32 reg; |
| 858 | |
| 859 | if (hw->mac.type != e1000_82576 || |
| 860 | (hw->phy.media_type != e1000_media_type_fiber && |
| 861 | hw->phy.media_type != e1000_media_type_internal_serdes)) |
| 862 | return; |
| 863 | |
| 864 | /* if the management interface is not enabled, then power down */ |
| 865 | if (!igb_enable_mng_pass_thru(hw)) { |
| 866 | /* Disable PCS to turn off link */ |
| 867 | reg = rd32(E1000_PCS_CFG0); |
| 868 | reg &= ~E1000_PCS_CFG_PCS_EN; |
| 869 | wr32(E1000_PCS_CFG0, reg); |
| 870 | |
| 871 | /* shutdown the laser */ |
| 872 | reg = rd32(E1000_CTRL_EXT); |
| 873 | reg |= E1000_CTRL_EXT_SDP7_DATA; |
| 874 | wr32(E1000_CTRL_EXT, reg); |
| 875 | |
| 876 | /* flush the write to verify completion */ |
| 877 | wrfl(); |
| 878 | msleep(1); |
| 879 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 880 | |
| 881 | return; |
| 882 | } |
| 883 | |
| 884 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 885 | * igb_reset_hw_82575 - Reset hardware |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 886 | * @hw: pointer to the HW structure |
| 887 | * |
| 888 | * This resets the hardware into a known state. This is a |
| 889 | * function pointer entry point called by the api module. |
| 890 | **/ |
| 891 | static s32 igb_reset_hw_82575(struct e1000_hw *hw) |
| 892 | { |
| 893 | u32 ctrl, icr; |
| 894 | s32 ret_val; |
| 895 | |
| 896 | /* |
| 897 | * Prevent the PCI-E bus from sticking if there is no TLP connection |
| 898 | * on the last TLP read/write transaction when MAC is reset. |
| 899 | */ |
| 900 | ret_val = igb_disable_pcie_master(hw); |
| 901 | if (ret_val) |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 902 | hw_dbg("PCI-E Master disable polling has failed.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 903 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 904 | hw_dbg("Masking off all interrupts\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 905 | wr32(E1000_IMC, 0xffffffff); |
| 906 | |
| 907 | wr32(E1000_RCTL, 0); |
| 908 | wr32(E1000_TCTL, E1000_TCTL_PSP); |
| 909 | wrfl(); |
| 910 | |
| 911 | msleep(10); |
| 912 | |
| 913 | ctrl = rd32(E1000_CTRL); |
| 914 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 915 | hw_dbg("Issuing a global reset to MAC\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 916 | wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); |
| 917 | |
| 918 | ret_val = igb_get_auto_rd_done(hw); |
| 919 | if (ret_val) { |
| 920 | /* |
| 921 | * When auto config read does not complete, do not |
| 922 | * return with an error. This can happen in situations |
| 923 | * where there is no eeprom and prevents getting link. |
| 924 | */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 925 | hw_dbg("Auto Read Done did not complete\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 926 | } |
| 927 | |
| 928 | /* If EEPROM is not present, run manual init scripts */ |
| 929 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) |
| 930 | igb_reset_init_script_82575(hw); |
| 931 | |
| 932 | /* Clear any pending interrupt events. */ |
| 933 | wr32(E1000_IMC, 0xffffffff); |
| 934 | icr = rd32(E1000_ICR); |
| 935 | |
| 936 | igb_check_alt_mac_addr(hw); |
| 937 | |
| 938 | return ret_val; |
| 939 | } |
| 940 | |
| 941 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 942 | * igb_init_hw_82575 - Initialize hardware |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 943 | * @hw: pointer to the HW structure |
| 944 | * |
| 945 | * This inits the hardware readying it for operation. |
| 946 | **/ |
| 947 | static s32 igb_init_hw_82575(struct e1000_hw *hw) |
| 948 | { |
| 949 | struct e1000_mac_info *mac = &hw->mac; |
| 950 | s32 ret_val; |
| 951 | u16 i, rar_count = mac->rar_entry_count; |
| 952 | |
| 953 | /* Initialize identification LED */ |
| 954 | ret_val = igb_id_led_init(hw); |
| 955 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 956 | hw_dbg("Error initializing identification LED\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 957 | /* This is not fatal and we should not stop init due to this */ |
| 958 | } |
| 959 | |
| 960 | /* Disabling VLAN filtering */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 961 | hw_dbg("Initializing the IEEE VLAN\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 962 | igb_clear_vfta(hw); |
| 963 | |
| 964 | /* Setup the receive address */ |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 965 | igb_init_rx_addrs_82575(hw, rar_count); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 966 | /* Zero out the Multicast HASH table */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 967 | hw_dbg("Zeroing the MTA\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 968 | for (i = 0; i < mac->mta_reg_count; i++) |
| 969 | array_wr32(E1000_MTA, i, 0); |
| 970 | |
| 971 | /* Setup link and flow control */ |
| 972 | ret_val = igb_setup_link(hw); |
| 973 | |
| 974 | /* |
| 975 | * Clear all of the statistics registers (clear on read). It is |
| 976 | * important that we do this after we have tried to establish link |
| 977 | * because the symbol error count will increment wildly if there |
| 978 | * is no link. |
| 979 | */ |
| 980 | igb_clear_hw_cntrs_82575(hw); |
| 981 | |
| 982 | return ret_val; |
| 983 | } |
| 984 | |
| 985 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 986 | * igb_setup_copper_link_82575 - Configure copper link settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 987 | * @hw: pointer to the HW structure |
| 988 | * |
| 989 | * Configures the link for auto-neg or forced speed and duplex. Then we check |
| 990 | * for link, once link is established calls to configure collision distance |
| 991 | * and flow control are called. |
| 992 | **/ |
| 993 | static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) |
| 994 | { |
| 995 | u32 ctrl, led_ctrl; |
| 996 | s32 ret_val; |
| 997 | bool link; |
| 998 | |
| 999 | ctrl = rd32(E1000_CTRL); |
| 1000 | ctrl |= E1000_CTRL_SLU; |
| 1001 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 1002 | wr32(E1000_CTRL, ctrl); |
| 1003 | |
| 1004 | switch (hw->phy.type) { |
| 1005 | case e1000_phy_m88: |
| 1006 | ret_val = igb_copper_link_setup_m88(hw); |
| 1007 | break; |
| 1008 | case e1000_phy_igp_3: |
| 1009 | ret_val = igb_copper_link_setup_igp(hw); |
| 1010 | /* Setup activity LED */ |
| 1011 | led_ctrl = rd32(E1000_LEDCTL); |
| 1012 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
| 1013 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
| 1014 | wr32(E1000_LEDCTL, led_ctrl); |
| 1015 | break; |
| 1016 | default: |
| 1017 | ret_val = -E1000_ERR_PHY; |
| 1018 | break; |
| 1019 | } |
| 1020 | |
| 1021 | if (ret_val) |
| 1022 | goto out; |
| 1023 | |
| 1024 | if (hw->mac.autoneg) { |
| 1025 | /* |
| 1026 | * Setup autoneg and flow control advertisement |
| 1027 | * and perform autonegotiation. |
| 1028 | */ |
| 1029 | ret_val = igb_copper_link_autoneg(hw); |
| 1030 | if (ret_val) |
| 1031 | goto out; |
| 1032 | } else { |
| 1033 | /* |
| 1034 | * PHY will be set to 10H, 10F, 100H or 100F |
| 1035 | * depending on user settings. |
| 1036 | */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1037 | hw_dbg("Forcing Speed and Duplex\n"); |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1038 | ret_val = hw->phy.ops.force_speed_duplex(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1039 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1040 | hw_dbg("Error Forcing Speed and Duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1041 | goto out; |
| 1042 | } |
| 1043 | } |
| 1044 | |
| 1045 | ret_val = igb_configure_pcs_link_82575(hw); |
| 1046 | if (ret_val) |
| 1047 | goto out; |
| 1048 | |
| 1049 | /* |
| 1050 | * Check link status. Wait up to 100 microseconds for link to become |
| 1051 | * valid. |
| 1052 | */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1053 | ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1054 | if (ret_val) |
| 1055 | goto out; |
| 1056 | |
| 1057 | if (link) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1058 | hw_dbg("Valid link established!!!\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1059 | /* Config the MAC and PHY after link is up */ |
| 1060 | igb_config_collision_dist(hw); |
| 1061 | ret_val = igb_config_fc_after_link_up(hw); |
| 1062 | } else { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1063 | hw_dbg("Unable to establish link!!!\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1064 | } |
| 1065 | |
| 1066 | out: |
| 1067 | return ret_val; |
| 1068 | } |
| 1069 | |
| 1070 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1071 | * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1072 | * @hw: pointer to the HW structure |
| 1073 | * |
| 1074 | * Configures speed and duplex for fiber and serdes links. |
| 1075 | **/ |
| 1076 | static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw) |
| 1077 | { |
| 1078 | u32 reg; |
| 1079 | |
| 1080 | /* |
| 1081 | * On the 82575, SerDes loopback mode persists until it is |
| 1082 | * explicitly turned off or a power cycle is performed. A read to |
| 1083 | * the register does not indicate its status. Therefore, we ensure |
| 1084 | * loopback mode is disabled during initialization. |
| 1085 | */ |
| 1086 | wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
| 1087 | |
| 1088 | /* Force link up, set 1gb, set both sw defined pins */ |
| 1089 | reg = rd32(E1000_CTRL); |
| 1090 | reg |= E1000_CTRL_SLU | |
| 1091 | E1000_CTRL_SPD_1000 | |
| 1092 | E1000_CTRL_FRCSPD | |
| 1093 | E1000_CTRL_SWDPIN0 | |
| 1094 | E1000_CTRL_SWDPIN1; |
| 1095 | wr32(E1000_CTRL, reg); |
| 1096 | |
Alexander Duyck | 921aa74 | 2009-01-21 14:42:28 -0800 | [diff] [blame] | 1097 | /* Power on phy for 82576 fiber adapters */ |
| 1098 | if (hw->mac.type == e1000_82576) { |
| 1099 | reg = rd32(E1000_CTRL_EXT); |
| 1100 | reg &= ~E1000_CTRL_EXT_SDP7_DATA; |
| 1101 | wr32(E1000_CTRL_EXT, reg); |
| 1102 | } |
| 1103 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1104 | /* Set switch control to serdes energy detect */ |
| 1105 | reg = rd32(E1000_CONNSW); |
| 1106 | reg |= E1000_CONNSW_ENRGSRC; |
| 1107 | wr32(E1000_CONNSW, reg); |
| 1108 | |
| 1109 | /* |
| 1110 | * New SerDes mode allows for forcing speed or autonegotiating speed |
| 1111 | * at 1gb. Autoneg should be default set by most drivers. This is the |
| 1112 | * mode that will be compatible with older link partners and switches. |
| 1113 | * However, both are supported by the hardware and some drivers/tools. |
| 1114 | */ |
| 1115 | reg = rd32(E1000_PCS_LCTL); |
| 1116 | |
| 1117 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | |
| 1118 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); |
| 1119 | |
| 1120 | if (hw->mac.autoneg) { |
| 1121 | /* Set PCS register for autoneg */ |
| 1122 | reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ |
| 1123 | E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ |
| 1124 | E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ |
| 1125 | E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1126 | hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1127 | } else { |
| 1128 | /* Set PCS register for forced speed */ |
| 1129 | reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ |
| 1130 | E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ |
| 1131 | E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ |
| 1132 | E1000_PCS_LCTL_FSD | /* Force Speed */ |
| 1133 | E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1134 | hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1135 | } |
Alexander Duyck | 726c09e | 2008-08-04 14:59:56 -0700 | [diff] [blame] | 1136 | |
| 1137 | if (hw->mac.type == e1000_82576) { |
| 1138 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; |
| 1139 | igb_force_mac_fc(hw); |
| 1140 | } |
| 1141 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1142 | wr32(E1000_PCS_LCTL, reg); |
| 1143 | |
| 1144 | return 0; |
| 1145 | } |
| 1146 | |
| 1147 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1148 | * igb_configure_pcs_link_82575 - Configure PCS link |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1149 | * @hw: pointer to the HW structure |
| 1150 | * |
| 1151 | * Configure the physical coding sub-layer (PCS) link. The PCS link is |
| 1152 | * only used on copper connections where the serialized gigabit media |
| 1153 | * independent interface (sgmii) is being used. Configures the link |
| 1154 | * for auto-negotiation or forces speed/duplex. |
| 1155 | **/ |
| 1156 | static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw) |
| 1157 | { |
| 1158 | struct e1000_mac_info *mac = &hw->mac; |
| 1159 | u32 reg = 0; |
| 1160 | |
| 1161 | if (hw->phy.media_type != e1000_media_type_copper || |
| 1162 | !(igb_sgmii_active_82575(hw))) |
| 1163 | goto out; |
| 1164 | |
| 1165 | /* For SGMII, we need to issue a PCS autoneg restart */ |
| 1166 | reg = rd32(E1000_PCS_LCTL); |
| 1167 | |
| 1168 | /* AN time out should be disabled for SGMII mode */ |
| 1169 | reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); |
| 1170 | |
| 1171 | if (mac->autoneg) { |
| 1172 | /* Make sure forced speed and force link are not set */ |
| 1173 | reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); |
| 1174 | |
| 1175 | /* |
| 1176 | * The PHY should be setup prior to calling this function. |
| 1177 | * All we need to do is restart autoneg and enable autoneg. |
| 1178 | */ |
| 1179 | reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; |
| 1180 | } else { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1181 | /* Set PCS register for forced speed */ |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1182 | |
| 1183 | /* Turn off bits for full duplex, speed, and autoneg */ |
| 1184 | reg &= ~(E1000_PCS_LCTL_FSV_1000 | |
| 1185 | E1000_PCS_LCTL_FSV_100 | |
| 1186 | E1000_PCS_LCTL_FDV_FULL | |
| 1187 | E1000_PCS_LCTL_AN_ENABLE); |
| 1188 | |
| 1189 | /* Check for duplex first */ |
| 1190 | if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX) |
| 1191 | reg |= E1000_PCS_LCTL_FDV_FULL; |
| 1192 | |
| 1193 | /* Now set speed */ |
| 1194 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) |
| 1195 | reg |= E1000_PCS_LCTL_FSV_100; |
| 1196 | |
| 1197 | /* Force speed and force link */ |
| 1198 | reg |= E1000_PCS_LCTL_FSD | |
| 1199 | E1000_PCS_LCTL_FORCE_LINK | |
| 1200 | E1000_PCS_LCTL_FLV_LINK_UP; |
| 1201 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1202 | hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n", |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1203 | reg); |
| 1204 | } |
| 1205 | wr32(E1000_PCS_LCTL, reg); |
| 1206 | |
| 1207 | out: |
| 1208 | return 0; |
| 1209 | } |
| 1210 | |
| 1211 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1212 | * igb_sgmii_active_82575 - Return sgmii state |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1213 | * @hw: pointer to the HW structure |
| 1214 | * |
| 1215 | * 82575 silicon has a serialized gigabit media independent interface (sgmii) |
| 1216 | * which can be enabled for use in the embedded applications. Simply |
| 1217 | * return the current state of the sgmii interface. |
| 1218 | **/ |
| 1219 | static bool igb_sgmii_active_82575(struct e1000_hw *hw) |
| 1220 | { |
Alexander Duyck | c1889bf | 2009-02-06 23:16:45 +0000 | [diff] [blame] | 1221 | struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1222 | |
Alexander Duyck | c1889bf | 2009-02-06 23:16:45 +0000 | [diff] [blame] | 1223 | if (hw->mac.type != e1000_82575 && hw->mac.type != e1000_82576) |
| 1224 | return false; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1225 | |
Alexander Duyck | c1889bf | 2009-02-06 23:16:45 +0000 | [diff] [blame] | 1226 | return dev_spec->sgmii_active; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1227 | } |
| 1228 | |
| 1229 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1230 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1231 | * @hw: pointer to the HW structure |
| 1232 | * |
| 1233 | * Inits recommended HW defaults after a reset when there is no EEPROM |
| 1234 | * detected. This is only for the 82575. |
| 1235 | **/ |
| 1236 | static s32 igb_reset_init_script_82575(struct e1000_hw *hw) |
| 1237 | { |
| 1238 | if (hw->mac.type == e1000_82575) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1239 | hw_dbg("Running reset init script for 82575\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1240 | /* SerDes configuration via SERDESCTRL */ |
| 1241 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); |
| 1242 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); |
| 1243 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); |
| 1244 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); |
| 1245 | |
| 1246 | /* CCM configuration via CCMCTL register */ |
| 1247 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); |
| 1248 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); |
| 1249 | |
| 1250 | /* PCIe lanes configuration */ |
| 1251 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); |
| 1252 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); |
| 1253 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); |
| 1254 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); |
| 1255 | |
| 1256 | /* PCIe PLL Configuration */ |
| 1257 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); |
| 1258 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); |
| 1259 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); |
| 1260 | } |
| 1261 | |
| 1262 | return 0; |
| 1263 | } |
| 1264 | |
| 1265 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1266 | * igb_read_mac_addr_82575 - Read device MAC address |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1267 | * @hw: pointer to the HW structure |
| 1268 | **/ |
| 1269 | static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) |
| 1270 | { |
| 1271 | s32 ret_val = 0; |
| 1272 | |
| 1273 | if (igb_check_alt_mac_addr(hw)) |
| 1274 | ret_val = igb_read_mac_addr(hw); |
| 1275 | |
| 1276 | return ret_val; |
| 1277 | } |
| 1278 | |
| 1279 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1280 | * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1281 | * @hw: pointer to the HW structure |
| 1282 | * |
| 1283 | * Clears the hardware counters by reading the counter registers. |
| 1284 | **/ |
| 1285 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) |
| 1286 | { |
| 1287 | u32 temp; |
| 1288 | |
| 1289 | igb_clear_hw_cntrs_base(hw); |
| 1290 | |
| 1291 | temp = rd32(E1000_PRC64); |
| 1292 | temp = rd32(E1000_PRC127); |
| 1293 | temp = rd32(E1000_PRC255); |
| 1294 | temp = rd32(E1000_PRC511); |
| 1295 | temp = rd32(E1000_PRC1023); |
| 1296 | temp = rd32(E1000_PRC1522); |
| 1297 | temp = rd32(E1000_PTC64); |
| 1298 | temp = rd32(E1000_PTC127); |
| 1299 | temp = rd32(E1000_PTC255); |
| 1300 | temp = rd32(E1000_PTC511); |
| 1301 | temp = rd32(E1000_PTC1023); |
| 1302 | temp = rd32(E1000_PTC1522); |
| 1303 | |
| 1304 | temp = rd32(E1000_ALGNERRC); |
| 1305 | temp = rd32(E1000_RXERRC); |
| 1306 | temp = rd32(E1000_TNCRS); |
| 1307 | temp = rd32(E1000_CEXTERR); |
| 1308 | temp = rd32(E1000_TSCTC); |
| 1309 | temp = rd32(E1000_TSCTFC); |
| 1310 | |
| 1311 | temp = rd32(E1000_MGTPRC); |
| 1312 | temp = rd32(E1000_MGTPDC); |
| 1313 | temp = rd32(E1000_MGTPTC); |
| 1314 | |
| 1315 | temp = rd32(E1000_IAC); |
| 1316 | temp = rd32(E1000_ICRXOC); |
| 1317 | |
| 1318 | temp = rd32(E1000_ICRXPTC); |
| 1319 | temp = rd32(E1000_ICRXATC); |
| 1320 | temp = rd32(E1000_ICTXPTC); |
| 1321 | temp = rd32(E1000_ICTXATC); |
| 1322 | temp = rd32(E1000_ICTXQEC); |
| 1323 | temp = rd32(E1000_ICTXQMTC); |
| 1324 | temp = rd32(E1000_ICRXDMTC); |
| 1325 | |
| 1326 | temp = rd32(E1000_CBTMPC); |
| 1327 | temp = rd32(E1000_HTDPMC); |
| 1328 | temp = rd32(E1000_CBRMPC); |
| 1329 | temp = rd32(E1000_RPTHC); |
| 1330 | temp = rd32(E1000_HGPTC); |
| 1331 | temp = rd32(E1000_HTCBDPC); |
| 1332 | temp = rd32(E1000_HGORCL); |
| 1333 | temp = rd32(E1000_HGORCH); |
| 1334 | temp = rd32(E1000_HGOTCL); |
| 1335 | temp = rd32(E1000_HGOTCH); |
| 1336 | temp = rd32(E1000_LENERRS); |
| 1337 | |
| 1338 | /* This register should not be read in copper configurations */ |
| 1339 | if (hw->phy.media_type == e1000_media_type_internal_serdes) |
| 1340 | temp = rd32(E1000_SCVPC); |
| 1341 | } |
| 1342 | |
Alexander Duyck | 662d720 | 2008-06-27 11:00:29 -0700 | [diff] [blame] | 1343 | /** |
| 1344 | * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable |
| 1345 | * @hw: pointer to the HW structure |
| 1346 | * |
| 1347 | * After rx enable if managability is enabled then there is likely some |
| 1348 | * bad data at the start of the fifo and possibly in the DMA fifo. This |
| 1349 | * function clears the fifos and flushes any packets that came in as rx was |
| 1350 | * being enabled. |
| 1351 | **/ |
| 1352 | void igb_rx_fifo_flush_82575(struct e1000_hw *hw) |
| 1353 | { |
| 1354 | u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; |
| 1355 | int i, ms_wait; |
| 1356 | |
| 1357 | if (hw->mac.type != e1000_82575 || |
| 1358 | !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) |
| 1359 | return; |
| 1360 | |
| 1361 | /* Disable all RX queues */ |
| 1362 | for (i = 0; i < 4; i++) { |
| 1363 | rxdctl[i] = rd32(E1000_RXDCTL(i)); |
| 1364 | wr32(E1000_RXDCTL(i), |
| 1365 | rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); |
| 1366 | } |
| 1367 | /* Poll all queues to verify they have shut down */ |
| 1368 | for (ms_wait = 0; ms_wait < 10; ms_wait++) { |
| 1369 | msleep(1); |
| 1370 | rx_enabled = 0; |
| 1371 | for (i = 0; i < 4; i++) |
| 1372 | rx_enabled |= rd32(E1000_RXDCTL(i)); |
| 1373 | if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) |
| 1374 | break; |
| 1375 | } |
| 1376 | |
| 1377 | if (ms_wait == 10) |
| 1378 | hw_dbg("Queue disable timed out after 10ms\n"); |
| 1379 | |
| 1380 | /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all |
| 1381 | * incoming packets are rejected. Set enable and wait 2ms so that |
| 1382 | * any packet that was coming in as RCTL.EN was set is flushed |
| 1383 | */ |
| 1384 | rfctl = rd32(E1000_RFCTL); |
| 1385 | wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); |
| 1386 | |
| 1387 | rlpml = rd32(E1000_RLPML); |
| 1388 | wr32(E1000_RLPML, 0); |
| 1389 | |
| 1390 | rctl = rd32(E1000_RCTL); |
| 1391 | temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); |
| 1392 | temp_rctl |= E1000_RCTL_LPE; |
| 1393 | |
| 1394 | wr32(E1000_RCTL, temp_rctl); |
| 1395 | wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); |
| 1396 | wrfl(); |
| 1397 | msleep(2); |
| 1398 | |
| 1399 | /* Enable RX queues that were previously enabled and restore our |
| 1400 | * previous state |
| 1401 | */ |
| 1402 | for (i = 0; i < 4; i++) |
| 1403 | wr32(E1000_RXDCTL(i), rxdctl[i]); |
| 1404 | wr32(E1000_RCTL, rctl); |
| 1405 | wrfl(); |
| 1406 | |
| 1407 | wr32(E1000_RLPML, rlpml); |
| 1408 | wr32(E1000_RFCTL, rfctl); |
| 1409 | |
| 1410 | /* Flush receive errors generated by workaround */ |
| 1411 | rd32(E1000_ROC); |
| 1412 | rd32(E1000_RNBC); |
| 1413 | rd32(E1000_MPC); |
| 1414 | } |
| 1415 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1416 | static struct e1000_mac_operations e1000_mac_ops_82575 = { |
| 1417 | .reset_hw = igb_reset_hw_82575, |
| 1418 | .init_hw = igb_init_hw_82575, |
| 1419 | .check_for_link = igb_check_for_link_82575, |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 1420 | .rar_set = igb_rar_set, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1421 | .read_mac_addr = igb_read_mac_addr_82575, |
| 1422 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, |
| 1423 | }; |
| 1424 | |
| 1425 | static struct e1000_phy_operations e1000_phy_ops_82575 = { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1426 | .acquire = igb_acquire_phy_82575, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1427 | .get_cfg_done = igb_get_cfg_done_82575, |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1428 | .release = igb_release_phy_82575, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1429 | }; |
| 1430 | |
| 1431 | static struct e1000_nvm_operations e1000_nvm_ops_82575 = { |
Alexander Duyck | 312c75a | 2009-02-06 23:17:47 +0000 | [diff] [blame] | 1432 | .acquire = igb_acquire_nvm_82575, |
| 1433 | .read = igb_read_nvm_eerd, |
| 1434 | .release = igb_release_nvm_82575, |
| 1435 | .write = igb_write_nvm_spi, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1436 | }; |
| 1437 | |
| 1438 | const struct e1000_info e1000_82575_info = { |
| 1439 | .get_invariants = igb_get_invariants_82575, |
| 1440 | .mac_ops = &e1000_mac_ops_82575, |
| 1441 | .phy_ops = &e1000_phy_ops_82575, |
| 1442 | .nvm_ops = &e1000_nvm_ops_82575, |
| 1443 | }; |
| 1444 | |