blob: efe2cd699b77d5ad6524faeec558bf95c5e74408 [file] [log] [blame]
Jarkko Nikula2e747962008-04-25 13:55:19 +02001/*
2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
Jarkko Nikula7ec41ee2011-08-11 15:44:57 +03006 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
Peter Ujfalusi56a87422011-05-03 18:14:06 +03007 * Peter Ujfalusi <peter.ujfalusi@ti.com>
Jarkko Nikula2e747962008-04-25 13:55:19 +02008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
Peter Ujfalusi2ee65952012-02-14 14:52:42 +020028#include <linux/pm_runtime.h>
Peter Ujfalusi11dd5862012-08-16 16:41:08 +030029#include <linux/of.h>
30#include <linux/of_device.h>
Jarkko Nikula2e747962008-04-25 13:55:19 +020031#include <sound/core.h>
32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/initval.h>
35#include <sound/soc.h>
Lars-Peter Clausen09ae3aa2013-04-03 11:06:05 +020036#include <sound/dmaengine_pcm.h>
Jyri Sarha87c19362014-05-26 11:51:14 +030037#include <sound/omap-pcm.h>
Jarkko Nikula2e747962008-04-25 13:55:19 +020038
Arnd Bergmann22037472012-08-24 15:21:06 +020039#include <linux/platform_data/asoc-ti-mcbsp.h>
Peter Ujfalusi219f4312012-02-03 13:11:47 +020040#include "mcbsp.h"
Jarkko Nikula2e747962008-04-25 13:55:19 +020041#include "omap-mcbsp.h"
Jarkko Nikula2e747962008-04-25 13:55:19 +020042
Jarkko Nikula0b604852008-11-12 17:05:51 +020043#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
Jarkko Nikula2e747962008-04-25 13:55:19 +020044
Ilkka Koskinen83905c12010-02-22 12:21:12 +000045#define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
46 xhandler_get, xhandler_put) \
47{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
48 .info = omap_mcbsp_st_info_volsw, \
49 .get = xhandler_get, .put = xhandler_put, \
50 .private_value = (unsigned long) &(struct soc_mixer_control) \
51 {.min = xmin, .max = xmax} }
52
Peter Ujfalusi219f4312012-02-03 13:11:47 +020053enum {
54 OMAP_MCBSP_WORD_8 = 0,
55 OMAP_MCBSP_WORD_12,
56 OMAP_MCBSP_WORD_16,
57 OMAP_MCBSP_WORD_20,
58 OMAP_MCBSP_WORD_24,
59 OMAP_MCBSP_WORD_32,
60};
61
Jarkko Nikula2e747962008-04-25 13:55:19 +020062/*
63 * Stream DMA parameters. DMA request line and port address are set runtime
64 * since they are different between OMAP1 and later OMAPs
65 */
Lars-Peter Clausenabe99372013-03-25 16:58:16 +010066static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
67 unsigned int packet_size)
Eduardo Valentincaebc0c2009-08-20 16:18:25 +030068{
69 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +000070 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
Peter Ujfalusi45656b42012-02-14 18:20:58 +020071 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi3f024032010-06-03 07:39:35 +030072 int words;
Eduardo Valentina0a499c2009-08-20 16:18:26 +030073
Peter Ujfalusi778a17c2012-03-15 12:20:32 +020074 /*
75 * Configure McBSP threshold based on either:
76 * packet_size, when the sDMA is in packet mode, or based on the
77 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
78 * for mono streams.
79 */
Lars-Peter Clausenabe99372013-03-25 16:58:16 +010080 if (packet_size)
81 words = packet_size;
Eduardo Valentina0a499c2009-08-20 16:18:26 +030082 else
Peter Ujfalusi3f024032010-06-03 07:39:35 +030083 words = 1;
Eduardo Valentincaebc0c2009-08-20 16:18:25 +030084
85 /* Configure McBSP internal buffer usage */
86 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
Peter Ujfalusi45656b42012-02-14 18:20:58 +020087 omap_mcbsp_set_tx_threshold(mcbsp, words);
Eduardo Valentincaebc0c2009-08-20 16:18:25 +030088 else
Peter Ujfalusi45656b42012-02-14 18:20:58 +020089 omap_mcbsp_set_rx_threshold(mcbsp, words);
Eduardo Valentincaebc0c2009-08-20 16:18:25 +030090}
91
Peter Ujfalusiddc29b02010-06-03 07:39:36 +030092static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
93 struct snd_pcm_hw_rule *rule)
94{
95 struct snd_interval *buffer_size = hw_param_interval(params,
96 SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
97 struct snd_interval *channels = hw_param_interval(params,
98 SNDRV_PCM_HW_PARAM_CHANNELS);
Peter Ujfalusi45656b42012-02-14 18:20:58 +020099 struct omap_mcbsp *mcbsp = rule->private;
Peter Ujfalusiddc29b02010-06-03 07:39:36 +0300100 struct snd_interval frames;
101 int size;
102
103 snd_interval_any(&frames);
Peter Ujfalusicb40b632012-02-13 16:26:54 +0200104 size = mcbsp->pdata->buffer_size;
Peter Ujfalusiddc29b02010-06-03 07:39:36 +0300105
106 frames.min = size / channels->min;
107 frames.integer = 1;
108 return snd_interval_refine(buffer_size, &frames);
109}
110
Mark Browndee89c42008-11-18 22:11:38 +0000111static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000112 struct snd_soc_dai *cpu_dai)
Jarkko Nikula2e747962008-04-25 13:55:19 +0200113{
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200114 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Jarkko Nikula2e747962008-04-25 13:55:19 +0200115 int err = 0;
116
Eduardo Valentincaebc0c2009-08-20 16:18:25 +0300117 if (!cpu_dai->active)
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200118 err = omap_mcbsp_request(mcbsp);
Eduardo Valentincaebc0c2009-08-20 16:18:25 +0300119
Peter Ujfalusiddc29b02010-06-03 07:39:36 +0300120 /*
121 * OMAP3 McBSP FIFO is word structured.
122 * McBSP2 has 1024 + 256 = 1280 word long buffer,
123 * McBSP1,3,4,5 has 128 word long buffer
124 * This means that the size of the FIFO depends on the sample format.
125 * For example on McBSP3:
126 * 16bit samples: size is 128 * 2 = 256 bytes
127 * 32bit samples: size is 128 * 4 = 512 bytes
128 * It is simpler to place constraint for buffer and period based on
129 * channels.
130 * McBSP3 as example again (16 or 32 bit samples):
131 * 1 channel (mono): size is 128 frames (128 words)
132 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
133 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
134 */
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200135 if (mcbsp->pdata->buffer_size) {
Jarkko Nikula69849922009-03-27 15:32:01 +0200136 /*
Peter Ujfalusi998a8a62010-07-29 09:51:28 +0300137 * Rule for the buffer size. We should not allow
Peter Ujfalusice37f5e2012-03-20 11:47:36 +0200138 * smaller buffer than the FIFO size to avoid underruns.
139 * This applies only for the playback stream.
Peter Ujfalusiddc29b02010-06-03 07:39:36 +0300140 */
Peter Ujfalusice37f5e2012-03-20 11:47:36 +0200141 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
142 snd_pcm_hw_rule_add(substream->runtime, 0,
143 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
144 omap_mcbsp_hwrule_min_buffersize,
145 mcbsp,
146 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
Peter Ujfalusiddc29b02010-06-03 07:39:36 +0300147
Peter Ujfalusi998a8a62010-07-29 09:51:28 +0300148 /* Make sure, that the period size is always even */
149 snd_pcm_hw_constraint_step(substream->runtime, 0,
150 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
Eduardo Valentincaebc0c2009-08-20 16:18:25 +0300151 }
Jarkko Nikula2e747962008-04-25 13:55:19 +0200152
153 return err;
154}
155
Mark Browndee89c42008-11-18 22:11:38 +0000156static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000157 struct snd_soc_dai *cpu_dai)
Jarkko Nikula2e747962008-04-25 13:55:19 +0200158{
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200159 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Jarkko Nikula2e747962008-04-25 13:55:19 +0200160
161 if (!cpu_dai->active) {
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200162 omap_mcbsp_free(mcbsp);
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200163 mcbsp->configured = 0;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200164 }
165}
166
Mark Browndee89c42008-11-18 22:11:38 +0000167static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000168 struct snd_soc_dai *cpu_dai)
Jarkko Nikula2e747962008-04-25 13:55:19 +0200169{
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200170 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Jarkko Nikulac12abc02009-08-07 09:59:47 +0300171 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
Jarkko Nikula2e747962008-04-25 13:55:19 +0200172
173 switch (cmd) {
174 case SNDRV_PCM_TRIGGER_START:
175 case SNDRV_PCM_TRIGGER_RESUME:
176 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200177 mcbsp->active++;
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200178 omap_mcbsp_start(mcbsp, play, !play);
Jarkko Nikula2e747962008-04-25 13:55:19 +0200179 break;
180
181 case SNDRV_PCM_TRIGGER_STOP:
182 case SNDRV_PCM_TRIGGER_SUSPEND:
183 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200184 omap_mcbsp_stop(mcbsp, play, !play);
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200185 mcbsp->active--;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200186 break;
187 default:
188 err = -EINVAL;
189 }
190
191 return err;
192}
193
Peter Ujfalusi75581d22010-03-03 15:08:09 +0200194static snd_pcm_sframes_t omap_mcbsp_dai_delay(
195 struct snd_pcm_substream *substream,
196 struct snd_soc_dai *dai)
197{
198 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000199 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200200 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi75581d22010-03-03 15:08:09 +0200201 u16 fifo_use;
202 snd_pcm_sframes_t delay;
203
204 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200205 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
Peter Ujfalusi75581d22010-03-03 15:08:09 +0200206 else
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200207 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
Peter Ujfalusi75581d22010-03-03 15:08:09 +0200208
209 /*
210 * Divide the used locations with the channel count to get the
211 * FIFO usage in samples (don't care about partial samples in the
212 * buffer).
213 */
214 delay = fifo_use / substream->runtime->channels;
215
216 return delay;
217}
218
Jarkko Nikula2e747962008-04-25 13:55:19 +0200219static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
Mark Browndee89c42008-11-18 22:11:38 +0000220 struct snd_pcm_hw_params *params,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000221 struct snd_soc_dai *cpu_dai)
Jarkko Nikula2e747962008-04-25 13:55:19 +0200222{
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200223 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200224 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
Lars-Peter Clausen09ae3aa2013-04-03 11:06:05 +0200225 struct snd_dmaengine_dai_dma_data *dma_data;
Peter Ujfalusi061fb362012-09-14 15:05:51 +0300226 int wlen, channels, wpf;
Peter Ujfalusicf80e152010-07-29 09:51:27 +0300227 int pkt_size = 0;
Graeme Gregory5f63ef92009-11-09 19:02:15 +0000228 unsigned int format, div, framesize, master;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200229
Peter Ujfalusibcd6da72012-09-14 15:05:57 +0300230 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
Peter Ujfalusi778a17c2012-03-15 12:20:32 +0200231 channels = params_channels(params);
Kishon Vijay Abraham I2686e072011-02-24 15:16:56 +0530232
Sergey Lapind98508a2010-05-13 19:48:16 +0400233 switch (params_format(params)) {
234 case SNDRV_PCM_FORMAT_S16_LE:
Peter Ujfalusicf80e152010-07-29 09:51:27 +0300235 wlen = 16;
Sergey Lapind98508a2010-05-13 19:48:16 +0400236 break;
237 case SNDRV_PCM_FORMAT_S32_LE:
Peter Ujfalusicf80e152010-07-29 09:51:27 +0300238 wlen = 32;
Sergey Lapind98508a2010-05-13 19:48:16 +0400239 break;
240 default:
241 return -EINVAL;
242 }
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200243 if (mcbsp->pdata->buffer_size) {
Peter Ujfalusicb40b632012-02-13 16:26:54 +0200244 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
Peter Ujfalusicf80e152010-07-29 09:51:27 +0300245 int period_words, max_thrsh;
Peter Ujfalusidffb3602012-09-14 15:05:49 +0300246 int divider = 0;
Peter Ujfalusicf80e152010-07-29 09:51:27 +0300247
248 period_words = params_period_bytes(params) / (wlen / 8);
249 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
Peter Ujfalusicb40b632012-02-13 16:26:54 +0200250 max_thrsh = mcbsp->max_tx_thres;
Peter Ujfalusicf80e152010-07-29 09:51:27 +0300251 else
Peter Ujfalusicb40b632012-02-13 16:26:54 +0200252 max_thrsh = mcbsp->max_rx_thres;
Peter Ujfalusicf80e152010-07-29 09:51:27 +0300253 /*
Peter Ujfalusidffb3602012-09-14 15:05:49 +0300254 * Use sDMA packet mode if McBSP is in threshold mode:
255 * If period words less than the FIFO size the packet
256 * size is set to the number of period words, otherwise
257 * Look for the biggest threshold value which divides
258 * the period size evenly.
Peter Ujfalusicf80e152010-07-29 09:51:27 +0300259 */
Peter Ujfalusidffb3602012-09-14 15:05:49 +0300260 divider = period_words / max_thrsh;
261 if (period_words % max_thrsh)
262 divider++;
263 while (period_words % divider &&
264 divider < period_words)
265 divider++;
266 if (divider == period_words)
267 return -EINVAL;
Peter Ujfalusicf80e152010-07-29 09:51:27 +0300268
Peter Ujfalusidffb3602012-09-14 15:05:49 +0300269 pkt_size = period_words / divider;
Peter Ujfalusi778a17c2012-03-15 12:20:32 +0200270 } else if (channels > 1) {
271 /* Use packet mode for non mono streams */
272 pkt_size = channels;
Peter Ujfalusicf80e152010-07-29 09:51:27 +0300273 }
Lars-Peter Clausenabe99372013-03-25 16:58:16 +0100274 omap_mcbsp_set_threshold(substream, pkt_size);
Peter Ujfalusi15d01432010-07-29 09:51:25 +0300275 }
276
Lars-Peter Clausen09ae3aa2013-04-03 11:06:05 +0200277 dma_data->maxburst = pkt_size;
Daniel Mackfd23b7d2010-03-19 14:52:55 +0000278
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200279 if (mcbsp->configured) {
Jarkko Nikula2e747962008-04-25 13:55:19 +0200280 /* McBSP already configured by another stream */
281 return 0;
282 }
283
Jarkko Nikula4dd04172011-09-30 16:07:44 +0300284 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
285 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
286 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
287 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200288 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
Peter Ujfalusi778a17c2012-03-15 12:20:32 +0200289 wpf = channels;
Peter Ujfalusi299a1512010-03-19 12:27:31 +0200290 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
291 format == SND_SOC_DAIFMT_LEFT_J)) {
Graeme Gregory5f63ef92009-11-09 19:02:15 +0000292 /* Use dual-phase frames */
293 regs->rcr2 |= RPHASE;
294 regs->xcr2 |= XPHASE;
295 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
296 wpf--;
297 regs->rcr2 |= RFRLEN2(wpf - 1);
298 regs->xcr2 |= XFRLEN2(wpf - 1);
Jarkko Nikula2e747962008-04-25 13:55:19 +0200299 }
300
Graeme Gregory5f63ef92009-11-09 19:02:15 +0000301 regs->rcr1 |= RFRLEN1(wpf - 1);
302 regs->xcr1 |= XFRLEN1(wpf - 1);
303
Jarkko Nikula2e747962008-04-25 13:55:19 +0200304 switch (params_format(params)) {
305 case SNDRV_PCM_FORMAT_S16_LE:
306 /* Set word lengths */
307 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
308 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
309 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
310 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
Jarkko Nikula2e747962008-04-25 13:55:19 +0200311 break;
Sergey Lapind98508a2010-05-13 19:48:16 +0400312 case SNDRV_PCM_FORMAT_S32_LE:
313 /* Set word lengths */
Sergey Lapind98508a2010-05-13 19:48:16 +0400314 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
315 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
316 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
317 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
318 break;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200319 default:
320 /* Unsupported PCM format */
321 return -EINVAL;
322 }
323
Graeme Gregory5f63ef92009-11-09 19:02:15 +0000324 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
325 * by _counting_ BCLKs. Calculate frame size in BCLKs */
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200326 master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
Graeme Gregory5f63ef92009-11-09 19:02:15 +0000327 if (master == SND_SOC_DAIFMT_CBS_CFS) {
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200328 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
329 framesize = (mcbsp->in_freq / div) / params_rate(params);
Graeme Gregory5f63ef92009-11-09 19:02:15 +0000330
331 if (framesize < wlen * channels) {
332 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
333 "channels\n", __func__);
334 return -EINVAL;
335 }
336 } else
337 framesize = wlen * channels;
338
Jarkko Nikulaba9d0fd2008-10-20 15:29:59 +0300339 /* Set FS period and length in terms of bit clock periods */
Jarkko Nikula4dd04172011-09-30 16:07:44 +0300340 regs->srgr2 &= ~FPER(0xfff);
341 regs->srgr1 &= ~FWID(0xff);
Peter Ujfalusic29b2062009-04-15 15:38:55 +0300342 switch (format) {
Jarkko Nikulaba9d0fd2008-10-20 15:29:59 +0300343 case SND_SOC_DAIFMT_I2S:
Peter Ujfalusi299a1512010-03-19 12:27:31 +0200344 case SND_SOC_DAIFMT_LEFT_J:
Graeme Gregory5f63ef92009-11-09 19:02:15 +0000345 regs->srgr2 |= FPER(framesize - 1);
346 regs->srgr1 |= FWID((framesize >> 1) - 1);
Jarkko Nikulaba9d0fd2008-10-20 15:29:59 +0300347 break;
Peter Ujfalusi3ba191c2009-04-15 15:38:56 +0300348 case SND_SOC_DAIFMT_DSP_A:
Jarkko Nikulabd258672008-12-22 10:21:36 +0200349 case SND_SOC_DAIFMT_DSP_B:
Graeme Gregory5f63ef92009-11-09 19:02:15 +0000350 regs->srgr2 |= FPER(framesize - 1);
Jarkko Nikula36ce8582009-04-15 13:48:16 +0300351 regs->srgr1 |= FWID(0);
Jarkko Nikulaba9d0fd2008-10-20 15:29:59 +0300352 break;
353 }
354
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200355 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
356 mcbsp->wlen = wlen;
357 mcbsp->configured = 1;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200358
359 return 0;
360}
361
362/*
363 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
364 * cache is initialized here
365 */
Liam Girdwood8687eb82008-07-07 16:08:07 +0100366static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
Jarkko Nikula2e747962008-04-25 13:55:19 +0200367 unsigned int fmt)
368{
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200369 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200370 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
Jarkko Nikula91a18ae2011-09-30 10:55:32 +0300371 bool inv_fs = false;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200372
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200373 if (mcbsp->configured)
Jarkko Nikula2e747962008-04-25 13:55:19 +0200374 return 0;
375
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200376 mcbsp->fmt = fmt;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200377 memset(regs, 0, sizeof(*regs));
378 /* Generic McBSP register settings */
379 regs->spcr2 |= XINTM(3) | FREE;
380 regs->spcr1 |= RINTM(3);
Peter Ujfalusidc26df52012-08-16 16:41:06 +0300381 /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
382 if (!mcbsp->pdata->has_ccr) {
Eero Nurkkalac721bbd2009-08-20 16:18:23 +0300383 regs->rcr2 |= RFIG;
384 regs->xcr2 |= XFIG;
385 }
Peter Ujfalusidc26df52012-08-16 16:41:06 +0300386
387 /* Configure XCCR/RCCR only for revisions which have ccr registers */
388 if (mcbsp->pdata->has_ccr) {
Jarkko Nikula32080af2009-08-23 12:24:26 +0300389 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
390 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
Misael Lopez Cruzef390c02009-01-29 13:29:46 +0200391 }
Jarkko Nikula2e747962008-04-25 13:55:19 +0200392
393 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
394 case SND_SOC_DAIFMT_I2S:
395 /* 1-bit data delay */
396 regs->rcr2 |= RDATDLY(1);
397 regs->xcr2 |= XDATDLY(1);
398 break;
Peter Ujfalusi299a1512010-03-19 12:27:31 +0200399 case SND_SOC_DAIFMT_LEFT_J:
400 /* 0-bit data delay */
401 regs->rcr2 |= RDATDLY(0);
402 regs->xcr2 |= XDATDLY(0);
403 regs->spcr1 |= RJUST(2);
404 /* Invert FS polarity configuration */
Jarkko Nikula91a18ae2011-09-30 10:55:32 +0300405 inv_fs = true;
Peter Ujfalusi299a1512010-03-19 12:27:31 +0200406 break;
Peter Ujfalusi3ba191c2009-04-15 15:38:56 +0300407 case SND_SOC_DAIFMT_DSP_A:
408 /* 1-bit data delay */
409 regs->rcr2 |= RDATDLY(1);
410 regs->xcr2 |= XDATDLY(1);
411 /* Invert FS polarity configuration */
Jarkko Nikula91a18ae2011-09-30 10:55:32 +0300412 inv_fs = true;
Peter Ujfalusi3ba191c2009-04-15 15:38:56 +0300413 break;
Jarkko Nikulabd258672008-12-22 10:21:36 +0200414 case SND_SOC_DAIFMT_DSP_B:
Arun KS3336c5b2008-10-02 15:07:06 +0530415 /* 0-bit data delay */
416 regs->rcr2 |= RDATDLY(0);
417 regs->xcr2 |= XDATDLY(0);
Jarkko Nikula36ce8582009-04-15 13:48:16 +0300418 /* Invert FS polarity configuration */
Jarkko Nikula91a18ae2011-09-30 10:55:32 +0300419 inv_fs = true;
Arun KS3336c5b2008-10-02 15:07:06 +0530420 break;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200421 default:
422 /* Unsupported data format */
423 return -EINVAL;
424 }
425
426 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
427 case SND_SOC_DAIFMT_CBS_CFS:
428 /* McBSP master. Set FS and bit clocks as outputs */
429 regs->pcr0 |= FSXM | FSRM |
430 CLKXM | CLKRM;
431 /* Sample rate generator drives the FS */
432 regs->srgr2 |= FSGM;
433 break;
Michael Trimarchi6e20b0d2013-07-21 18:24:01 +0200434 case SND_SOC_DAIFMT_CBM_CFS:
435 /* McBSP slave. FS clock as output */
436 regs->srgr2 |= FSGM;
437 regs->pcr0 |= FSXM;
438 break;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200439 case SND_SOC_DAIFMT_CBM_CFM:
440 /* McBSP slave */
441 break;
442 default:
443 /* Unsupported master/slave configuration */
444 return -EINVAL;
445 }
446
447 /* Set bit clock (CLKX/CLKR) and FS polarities */
Jarkko Nikula91a18ae2011-09-30 10:55:32 +0300448 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
Jarkko Nikula2e747962008-04-25 13:55:19 +0200449 case SND_SOC_DAIFMT_NB_NF:
450 /*
451 * Normal BCLK + FS.
452 * FS active low. TX data driven on falling edge of bit clock
453 * and RX data sampled on rising edge of bit clock.
454 */
455 regs->pcr0 |= FSXP | FSRP |
456 CLKXP | CLKRP;
457 break;
458 case SND_SOC_DAIFMT_NB_IF:
459 regs->pcr0 |= CLKXP | CLKRP;
460 break;
461 case SND_SOC_DAIFMT_IB_NF:
462 regs->pcr0 |= FSXP | FSRP;
463 break;
464 case SND_SOC_DAIFMT_IB_IF:
465 break;
466 default:
467 return -EINVAL;
468 }
Jarkko Nikula91a18ae2011-09-30 10:55:32 +0300469 if (inv_fs == true)
470 regs->pcr0 ^= FSXP | FSRP;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200471
472 return 0;
473}
474
Liam Girdwood8687eb82008-07-07 16:08:07 +0100475static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
Jarkko Nikula2e747962008-04-25 13:55:19 +0200476 int div_id, int div)
477{
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200478 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200479 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200480
481 if (div_id != OMAP_MCBSP_CLKGDV)
482 return -ENODEV;
483
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200484 mcbsp->clk_div = div;
Jarkko Nikula4dd04172011-09-30 16:07:44 +0300485 regs->srgr1 &= ~CLKGDV(0xff);
Jarkko Nikula2e747962008-04-25 13:55:19 +0200486 regs->srgr1 |= CLKGDV(div - 1);
487
488 return 0;
489}
490
Liam Girdwood8687eb82008-07-07 16:08:07 +0100491static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
Jarkko Nikula2e747962008-04-25 13:55:19 +0200492 int clk_id, unsigned int freq,
493 int dir)
494{
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200495 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200496 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200497 int err = 0;
498
Peter Ujfalusi256d9c22012-02-14 15:23:15 +0200499 if (mcbsp->active) {
500 if (freq == mcbsp->in_freq)
Jarkko Nikula34c86982011-09-23 11:19:13 +0300501 return 0;
502 else
503 return -EBUSY;
Peter Ujfalusi141947e2011-09-26 10:56:42 +0300504 }
Jarkko Nikula34c86982011-09-23 11:19:13 +0300505
Peter Ujfalusi8fef6262012-08-16 16:41:04 +0300506 mcbsp->in_freq = freq;
507 regs->srgr2 &= ~CLKSM;
508 regs->pcr0 &= ~SCLKME;
Graeme Gregory5f63ef92009-11-09 19:02:15 +0000509
Jarkko Nikula2e747962008-04-25 13:55:19 +0200510 switch (clk_id) {
511 case OMAP_MCBSP_SYSCLK_CLK:
512 regs->srgr2 |= CLKSM;
513 break;
514 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
Tony Lindgrene6507942012-11-21 09:42:25 -0800515 if (mcbsp_omap1()) {
Paul Walmsleyd1358652010-10-08 11:40:19 -0600516 err = -EINVAL;
517 break;
518 }
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200519 err = omap2_mcbsp_set_clks_src(mcbsp,
Paul Walmsleyd1358652010-10-08 11:40:19 -0600520 MCBSP_CLKS_PRCM_SRC);
521 break;
Jarkko Nikula2e747962008-04-25 13:55:19 +0200522 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
Tony Lindgrene6507942012-11-21 09:42:25 -0800523 if (mcbsp_omap1()) {
Paul Walmsleyd1358652010-10-08 11:40:19 -0600524 err = 0;
525 break;
526 }
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200527 err = omap2_mcbsp_set_clks_src(mcbsp,
Paul Walmsleyd1358652010-10-08 11:40:19 -0600528 MCBSP_CLKS_PAD_SRC);
Jarkko Nikula2e747962008-04-25 13:55:19 +0200529 break;
530
531 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
532 regs->srgr2 |= CLKSM;
533 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
534 regs->pcr0 |= SCLKME;
535 break;
536 default:
537 err = -ENODEV;
538 }
539
540 return err;
541}
542
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100543static const struct snd_soc_dai_ops mcbsp_dai_ops = {
Eric Miao6335d052009-03-03 09:41:00 +0800544 .startup = omap_mcbsp_dai_startup,
545 .shutdown = omap_mcbsp_dai_shutdown,
546 .trigger = omap_mcbsp_dai_trigger,
Peter Ujfalusi75581d22010-03-03 15:08:09 +0200547 .delay = omap_mcbsp_dai_delay,
Eric Miao6335d052009-03-03 09:41:00 +0800548 .hw_params = omap_mcbsp_dai_hw_params,
549 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
550 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
551 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
552};
553
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200554static int omap_mcbsp_probe(struct snd_soc_dai *dai)
555{
556 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
557
558 pm_runtime_enable(mcbsp->dev);
559
Peter Ujfalusi3fe856b2014-04-16 15:46:15 +0300560 snd_soc_dai_init_dma_data(dai,
561 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
562 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
563
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200564 return 0;
565}
566
567static int omap_mcbsp_remove(struct snd_soc_dai *dai)
568{
569 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
570
571 pm_runtime_disable(mcbsp->dev);
572
573 return 0;
574}
575
Michael Opdenacker6179b772011-10-10 07:07:08 +0200576static struct snd_soc_dai_driver omap_mcbsp_dai = {
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200577 .probe = omap_mcbsp_probe,
578 .remove = omap_mcbsp_remove,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000579 .playback = {
580 .channels_min = 1,
581 .channels_max = 16,
582 .rates = OMAP_MCBSP_RATES,
583 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
584 },
585 .capture = {
586 .channels_min = 1,
587 .channels_max = 16,
588 .rates = OMAP_MCBSP_RATES,
589 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
590 },
591 .ops = &mcbsp_dai_ops,
Jarkko Nikula2e747962008-04-25 13:55:19 +0200592};
Jarkko Nikula8def4642008-10-09 15:57:22 +0300593
Kuninori Morimoto43cd8142013-03-21 03:33:25 -0700594static const struct snd_soc_component_driver omap_mcbsp_component = {
595 .name = "omap-mcbsp",
596};
597
G, Manjunath Kondaiah34844572010-09-08 08:53:43 +0530598static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000599 struct snd_ctl_elem_info *uinfo)
600{
601 struct soc_mixer_control *mc =
602 (struct soc_mixer_control *)kcontrol->private_value;
603 int max = mc->max;
604 int min = mc->min;
605
606 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
607 uinfo->count = 1;
608 uinfo->value.integer.min = min;
609 uinfo->value.integer.max = max;
610 return 0;
611}
612
Peter Ujfalusidb615502012-08-22 13:11:43 +0300613#define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel) \
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000614static int \
Peter Ujfalusidb615502012-08-22 13:11:43 +0300615omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000616 struct snd_ctl_elem_value *uc) \
617{ \
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200618 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
619 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000620 struct soc_mixer_control *mc = \
621 (struct soc_mixer_control *)kc->private_value; \
622 int max = mc->max; \
623 int min = mc->min; \
624 int val = uc->value.integer.value[0]; \
625 \
626 if (val < min || val > max) \
627 return -EINVAL; \
628 \
629 /* OMAP McBSP implementation uses index values 0..4 */ \
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200630 return omap_st_set_chgain(mcbsp, channel, val); \
Peter Ujfalusidb615502012-08-22 13:11:43 +0300631} \
632 \
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000633static int \
Peter Ujfalusidb615502012-08-22 13:11:43 +0300634omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000635 struct snd_ctl_elem_value *uc) \
636{ \
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200637 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
638 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000639 s16 chgain; \
640 \
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200641 if (omap_st_get_chgain(mcbsp, channel, &chgain)) \
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000642 return -EAGAIN; \
643 \
644 uc->value.integer.value[0] = chgain; \
645 return 0; \
646}
647
Peter Ujfalusidb615502012-08-22 13:11:43 +0300648OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
649OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000650
651static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
652 struct snd_ctl_elem_value *ucontrol)
653{
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200654 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
655 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000656 u8 value = ucontrol->value.integer.value[0];
657
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200658 if (value == omap_st_is_enabled(mcbsp))
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000659 return 0;
660
661 if (value)
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200662 omap_st_enable(mcbsp);
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000663 else
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200664 omap_st_disable(mcbsp);
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000665
666 return 1;
667}
668
669static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
670 struct snd_ctl_elem_value *ucontrol)
671{
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200672 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
673 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000674
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200675 ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000676 return 0;
677}
678
Peter Ujfalusi8996a312012-08-22 13:11:42 +0300679#define OMAP_MCBSP_ST_CONTROLS(port) \
680static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
681SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0, \
682 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), \
683OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
684 -32768, 32767, \
685 omap_mcbsp_get_st_ch0_volume, \
686 omap_mcbsp_set_st_ch0_volume), \
687OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
688 -32768, 32767, \
689 omap_mcbsp_get_st_ch1_volume, \
690 omap_mcbsp_set_st_ch1_volume), \
691}
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000692
Peter Ujfalusi8996a312012-08-22 13:11:42 +0300693OMAP_MCBSP_ST_CONTROLS(2);
694OMAP_MCBSP_ST_CONTROLS(3);
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000695
Sebastian Reichel0a17a372014-04-28 16:07:23 +0200696int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd, int port_id)
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000697{
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200698 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
699 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
700
Peter Ujfalusi8a88df42012-08-22 13:11:41 +0300701 if (!mcbsp->st_data) {
702 dev_warn(mcbsp->dev, "No sidetone data for port\n");
703 return 0;
704 }
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000705
Sebastian Reichel0a17a372014-04-28 16:07:23 +0200706 switch (port_id) {
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200707 case 2: /* McBSP 2 */
708 return snd_soc_add_dai_controls(cpu_dai,
709 omap_mcbsp2_st_controls,
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000710 ARRAY_SIZE(omap_mcbsp2_st_controls));
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200711 case 3: /* McBSP 3 */
712 return snd_soc_add_dai_controls(cpu_dai,
713 omap_mcbsp3_st_controls,
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000714 ARRAY_SIZE(omap_mcbsp3_st_controls));
715 default:
Sebastian Reichel0a17a372014-04-28 16:07:23 +0200716 dev_err(mcbsp->dev, "Port %d not supported\n", port_id);
Ilkka Koskinen83905c12010-02-22 12:21:12 +0000717 break;
718 }
719
720 return -EINVAL;
721}
722EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
723
Peter Ujfalusi11dd5862012-08-16 16:41:08 +0300724static struct omap_mcbsp_platform_data omap2420_pdata = {
725 .reg_step = 4,
726 .reg_size = 2,
727};
728
729static struct omap_mcbsp_platform_data omap2430_pdata = {
730 .reg_step = 4,
731 .reg_size = 4,
732 .has_ccr = true,
733};
734
735static struct omap_mcbsp_platform_data omap3_pdata = {
736 .reg_step = 4,
737 .reg_size = 4,
738 .has_ccr = true,
739 .has_wakeup = true,
740};
741
742static struct omap_mcbsp_platform_data omap4_pdata = {
743 .reg_step = 4,
744 .reg_size = 4,
745 .has_ccr = true,
746 .has_wakeup = true,
747};
748
749static const struct of_device_id omap_mcbsp_of_match[] = {
750 {
751 .compatible = "ti,omap2420-mcbsp",
752 .data = &omap2420_pdata,
753 },
754 {
755 .compatible = "ti,omap2430-mcbsp",
756 .data = &omap2430_pdata,
757 },
758 {
759 .compatible = "ti,omap3-mcbsp",
760 .data = &omap3_pdata,
761 },
762 {
763 .compatible = "ti,omap4-mcbsp",
764 .data = &omap4_pdata,
765 },
766 { },
767};
768MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
769
Bill Pemberton7ff60002012-12-07 09:26:29 -0500770static int asoc_mcbsp_probe(struct platform_device *pdev)
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000771{
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200772 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
773 struct omap_mcbsp *mcbsp;
Peter Ujfalusi11dd5862012-08-16 16:41:08 +0300774 const struct of_device_id *match;
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200775 int ret;
776
Peter Ujfalusi11dd5862012-08-16 16:41:08 +0300777 match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
778 if (match) {
779 struct device_node *node = pdev->dev.of_node;
780 int buffer_size;
781
782 pdata = devm_kzalloc(&pdev->dev,
783 sizeof(struct omap_mcbsp_platform_data),
784 GFP_KERNEL);
785 if (!pdata)
786 return -ENOMEM;
787
788 memcpy(pdata, match->data, sizeof(*pdata));
789 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
790 pdata->buffer_size = buffer_size;
791 } else if (!pdata) {
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200792 dev_err(&pdev->dev, "missing platform data.\n");
793 return -EINVAL;
794 }
795 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
796 if (!mcbsp)
797 return -ENOMEM;
798
799 mcbsp->id = pdev->id;
800 mcbsp->pdata = pdata;
801 mcbsp->dev = &pdev->dev;
802 platform_set_drvdata(pdev, mcbsp);
803
804 ret = omap_mcbsp_init(pdev);
Peter Ujfalusi64241422014-04-16 15:46:16 +0300805 if (ret)
806 return ret;
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200807
Peter Ujfalusi64241422014-04-16 15:46:16 +0300808 ret = snd_soc_register_component(&pdev->dev, &omap_mcbsp_component,
809 &omap_mcbsp_dai, 1);
810 if (ret)
811 return ret;
812
813 return omap_pcm_platform_register(&pdev->dev);
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000814}
815
Bill Pemberton7ff60002012-12-07 09:26:29 -0500816static int asoc_mcbsp_remove(struct platform_device *pdev)
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000817{
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200818 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
819
Kuninori Morimoto43cd8142013-03-21 03:33:25 -0700820 snd_soc_unregister_component(&pdev->dev);
Peter Ujfalusi2ee65952012-02-14 14:52:42 +0200821
822 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
823 mcbsp->pdata->ops->free(mcbsp->id);
824
825 omap_mcbsp_sysfs_remove(mcbsp);
826
827 clk_put(mcbsp->fclk);
828
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000829 return 0;
830}
831
832static struct platform_driver asoc_mcbsp_driver = {
833 .driver = {
Peter Ujfalusi45656b42012-02-14 18:20:58 +0200834 .name = "omap-mcbsp",
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000835 .owner = THIS_MODULE,
Peter Ujfalusi11dd5862012-08-16 16:41:08 +0300836 .of_match_table = omap_mcbsp_of_match,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000837 },
838
839 .probe = asoc_mcbsp_probe,
Bill Pemberton7ff60002012-12-07 09:26:29 -0500840 .remove = asoc_mcbsp_remove,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000841};
842
Axel Linbeda5bf52011-11-25 10:12:16 +0800843module_platform_driver(asoc_mcbsp_driver);
Mark Brown3f4b7832008-12-03 19:26:35 +0000844
Jarkko Nikula7ec41ee2011-08-11 15:44:57 +0300845MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
Jarkko Nikula2e747962008-04-25 13:55:19 +0200846MODULE_DESCRIPTION("OMAP I2S SoC Interface");
847MODULE_LICENSE("GPL");
Guillaume Gardet5e70b7fc2012-07-12 15:08:16 +0200848MODULE_ALIAS("platform:omap-mcbsp");