Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * drivers/dma/imx-sdma.c |
| 3 | * |
| 4 | * This file contains a driver for the Freescale Smart DMA engine |
| 5 | * |
| 6 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> |
| 7 | * |
| 8 | * Based on code from Freescale: |
| 9 | * |
| 10 | * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
| 11 | * |
| 12 | * The code contained herein is licensed under the GNU General Public |
| 13 | * License. You may obtain a copy of the GNU General Public License |
| 14 | * Version 2 or later at the following locations: |
| 15 | * |
| 16 | * http://www.opensource.org/licenses/gpl-license.html |
| 17 | * http://www.gnu.org/copyleft/gpl.html |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
Axel Lin | f8de8f4 | 2011-08-30 15:08:24 +0800 | [diff] [blame] | 21 | #include <linux/module.h> |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 22 | #include <linux/types.h> |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 23 | #include <linux/bitops.h> |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 24 | #include <linux/mm.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/clk.h> |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 27 | #include <linux/delay.h> |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 28 | #include <linux/sched.h> |
| 29 | #include <linux/semaphore.h> |
| 30 | #include <linux/spinlock.h> |
| 31 | #include <linux/device.h> |
| 32 | #include <linux/dma-mapping.h> |
| 33 | #include <linux/firmware.h> |
| 34 | #include <linux/slab.h> |
| 35 | #include <linux/platform_device.h> |
| 36 | #include <linux/dmaengine.h> |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 37 | #include <linux/of.h> |
| 38 | #include <linux/of_device.h> |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 39 | |
| 40 | #include <asm/irq.h> |
Arnd Bergmann | 82906b1 | 2012-08-24 15:14:29 +0200 | [diff] [blame] | 41 | #include <linux/platform_data/dma-imx-sdma.h> |
| 42 | #include <linux/platform_data/dma-imx.h> |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 43 | |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 44 | #include "dmaengine.h" |
| 45 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 46 | /* SDMA registers */ |
| 47 | #define SDMA_H_C0PTR 0x000 |
| 48 | #define SDMA_H_INTR 0x004 |
| 49 | #define SDMA_H_STATSTOP 0x008 |
| 50 | #define SDMA_H_START 0x00c |
| 51 | #define SDMA_H_EVTOVR 0x010 |
| 52 | #define SDMA_H_DSPOVR 0x014 |
| 53 | #define SDMA_H_HOSTOVR 0x018 |
| 54 | #define SDMA_H_EVTPEND 0x01c |
| 55 | #define SDMA_H_DSPENBL 0x020 |
| 56 | #define SDMA_H_RESET 0x024 |
| 57 | #define SDMA_H_EVTERR 0x028 |
| 58 | #define SDMA_H_INTRMSK 0x02c |
| 59 | #define SDMA_H_PSW 0x030 |
| 60 | #define SDMA_H_EVTERRDBG 0x034 |
| 61 | #define SDMA_H_CONFIG 0x038 |
| 62 | #define SDMA_ONCE_ENB 0x040 |
| 63 | #define SDMA_ONCE_DATA 0x044 |
| 64 | #define SDMA_ONCE_INSTR 0x048 |
| 65 | #define SDMA_ONCE_STAT 0x04c |
| 66 | #define SDMA_ONCE_CMD 0x050 |
| 67 | #define SDMA_EVT_MIRROR 0x054 |
| 68 | #define SDMA_ILLINSTADDR 0x058 |
| 69 | #define SDMA_CHN0ADDR 0x05c |
| 70 | #define SDMA_ONCE_RTB 0x060 |
| 71 | #define SDMA_XTRIG_CONF1 0x070 |
| 72 | #define SDMA_XTRIG_CONF2 0x074 |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 73 | #define SDMA_CHNENBL0_IMX35 0x200 |
| 74 | #define SDMA_CHNENBL0_IMX31 0x080 |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 75 | #define SDMA_CHNPRI_0 0x100 |
| 76 | |
| 77 | /* |
| 78 | * Buffer descriptor status values. |
| 79 | */ |
| 80 | #define BD_DONE 0x01 |
| 81 | #define BD_WRAP 0x02 |
| 82 | #define BD_CONT 0x04 |
| 83 | #define BD_INTR 0x08 |
| 84 | #define BD_RROR 0x10 |
| 85 | #define BD_LAST 0x20 |
| 86 | #define BD_EXTD 0x80 |
| 87 | |
| 88 | /* |
| 89 | * Data Node descriptor status values. |
| 90 | */ |
| 91 | #define DND_END_OF_FRAME 0x80 |
| 92 | #define DND_END_OF_XFER 0x40 |
| 93 | #define DND_DONE 0x20 |
| 94 | #define DND_UNUSED 0x01 |
| 95 | |
| 96 | /* |
| 97 | * IPCV2 descriptor status values. |
| 98 | */ |
| 99 | #define BD_IPCV2_END_OF_FRAME 0x40 |
| 100 | |
| 101 | #define IPCV2_MAX_NODES 50 |
| 102 | /* |
| 103 | * Error bit set in the CCB status field by the SDMA, |
| 104 | * in setbd routine, in case of a transfer error |
| 105 | */ |
| 106 | #define DATA_ERROR 0x10000000 |
| 107 | |
| 108 | /* |
| 109 | * Buffer descriptor commands. |
| 110 | */ |
| 111 | #define C0_ADDR 0x01 |
| 112 | #define C0_LOAD 0x02 |
| 113 | #define C0_DUMP 0x03 |
| 114 | #define C0_SETCTX 0x07 |
| 115 | #define C0_GETCTX 0x03 |
| 116 | #define C0_SETDM 0x01 |
| 117 | #define C0_SETPM 0x04 |
| 118 | #define C0_GETDM 0x02 |
| 119 | #define C0_GETPM 0x08 |
| 120 | /* |
| 121 | * Change endianness indicator in the BD command field |
| 122 | */ |
| 123 | #define CHANGE_ENDIANNESS 0x80 |
| 124 | |
| 125 | /* |
| 126 | * Mode/Count of data node descriptors - IPCv2 |
| 127 | */ |
| 128 | struct sdma_mode_count { |
| 129 | u32 count : 16; /* size of the buffer pointed by this BD */ |
| 130 | u32 status : 8; /* E,R,I,C,W,D status bits stored here */ |
| 131 | u32 command : 8; /* command mostlky used for channel 0 */ |
| 132 | }; |
| 133 | |
| 134 | /* |
| 135 | * Buffer descriptor |
| 136 | */ |
| 137 | struct sdma_buffer_descriptor { |
| 138 | struct sdma_mode_count mode; |
| 139 | u32 buffer_addr; /* address of the buffer described */ |
| 140 | u32 ext_buffer_addr; /* extended buffer address */ |
| 141 | } __attribute__ ((packed)); |
| 142 | |
| 143 | /** |
| 144 | * struct sdma_channel_control - Channel control Block |
| 145 | * |
| 146 | * @current_bd_ptr current buffer descriptor processed |
| 147 | * @base_bd_ptr first element of buffer descriptor array |
| 148 | * @unused padding. The SDMA engine expects an array of 128 byte |
| 149 | * control blocks |
| 150 | */ |
| 151 | struct sdma_channel_control { |
| 152 | u32 current_bd_ptr; |
| 153 | u32 base_bd_ptr; |
| 154 | u32 unused[2]; |
| 155 | } __attribute__ ((packed)); |
| 156 | |
| 157 | /** |
| 158 | * struct sdma_state_registers - SDMA context for a channel |
| 159 | * |
| 160 | * @pc: program counter |
| 161 | * @t: test bit: status of arithmetic & test instruction |
| 162 | * @rpc: return program counter |
| 163 | * @sf: source fault while loading data |
| 164 | * @spc: loop start program counter |
| 165 | * @df: destination fault while storing data |
| 166 | * @epc: loop end program counter |
| 167 | * @lm: loop mode |
| 168 | */ |
| 169 | struct sdma_state_registers { |
| 170 | u32 pc :14; |
| 171 | u32 unused1: 1; |
| 172 | u32 t : 1; |
| 173 | u32 rpc :14; |
| 174 | u32 unused0: 1; |
| 175 | u32 sf : 1; |
| 176 | u32 spc :14; |
| 177 | u32 unused2: 1; |
| 178 | u32 df : 1; |
| 179 | u32 epc :14; |
| 180 | u32 lm : 2; |
| 181 | } __attribute__ ((packed)); |
| 182 | |
| 183 | /** |
| 184 | * struct sdma_context_data - sdma context specific to a channel |
| 185 | * |
| 186 | * @channel_state: channel state bits |
| 187 | * @gReg: general registers |
| 188 | * @mda: burst dma destination address register |
| 189 | * @msa: burst dma source address register |
| 190 | * @ms: burst dma status register |
| 191 | * @md: burst dma data register |
| 192 | * @pda: peripheral dma destination address register |
| 193 | * @psa: peripheral dma source address register |
| 194 | * @ps: peripheral dma status register |
| 195 | * @pd: peripheral dma data register |
| 196 | * @ca: CRC polynomial register |
| 197 | * @cs: CRC accumulator register |
| 198 | * @dda: dedicated core destination address register |
| 199 | * @dsa: dedicated core source address register |
| 200 | * @ds: dedicated core status register |
| 201 | * @dd: dedicated core data register |
| 202 | */ |
| 203 | struct sdma_context_data { |
| 204 | struct sdma_state_registers channel_state; |
| 205 | u32 gReg[8]; |
| 206 | u32 mda; |
| 207 | u32 msa; |
| 208 | u32 ms; |
| 209 | u32 md; |
| 210 | u32 pda; |
| 211 | u32 psa; |
| 212 | u32 ps; |
| 213 | u32 pd; |
| 214 | u32 ca; |
| 215 | u32 cs; |
| 216 | u32 dda; |
| 217 | u32 dsa; |
| 218 | u32 ds; |
| 219 | u32 dd; |
| 220 | u32 scratch0; |
| 221 | u32 scratch1; |
| 222 | u32 scratch2; |
| 223 | u32 scratch3; |
| 224 | u32 scratch4; |
| 225 | u32 scratch5; |
| 226 | u32 scratch6; |
| 227 | u32 scratch7; |
| 228 | } __attribute__ ((packed)); |
| 229 | |
| 230 | #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) |
| 231 | |
| 232 | struct sdma_engine; |
| 233 | |
| 234 | /** |
| 235 | * struct sdma_channel - housekeeping for a SDMA channel |
| 236 | * |
| 237 | * @sdma pointer to the SDMA engine for this channel |
Sascha Hauer | 23889c6 | 2011-01-31 10:56:58 +0100 | [diff] [blame] | 238 | * @channel the channel number, matches dmaengine chan_id + 1 |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 239 | * @direction transfer type. Needed for setting SDMA script |
| 240 | * @peripheral_type Peripheral type. Needed for setting SDMA script |
| 241 | * @event_id0 aka dma request line |
| 242 | * @event_id1 for channels that use 2 events |
| 243 | * @word_size peripheral access size |
| 244 | * @buf_tail ID of the buffer that was processed |
| 245 | * @done channel completion |
| 246 | * @num_bd max NUM_BD. number of descriptors currently handling |
| 247 | */ |
| 248 | struct sdma_channel { |
| 249 | struct sdma_engine *sdma; |
| 250 | unsigned int channel; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 251 | enum dma_transfer_direction direction; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 252 | enum sdma_peripheral_type peripheral_type; |
| 253 | unsigned int event_id0; |
| 254 | unsigned int event_id1; |
| 255 | enum dma_slave_buswidth word_size; |
| 256 | unsigned int buf_tail; |
| 257 | struct completion done; |
| 258 | unsigned int num_bd; |
| 259 | struct sdma_buffer_descriptor *bd; |
| 260 | dma_addr_t bd_phys; |
| 261 | unsigned int pc_from_device, pc_to_device; |
| 262 | unsigned long flags; |
| 263 | dma_addr_t per_address; |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 264 | unsigned long event_mask[2]; |
| 265 | unsigned long watermark_level; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 266 | u32 shp_addr, per_addr; |
| 267 | struct dma_chan chan; |
| 268 | spinlock_t lock; |
| 269 | struct dma_async_tx_descriptor desc; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 270 | enum dma_status status; |
Huang Shijie | ab59a51 | 2011-12-02 10:16:25 +0800 | [diff] [blame] | 271 | unsigned int chn_count; |
| 272 | unsigned int chn_real_count; |
Huang Shijie | abd9ccc | 2012-04-28 18:15:42 +0800 | [diff] [blame] | 273 | struct tasklet_struct tasklet; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 274 | }; |
| 275 | |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 276 | #define IMX_DMA_SG_LOOP BIT(0) |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 277 | |
| 278 | #define MAX_DMA_CHANNELS 32 |
| 279 | #define MXC_SDMA_DEFAULT_PRIORITY 1 |
| 280 | #define MXC_SDMA_MIN_PRIORITY 1 |
| 281 | #define MXC_SDMA_MAX_PRIORITY 7 |
| 282 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 283 | #define SDMA_FIRMWARE_MAGIC 0x414d4453 |
| 284 | |
| 285 | /** |
| 286 | * struct sdma_firmware_header - Layout of the firmware image |
| 287 | * |
| 288 | * @magic "SDMA" |
| 289 | * @version_major increased whenever layout of struct sdma_script_start_addrs |
| 290 | * changes. |
| 291 | * @version_minor firmware minor version (for binary compatible changes) |
| 292 | * @script_addrs_start offset of struct sdma_script_start_addrs in this image |
| 293 | * @num_script_addrs Number of script addresses in this image |
| 294 | * @ram_code_start offset of SDMA ram image in this firmware image |
| 295 | * @ram_code_size size of SDMA ram image |
| 296 | * @script_addrs Stores the start address of the SDMA scripts |
| 297 | * (in SDMA memory space) |
| 298 | */ |
| 299 | struct sdma_firmware_header { |
| 300 | u32 magic; |
| 301 | u32 version_major; |
| 302 | u32 version_minor; |
| 303 | u32 script_addrs_start; |
| 304 | u32 num_script_addrs; |
| 305 | u32 ram_code_start; |
| 306 | u32 ram_code_size; |
| 307 | }; |
| 308 | |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 309 | enum sdma_devtype { |
| 310 | IMX31_SDMA, /* runs on i.mx31 */ |
| 311 | IMX35_SDMA, /* runs on i.mx35 and later */ |
| 312 | }; |
| 313 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 314 | struct sdma_engine { |
| 315 | struct device *dev; |
Sascha Hauer | b9b3f82 | 2011-01-12 12:12:31 +0100 | [diff] [blame] | 316 | struct device_dma_parameters dma_parms; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 317 | struct sdma_channel channel[MAX_DMA_CHANNELS]; |
| 318 | struct sdma_channel_control *channel_control; |
| 319 | void __iomem *regs; |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 320 | enum sdma_devtype devtype; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 321 | unsigned int num_events; |
| 322 | struct sdma_context_data *context; |
| 323 | dma_addr_t context_phys; |
| 324 | struct dma_device dma_device; |
Sascha Hauer | 7560e3f | 2012-03-07 09:30:06 +0100 | [diff] [blame] | 325 | struct clk *clk_ipg; |
| 326 | struct clk *clk_ahb; |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 327 | spinlock_t channel_0_lock; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 328 | struct sdma_script_start_addrs *script_addrs; |
| 329 | }; |
| 330 | |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 331 | static struct platform_device_id sdma_devtypes[] = { |
| 332 | { |
| 333 | .name = "imx31-sdma", |
| 334 | .driver_data = IMX31_SDMA, |
| 335 | }, { |
| 336 | .name = "imx35-sdma", |
| 337 | .driver_data = IMX35_SDMA, |
| 338 | }, { |
| 339 | /* sentinel */ |
| 340 | } |
| 341 | }; |
| 342 | MODULE_DEVICE_TABLE(platform, sdma_devtypes); |
| 343 | |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 344 | static const struct of_device_id sdma_dt_ids[] = { |
| 345 | { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], }, |
| 346 | { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], }, |
| 347 | { /* sentinel */ } |
| 348 | }; |
| 349 | MODULE_DEVICE_TABLE(of, sdma_dt_ids); |
| 350 | |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 351 | #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ |
| 352 | #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ |
| 353 | #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 354 | #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ |
| 355 | |
| 356 | static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) |
| 357 | { |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 358 | u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 : |
| 359 | SDMA_CHNENBL0_IMX35); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 360 | return chnenbl0 + event * 4; |
| 361 | } |
| 362 | |
| 363 | static int sdma_config_ownership(struct sdma_channel *sdmac, |
| 364 | bool event_override, bool mcu_override, bool dsp_override) |
| 365 | { |
| 366 | struct sdma_engine *sdma = sdmac->sdma; |
| 367 | int channel = sdmac->channel; |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 368 | unsigned long evt, mcu, dsp; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 369 | |
| 370 | if (event_override && mcu_override && dsp_override) |
| 371 | return -EINVAL; |
| 372 | |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 373 | evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); |
| 374 | mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); |
| 375 | dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 376 | |
| 377 | if (dsp_override) |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 378 | __clear_bit(channel, &dsp); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 379 | else |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 380 | __set_bit(channel, &dsp); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 381 | |
| 382 | if (event_override) |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 383 | __clear_bit(channel, &evt); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 384 | else |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 385 | __set_bit(channel, &evt); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 386 | |
| 387 | if (mcu_override) |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 388 | __clear_bit(channel, &mcu); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 389 | else |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 390 | __set_bit(channel, &mcu); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 391 | |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 392 | writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); |
| 393 | writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); |
| 394 | writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 395 | |
| 396 | return 0; |
| 397 | } |
| 398 | |
Richard Zhao | b9a59166 | 2012-01-13 11:09:56 +0800 | [diff] [blame] | 399 | static void sdma_enable_channel(struct sdma_engine *sdma, int channel) |
| 400 | { |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 401 | writel(BIT(channel), sdma->regs + SDMA_H_START); |
Richard Zhao | b9a59166 | 2012-01-13 11:09:56 +0800 | [diff] [blame] | 402 | } |
| 403 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 404 | /* |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 405 | * sdma_run_channel0 - run a channel and wait till it's done |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 406 | */ |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 407 | static int sdma_run_channel0(struct sdma_engine *sdma) |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 408 | { |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 409 | int ret; |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 410 | unsigned long timeout = 500; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 411 | |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 412 | sdma_enable_channel(sdma, 0); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 413 | |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 414 | while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) { |
| 415 | if (timeout-- <= 0) |
| 416 | break; |
| 417 | udelay(1); |
| 418 | } |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 419 | |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 420 | if (ret) { |
| 421 | /* Clear the interrupt status */ |
| 422 | writel_relaxed(ret, sdma->regs + SDMA_H_INTR); |
| 423 | } else { |
| 424 | dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); |
| 425 | } |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 426 | |
| 427 | return ret ? 0 : -ETIMEDOUT; |
| 428 | } |
| 429 | |
| 430 | static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, |
| 431 | u32 address) |
| 432 | { |
| 433 | struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; |
| 434 | void *buf_virt; |
| 435 | dma_addr_t buf_phys; |
| 436 | int ret; |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 437 | unsigned long flags; |
Sascha Hauer | 73eab97 | 2011-08-25 11:03:35 +0200 | [diff] [blame] | 438 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 439 | buf_virt = dma_alloc_coherent(NULL, |
| 440 | size, |
| 441 | &buf_phys, GFP_KERNEL); |
Sascha Hauer | 73eab97 | 2011-08-25 11:03:35 +0200 | [diff] [blame] | 442 | if (!buf_virt) { |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 443 | return -ENOMEM; |
Sascha Hauer | 73eab97 | 2011-08-25 11:03:35 +0200 | [diff] [blame] | 444 | } |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 445 | |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 446 | spin_lock_irqsave(&sdma->channel_0_lock, flags); |
| 447 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 448 | bd0->mode.command = C0_SETPM; |
| 449 | bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; |
| 450 | bd0->mode.count = size / 2; |
| 451 | bd0->buffer_addr = buf_phys; |
| 452 | bd0->ext_buffer_addr = address; |
| 453 | |
| 454 | memcpy(buf_virt, buf, size); |
| 455 | |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 456 | ret = sdma_run_channel0(sdma); |
| 457 | |
| 458 | spin_unlock_irqrestore(&sdma->channel_0_lock, flags); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 459 | |
| 460 | dma_free_coherent(NULL, size, buf_virt, buf_phys); |
| 461 | |
| 462 | return ret; |
| 463 | } |
| 464 | |
| 465 | static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) |
| 466 | { |
| 467 | struct sdma_engine *sdma = sdmac->sdma; |
| 468 | int channel = sdmac->channel; |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 469 | unsigned long val; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 470 | u32 chnenbl = chnenbl_ofs(sdma, event); |
| 471 | |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 472 | val = readl_relaxed(sdma->regs + chnenbl); |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 473 | __set_bit(channel, &val); |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 474 | writel_relaxed(val, sdma->regs + chnenbl); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 475 | } |
| 476 | |
| 477 | static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) |
| 478 | { |
| 479 | struct sdma_engine *sdma = sdmac->sdma; |
| 480 | int channel = sdmac->channel; |
| 481 | u32 chnenbl = chnenbl_ofs(sdma, event); |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 482 | unsigned long val; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 483 | |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 484 | val = readl_relaxed(sdma->regs + chnenbl); |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 485 | __clear_bit(channel, &val); |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 486 | writel_relaxed(val, sdma->regs + chnenbl); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 487 | } |
| 488 | |
| 489 | static void sdma_handle_channel_loop(struct sdma_channel *sdmac) |
| 490 | { |
| 491 | struct sdma_buffer_descriptor *bd; |
| 492 | |
| 493 | /* |
| 494 | * loop mode. Iterate over descriptors, re-setup them and |
| 495 | * call callback function. |
| 496 | */ |
| 497 | while (1) { |
| 498 | bd = &sdmac->bd[sdmac->buf_tail]; |
| 499 | |
| 500 | if (bd->mode.status & BD_DONE) |
| 501 | break; |
| 502 | |
| 503 | if (bd->mode.status & BD_RROR) |
| 504 | sdmac->status = DMA_ERROR; |
| 505 | else |
Shawn Guo | 1e9cebb | 2011-01-20 05:50:38 +0800 | [diff] [blame] | 506 | sdmac->status = DMA_IN_PROGRESS; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 507 | |
| 508 | bd->mode.status |= BD_DONE; |
| 509 | sdmac->buf_tail++; |
| 510 | sdmac->buf_tail %= sdmac->num_bd; |
| 511 | |
| 512 | if (sdmac->desc.callback) |
| 513 | sdmac->desc.callback(sdmac->desc.callback_param); |
| 514 | } |
| 515 | } |
| 516 | |
| 517 | static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac) |
| 518 | { |
| 519 | struct sdma_buffer_descriptor *bd; |
| 520 | int i, error = 0; |
| 521 | |
Huang Shijie | ab59a51 | 2011-12-02 10:16:25 +0800 | [diff] [blame] | 522 | sdmac->chn_real_count = 0; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 523 | /* |
| 524 | * non loop mode. Iterate over all descriptors, collect |
| 525 | * errors and call callback function |
| 526 | */ |
| 527 | for (i = 0; i < sdmac->num_bd; i++) { |
| 528 | bd = &sdmac->bd[i]; |
| 529 | |
| 530 | if (bd->mode.status & (BD_DONE | BD_RROR)) |
| 531 | error = -EIO; |
Huang Shijie | ab59a51 | 2011-12-02 10:16:25 +0800 | [diff] [blame] | 532 | sdmac->chn_real_count += bd->mode.count; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | if (error) |
| 536 | sdmac->status = DMA_ERROR; |
| 537 | else |
| 538 | sdmac->status = DMA_SUCCESS; |
| 539 | |
Russell King - ARM Linux | f7fbce0 | 2012-03-06 22:35:07 +0000 | [diff] [blame] | 540 | dma_cookie_complete(&sdmac->desc); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 541 | if (sdmac->desc.callback) |
| 542 | sdmac->desc.callback(sdmac->desc.callback_param); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 543 | } |
| 544 | |
Huang Shijie | abd9ccc | 2012-04-28 18:15:42 +0800 | [diff] [blame] | 545 | static void sdma_tasklet(unsigned long data) |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 546 | { |
Huang Shijie | abd9ccc | 2012-04-28 18:15:42 +0800 | [diff] [blame] | 547 | struct sdma_channel *sdmac = (struct sdma_channel *) data; |
| 548 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 549 | complete(&sdmac->done); |
| 550 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 551 | if (sdmac->flags & IMX_DMA_SG_LOOP) |
| 552 | sdma_handle_channel_loop(sdmac); |
| 553 | else |
| 554 | mxc_sdma_handle_channel_normal(sdmac); |
| 555 | } |
| 556 | |
| 557 | static irqreturn_t sdma_int_handler(int irq, void *dev_id) |
| 558 | { |
| 559 | struct sdma_engine *sdma = dev_id; |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 560 | unsigned long stat; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 561 | |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 562 | stat = readl_relaxed(sdma->regs + SDMA_H_INTR); |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 563 | /* not interested in channel 0 interrupts */ |
| 564 | stat &= ~1; |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 565 | writel_relaxed(stat, sdma->regs + SDMA_H_INTR); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 566 | |
| 567 | while (stat) { |
| 568 | int channel = fls(stat) - 1; |
| 569 | struct sdma_channel *sdmac = &sdma->channel[channel]; |
| 570 | |
Huang Shijie | abd9ccc | 2012-04-28 18:15:42 +0800 | [diff] [blame] | 571 | tasklet_schedule(&sdmac->tasklet); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 572 | |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 573 | __clear_bit(channel, &stat); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 574 | } |
| 575 | |
| 576 | return IRQ_HANDLED; |
| 577 | } |
| 578 | |
| 579 | /* |
| 580 | * sets the pc of SDMA script according to the peripheral type |
| 581 | */ |
| 582 | static void sdma_get_pc(struct sdma_channel *sdmac, |
| 583 | enum sdma_peripheral_type peripheral_type) |
| 584 | { |
| 585 | struct sdma_engine *sdma = sdmac->sdma; |
| 586 | int per_2_emi = 0, emi_2_per = 0; |
| 587 | /* |
| 588 | * These are needed once we start to support transfers between |
| 589 | * two peripherals or memory-to-memory transfers |
| 590 | */ |
| 591 | int per_2_per = 0, emi_2_emi = 0; |
| 592 | |
| 593 | sdmac->pc_from_device = 0; |
| 594 | sdmac->pc_to_device = 0; |
| 595 | |
| 596 | switch (peripheral_type) { |
| 597 | case IMX_DMATYPE_MEMORY: |
| 598 | emi_2_emi = sdma->script_addrs->ap_2_ap_addr; |
| 599 | break; |
| 600 | case IMX_DMATYPE_DSP: |
| 601 | emi_2_per = sdma->script_addrs->bp_2_ap_addr; |
| 602 | per_2_emi = sdma->script_addrs->ap_2_bp_addr; |
| 603 | break; |
| 604 | case IMX_DMATYPE_FIRI: |
| 605 | per_2_emi = sdma->script_addrs->firi_2_mcu_addr; |
| 606 | emi_2_per = sdma->script_addrs->mcu_2_firi_addr; |
| 607 | break; |
| 608 | case IMX_DMATYPE_UART: |
| 609 | per_2_emi = sdma->script_addrs->uart_2_mcu_addr; |
| 610 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; |
| 611 | break; |
| 612 | case IMX_DMATYPE_UART_SP: |
| 613 | per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; |
| 614 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; |
| 615 | break; |
| 616 | case IMX_DMATYPE_ATA: |
| 617 | per_2_emi = sdma->script_addrs->ata_2_mcu_addr; |
| 618 | emi_2_per = sdma->script_addrs->mcu_2_ata_addr; |
| 619 | break; |
| 620 | case IMX_DMATYPE_CSPI: |
| 621 | case IMX_DMATYPE_EXT: |
| 622 | case IMX_DMATYPE_SSI: |
| 623 | per_2_emi = sdma->script_addrs->app_2_mcu_addr; |
| 624 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; |
| 625 | break; |
| 626 | case IMX_DMATYPE_SSI_SP: |
| 627 | case IMX_DMATYPE_MMC: |
| 628 | case IMX_DMATYPE_SDHC: |
| 629 | case IMX_DMATYPE_CSPI_SP: |
| 630 | case IMX_DMATYPE_ESAI: |
| 631 | case IMX_DMATYPE_MSHC_SP: |
| 632 | per_2_emi = sdma->script_addrs->shp_2_mcu_addr; |
| 633 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; |
| 634 | break; |
| 635 | case IMX_DMATYPE_ASRC: |
| 636 | per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; |
| 637 | emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; |
| 638 | per_2_per = sdma->script_addrs->per_2_per_addr; |
| 639 | break; |
| 640 | case IMX_DMATYPE_MSHC: |
| 641 | per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; |
| 642 | emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; |
| 643 | break; |
| 644 | case IMX_DMATYPE_CCM: |
| 645 | per_2_emi = sdma->script_addrs->dptc_dvfs_addr; |
| 646 | break; |
| 647 | case IMX_DMATYPE_SPDIF: |
| 648 | per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; |
| 649 | emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; |
| 650 | break; |
| 651 | case IMX_DMATYPE_IPU_MEMORY: |
| 652 | emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; |
| 653 | break; |
| 654 | default: |
| 655 | break; |
| 656 | } |
| 657 | |
| 658 | sdmac->pc_from_device = per_2_emi; |
| 659 | sdmac->pc_to_device = emi_2_per; |
| 660 | } |
| 661 | |
| 662 | static int sdma_load_context(struct sdma_channel *sdmac) |
| 663 | { |
| 664 | struct sdma_engine *sdma = sdmac->sdma; |
| 665 | int channel = sdmac->channel; |
| 666 | int load_address; |
| 667 | struct sdma_context_data *context = sdma->context; |
| 668 | struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; |
| 669 | int ret; |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 670 | unsigned long flags; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 671 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 672 | if (sdmac->direction == DMA_DEV_TO_MEM) { |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 673 | load_address = sdmac->pc_from_device; |
| 674 | } else { |
| 675 | load_address = sdmac->pc_to_device; |
| 676 | } |
| 677 | |
| 678 | if (load_address < 0) |
| 679 | return load_address; |
| 680 | |
| 681 | dev_dbg(sdma->dev, "load_address = %d\n", load_address); |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 682 | dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 683 | dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); |
| 684 | dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 685 | dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); |
| 686 | dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 687 | |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 688 | spin_lock_irqsave(&sdma->channel_0_lock, flags); |
Sascha Hauer | 73eab97 | 2011-08-25 11:03:35 +0200 | [diff] [blame] | 689 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 690 | memset(context, 0, sizeof(*context)); |
| 691 | context->channel_state.pc = load_address; |
| 692 | |
| 693 | /* Send by context the event mask,base address for peripheral |
| 694 | * and watermark level |
| 695 | */ |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 696 | context->gReg[0] = sdmac->event_mask[1]; |
| 697 | context->gReg[1] = sdmac->event_mask[0]; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 698 | context->gReg[2] = sdmac->per_addr; |
| 699 | context->gReg[6] = sdmac->shp_addr; |
| 700 | context->gReg[7] = sdmac->watermark_level; |
| 701 | |
| 702 | bd0->mode.command = C0_SETDM; |
| 703 | bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; |
| 704 | bd0->mode.count = sizeof(*context) / 4; |
| 705 | bd0->buffer_addr = sdma->context_phys; |
| 706 | bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 707 | ret = sdma_run_channel0(sdma); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 708 | |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 709 | spin_unlock_irqrestore(&sdma->channel_0_lock, flags); |
Sascha Hauer | 73eab97 | 2011-08-25 11:03:35 +0200 | [diff] [blame] | 710 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 711 | return ret; |
| 712 | } |
| 713 | |
| 714 | static void sdma_disable_channel(struct sdma_channel *sdmac) |
| 715 | { |
| 716 | struct sdma_engine *sdma = sdmac->sdma; |
| 717 | int channel = sdmac->channel; |
| 718 | |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 719 | writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 720 | sdmac->status = DMA_ERROR; |
| 721 | } |
| 722 | |
| 723 | static int sdma_config_channel(struct sdma_channel *sdmac) |
| 724 | { |
| 725 | int ret; |
| 726 | |
| 727 | sdma_disable_channel(sdmac); |
| 728 | |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 729 | sdmac->event_mask[0] = 0; |
| 730 | sdmac->event_mask[1] = 0; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 731 | sdmac->shp_addr = 0; |
| 732 | sdmac->per_addr = 0; |
| 733 | |
| 734 | if (sdmac->event_id0) { |
Richard Zhao | b78bd91 | 2012-01-13 11:10:00 +0800 | [diff] [blame] | 735 | if (sdmac->event_id0 >= sdmac->sdma->num_events) |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 736 | return -EINVAL; |
| 737 | sdma_event_enable(sdmac, sdmac->event_id0); |
| 738 | } |
| 739 | |
| 740 | switch (sdmac->peripheral_type) { |
| 741 | case IMX_DMATYPE_DSP: |
| 742 | sdma_config_ownership(sdmac, false, true, true); |
| 743 | break; |
| 744 | case IMX_DMATYPE_MEMORY: |
| 745 | sdma_config_ownership(sdmac, false, true, false); |
| 746 | break; |
| 747 | default: |
| 748 | sdma_config_ownership(sdmac, true, true, false); |
| 749 | break; |
| 750 | } |
| 751 | |
| 752 | sdma_get_pc(sdmac, sdmac->peripheral_type); |
| 753 | |
| 754 | if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && |
| 755 | (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { |
| 756 | /* Handle multiple event channels differently */ |
| 757 | if (sdmac->event_id1) { |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 758 | sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 759 | if (sdmac->event_id1 > 31) |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 760 | __set_bit(31, &sdmac->watermark_level); |
| 761 | sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 762 | if (sdmac->event_id0 > 31) |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 763 | __set_bit(30, &sdmac->watermark_level); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 764 | } else { |
Richard Zhao | 0bbc141 | 2012-01-13 11:10:01 +0800 | [diff] [blame] | 765 | __set_bit(sdmac->event_id0, sdmac->event_mask); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 766 | } |
| 767 | /* Watermark Level */ |
| 768 | sdmac->watermark_level |= sdmac->watermark_level; |
| 769 | /* Address */ |
| 770 | sdmac->shp_addr = sdmac->per_address; |
| 771 | } else { |
| 772 | sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ |
| 773 | } |
| 774 | |
| 775 | ret = sdma_load_context(sdmac); |
| 776 | |
| 777 | return ret; |
| 778 | } |
| 779 | |
| 780 | static int sdma_set_channel_priority(struct sdma_channel *sdmac, |
| 781 | unsigned int priority) |
| 782 | { |
| 783 | struct sdma_engine *sdma = sdmac->sdma; |
| 784 | int channel = sdmac->channel; |
| 785 | |
| 786 | if (priority < MXC_SDMA_MIN_PRIORITY |
| 787 | || priority > MXC_SDMA_MAX_PRIORITY) { |
| 788 | return -EINVAL; |
| 789 | } |
| 790 | |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 791 | writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 792 | |
| 793 | return 0; |
| 794 | } |
| 795 | |
| 796 | static int sdma_request_channel(struct sdma_channel *sdmac) |
| 797 | { |
| 798 | struct sdma_engine *sdma = sdmac->sdma; |
| 799 | int channel = sdmac->channel; |
| 800 | int ret = -EBUSY; |
| 801 | |
| 802 | sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL); |
| 803 | if (!sdmac->bd) { |
| 804 | ret = -ENOMEM; |
| 805 | goto out; |
| 806 | } |
| 807 | |
| 808 | memset(sdmac->bd, 0, PAGE_SIZE); |
| 809 | |
| 810 | sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; |
| 811 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; |
| 812 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 813 | sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); |
| 814 | |
| 815 | init_completion(&sdmac->done); |
| 816 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 817 | return 0; |
| 818 | out: |
| 819 | |
| 820 | return ret; |
| 821 | } |
| 822 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 823 | static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) |
| 824 | { |
| 825 | return container_of(chan, struct sdma_channel, chan); |
| 826 | } |
| 827 | |
| 828 | static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) |
| 829 | { |
Haitao Zhang | f69f2e2 | 2012-01-01 11:30:06 +0800 | [diff] [blame] | 830 | unsigned long flags; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 831 | struct sdma_channel *sdmac = to_sdma_chan(tx->chan); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 832 | dma_cookie_t cookie; |
| 833 | |
Haitao Zhang | f69f2e2 | 2012-01-01 11:30:06 +0800 | [diff] [blame] | 834 | spin_lock_irqsave(&sdmac->lock, flags); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 835 | |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 836 | cookie = dma_cookie_assign(tx); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 837 | |
Haitao Zhang | f69f2e2 | 2012-01-01 11:30:06 +0800 | [diff] [blame] | 838 | spin_unlock_irqrestore(&sdmac->lock, flags); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 839 | |
| 840 | return cookie; |
| 841 | } |
| 842 | |
| 843 | static int sdma_alloc_chan_resources(struct dma_chan *chan) |
| 844 | { |
| 845 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
| 846 | struct imx_dma_data *data = chan->private; |
| 847 | int prio, ret; |
| 848 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 849 | if (!data) |
| 850 | return -EINVAL; |
| 851 | |
| 852 | switch (data->priority) { |
| 853 | case DMA_PRIO_HIGH: |
| 854 | prio = 3; |
| 855 | break; |
| 856 | case DMA_PRIO_MEDIUM: |
| 857 | prio = 2; |
| 858 | break; |
| 859 | case DMA_PRIO_LOW: |
| 860 | default: |
| 861 | prio = 1; |
| 862 | break; |
| 863 | } |
| 864 | |
| 865 | sdmac->peripheral_type = data->peripheral_type; |
| 866 | sdmac->event_id0 = data->dma_request; |
Richard Zhao | c2c744d | 2012-01-13 11:09:59 +0800 | [diff] [blame] | 867 | |
Sascha Hauer | 7560e3f | 2012-03-07 09:30:06 +0100 | [diff] [blame] | 868 | clk_enable(sdmac->sdma->clk_ipg); |
| 869 | clk_enable(sdmac->sdma->clk_ahb); |
Richard Zhao | c2c744d | 2012-01-13 11:09:59 +0800 | [diff] [blame] | 870 | |
Richard Zhao | 3bb5e7c | 2012-01-13 11:09:58 +0800 | [diff] [blame] | 871 | ret = sdma_request_channel(sdmac); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 872 | if (ret) |
| 873 | return ret; |
| 874 | |
Richard Zhao | 3bb5e7c | 2012-01-13 11:09:58 +0800 | [diff] [blame] | 875 | ret = sdma_set_channel_priority(sdmac, prio); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 876 | if (ret) |
| 877 | return ret; |
| 878 | |
| 879 | dma_async_tx_descriptor_init(&sdmac->desc, chan); |
| 880 | sdmac->desc.tx_submit = sdma_tx_submit; |
| 881 | /* txd.flags will be overwritten in prep funcs */ |
| 882 | sdmac->desc.flags = DMA_CTRL_ACK; |
| 883 | |
| 884 | return 0; |
| 885 | } |
| 886 | |
| 887 | static void sdma_free_chan_resources(struct dma_chan *chan) |
| 888 | { |
| 889 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
| 890 | struct sdma_engine *sdma = sdmac->sdma; |
| 891 | |
| 892 | sdma_disable_channel(sdmac); |
| 893 | |
| 894 | if (sdmac->event_id0) |
| 895 | sdma_event_disable(sdmac, sdmac->event_id0); |
| 896 | if (sdmac->event_id1) |
| 897 | sdma_event_disable(sdmac, sdmac->event_id1); |
| 898 | |
| 899 | sdmac->event_id0 = 0; |
| 900 | sdmac->event_id1 = 0; |
| 901 | |
| 902 | sdma_set_channel_priority(sdmac, 0); |
| 903 | |
| 904 | dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); |
| 905 | |
Sascha Hauer | 7560e3f | 2012-03-07 09:30:06 +0100 | [diff] [blame] | 906 | clk_disable(sdma->clk_ipg); |
| 907 | clk_disable(sdma->clk_ahb); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 908 | } |
| 909 | |
| 910 | static struct dma_async_tx_descriptor *sdma_prep_slave_sg( |
| 911 | struct dma_chan *chan, struct scatterlist *sgl, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 912 | unsigned int sg_len, enum dma_transfer_direction direction, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 913 | unsigned long flags, void *context) |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 914 | { |
| 915 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
| 916 | struct sdma_engine *sdma = sdmac->sdma; |
| 917 | int ret, i, count; |
Sascha Hauer | 23889c6 | 2011-01-31 10:56:58 +0100 | [diff] [blame] | 918 | int channel = sdmac->channel; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 919 | struct scatterlist *sg; |
| 920 | |
| 921 | if (sdmac->status == DMA_IN_PROGRESS) |
| 922 | return NULL; |
| 923 | sdmac->status = DMA_IN_PROGRESS; |
| 924 | |
| 925 | sdmac->flags = 0; |
| 926 | |
Richard Zhao | 8e2e27c | 2012-06-04 09:17:24 +0800 | [diff] [blame] | 927 | sdmac->buf_tail = 0; |
| 928 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 929 | dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", |
| 930 | sg_len, channel); |
| 931 | |
| 932 | sdmac->direction = direction; |
| 933 | ret = sdma_load_context(sdmac); |
| 934 | if (ret) |
| 935 | goto err_out; |
| 936 | |
| 937 | if (sg_len > NUM_BD) { |
| 938 | dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", |
| 939 | channel, sg_len, NUM_BD); |
| 940 | ret = -EINVAL; |
| 941 | goto err_out; |
| 942 | } |
| 943 | |
Huang Shijie | ab59a51 | 2011-12-02 10:16:25 +0800 | [diff] [blame] | 944 | sdmac->chn_count = 0; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 945 | for_each_sg(sgl, sg, sg_len, i) { |
| 946 | struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; |
| 947 | int param; |
| 948 | |
Anatolij Gustschin | d2f5c27 | 2010-11-22 18:35:18 +0100 | [diff] [blame] | 949 | bd->buffer_addr = sg->dma_address; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 950 | |
Lars-Peter Clausen | fdaf9c4 | 2012-04-25 20:50:52 +0200 | [diff] [blame] | 951 | count = sg_dma_len(sg); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 952 | |
| 953 | if (count > 0xffff) { |
| 954 | dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", |
| 955 | channel, count, 0xffff); |
| 956 | ret = -EINVAL; |
| 957 | goto err_out; |
| 958 | } |
| 959 | |
| 960 | bd->mode.count = count; |
Huang Shijie | ab59a51 | 2011-12-02 10:16:25 +0800 | [diff] [blame] | 961 | sdmac->chn_count += count; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 962 | |
| 963 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { |
| 964 | ret = -EINVAL; |
| 965 | goto err_out; |
| 966 | } |
Sascha Hauer | 1fa81c2 | 2011-01-12 13:02:28 +0100 | [diff] [blame] | 967 | |
| 968 | switch (sdmac->word_size) { |
| 969 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 970 | bd->mode.command = 0; |
Sascha Hauer | 1fa81c2 | 2011-01-12 13:02:28 +0100 | [diff] [blame] | 971 | if (count & 3 || sg->dma_address & 3) |
| 972 | return NULL; |
| 973 | break; |
| 974 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
| 975 | bd->mode.command = 2; |
| 976 | if (count & 1 || sg->dma_address & 1) |
| 977 | return NULL; |
| 978 | break; |
| 979 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
| 980 | bd->mode.command = 1; |
| 981 | break; |
| 982 | default: |
| 983 | return NULL; |
| 984 | } |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 985 | |
| 986 | param = BD_DONE | BD_EXTD | BD_CONT; |
| 987 | |
Shawn Guo | 341b941 | 2011-01-20 05:50:39 +0800 | [diff] [blame] | 988 | if (i + 1 == sg_len) { |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 989 | param |= BD_INTR; |
Shawn Guo | 341b941 | 2011-01-20 05:50:39 +0800 | [diff] [blame] | 990 | param |= BD_LAST; |
| 991 | param &= ~BD_CONT; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 992 | } |
| 993 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 994 | dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n", |
| 995 | i, count, sg->dma_address, |
| 996 | param & BD_WRAP ? "wrap" : "", |
| 997 | param & BD_INTR ? " intr" : ""); |
| 998 | |
| 999 | bd->mode.status = param; |
| 1000 | } |
| 1001 | |
| 1002 | sdmac->num_bd = sg_len; |
| 1003 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; |
| 1004 | |
| 1005 | return &sdmac->desc; |
| 1006 | err_out: |
Shawn Guo | 4b2ce9d | 2011-01-20 05:50:36 +0800 | [diff] [blame] | 1007 | sdmac->status = DMA_ERROR; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1008 | return NULL; |
| 1009 | } |
| 1010 | |
| 1011 | static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( |
| 1012 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 1013 | size_t period_len, enum dma_transfer_direction direction, |
Peter Ujfalusi | ec8b5e4 | 2012-09-14 15:05:47 +0300 | [diff] [blame] | 1014 | unsigned long flags, void *context) |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1015 | { |
| 1016 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
| 1017 | struct sdma_engine *sdma = sdmac->sdma; |
| 1018 | int num_periods = buf_len / period_len; |
Sascha Hauer | 23889c6 | 2011-01-31 10:56:58 +0100 | [diff] [blame] | 1019 | int channel = sdmac->channel; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1020 | int ret, i = 0, buf = 0; |
| 1021 | |
| 1022 | dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); |
| 1023 | |
| 1024 | if (sdmac->status == DMA_IN_PROGRESS) |
| 1025 | return NULL; |
| 1026 | |
| 1027 | sdmac->status = DMA_IN_PROGRESS; |
| 1028 | |
Richard Zhao | 8e2e27c | 2012-06-04 09:17:24 +0800 | [diff] [blame] | 1029 | sdmac->buf_tail = 0; |
| 1030 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1031 | sdmac->flags |= IMX_DMA_SG_LOOP; |
| 1032 | sdmac->direction = direction; |
| 1033 | ret = sdma_load_context(sdmac); |
| 1034 | if (ret) |
| 1035 | goto err_out; |
| 1036 | |
| 1037 | if (num_periods > NUM_BD) { |
| 1038 | dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", |
| 1039 | channel, num_periods, NUM_BD); |
| 1040 | goto err_out; |
| 1041 | } |
| 1042 | |
| 1043 | if (period_len > 0xffff) { |
| 1044 | dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n", |
| 1045 | channel, period_len, 0xffff); |
| 1046 | goto err_out; |
| 1047 | } |
| 1048 | |
| 1049 | while (buf < buf_len) { |
| 1050 | struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; |
| 1051 | int param; |
| 1052 | |
| 1053 | bd->buffer_addr = dma_addr; |
| 1054 | |
| 1055 | bd->mode.count = period_len; |
| 1056 | |
| 1057 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) |
| 1058 | goto err_out; |
| 1059 | if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) |
| 1060 | bd->mode.command = 0; |
| 1061 | else |
| 1062 | bd->mode.command = sdmac->word_size; |
| 1063 | |
| 1064 | param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; |
| 1065 | if (i + 1 == num_periods) |
| 1066 | param |= BD_WRAP; |
| 1067 | |
| 1068 | dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n", |
| 1069 | i, period_len, dma_addr, |
| 1070 | param & BD_WRAP ? "wrap" : "", |
| 1071 | param & BD_INTR ? " intr" : ""); |
| 1072 | |
| 1073 | bd->mode.status = param; |
| 1074 | |
| 1075 | dma_addr += period_len; |
| 1076 | buf += period_len; |
| 1077 | |
| 1078 | i++; |
| 1079 | } |
| 1080 | |
| 1081 | sdmac->num_bd = num_periods; |
| 1082 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; |
| 1083 | |
| 1084 | return &sdmac->desc; |
| 1085 | err_out: |
| 1086 | sdmac->status = DMA_ERROR; |
| 1087 | return NULL; |
| 1088 | } |
| 1089 | |
| 1090 | static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 1091 | unsigned long arg) |
| 1092 | { |
| 1093 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
| 1094 | struct dma_slave_config *dmaengine_cfg = (void *)arg; |
| 1095 | |
| 1096 | switch (cmd) { |
| 1097 | case DMA_TERMINATE_ALL: |
| 1098 | sdma_disable_channel(sdmac); |
| 1099 | return 0; |
| 1100 | case DMA_SLAVE_CONFIG: |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1101 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1102 | sdmac->per_address = dmaengine_cfg->src_addr; |
Philippe Rétornaz | 94ac27a | 2012-01-24 14:22:01 +0100 | [diff] [blame] | 1103 | sdmac->watermark_level = dmaengine_cfg->src_maxburst * |
| 1104 | dmaengine_cfg->src_addr_width; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1105 | sdmac->word_size = dmaengine_cfg->src_addr_width; |
| 1106 | } else { |
| 1107 | sdmac->per_address = dmaengine_cfg->dst_addr; |
Philippe Rétornaz | 94ac27a | 2012-01-24 14:22:01 +0100 | [diff] [blame] | 1108 | sdmac->watermark_level = dmaengine_cfg->dst_maxburst * |
| 1109 | dmaengine_cfg->dst_addr_width; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1110 | sdmac->word_size = dmaengine_cfg->dst_addr_width; |
| 1111 | } |
Huang Shijie | e696643 | 2011-11-18 16:38:02 +0800 | [diff] [blame] | 1112 | sdmac->direction = dmaengine_cfg->direction; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1113 | return sdma_config_channel(sdmac); |
| 1114 | default: |
| 1115 | return -ENOSYS; |
| 1116 | } |
| 1117 | |
| 1118 | return -EINVAL; |
| 1119 | } |
| 1120 | |
| 1121 | static enum dma_status sdma_tx_status(struct dma_chan *chan, |
| 1122 | dma_cookie_t cookie, |
| 1123 | struct dma_tx_state *txstate) |
| 1124 | { |
| 1125 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
| 1126 | dma_cookie_t last_used; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1127 | |
| 1128 | last_used = chan->cookie; |
| 1129 | |
Russell King - ARM Linux | 4d4e58d | 2012-03-06 22:34:06 +0000 | [diff] [blame] | 1130 | dma_set_tx_state(txstate, chan->completed_cookie, last_used, |
Huang Shijie | ab59a51 | 2011-12-02 10:16:25 +0800 | [diff] [blame] | 1131 | sdmac->chn_count - sdmac->chn_real_count); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1132 | |
Shawn Guo | 8a96591 | 2011-01-20 05:50:37 +0800 | [diff] [blame] | 1133 | return sdmac->status; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1134 | } |
| 1135 | |
| 1136 | static void sdma_issue_pending(struct dma_chan *chan) |
| 1137 | { |
Sascha Hauer | 2b4f130 | 2012-01-09 10:32:50 +0100 | [diff] [blame] | 1138 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
| 1139 | struct sdma_engine *sdma = sdmac->sdma; |
| 1140 | |
| 1141 | if (sdmac->status == DMA_IN_PROGRESS) |
| 1142 | sdma_enable_channel(sdma, sdmac->channel); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1143 | } |
| 1144 | |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1145 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 |
| 1146 | |
| 1147 | static void sdma_add_scripts(struct sdma_engine *sdma, |
| 1148 | const struct sdma_script_start_addrs *addr) |
| 1149 | { |
| 1150 | s32 *addr_arr = (u32 *)addr; |
| 1151 | s32 *saddr_arr = (u32 *)sdma->script_addrs; |
| 1152 | int i; |
| 1153 | |
| 1154 | for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) |
| 1155 | if (addr_arr[i] > 0) |
| 1156 | saddr_arr[i] = addr_arr[i]; |
| 1157 | } |
| 1158 | |
Sascha Hauer | 7b4b88e | 2011-08-25 11:03:37 +0200 | [diff] [blame] | 1159 | static void sdma_load_firmware(const struct firmware *fw, void *context) |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1160 | { |
Sascha Hauer | 7b4b88e | 2011-08-25 11:03:37 +0200 | [diff] [blame] | 1161 | struct sdma_engine *sdma = context; |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1162 | const struct sdma_firmware_header *header; |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1163 | const struct sdma_script_start_addrs *addr; |
| 1164 | unsigned short *ram_code; |
| 1165 | |
Sascha Hauer | 7b4b88e | 2011-08-25 11:03:37 +0200 | [diff] [blame] | 1166 | if (!fw) { |
| 1167 | dev_err(sdma->dev, "firmware not found\n"); |
| 1168 | return; |
| 1169 | } |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1170 | |
| 1171 | if (fw->size < sizeof(*header)) |
| 1172 | goto err_firmware; |
| 1173 | |
| 1174 | header = (struct sdma_firmware_header *)fw->data; |
| 1175 | |
| 1176 | if (header->magic != SDMA_FIRMWARE_MAGIC) |
| 1177 | goto err_firmware; |
| 1178 | if (header->ram_code_start + header->ram_code_size > fw->size) |
| 1179 | goto err_firmware; |
| 1180 | |
| 1181 | addr = (void *)header + header->script_addrs_start; |
| 1182 | ram_code = (void *)header + header->ram_code_start; |
| 1183 | |
Sascha Hauer | 7560e3f | 2012-03-07 09:30:06 +0100 | [diff] [blame] | 1184 | clk_enable(sdma->clk_ipg); |
| 1185 | clk_enable(sdma->clk_ahb); |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1186 | /* download the RAM image for SDMA */ |
| 1187 | sdma_load_script(sdma, ram_code, |
| 1188 | header->ram_code_size, |
Sascha Hauer | 6866fd3 | 2011-01-12 11:18:14 +0100 | [diff] [blame] | 1189 | addr->ram_code_start_addr); |
Sascha Hauer | 7560e3f | 2012-03-07 09:30:06 +0100 | [diff] [blame] | 1190 | clk_disable(sdma->clk_ipg); |
| 1191 | clk_disable(sdma->clk_ahb); |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1192 | |
| 1193 | sdma_add_scripts(sdma, addr); |
| 1194 | |
| 1195 | dev_info(sdma->dev, "loaded firmware %d.%d\n", |
| 1196 | header->version_major, |
| 1197 | header->version_minor); |
| 1198 | |
| 1199 | err_firmware: |
| 1200 | release_firmware(fw); |
Sascha Hauer | 7b4b88e | 2011-08-25 11:03:37 +0200 | [diff] [blame] | 1201 | } |
| 1202 | |
| 1203 | static int __init sdma_get_firmware(struct sdma_engine *sdma, |
| 1204 | const char *fw_name) |
| 1205 | { |
| 1206 | int ret; |
| 1207 | |
| 1208 | ret = request_firmware_nowait(THIS_MODULE, |
| 1209 | FW_ACTION_HOTPLUG, fw_name, sdma->dev, |
| 1210 | GFP_KERNEL, sdma, sdma_load_firmware); |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1211 | |
| 1212 | return ret; |
| 1213 | } |
| 1214 | |
| 1215 | static int __init sdma_init(struct sdma_engine *sdma) |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1216 | { |
| 1217 | int i, ret; |
| 1218 | dma_addr_t ccb_phys; |
| 1219 | |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 1220 | switch (sdma->devtype) { |
| 1221 | case IMX31_SDMA: |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1222 | sdma->num_events = 32; |
| 1223 | break; |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 1224 | case IMX35_SDMA: |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1225 | sdma->num_events = 48; |
| 1226 | break; |
| 1227 | default: |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 1228 | dev_err(sdma->dev, "Unknown sdma type %d. aborting\n", |
| 1229 | sdma->devtype); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1230 | return -ENODEV; |
| 1231 | } |
| 1232 | |
Sascha Hauer | 7560e3f | 2012-03-07 09:30:06 +0100 | [diff] [blame] | 1233 | clk_enable(sdma->clk_ipg); |
| 1234 | clk_enable(sdma->clk_ahb); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1235 | |
| 1236 | /* Be sure SDMA has not started yet */ |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 1237 | writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1238 | |
| 1239 | sdma->channel_control = dma_alloc_coherent(NULL, |
| 1240 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + |
| 1241 | sizeof(struct sdma_context_data), |
| 1242 | &ccb_phys, GFP_KERNEL); |
| 1243 | |
| 1244 | if (!sdma->channel_control) { |
| 1245 | ret = -ENOMEM; |
| 1246 | goto err_dma_alloc; |
| 1247 | } |
| 1248 | |
| 1249 | sdma->context = (void *)sdma->channel_control + |
| 1250 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); |
| 1251 | sdma->context_phys = ccb_phys + |
| 1252 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); |
| 1253 | |
| 1254 | /* Zero-out the CCB structures array just allocated */ |
| 1255 | memset(sdma->channel_control, 0, |
| 1256 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); |
| 1257 | |
| 1258 | /* disable all channels */ |
| 1259 | for (i = 0; i < sdma->num_events; i++) |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 1260 | writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1261 | |
| 1262 | /* All channels have priority 0 */ |
| 1263 | for (i = 0; i < MAX_DMA_CHANNELS; i++) |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 1264 | writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1265 | |
| 1266 | ret = sdma_request_channel(&sdma->channel[0]); |
| 1267 | if (ret) |
| 1268 | goto err_dma_alloc; |
| 1269 | |
| 1270 | sdma_config_ownership(&sdma->channel[0], false, true, false); |
| 1271 | |
| 1272 | /* Set Command Channel (Channel Zero) */ |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 1273 | writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1274 | |
| 1275 | /* Set bits of CONFIG register but with static context switching */ |
| 1276 | /* FIXME: Check whether to set ACR bit depending on clock ratios */ |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 1277 | writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1278 | |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 1279 | writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1280 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1281 | /* Set bits of CONFIG register with given context switching mode */ |
Richard Zhao | c4b5685 | 2012-01-13 11:09:57 +0800 | [diff] [blame] | 1282 | writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1283 | |
| 1284 | /* Initializes channel's priorities */ |
| 1285 | sdma_set_channel_priority(&sdma->channel[0], 7); |
| 1286 | |
Sascha Hauer | 7560e3f | 2012-03-07 09:30:06 +0100 | [diff] [blame] | 1287 | clk_disable(sdma->clk_ipg); |
| 1288 | clk_disable(sdma->clk_ahb); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1289 | |
| 1290 | return 0; |
| 1291 | |
| 1292 | err_dma_alloc: |
Sascha Hauer | 7560e3f | 2012-03-07 09:30:06 +0100 | [diff] [blame] | 1293 | clk_disable(sdma->clk_ipg); |
| 1294 | clk_disable(sdma->clk_ahb); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1295 | dev_err(sdma->dev, "initialisation failed with %d\n", ret); |
| 1296 | return ret; |
| 1297 | } |
| 1298 | |
| 1299 | static int __init sdma_probe(struct platform_device *pdev) |
| 1300 | { |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 1301 | const struct of_device_id *of_id = |
| 1302 | of_match_device(sdma_dt_ids, &pdev->dev); |
| 1303 | struct device_node *np = pdev->dev.of_node; |
| 1304 | const char *fw_name; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1305 | int ret; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1306 | int irq; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1307 | struct resource *iores; |
| 1308 | struct sdma_platform_data *pdata = pdev->dev.platform_data; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1309 | int i; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1310 | struct sdma_engine *sdma; |
Sascha Hauer | 36e2f21 | 2011-08-25 11:03:36 +0200 | [diff] [blame] | 1311 | s32 *saddr_arr; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1312 | |
| 1313 | sdma = kzalloc(sizeof(*sdma), GFP_KERNEL); |
| 1314 | if (!sdma) |
| 1315 | return -ENOMEM; |
| 1316 | |
Richard Zhao | 2ccaef0 | 2012-05-11 15:14:27 +0800 | [diff] [blame] | 1317 | spin_lock_init(&sdma->channel_0_lock); |
Sascha Hauer | 73eab97 | 2011-08-25 11:03:35 +0200 | [diff] [blame] | 1318 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1319 | sdma->dev = &pdev->dev; |
| 1320 | |
| 1321 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1322 | irq = platform_get_irq(pdev, 0); |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 1323 | if (!iores || irq < 0) { |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1324 | ret = -EINVAL; |
| 1325 | goto err_irq; |
| 1326 | } |
| 1327 | |
| 1328 | if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) { |
| 1329 | ret = -EBUSY; |
| 1330 | goto err_request_region; |
| 1331 | } |
| 1332 | |
Sascha Hauer | 7560e3f | 2012-03-07 09:30:06 +0100 | [diff] [blame] | 1333 | sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
| 1334 | if (IS_ERR(sdma->clk_ipg)) { |
| 1335 | ret = PTR_ERR(sdma->clk_ipg); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1336 | goto err_clk; |
| 1337 | } |
| 1338 | |
Sascha Hauer | 7560e3f | 2012-03-07 09:30:06 +0100 | [diff] [blame] | 1339 | sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); |
| 1340 | if (IS_ERR(sdma->clk_ahb)) { |
| 1341 | ret = PTR_ERR(sdma->clk_ahb); |
| 1342 | goto err_clk; |
| 1343 | } |
| 1344 | |
| 1345 | clk_prepare(sdma->clk_ipg); |
| 1346 | clk_prepare(sdma->clk_ahb); |
| 1347 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1348 | sdma->regs = ioremap(iores->start, resource_size(iores)); |
| 1349 | if (!sdma->regs) { |
| 1350 | ret = -ENOMEM; |
| 1351 | goto err_ioremap; |
| 1352 | } |
| 1353 | |
| 1354 | ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma); |
| 1355 | if (ret) |
| 1356 | goto err_request_irq; |
| 1357 | |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1358 | sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); |
Axel Lin | 1c1d954 | 2011-07-12 21:00:13 +0800 | [diff] [blame] | 1359 | if (!sdma->script_addrs) { |
| 1360 | ret = -ENOMEM; |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1361 | goto err_alloc; |
Axel Lin | 1c1d954 | 2011-07-12 21:00:13 +0800 | [diff] [blame] | 1362 | } |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1363 | |
Sascha Hauer | 36e2f21 | 2011-08-25 11:03:36 +0200 | [diff] [blame] | 1364 | /* initially no scripts available */ |
| 1365 | saddr_arr = (s32 *)sdma->script_addrs; |
| 1366 | for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) |
| 1367 | saddr_arr[i] = -EINVAL; |
| 1368 | |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 1369 | if (of_id) |
| 1370 | pdev->id_entry = of_id->data; |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 1371 | sdma->devtype = pdev->id_entry->driver_data; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1372 | |
Sascha Hauer | 7214a8b | 2011-01-31 10:21:35 +0100 | [diff] [blame] | 1373 | dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); |
| 1374 | dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); |
| 1375 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1376 | INIT_LIST_HEAD(&sdma->dma_device.channels); |
| 1377 | /* Initialize channel parameters */ |
| 1378 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { |
| 1379 | struct sdma_channel *sdmac = &sdma->channel[i]; |
| 1380 | |
| 1381 | sdmac->sdma = sdma; |
| 1382 | spin_lock_init(&sdmac->lock); |
| 1383 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1384 | sdmac->chan.device = &sdma->dma_device; |
Russell King - ARM Linux | 8ac6954 | 2012-03-06 22:36:27 +0000 | [diff] [blame] | 1385 | dma_cookie_init(&sdmac->chan); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1386 | sdmac->channel = i; |
| 1387 | |
Huang Shijie | abd9ccc | 2012-04-28 18:15:42 +0800 | [diff] [blame] | 1388 | tasklet_init(&sdmac->tasklet, sdma_tasklet, |
| 1389 | (unsigned long) sdmac); |
Sascha Hauer | 23889c6 | 2011-01-31 10:56:58 +0100 | [diff] [blame] | 1390 | /* |
| 1391 | * Add the channel to the DMAC list. Do not add channel 0 though |
| 1392 | * because we need it internally in the SDMA driver. This also means |
| 1393 | * that channel 0 in dmaengine counting matches sdma channel 1. |
| 1394 | */ |
| 1395 | if (i) |
| 1396 | list_add_tail(&sdmac->chan.device_node, |
| 1397 | &sdma->dma_device.channels); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1398 | } |
| 1399 | |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1400 | ret = sdma_init(sdma); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1401 | if (ret) |
| 1402 | goto err_init; |
| 1403 | |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 1404 | if (pdata && pdata->script_addrs) |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1405 | sdma_add_scripts(sdma, pdata->script_addrs); |
| 1406 | |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 1407 | if (pdata) { |
Fabio Estevam | 6d0d7e2 | 2012-02-29 11:20:38 -0300 | [diff] [blame] | 1408 | ret = sdma_get_firmware(sdma, pdata->fw_name); |
| 1409 | if (ret) |
Fabio Estevam | ad1122e | 2012-03-08 09:26:39 -0300 | [diff] [blame] | 1410 | dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 1411 | } else { |
| 1412 | /* |
| 1413 | * Because that device tree does not encode ROM script address, |
| 1414 | * the RAM script in firmware is mandatory for device tree |
| 1415 | * probe, otherwise it fails. |
| 1416 | */ |
| 1417 | ret = of_property_read_string(np, "fsl,sdma-ram-script-name", |
| 1418 | &fw_name); |
Fabio Estevam | 6602b0d | 2012-02-29 11:20:37 -0300 | [diff] [blame] | 1419 | if (ret) |
Fabio Estevam | ad1122e | 2012-03-08 09:26:39 -0300 | [diff] [blame] | 1420 | dev_warn(&pdev->dev, "failed to get firmware name\n"); |
Fabio Estevam | 6602b0d | 2012-02-29 11:20:37 -0300 | [diff] [blame] | 1421 | else { |
| 1422 | ret = sdma_get_firmware(sdma, fw_name); |
| 1423 | if (ret) |
Fabio Estevam | ad1122e | 2012-03-08 09:26:39 -0300 | [diff] [blame] | 1424 | dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 1425 | } |
| 1426 | } |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1427 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1428 | sdma->dma_device.dev = &pdev->dev; |
| 1429 | |
| 1430 | sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; |
| 1431 | sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; |
| 1432 | sdma->dma_device.device_tx_status = sdma_tx_status; |
| 1433 | sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; |
| 1434 | sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; |
| 1435 | sdma->dma_device.device_control = sdma_control; |
| 1436 | sdma->dma_device.device_issue_pending = sdma_issue_pending; |
Sascha Hauer | b9b3f82 | 2011-01-12 12:12:31 +0100 | [diff] [blame] | 1437 | sdma->dma_device.dev->dma_parms = &sdma->dma_parms; |
| 1438 | dma_set_max_seg_size(sdma->dma_device.dev, 65535); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1439 | |
| 1440 | ret = dma_async_device_register(&sdma->dma_device); |
| 1441 | if (ret) { |
| 1442 | dev_err(&pdev->dev, "unable to register\n"); |
| 1443 | goto err_init; |
| 1444 | } |
| 1445 | |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1446 | dev_info(sdma->dev, "initialized\n"); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1447 | |
| 1448 | return 0; |
| 1449 | |
| 1450 | err_init: |
| 1451 | kfree(sdma->script_addrs); |
Sascha Hauer | 5b28aa3 | 2010-10-06 15:41:15 +0200 | [diff] [blame] | 1452 | err_alloc: |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1453 | free_irq(irq, sdma); |
| 1454 | err_request_irq: |
| 1455 | iounmap(sdma->regs); |
| 1456 | err_ioremap: |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1457 | err_clk: |
| 1458 | release_mem_region(iores->start, resource_size(iores)); |
| 1459 | err_request_region: |
| 1460 | err_irq: |
| 1461 | kfree(sdma); |
Shawn Guo | 939fd4f | 2011-01-19 19:13:06 +0800 | [diff] [blame] | 1462 | return ret; |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1463 | } |
| 1464 | |
| 1465 | static int __exit sdma_remove(struct platform_device *pdev) |
| 1466 | { |
| 1467 | return -EBUSY; |
| 1468 | } |
| 1469 | |
| 1470 | static struct platform_driver sdma_driver = { |
| 1471 | .driver = { |
| 1472 | .name = "imx-sdma", |
Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 1473 | .of_match_table = sdma_dt_ids, |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1474 | }, |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 1475 | .id_table = sdma_devtypes, |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1476 | .remove = __exit_p(sdma_remove), |
| 1477 | }; |
| 1478 | |
| 1479 | static int __init sdma_module_init(void) |
| 1480 | { |
| 1481 | return platform_driver_probe(&sdma_driver, sdma_probe); |
| 1482 | } |
Sascha Hauer | c989a7f | 2010-12-06 11:09:57 +0100 | [diff] [blame] | 1483 | module_init(sdma_module_init); |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 1484 | |
| 1485 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); |
| 1486 | MODULE_DESCRIPTION("i.MX SDMA driver"); |
| 1487 | MODULE_LICENSE("GPL"); |