Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Driver for ESS Maestro3/Allegro (ES1988) soundcards. |
| 3 | * Copyright (c) 2000 by Zach Brown <zab@zabbo.net> |
| 4 | * Takashi Iwai <tiwai@suse.de> |
| 5 | * |
| 6 | * Most of the hardware init stuffs are based on maestro3 driver for |
| 7 | * OSS/Free by Zach Brown. Many thanks to Zach! |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * |
| 24 | * ChangeLog: |
| 25 | * Aug. 27, 2001 |
| 26 | * - Fixed deadlock on capture |
| 27 | * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org> |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2" |
| 32 | #define DRIVER_NAME "Maestro3" |
| 33 | |
| 34 | #include <sound/driver.h> |
| 35 | #include <asm/io.h> |
| 36 | #include <linux/delay.h> |
| 37 | #include <linux/interrupt.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/pci.h> |
| 40 | #include <linux/slab.h> |
| 41 | #include <linux/vmalloc.h> |
| 42 | #include <linux/moduleparam.h> |
| 43 | #include <sound/core.h> |
| 44 | #include <sound/info.h> |
| 45 | #include <sound/control.h> |
| 46 | #include <sound/pcm.h> |
| 47 | #include <sound/mpu401.h> |
| 48 | #include <sound/ac97_codec.h> |
| 49 | #include <sound/initval.h> |
| 50 | |
| 51 | MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>"); |
| 52 | MODULE_DESCRIPTION("ESS Maestro3 PCI"); |
| 53 | MODULE_LICENSE("GPL"); |
| 54 | MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI}," |
| 55 | "{ESS,ES1988}," |
| 56 | "{ESS,Allegro PCI}," |
| 57 | "{ESS,Allegro-1 PCI}," |
| 58 | "{ESS,Canyon3D-2/LE PCI}}"); |
| 59 | |
| 60 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
| 61 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ |
| 62 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */ |
| 63 | static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1}; |
| 64 | static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1}; |
| 65 | |
| 66 | module_param_array(index, int, NULL, 0444); |
| 67 | MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); |
| 68 | module_param_array(id, charp, NULL, 0444); |
| 69 | MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); |
| 70 | module_param_array(enable, bool, NULL, 0444); |
| 71 | MODULE_PARM_DESC(enable, "Enable this soundcard."); |
| 72 | module_param_array(external_amp, bool, NULL, 0444); |
| 73 | MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard."); |
| 74 | module_param_array(amp_gpio, int, NULL, 0444); |
| 75 | MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)"); |
| 76 | |
| 77 | #define MAX_PLAYBACKS 2 |
| 78 | #define MAX_CAPTURES 1 |
| 79 | #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES) |
| 80 | |
| 81 | |
| 82 | /* |
| 83 | * maestro3 registers |
| 84 | */ |
| 85 | |
| 86 | /* Allegro PCI configuration registers */ |
| 87 | #define PCI_LEGACY_AUDIO_CTRL 0x40 |
| 88 | #define SOUND_BLASTER_ENABLE 0x00000001 |
| 89 | #define FM_SYNTHESIS_ENABLE 0x00000002 |
| 90 | #define GAME_PORT_ENABLE 0x00000004 |
| 91 | #define MPU401_IO_ENABLE 0x00000008 |
| 92 | #define MPU401_IRQ_ENABLE 0x00000010 |
| 93 | #define ALIAS_10BIT_IO 0x00000020 |
| 94 | #define SB_DMA_MASK 0x000000C0 |
| 95 | #define SB_DMA_0 0x00000040 |
| 96 | #define SB_DMA_1 0x00000040 |
| 97 | #define SB_DMA_R 0x00000080 |
| 98 | #define SB_DMA_3 0x000000C0 |
| 99 | #define SB_IRQ_MASK 0x00000700 |
| 100 | #define SB_IRQ_5 0x00000000 |
| 101 | #define SB_IRQ_7 0x00000100 |
| 102 | #define SB_IRQ_9 0x00000200 |
| 103 | #define SB_IRQ_10 0x00000300 |
| 104 | #define MIDI_IRQ_MASK 0x00003800 |
| 105 | #define SERIAL_IRQ_ENABLE 0x00004000 |
| 106 | #define DISABLE_LEGACY 0x00008000 |
| 107 | |
| 108 | #define PCI_ALLEGRO_CONFIG 0x50 |
| 109 | #define SB_ADDR_240 0x00000004 |
| 110 | #define MPU_ADDR_MASK 0x00000018 |
| 111 | #define MPU_ADDR_330 0x00000000 |
| 112 | #define MPU_ADDR_300 0x00000008 |
| 113 | #define MPU_ADDR_320 0x00000010 |
| 114 | #define MPU_ADDR_340 0x00000018 |
| 115 | #define USE_PCI_TIMING 0x00000040 |
| 116 | #define POSTED_WRITE_ENABLE 0x00000080 |
| 117 | #define DMA_POLICY_MASK 0x00000700 |
| 118 | #define DMA_DDMA 0x00000000 |
| 119 | #define DMA_TDMA 0x00000100 |
| 120 | #define DMA_PCPCI 0x00000200 |
| 121 | #define DMA_WBDMA16 0x00000400 |
| 122 | #define DMA_WBDMA4 0x00000500 |
| 123 | #define DMA_WBDMA2 0x00000600 |
| 124 | #define DMA_WBDMA1 0x00000700 |
| 125 | #define DMA_SAFE_GUARD 0x00000800 |
| 126 | #define HI_PERF_GP_ENABLE 0x00001000 |
| 127 | #define PIC_SNOOP_MODE_0 0x00002000 |
| 128 | #define PIC_SNOOP_MODE_1 0x00004000 |
| 129 | #define SOUNDBLASTER_IRQ_MASK 0x00008000 |
| 130 | #define RING_IN_ENABLE 0x00010000 |
| 131 | #define SPDIF_TEST_MODE 0x00020000 |
| 132 | #define CLK_MULT_MODE_SELECT_2 0x00040000 |
| 133 | #define EEPROM_WRITE_ENABLE 0x00080000 |
| 134 | #define CODEC_DIR_IN 0x00100000 |
| 135 | #define HV_BUTTON_FROM_GD 0x00200000 |
| 136 | #define REDUCED_DEBOUNCE 0x00400000 |
| 137 | #define HV_CTRL_ENABLE 0x00800000 |
| 138 | #define SPDIF_ENABLE 0x01000000 |
| 139 | #define CLK_DIV_SELECT 0x06000000 |
| 140 | #define CLK_DIV_BY_48 0x00000000 |
| 141 | #define CLK_DIV_BY_49 0x02000000 |
| 142 | #define CLK_DIV_BY_50 0x04000000 |
| 143 | #define CLK_DIV_RESERVED 0x06000000 |
| 144 | #define PM_CTRL_ENABLE 0x08000000 |
| 145 | #define CLK_MULT_MODE_SELECT 0x30000000 |
| 146 | #define CLK_MULT_MODE_SHIFT 28 |
| 147 | #define CLK_MULT_MODE_0 0x00000000 |
| 148 | #define CLK_MULT_MODE_1 0x10000000 |
| 149 | #define CLK_MULT_MODE_2 0x20000000 |
| 150 | #define CLK_MULT_MODE_3 0x30000000 |
| 151 | #define INT_CLK_SELECT 0x40000000 |
| 152 | #define INT_CLK_MULT_RESET 0x80000000 |
| 153 | |
| 154 | /* M3 */ |
| 155 | #define INT_CLK_SRC_NOT_PCI 0x00100000 |
| 156 | #define INT_CLK_MULT_ENABLE 0x80000000 |
| 157 | |
| 158 | #define PCI_ACPI_CONTROL 0x54 |
| 159 | #define PCI_ACPI_D0 0x00000000 |
| 160 | #define PCI_ACPI_D1 0xB4F70000 |
| 161 | #define PCI_ACPI_D2 0xB4F7B4F7 |
| 162 | |
| 163 | #define PCI_USER_CONFIG 0x58 |
| 164 | #define EXT_PCI_MASTER_ENABLE 0x00000001 |
| 165 | #define SPDIF_OUT_SELECT 0x00000002 |
| 166 | #define TEST_PIN_DIR_CTRL 0x00000004 |
| 167 | #define AC97_CODEC_TEST 0x00000020 |
| 168 | #define TRI_STATE_BUFFER 0x00000080 |
| 169 | #define IN_CLK_12MHZ_SELECT 0x00000100 |
| 170 | #define MULTI_FUNC_DISABLE 0x00000200 |
| 171 | #define EXT_MASTER_PAIR_SEL 0x00000400 |
| 172 | #define PCI_MASTER_SUPPORT 0x00000800 |
| 173 | #define STOP_CLOCK_ENABLE 0x00001000 |
| 174 | #define EAPD_DRIVE_ENABLE 0x00002000 |
| 175 | #define REQ_TRI_STATE_ENABLE 0x00004000 |
| 176 | #define REQ_LOW_ENABLE 0x00008000 |
| 177 | #define MIDI_1_ENABLE 0x00010000 |
| 178 | #define MIDI_2_ENABLE 0x00020000 |
| 179 | #define SB_AUDIO_SYNC 0x00040000 |
| 180 | #define HV_CTRL_TEST 0x00100000 |
| 181 | #define SOUNDBLASTER_TEST 0x00400000 |
| 182 | |
| 183 | #define PCI_USER_CONFIG_C 0x5C |
| 184 | |
| 185 | #define PCI_DDMA_CTRL 0x60 |
| 186 | #define DDMA_ENABLE 0x00000001 |
| 187 | |
| 188 | |
| 189 | /* Allegro registers */ |
| 190 | #define HOST_INT_CTRL 0x18 |
| 191 | #define SB_INT_ENABLE 0x0001 |
| 192 | #define MPU401_INT_ENABLE 0x0002 |
| 193 | #define ASSP_INT_ENABLE 0x0010 |
| 194 | #define RING_INT_ENABLE 0x0020 |
| 195 | #define HV_INT_ENABLE 0x0040 |
| 196 | #define CLKRUN_GEN_ENABLE 0x0100 |
| 197 | #define HV_CTRL_TO_PME 0x0400 |
| 198 | #define SOFTWARE_RESET_ENABLE 0x8000 |
| 199 | |
| 200 | /* |
| 201 | * should be using the above defines, probably. |
| 202 | */ |
| 203 | #define REGB_ENABLE_RESET 0x01 |
| 204 | #define REGB_STOP_CLOCK 0x10 |
| 205 | |
| 206 | #define HOST_INT_STATUS 0x1A |
| 207 | #define SB_INT_PENDING 0x01 |
| 208 | #define MPU401_INT_PENDING 0x02 |
| 209 | #define ASSP_INT_PENDING 0x10 |
| 210 | #define RING_INT_PENDING 0x20 |
| 211 | #define HV_INT_PENDING 0x40 |
| 212 | |
| 213 | #define HARDWARE_VOL_CTRL 0x1B |
| 214 | #define SHADOW_MIX_REG_VOICE 0x1C |
| 215 | #define HW_VOL_COUNTER_VOICE 0x1D |
| 216 | #define SHADOW_MIX_REG_MASTER 0x1E |
| 217 | #define HW_VOL_COUNTER_MASTER 0x1F |
| 218 | |
| 219 | #define CODEC_COMMAND 0x30 |
| 220 | #define CODEC_READ_B 0x80 |
| 221 | |
| 222 | #define CODEC_STATUS 0x30 |
| 223 | #define CODEC_BUSY_B 0x01 |
| 224 | |
| 225 | #define CODEC_DATA 0x32 |
| 226 | |
| 227 | #define RING_BUS_CTRL_A 0x36 |
| 228 | #define RAC_PME_ENABLE 0x0100 |
| 229 | #define RAC_SDFS_ENABLE 0x0200 |
| 230 | #define LAC_PME_ENABLE 0x0400 |
| 231 | #define LAC_SDFS_ENABLE 0x0800 |
| 232 | #define SERIAL_AC_LINK_ENABLE 0x1000 |
| 233 | #define IO_SRAM_ENABLE 0x2000 |
| 234 | #define IIS_INPUT_ENABLE 0x8000 |
| 235 | |
| 236 | #define RING_BUS_CTRL_B 0x38 |
| 237 | #define SECOND_CODEC_ID_MASK 0x0003 |
| 238 | #define SPDIF_FUNC_ENABLE 0x0010 |
| 239 | #define SECOND_AC_ENABLE 0x0020 |
| 240 | #define SB_MODULE_INTF_ENABLE 0x0040 |
| 241 | #define SSPE_ENABLE 0x0040 |
| 242 | #define M3I_DOCK_ENABLE 0x0080 |
| 243 | |
| 244 | #define SDO_OUT_DEST_CTRL 0x3A |
| 245 | #define COMMAND_ADDR_OUT 0x0003 |
| 246 | #define PCM_LR_OUT_LOCAL 0x0000 |
| 247 | #define PCM_LR_OUT_REMOTE 0x0004 |
| 248 | #define PCM_LR_OUT_MUTE 0x0008 |
| 249 | #define PCM_LR_OUT_BOTH 0x000C |
| 250 | #define LINE1_DAC_OUT_LOCAL 0x0000 |
| 251 | #define LINE1_DAC_OUT_REMOTE 0x0010 |
| 252 | #define LINE1_DAC_OUT_MUTE 0x0020 |
| 253 | #define LINE1_DAC_OUT_BOTH 0x0030 |
| 254 | #define PCM_CLS_OUT_LOCAL 0x0000 |
| 255 | #define PCM_CLS_OUT_REMOTE 0x0040 |
| 256 | #define PCM_CLS_OUT_MUTE 0x0080 |
| 257 | #define PCM_CLS_OUT_BOTH 0x00C0 |
| 258 | #define PCM_RLF_OUT_LOCAL 0x0000 |
| 259 | #define PCM_RLF_OUT_REMOTE 0x0100 |
| 260 | #define PCM_RLF_OUT_MUTE 0x0200 |
| 261 | #define PCM_RLF_OUT_BOTH 0x0300 |
| 262 | #define LINE2_DAC_OUT_LOCAL 0x0000 |
| 263 | #define LINE2_DAC_OUT_REMOTE 0x0400 |
| 264 | #define LINE2_DAC_OUT_MUTE 0x0800 |
| 265 | #define LINE2_DAC_OUT_BOTH 0x0C00 |
| 266 | #define HANDSET_OUT_LOCAL 0x0000 |
| 267 | #define HANDSET_OUT_REMOTE 0x1000 |
| 268 | #define HANDSET_OUT_MUTE 0x2000 |
| 269 | #define HANDSET_OUT_BOTH 0x3000 |
| 270 | #define IO_CTRL_OUT_LOCAL 0x0000 |
| 271 | #define IO_CTRL_OUT_REMOTE 0x4000 |
| 272 | #define IO_CTRL_OUT_MUTE 0x8000 |
| 273 | #define IO_CTRL_OUT_BOTH 0xC000 |
| 274 | |
| 275 | #define SDO_IN_DEST_CTRL 0x3C |
| 276 | #define STATUS_ADDR_IN 0x0003 |
| 277 | #define PCM_LR_IN_LOCAL 0x0000 |
| 278 | #define PCM_LR_IN_REMOTE 0x0004 |
| 279 | #define PCM_LR_RESERVED 0x0008 |
| 280 | #define PCM_LR_IN_BOTH 0x000C |
| 281 | #define LINE1_ADC_IN_LOCAL 0x0000 |
| 282 | #define LINE1_ADC_IN_REMOTE 0x0010 |
| 283 | #define LINE1_ADC_IN_MUTE 0x0020 |
| 284 | #define MIC_ADC_IN_LOCAL 0x0000 |
| 285 | #define MIC_ADC_IN_REMOTE 0x0040 |
| 286 | #define MIC_ADC_IN_MUTE 0x0080 |
| 287 | #define LINE2_DAC_IN_LOCAL 0x0000 |
| 288 | #define LINE2_DAC_IN_REMOTE 0x0400 |
| 289 | #define LINE2_DAC_IN_MUTE 0x0800 |
| 290 | #define HANDSET_IN_LOCAL 0x0000 |
| 291 | #define HANDSET_IN_REMOTE 0x1000 |
| 292 | #define HANDSET_IN_MUTE 0x2000 |
| 293 | #define IO_STATUS_IN_LOCAL 0x0000 |
| 294 | #define IO_STATUS_IN_REMOTE 0x4000 |
| 295 | |
| 296 | #define SPDIF_IN_CTRL 0x3E |
| 297 | #define SPDIF_IN_ENABLE 0x0001 |
| 298 | |
| 299 | #define GPIO_DATA 0x60 |
| 300 | #define GPIO_DATA_MASK 0x0FFF |
| 301 | #define GPIO_HV_STATUS 0x3000 |
| 302 | #define GPIO_PME_STATUS 0x4000 |
| 303 | |
| 304 | #define GPIO_MASK 0x64 |
| 305 | #define GPIO_DIRECTION 0x68 |
| 306 | #define GPO_PRIMARY_AC97 0x0001 |
| 307 | #define GPI_LINEOUT_SENSE 0x0004 |
| 308 | #define GPO_SECONDARY_AC97 0x0008 |
| 309 | #define GPI_VOL_DOWN 0x0010 |
| 310 | #define GPI_VOL_UP 0x0020 |
| 311 | #define GPI_IIS_CLK 0x0040 |
| 312 | #define GPI_IIS_LRCLK 0x0080 |
| 313 | #define GPI_IIS_DATA 0x0100 |
| 314 | #define GPI_DOCKING_STATUS 0x0100 |
| 315 | #define GPI_HEADPHONE_SENSE 0x0200 |
| 316 | #define GPO_EXT_AMP_SHUTDOWN 0x1000 |
| 317 | |
| 318 | #define GPO_EXT_AMP_M3 1 /* default m3 amp */ |
| 319 | #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */ |
| 320 | |
| 321 | /* M3 */ |
| 322 | #define GPO_M3_EXT_AMP_SHUTDN 0x0002 |
| 323 | |
| 324 | #define ASSP_INDEX_PORT 0x80 |
| 325 | #define ASSP_MEMORY_PORT 0x82 |
| 326 | #define ASSP_DATA_PORT 0x84 |
| 327 | |
| 328 | #define MPU401_DATA_PORT 0x98 |
| 329 | #define MPU401_STATUS_PORT 0x99 |
| 330 | |
| 331 | #define CLK_MULT_DATA_PORT 0x9C |
| 332 | |
| 333 | #define ASSP_CONTROL_A 0xA2 |
| 334 | #define ASSP_0_WS_ENABLE 0x01 |
| 335 | #define ASSP_CTRL_A_RESERVED1 0x02 |
| 336 | #define ASSP_CTRL_A_RESERVED2 0x04 |
| 337 | #define ASSP_CLK_49MHZ_SELECT 0x08 |
| 338 | #define FAST_PLU_ENABLE 0x10 |
| 339 | #define ASSP_CTRL_A_RESERVED3 0x20 |
| 340 | #define DSP_CLK_36MHZ_SELECT 0x40 |
| 341 | |
| 342 | #define ASSP_CONTROL_B 0xA4 |
| 343 | #define RESET_ASSP 0x00 |
| 344 | #define RUN_ASSP 0x01 |
| 345 | #define ENABLE_ASSP_CLOCK 0x00 |
| 346 | #define STOP_ASSP_CLOCK 0x10 |
| 347 | #define RESET_TOGGLE 0x40 |
| 348 | |
| 349 | #define ASSP_CONTROL_C 0xA6 |
| 350 | #define ASSP_HOST_INT_ENABLE 0x01 |
| 351 | #define FM_ADDR_REMAP_DISABLE 0x02 |
| 352 | #define HOST_WRITE_PORT_ENABLE 0x08 |
| 353 | |
| 354 | #define ASSP_HOST_INT_STATUS 0xAC |
| 355 | #define DSP2HOST_REQ_PIORECORD 0x01 |
| 356 | #define DSP2HOST_REQ_I2SRATE 0x02 |
| 357 | #define DSP2HOST_REQ_TIMER 0x04 |
| 358 | |
| 359 | /* AC97 registers */ |
| 360 | /* XXX fix this crap up */ |
| 361 | /*#define AC97_RESET 0x00*/ |
| 362 | |
| 363 | #define AC97_VOL_MUTE_B 0x8000 |
| 364 | #define AC97_VOL_M 0x1F |
| 365 | #define AC97_LEFT_VOL_S 8 |
| 366 | |
| 367 | #define AC97_MASTER_VOL 0x02 |
| 368 | #define AC97_LINE_LEVEL_VOL 0x04 |
| 369 | #define AC97_MASTER_MONO_VOL 0x06 |
| 370 | #define AC97_PC_BEEP_VOL 0x0A |
| 371 | #define AC97_PC_BEEP_VOL_M 0x0F |
| 372 | #define AC97_SROUND_MASTER_VOL 0x38 |
| 373 | #define AC97_PC_BEEP_VOL_S 1 |
| 374 | |
| 375 | /*#define AC97_PHONE_VOL 0x0C |
| 376 | #define AC97_MIC_VOL 0x0E*/ |
| 377 | #define AC97_MIC_20DB_ENABLE 0x40 |
| 378 | |
| 379 | /*#define AC97_LINEIN_VOL 0x10 |
| 380 | #define AC97_CD_VOL 0x12 |
| 381 | #define AC97_VIDEO_VOL 0x14 |
| 382 | #define AC97_AUX_VOL 0x16*/ |
| 383 | #define AC97_PCM_OUT_VOL 0x18 |
| 384 | /*#define AC97_RECORD_SELECT 0x1A*/ |
| 385 | #define AC97_RECORD_MIC 0x00 |
| 386 | #define AC97_RECORD_CD 0x01 |
| 387 | #define AC97_RECORD_VIDEO 0x02 |
| 388 | #define AC97_RECORD_AUX 0x03 |
| 389 | #define AC97_RECORD_MONO_MUX 0x02 |
| 390 | #define AC97_RECORD_DIGITAL 0x03 |
| 391 | #define AC97_RECORD_LINE 0x04 |
| 392 | #define AC97_RECORD_STEREO 0x05 |
| 393 | #define AC97_RECORD_MONO 0x06 |
| 394 | #define AC97_RECORD_PHONE 0x07 |
| 395 | |
| 396 | /*#define AC97_RECORD_GAIN 0x1C*/ |
| 397 | #define AC97_RECORD_VOL_M 0x0F |
| 398 | |
| 399 | /*#define AC97_GENERAL_PURPOSE 0x20*/ |
| 400 | #define AC97_POWER_DOWN_CTRL 0x26 |
| 401 | #define AC97_ADC_READY 0x0001 |
| 402 | #define AC97_DAC_READY 0x0002 |
| 403 | #define AC97_ANALOG_READY 0x0004 |
| 404 | #define AC97_VREF_ON 0x0008 |
| 405 | #define AC97_PR0 0x0100 |
| 406 | #define AC97_PR1 0x0200 |
| 407 | #define AC97_PR2 0x0400 |
| 408 | #define AC97_PR3 0x0800 |
| 409 | #define AC97_PR4 0x1000 |
| 410 | |
| 411 | #define AC97_RESERVED1 0x28 |
| 412 | |
| 413 | #define AC97_VENDOR_TEST 0x5A |
| 414 | |
| 415 | #define AC97_CLOCK_DELAY 0x5C |
| 416 | #define AC97_LINEOUT_MUX_SEL 0x0001 |
| 417 | #define AC97_MONO_MUX_SEL 0x0002 |
| 418 | #define AC97_CLOCK_DELAY_SEL 0x1F |
| 419 | #define AC97_DAC_CDS_SHIFT 6 |
| 420 | #define AC97_ADC_CDS_SHIFT 11 |
| 421 | |
| 422 | #define AC97_MULTI_CHANNEL_SEL 0x74 |
| 423 | |
| 424 | /*#define AC97_VENDOR_ID1 0x7C |
| 425 | #define AC97_VENDOR_ID2 0x7E*/ |
| 426 | |
| 427 | /* |
| 428 | * ASSP control regs |
| 429 | */ |
| 430 | #define DSP_PORT_TIMER_COUNT 0x06 |
| 431 | |
| 432 | #define DSP_PORT_MEMORY_INDEX 0x80 |
| 433 | |
| 434 | #define DSP_PORT_MEMORY_TYPE 0x82 |
| 435 | #define MEMTYPE_INTERNAL_CODE 0x0002 |
| 436 | #define MEMTYPE_INTERNAL_DATA 0x0003 |
| 437 | #define MEMTYPE_MASK 0x0003 |
| 438 | |
| 439 | #define DSP_PORT_MEMORY_DATA 0x84 |
| 440 | |
| 441 | #define DSP_PORT_CONTROL_REG_A 0xA2 |
| 442 | #define DSP_PORT_CONTROL_REG_B 0xA4 |
| 443 | #define DSP_PORT_CONTROL_REG_C 0xA6 |
| 444 | |
| 445 | #define REV_A_CODE_MEMORY_BEGIN 0x0000 |
| 446 | #define REV_A_CODE_MEMORY_END 0x0FFF |
| 447 | #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 |
| 448 | #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) |
| 449 | |
| 450 | #define REV_B_CODE_MEMORY_BEGIN 0x0000 |
| 451 | #define REV_B_CODE_MEMORY_END 0x0BFF |
| 452 | #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 |
| 453 | #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) |
| 454 | |
| 455 | #define REV_A_DATA_MEMORY_BEGIN 0x1000 |
| 456 | #define REV_A_DATA_MEMORY_END 0x2FFF |
| 457 | #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 |
| 458 | #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) |
| 459 | |
| 460 | #define REV_B_DATA_MEMORY_BEGIN 0x1000 |
| 461 | #define REV_B_DATA_MEMORY_END 0x2BFF |
| 462 | #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 |
| 463 | #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) |
| 464 | |
| 465 | |
| 466 | #define NUM_UNITS_KERNEL_CODE 16 |
| 467 | #define NUM_UNITS_KERNEL_DATA 2 |
| 468 | |
| 469 | #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 |
| 470 | #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 |
| 471 | |
| 472 | /* |
| 473 | * Kernel data layout |
| 474 | */ |
| 475 | |
| 476 | #define DP_SHIFT_COUNT 7 |
| 477 | |
| 478 | #define KDATA_BASE_ADDR 0x1000 |
| 479 | #define KDATA_BASE_ADDR2 0x1080 |
| 480 | |
| 481 | #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) |
| 482 | #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) |
| 483 | #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) |
| 484 | #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) |
| 485 | #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) |
| 486 | #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) |
| 487 | #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) |
| 488 | #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) |
| 489 | #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) |
| 490 | |
| 491 | #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) |
| 492 | #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) |
| 493 | |
| 494 | #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) |
| 495 | #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) |
| 496 | #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) |
| 497 | #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) |
| 498 | #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) |
| 499 | #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) |
| 500 | #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) |
| 501 | #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) |
| 502 | #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) |
| 503 | #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) |
| 504 | |
| 505 | #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) |
| 506 | #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) |
| 507 | |
| 508 | #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) |
| 509 | #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) |
| 510 | |
| 511 | #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) |
| 512 | #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) |
| 513 | |
| 514 | #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) |
| 515 | #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) |
| 516 | #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) |
| 517 | |
| 518 | #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) |
| 519 | #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) |
| 520 | #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) |
| 521 | #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) |
| 522 | #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) |
| 523 | |
| 524 | #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) |
| 525 | #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) |
| 526 | #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) |
| 527 | |
| 528 | #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) |
| 529 | #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) |
| 530 | #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) |
| 531 | |
| 532 | #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) |
| 533 | #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) |
| 534 | #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) |
| 535 | #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) |
| 536 | #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) |
| 537 | #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) |
| 538 | #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) |
| 539 | #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) |
| 540 | #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) |
| 541 | #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) |
| 542 | |
| 543 | #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) |
| 544 | #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) |
| 545 | #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) |
| 546 | |
| 547 | #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) |
| 548 | #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) |
| 549 | |
| 550 | #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) |
| 551 | #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) |
| 552 | #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) |
| 553 | |
| 554 | #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) |
| 555 | #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) |
| 556 | #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) |
| 557 | #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) |
| 558 | #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) |
| 559 | #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) |
| 560 | |
| 561 | #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) |
| 562 | #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) |
| 563 | #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) |
| 564 | #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) |
| 565 | #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) |
| 566 | #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) |
| 567 | |
| 568 | #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) |
| 569 | #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) |
| 570 | #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) |
| 571 | #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) |
| 572 | #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) |
| 573 | #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) |
| 574 | |
| 575 | #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) |
| 576 | #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) |
| 577 | #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) |
| 578 | #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) |
| 579 | |
| 580 | #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) |
| 581 | #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) |
| 582 | |
| 583 | #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) |
| 584 | #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) |
| 585 | |
| 586 | #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) |
| 587 | #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) |
| 588 | #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) |
| 589 | #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) |
| 590 | #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) |
| 591 | |
| 592 | #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) |
| 593 | #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) |
| 594 | |
| 595 | #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) |
| 596 | #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) |
| 597 | #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) |
| 598 | |
| 599 | #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) |
| 600 | #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) |
| 601 | |
| 602 | #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) |
| 603 | |
| 604 | #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) |
| 605 | #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) |
| 606 | #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) |
| 607 | #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) |
| 608 | #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) |
| 609 | #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) |
| 610 | #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) |
| 611 | #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) |
| 612 | #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) |
| 613 | #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) |
| 614 | #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) |
| 615 | #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) |
| 616 | |
| 617 | #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) |
| 618 | #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) |
| 619 | #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) |
| 620 | #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) |
| 621 | |
| 622 | #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) |
| 623 | #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) |
| 624 | |
| 625 | #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) |
| 626 | #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) |
| 627 | #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) |
| 628 | #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) |
| 629 | |
| 630 | #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) |
| 631 | #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) |
| 632 | #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) |
| 633 | #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) |
| 634 | #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) |
| 635 | |
| 636 | /* |
| 637 | * second 'segment' (?) reserved for mixer |
| 638 | * buffers.. |
| 639 | */ |
| 640 | |
| 641 | #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) |
| 642 | #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) |
| 643 | #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) |
| 644 | #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) |
| 645 | #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) |
| 646 | #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) |
| 647 | #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) |
| 648 | #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) |
| 649 | #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) |
| 650 | #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) |
| 651 | #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) |
| 652 | #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) |
| 653 | #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) |
| 654 | #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) |
| 655 | #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) |
| 656 | #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) |
| 657 | |
| 658 | #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) |
| 659 | #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) |
| 660 | #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) |
| 661 | #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) |
| 662 | #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) |
| 663 | #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) |
| 664 | #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) |
| 665 | #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) |
| 666 | #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) |
| 667 | #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) |
| 668 | #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) |
| 669 | |
| 670 | #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) |
| 671 | #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) |
| 672 | #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) |
| 673 | #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) |
| 674 | #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) |
| 675 | #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) |
| 676 | |
| 677 | #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC) |
| 678 | #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0) |
| 679 | #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0) |
| 680 | #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0) |
| 681 | |
| 682 | /* |
| 683 | * client data area offsets |
| 684 | */ |
| 685 | #define CDATA_INSTANCE_READY 0x00 |
| 686 | |
| 687 | #define CDATA_HOST_SRC_ADDRL 0x01 |
| 688 | #define CDATA_HOST_SRC_ADDRH 0x02 |
| 689 | #define CDATA_HOST_SRC_END_PLUS_1L 0x03 |
| 690 | #define CDATA_HOST_SRC_END_PLUS_1H 0x04 |
| 691 | #define CDATA_HOST_SRC_CURRENTL 0x05 |
| 692 | #define CDATA_HOST_SRC_CURRENTH 0x06 |
| 693 | |
| 694 | #define CDATA_IN_BUF_CONNECT 0x07 |
| 695 | #define CDATA_OUT_BUF_CONNECT 0x08 |
| 696 | |
| 697 | #define CDATA_IN_BUF_BEGIN 0x09 |
| 698 | #define CDATA_IN_BUF_END_PLUS_1 0x0A |
| 699 | #define CDATA_IN_BUF_HEAD 0x0B |
| 700 | #define CDATA_IN_BUF_TAIL 0x0C |
| 701 | #define CDATA_OUT_BUF_BEGIN 0x0D |
| 702 | #define CDATA_OUT_BUF_END_PLUS_1 0x0E |
| 703 | #define CDATA_OUT_BUF_HEAD 0x0F |
| 704 | #define CDATA_OUT_BUF_TAIL 0x10 |
| 705 | |
| 706 | #define CDATA_DMA_CONTROL 0x11 |
| 707 | #define CDATA_RESERVED 0x12 |
| 708 | |
| 709 | #define CDATA_FREQUENCY 0x13 |
| 710 | #define CDATA_LEFT_VOLUME 0x14 |
| 711 | #define CDATA_RIGHT_VOLUME 0x15 |
| 712 | #define CDATA_LEFT_SUR_VOL 0x16 |
| 713 | #define CDATA_RIGHT_SUR_VOL 0x17 |
| 714 | |
| 715 | #define CDATA_HEADER_LEN 0x18 |
| 716 | |
| 717 | #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN |
| 718 | #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1) |
| 719 | #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2) |
| 720 | #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3) |
| 721 | #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8) |
| 722 | #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10) |
| 723 | #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16) |
| 724 | #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17) |
| 725 | |
| 726 | #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) |
| 727 | #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) |
| 728 | #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) |
| 729 | #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) |
| 730 | #define MINISRC_BIQUAD_STAGE 2 |
| 731 | #define MINISRC_COEF_LOC 0x175 |
| 732 | |
| 733 | #define DMACONTROL_BLOCK_MASK 0x000F |
| 734 | #define DMAC_BLOCK0_SELECTOR 0x0000 |
| 735 | #define DMAC_BLOCK1_SELECTOR 0x0001 |
| 736 | #define DMAC_BLOCK2_SELECTOR 0x0002 |
| 737 | #define DMAC_BLOCK3_SELECTOR 0x0003 |
| 738 | #define DMAC_BLOCK4_SELECTOR 0x0004 |
| 739 | #define DMAC_BLOCK5_SELECTOR 0x0005 |
| 740 | #define DMAC_BLOCK6_SELECTOR 0x0006 |
| 741 | #define DMAC_BLOCK7_SELECTOR 0x0007 |
| 742 | #define DMAC_BLOCK8_SELECTOR 0x0008 |
| 743 | #define DMAC_BLOCK9_SELECTOR 0x0009 |
| 744 | #define DMAC_BLOCKA_SELECTOR 0x000A |
| 745 | #define DMAC_BLOCKB_SELECTOR 0x000B |
| 746 | #define DMAC_BLOCKC_SELECTOR 0x000C |
| 747 | #define DMAC_BLOCKD_SELECTOR 0x000D |
| 748 | #define DMAC_BLOCKE_SELECTOR 0x000E |
| 749 | #define DMAC_BLOCKF_SELECTOR 0x000F |
| 750 | #define DMACONTROL_PAGE_MASK 0x00F0 |
| 751 | #define DMAC_PAGE0_SELECTOR 0x0030 |
| 752 | #define DMAC_PAGE1_SELECTOR 0x0020 |
| 753 | #define DMAC_PAGE2_SELECTOR 0x0010 |
| 754 | #define DMAC_PAGE3_SELECTOR 0x0000 |
| 755 | #define DMACONTROL_AUTOREPEAT 0x1000 |
| 756 | #define DMACONTROL_STOPPED 0x2000 |
| 757 | #define DMACONTROL_DIRECTION 0x0100 |
| 758 | |
| 759 | /* |
| 760 | * an arbitrary volume we set the internal |
| 761 | * volume settings to so that the ac97 volume |
| 762 | * range is a little less insane. 0x7fff is |
| 763 | * max. |
| 764 | */ |
| 765 | #define ARB_VOLUME ( 0x6800 ) |
| 766 | |
| 767 | /* |
| 768 | */ |
| 769 | |
| 770 | typedef struct snd_m3_dma m3_dma_t; |
| 771 | typedef struct snd_m3 m3_t; |
| 772 | |
| 773 | /* quirk lists */ |
| 774 | struct m3_quirk { |
| 775 | const char *name; /* device name */ |
| 776 | u16 vendor, device; /* subsystem ids */ |
| 777 | int amp_gpio; /* gpio pin # for external amp, -1 = default */ |
| 778 | int irda_workaround; /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION |
| 779 | (e.g. for IrDA on Dell Inspirons) */ |
| 780 | }; |
| 781 | |
| 782 | struct m3_list { |
| 783 | int curlen; |
| 784 | int mem_addr; |
| 785 | int max; |
| 786 | }; |
| 787 | |
| 788 | struct snd_m3_dma { |
| 789 | |
| 790 | int number; |
| 791 | m3_t *chip; |
| 792 | snd_pcm_substream_t *substream; |
| 793 | |
| 794 | struct assp_instance { |
| 795 | unsigned short code, data; |
| 796 | } inst; |
| 797 | |
| 798 | int running; |
| 799 | int opened; |
| 800 | |
| 801 | unsigned long buffer_addr; |
| 802 | int dma_size; |
| 803 | int period_size; |
| 804 | unsigned int hwptr; |
| 805 | int count; |
| 806 | |
| 807 | int index[3]; |
| 808 | struct m3_list *index_list[3]; |
| 809 | |
| 810 | int in_lists; |
| 811 | |
| 812 | struct list_head list; |
| 813 | |
| 814 | }; |
| 815 | |
| 816 | struct snd_m3 { |
| 817 | |
| 818 | snd_card_t *card; |
| 819 | |
| 820 | unsigned long iobase; |
| 821 | |
| 822 | int irq; |
| 823 | unsigned int allegro_flag : 1; |
| 824 | |
| 825 | ac97_t *ac97; |
| 826 | |
| 827 | snd_pcm_t *pcm; |
| 828 | |
| 829 | struct pci_dev *pci; |
| 830 | struct m3_quirk *quirk; |
| 831 | |
| 832 | int dacs_active; |
| 833 | int timer_users; |
| 834 | |
| 835 | struct m3_list msrc_list; |
| 836 | struct m3_list mixer_list; |
| 837 | struct m3_list adc1_list; |
| 838 | struct m3_list dma_list; |
| 839 | |
| 840 | /* for storing reset state..*/ |
| 841 | u8 reset_state; |
| 842 | |
| 843 | int external_amp; |
| 844 | int amp_gpio; |
| 845 | |
| 846 | /* midi */ |
| 847 | snd_rawmidi_t *rmidi; |
| 848 | |
| 849 | /* pcm streams */ |
| 850 | int num_substreams; |
| 851 | m3_dma_t *substreams; |
| 852 | |
| 853 | spinlock_t reg_lock; |
| 854 | |
| 855 | #ifdef CONFIG_PM |
| 856 | u16 *suspend_mem; |
| 857 | #endif |
| 858 | }; |
| 859 | |
| 860 | /* |
| 861 | * pci ids |
| 862 | */ |
| 863 | |
| 864 | #ifndef PCI_VENDOR_ID_ESS |
| 865 | #define PCI_VENDOR_ID_ESS 0x125D |
| 866 | #endif |
| 867 | #ifndef PCI_DEVICE_ID_ESS_ALLEGRO_1 |
| 868 | #define PCI_DEVICE_ID_ESS_ALLEGRO_1 0x1988 |
| 869 | #endif |
| 870 | #ifndef PCI_DEVICE_ID_ESS_ALLEGRO |
| 871 | #define PCI_DEVICE_ID_ESS_ALLEGRO 0x1989 |
| 872 | #endif |
| 873 | #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2LE |
| 874 | #define PCI_DEVICE_ID_ESS_CANYON3D_2LE 0x1990 |
| 875 | #endif |
| 876 | #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2 |
| 877 | #define PCI_DEVICE_ID_ESS_CANYON3D_2 0x1992 |
| 878 | #endif |
| 879 | #ifndef PCI_DEVICE_ID_ESS_MAESTRO3 |
| 880 | #define PCI_DEVICE_ID_ESS_MAESTRO3 0x1998 |
| 881 | #endif |
| 882 | #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_1 |
| 883 | #define PCI_DEVICE_ID_ESS_MAESTRO3_1 0x1999 |
| 884 | #endif |
| 885 | #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_HW |
| 886 | #define PCI_DEVICE_ID_ESS_MAESTRO3_HW 0x199a |
| 887 | #endif |
| 888 | #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_2 |
| 889 | #define PCI_DEVICE_ID_ESS_MAESTRO3_2 0x199b |
| 890 | #endif |
| 891 | |
| 892 | static struct pci_device_id snd_m3_ids[] = { |
| 893 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID, |
| 894 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
| 895 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID, |
| 896 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
| 897 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID, |
| 898 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
| 899 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID, |
| 900 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
| 901 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID, |
| 902 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
| 903 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID, |
| 904 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
| 905 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID, |
| 906 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
| 907 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID, |
| 908 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
| 909 | {0,}, |
| 910 | }; |
| 911 | |
| 912 | MODULE_DEVICE_TABLE(pci, snd_m3_ids); |
| 913 | |
| 914 | static struct m3_quirk m3_quirk_list[] = { |
| 915 | /* panasonic CF-28 "toughbook" */ |
| 916 | { |
| 917 | .name = "Panasonic CF-28", |
| 918 | .vendor = 0x10f7, |
| 919 | .device = 0x833e, |
| 920 | .amp_gpio = 0x0d, |
| 921 | }, |
| 922 | /* panasonic CF-72 "toughbook" */ |
| 923 | { |
| 924 | .name = "Panasonic CF-72", |
| 925 | .vendor = 0x10f7, |
| 926 | .device = 0x833d, |
| 927 | .amp_gpio = 0x0d, |
| 928 | }, |
| 929 | /* Dell Inspiron 4000 */ |
| 930 | { |
| 931 | .name = "Dell Inspiron 4000", |
| 932 | .vendor = 0x1028, |
| 933 | .device = 0x00b0, |
| 934 | .amp_gpio = -1, |
| 935 | .irda_workaround = 1, |
| 936 | }, |
| 937 | /* Dell Inspiron 8000 */ |
| 938 | { |
| 939 | .name = "Dell Inspiron 8000", |
| 940 | .vendor = 0x1028, |
| 941 | .device = 0x00a4, |
| 942 | .amp_gpio = -1, |
| 943 | .irda_workaround = 1, |
| 944 | }, |
| 945 | /* Dell Inspiron 8100 */ |
| 946 | { |
| 947 | .name = "Dell Inspiron 8100", |
| 948 | .vendor = 0x1028, |
| 949 | .device = 0x00e6, |
| 950 | .amp_gpio = -1, |
| 951 | .irda_workaround = 1, |
| 952 | }, |
| 953 | /* NEC LM800J/7 */ |
| 954 | { |
| 955 | .name = "NEC LM800J/7", |
| 956 | .vendor = 0x1033, |
| 957 | .device = 0x80f1, |
| 958 | .amp_gpio = 0x03, |
| 959 | }, |
| 960 | /* LEGEND ZhaoYang 3100CF */ |
| 961 | { |
| 962 | .name = "LEGEND ZhaoYang 3100CF", |
| 963 | .vendor = 0x1509, |
| 964 | .device = 0x1740, |
| 965 | .amp_gpio = 0x03, |
| 966 | }, |
| 967 | /* END */ |
| 968 | { NULL } |
| 969 | }; |
| 970 | |
| 971 | |
| 972 | /* |
| 973 | * lowlevel functions |
| 974 | */ |
| 975 | |
| 976 | #define big_mdelay(msec) do {\ |
| 977 | set_current_state(TASK_UNINTERRUPTIBLE);\ |
| 978 | schedule_timeout(((msec) * HZ) / 1000);\ |
| 979 | } while (0) |
| 980 | |
| 981 | inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg) |
| 982 | { |
| 983 | outw(value, chip->iobase + reg); |
| 984 | } |
| 985 | |
| 986 | inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg) |
| 987 | { |
| 988 | return inw(chip->iobase + reg); |
| 989 | } |
| 990 | |
| 991 | inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg) |
| 992 | { |
| 993 | outb(value, chip->iobase + reg); |
| 994 | } |
| 995 | |
| 996 | inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg) |
| 997 | { |
| 998 | return inb(chip->iobase + reg); |
| 999 | } |
| 1000 | |
| 1001 | /* |
| 1002 | * access 16bit words to the code or data regions of the dsp's memory. |
| 1003 | * index addresses 16bit words. |
| 1004 | */ |
| 1005 | static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index) |
| 1006 | { |
| 1007 | snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); |
| 1008 | snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); |
| 1009 | return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA); |
| 1010 | } |
| 1011 | |
| 1012 | static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data) |
| 1013 | { |
| 1014 | snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); |
| 1015 | snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); |
| 1016 | snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA); |
| 1017 | } |
| 1018 | |
| 1019 | static void snd_m3_assp_halt(m3_t *chip) |
| 1020 | { |
| 1021 | chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK; |
| 1022 | big_mdelay(10); |
| 1023 | snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); |
| 1024 | } |
| 1025 | |
| 1026 | static void snd_m3_assp_continue(m3_t *chip) |
| 1027 | { |
| 1028 | snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); |
| 1029 | } |
| 1030 | |
| 1031 | |
| 1032 | /* |
| 1033 | * This makes me sad. the maestro3 has lists |
| 1034 | * internally that must be packed.. 0 terminates, |
| 1035 | * apparently, or maybe all unused entries have |
| 1036 | * to be 0, the lists have static lengths set |
| 1037 | * by the binary code images. |
| 1038 | */ |
| 1039 | |
| 1040 | static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val) |
| 1041 | { |
| 1042 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1043 | list->mem_addr + list->curlen, |
| 1044 | val); |
| 1045 | return list->curlen++; |
| 1046 | } |
| 1047 | |
| 1048 | static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index) |
| 1049 | { |
| 1050 | u16 val; |
| 1051 | int lastindex = list->curlen - 1; |
| 1052 | |
| 1053 | if (index != lastindex) { |
| 1054 | val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, |
| 1055 | list->mem_addr + lastindex); |
| 1056 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1057 | list->mem_addr + index, |
| 1058 | val); |
| 1059 | } |
| 1060 | |
| 1061 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1062 | list->mem_addr + lastindex, |
| 1063 | 0); |
| 1064 | |
| 1065 | list->curlen--; |
| 1066 | } |
| 1067 | |
| 1068 | static void snd_m3_inc_timer_users(m3_t *chip) |
| 1069 | { |
| 1070 | chip->timer_users++; |
| 1071 | if (chip->timer_users != 1) |
| 1072 | return; |
| 1073 | |
| 1074 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1075 | KDATA_TIMER_COUNT_RELOAD, |
| 1076 | 240); |
| 1077 | |
| 1078 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1079 | KDATA_TIMER_COUNT_CURRENT, |
| 1080 | 240); |
| 1081 | |
| 1082 | snd_m3_outw(chip, |
| 1083 | snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE, |
| 1084 | HOST_INT_CTRL); |
| 1085 | } |
| 1086 | |
| 1087 | static void snd_m3_dec_timer_users(m3_t *chip) |
| 1088 | { |
| 1089 | chip->timer_users--; |
| 1090 | if (chip->timer_users > 0) |
| 1091 | return; |
| 1092 | |
| 1093 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1094 | KDATA_TIMER_COUNT_RELOAD, |
| 1095 | 0); |
| 1096 | |
| 1097 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1098 | KDATA_TIMER_COUNT_CURRENT, |
| 1099 | 0); |
| 1100 | |
| 1101 | snd_m3_outw(chip, |
| 1102 | snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE, |
| 1103 | HOST_INT_CTRL); |
| 1104 | } |
| 1105 | |
| 1106 | /* |
| 1107 | * start/stop |
| 1108 | */ |
| 1109 | |
| 1110 | /* spinlock held! */ |
| 1111 | static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) |
| 1112 | { |
| 1113 | if (! s || ! subs) |
| 1114 | return -EINVAL; |
| 1115 | |
| 1116 | snd_m3_inc_timer_users(chip); |
| 1117 | switch (subs->stream) { |
| 1118 | case SNDRV_PCM_STREAM_PLAYBACK: |
| 1119 | chip->dacs_active++; |
| 1120 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1121 | s->inst.data + CDATA_INSTANCE_READY, 1); |
| 1122 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1123 | KDATA_MIXER_TASK_NUMBER, |
| 1124 | chip->dacs_active); |
| 1125 | break; |
| 1126 | case SNDRV_PCM_STREAM_CAPTURE: |
| 1127 | snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA, |
| 1128 | KDATA_ADC1_REQUEST, 1); |
| 1129 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1130 | s->inst.data + CDATA_INSTANCE_READY, 1); |
| 1131 | break; |
| 1132 | } |
| 1133 | return 0; |
| 1134 | } |
| 1135 | |
| 1136 | /* spinlock held! */ |
| 1137 | static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) |
| 1138 | { |
| 1139 | if (! s || ! subs) |
| 1140 | return -EINVAL; |
| 1141 | |
| 1142 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1143 | s->inst.data + CDATA_INSTANCE_READY, 0); |
| 1144 | snd_m3_dec_timer_users(chip); |
| 1145 | switch (subs->stream) { |
| 1146 | case SNDRV_PCM_STREAM_PLAYBACK: |
| 1147 | chip->dacs_active--; |
| 1148 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1149 | KDATA_MIXER_TASK_NUMBER, |
| 1150 | chip->dacs_active); |
| 1151 | break; |
| 1152 | case SNDRV_PCM_STREAM_CAPTURE: |
| 1153 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1154 | KDATA_ADC1_REQUEST, 0); |
| 1155 | break; |
| 1156 | } |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
| 1160 | static int |
| 1161 | snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd) |
| 1162 | { |
| 1163 | m3_t *chip = snd_pcm_substream_chip(subs); |
| 1164 | m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data; |
| 1165 | int err = -EINVAL; |
| 1166 | |
| 1167 | snd_assert(s != NULL, return -ENXIO); |
| 1168 | |
| 1169 | spin_lock(&chip->reg_lock); |
| 1170 | switch (cmd) { |
| 1171 | case SNDRV_PCM_TRIGGER_START: |
| 1172 | case SNDRV_PCM_TRIGGER_RESUME: |
| 1173 | if (s->running) |
| 1174 | err = -EBUSY; |
| 1175 | else { |
| 1176 | s->running = 1; |
| 1177 | err = snd_m3_pcm_start(chip, s, subs); |
| 1178 | } |
| 1179 | break; |
| 1180 | case SNDRV_PCM_TRIGGER_STOP: |
| 1181 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 1182 | if (! s->running) |
| 1183 | err = 0; /* should return error? */ |
| 1184 | else { |
| 1185 | s->running = 0; |
| 1186 | err = snd_m3_pcm_stop(chip, s, subs); |
| 1187 | } |
| 1188 | break; |
| 1189 | } |
| 1190 | spin_unlock(&chip->reg_lock); |
| 1191 | return err; |
| 1192 | } |
| 1193 | |
| 1194 | /* |
| 1195 | * setup |
| 1196 | */ |
| 1197 | static void |
| 1198 | snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) |
| 1199 | { |
| 1200 | int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer; |
| 1201 | snd_pcm_runtime_t *runtime = subs->runtime; |
| 1202 | |
| 1203 | if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 1204 | dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); |
| 1205 | dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); |
| 1206 | } else { |
| 1207 | dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2); |
| 1208 | dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); |
| 1209 | } |
| 1210 | dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2); |
| 1211 | dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1; |
| 1212 | |
| 1213 | s->dma_size = frames_to_bytes(runtime, runtime->buffer_size); |
| 1214 | s->period_size = frames_to_bytes(runtime, runtime->period_size); |
| 1215 | s->hwptr = 0; |
| 1216 | s->count = 0; |
| 1217 | |
| 1218 | #define LO(x) ((x) & 0xffff) |
| 1219 | #define HI(x) LO((x) >> 16) |
| 1220 | |
| 1221 | /* host dma buffer pointers */ |
| 1222 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1223 | s->inst.data + CDATA_HOST_SRC_ADDRL, |
| 1224 | LO(s->buffer_addr)); |
| 1225 | |
| 1226 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1227 | s->inst.data + CDATA_HOST_SRC_ADDRH, |
| 1228 | HI(s->buffer_addr)); |
| 1229 | |
| 1230 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1231 | s->inst.data + CDATA_HOST_SRC_END_PLUS_1L, |
| 1232 | LO(s->buffer_addr + s->dma_size)); |
| 1233 | |
| 1234 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1235 | s->inst.data + CDATA_HOST_SRC_END_PLUS_1H, |
| 1236 | HI(s->buffer_addr + s->dma_size)); |
| 1237 | |
| 1238 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1239 | s->inst.data + CDATA_HOST_SRC_CURRENTL, |
| 1240 | LO(s->buffer_addr)); |
| 1241 | |
| 1242 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1243 | s->inst.data + CDATA_HOST_SRC_CURRENTH, |
| 1244 | HI(s->buffer_addr)); |
| 1245 | #undef LO |
| 1246 | #undef HI |
| 1247 | |
| 1248 | /* dsp buffers */ |
| 1249 | |
| 1250 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1251 | s->inst.data + CDATA_IN_BUF_BEGIN, |
| 1252 | dsp_in_buffer); |
| 1253 | |
| 1254 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1255 | s->inst.data + CDATA_IN_BUF_END_PLUS_1, |
| 1256 | dsp_in_buffer + (dsp_in_size / 2)); |
| 1257 | |
| 1258 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1259 | s->inst.data + CDATA_IN_BUF_HEAD, |
| 1260 | dsp_in_buffer); |
| 1261 | |
| 1262 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1263 | s->inst.data + CDATA_IN_BUF_TAIL, |
| 1264 | dsp_in_buffer); |
| 1265 | |
| 1266 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1267 | s->inst.data + CDATA_OUT_BUF_BEGIN, |
| 1268 | dsp_out_buffer); |
| 1269 | |
| 1270 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1271 | s->inst.data + CDATA_OUT_BUF_END_PLUS_1, |
| 1272 | dsp_out_buffer + (dsp_out_size / 2)); |
| 1273 | |
| 1274 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1275 | s->inst.data + CDATA_OUT_BUF_HEAD, |
| 1276 | dsp_out_buffer); |
| 1277 | |
| 1278 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1279 | s->inst.data + CDATA_OUT_BUF_TAIL, |
| 1280 | dsp_out_buffer); |
| 1281 | } |
| 1282 | |
| 1283 | static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime) |
| 1284 | { |
| 1285 | u32 freq; |
| 1286 | |
| 1287 | /* |
| 1288 | * put us in the lists if we're not already there |
| 1289 | */ |
| 1290 | if (! s->in_lists) { |
| 1291 | s->index[0] = snd_m3_add_list(chip, s->index_list[0], |
| 1292 | s->inst.data >> DP_SHIFT_COUNT); |
| 1293 | s->index[1] = snd_m3_add_list(chip, s->index_list[1], |
| 1294 | s->inst.data >> DP_SHIFT_COUNT); |
| 1295 | s->index[2] = snd_m3_add_list(chip, s->index_list[2], |
| 1296 | s->inst.data >> DP_SHIFT_COUNT); |
| 1297 | s->in_lists = 1; |
| 1298 | } |
| 1299 | |
| 1300 | /* write to 'mono' word */ |
| 1301 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1302 | s->inst.data + SRC3_DIRECTION_OFFSET + 1, |
| 1303 | runtime->channels == 2 ? 0 : 1); |
| 1304 | /* write to '8bit' word */ |
| 1305 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1306 | s->inst.data + SRC3_DIRECTION_OFFSET + 2, |
| 1307 | snd_pcm_format_width(runtime->format) == 16 ? 0 : 1); |
| 1308 | |
| 1309 | /* set up dac/adc rate */ |
| 1310 | freq = ((runtime->rate << 15) + 24000 ) / 48000; |
| 1311 | if (freq) |
| 1312 | freq--; |
| 1313 | |
| 1314 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1315 | s->inst.data + CDATA_FREQUENCY, |
| 1316 | freq); |
| 1317 | } |
| 1318 | |
| 1319 | |
| 1320 | static struct play_vals { |
| 1321 | u16 addr, val; |
| 1322 | } pv[] = { |
| 1323 | {CDATA_LEFT_VOLUME, ARB_VOLUME}, |
| 1324 | {CDATA_RIGHT_VOLUME, ARB_VOLUME}, |
| 1325 | {SRC3_DIRECTION_OFFSET, 0} , |
| 1326 | /* +1, +2 are stereo/16 bit */ |
| 1327 | {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ |
| 1328 | {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ |
| 1329 | {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ |
| 1330 | {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ |
| 1331 | {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ |
| 1332 | {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ |
| 1333 | {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ |
| 1334 | {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ |
| 1335 | {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ |
| 1336 | {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ |
| 1337 | {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ |
| 1338 | {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ |
| 1339 | {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */ |
| 1340 | {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */ |
| 1341 | {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */ |
| 1342 | {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ |
| 1343 | {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */ |
| 1344 | }; |
| 1345 | |
| 1346 | |
| 1347 | /* the mode passed should be already shifted and masked */ |
| 1348 | static void |
| 1349 | snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) |
| 1350 | { |
| 1351 | unsigned int i; |
| 1352 | |
| 1353 | /* |
| 1354 | * some per client initializers |
| 1355 | */ |
| 1356 | |
| 1357 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1358 | s->inst.data + SRC3_DIRECTION_OFFSET + 12, |
| 1359 | s->inst.data + 40 + 8); |
| 1360 | |
| 1361 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1362 | s->inst.data + SRC3_DIRECTION_OFFSET + 19, |
| 1363 | s->inst.code + MINISRC_COEF_LOC); |
| 1364 | |
| 1365 | /* enable or disable low pass filter? */ |
| 1366 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1367 | s->inst.data + SRC3_DIRECTION_OFFSET + 22, |
| 1368 | subs->runtime->rate > 45000 ? 0xff : 0); |
| 1369 | |
| 1370 | /* tell it which way dma is going? */ |
| 1371 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1372 | s->inst.data + CDATA_DMA_CONTROL, |
| 1373 | DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); |
| 1374 | |
| 1375 | /* |
| 1376 | * set an armload of static initializers |
| 1377 | */ |
| 1378 | for (i = 0; i < ARRAY_SIZE(pv); i++) |
| 1379 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1380 | s->inst.data + pv[i].addr, pv[i].val); |
| 1381 | } |
| 1382 | |
| 1383 | /* |
| 1384 | * Native record driver |
| 1385 | */ |
| 1386 | static struct rec_vals { |
| 1387 | u16 addr, val; |
| 1388 | } rv[] = { |
| 1389 | {CDATA_LEFT_VOLUME, ARB_VOLUME}, |
| 1390 | {CDATA_RIGHT_VOLUME, ARB_VOLUME}, |
| 1391 | {SRC3_DIRECTION_OFFSET, 1} , |
| 1392 | /* +1, +2 are stereo/16 bit */ |
| 1393 | {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ |
| 1394 | {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ |
| 1395 | {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ |
| 1396 | {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ |
| 1397 | {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ |
| 1398 | {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ |
| 1399 | {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ |
| 1400 | {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ |
| 1401 | {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ |
| 1402 | {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ |
| 1403 | {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ |
| 1404 | {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ |
| 1405 | {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */ |
| 1406 | {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */ |
| 1407 | {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */ |
| 1408 | {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */ |
| 1409 | {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ |
| 1410 | {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */ |
| 1411 | {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */ |
| 1412 | }; |
| 1413 | |
| 1414 | static void |
| 1415 | snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) |
| 1416 | { |
| 1417 | unsigned int i; |
| 1418 | |
| 1419 | /* |
| 1420 | * some per client initializers |
| 1421 | */ |
| 1422 | |
| 1423 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1424 | s->inst.data + SRC3_DIRECTION_OFFSET + 12, |
| 1425 | s->inst.data + 40 + 8); |
| 1426 | |
| 1427 | /* tell it which way dma is going? */ |
| 1428 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1429 | s->inst.data + CDATA_DMA_CONTROL, |
| 1430 | DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + |
| 1431 | DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); |
| 1432 | |
| 1433 | /* |
| 1434 | * set an armload of static initializers |
| 1435 | */ |
| 1436 | for (i = 0; i < ARRAY_SIZE(rv); i++) |
| 1437 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 1438 | s->inst.data + rv[i].addr, rv[i].val); |
| 1439 | } |
| 1440 | |
| 1441 | static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream, |
| 1442 | snd_pcm_hw_params_t * hw_params) |
| 1443 | { |
| 1444 | m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data; |
| 1445 | int err; |
| 1446 | |
| 1447 | if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) |
| 1448 | return err; |
| 1449 | /* set buffer address */ |
| 1450 | s->buffer_addr = substream->runtime->dma_addr; |
| 1451 | if (s->buffer_addr & 0x3) { |
| 1452 | snd_printk("oh my, not aligned\n"); |
| 1453 | s->buffer_addr = s->buffer_addr & ~0x3; |
| 1454 | } |
| 1455 | return 0; |
| 1456 | } |
| 1457 | |
| 1458 | static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream) |
| 1459 | { |
| 1460 | m3_dma_t *s; |
| 1461 | |
| 1462 | if (substream->runtime->private_data == NULL) |
| 1463 | return 0; |
| 1464 | s = (m3_dma_t*) substream->runtime->private_data; |
| 1465 | snd_pcm_lib_free_pages(substream); |
| 1466 | s->buffer_addr = 0; |
| 1467 | return 0; |
| 1468 | } |
| 1469 | |
| 1470 | static int |
| 1471 | snd_m3_pcm_prepare(snd_pcm_substream_t *subs) |
| 1472 | { |
| 1473 | m3_t *chip = snd_pcm_substream_chip(subs); |
| 1474 | snd_pcm_runtime_t *runtime = subs->runtime; |
| 1475 | m3_dma_t *s = (m3_dma_t*)runtime->private_data; |
| 1476 | |
| 1477 | snd_assert(s != NULL, return -ENXIO); |
| 1478 | |
| 1479 | if (runtime->format != SNDRV_PCM_FORMAT_U8 && |
| 1480 | runtime->format != SNDRV_PCM_FORMAT_S16_LE) |
| 1481 | return -EINVAL; |
| 1482 | if (runtime->rate > 48000 || |
| 1483 | runtime->rate < 8000) |
| 1484 | return -EINVAL; |
| 1485 | |
| 1486 | spin_lock_irq(&chip->reg_lock); |
| 1487 | |
| 1488 | snd_m3_pcm_setup1(chip, s, subs); |
| 1489 | |
| 1490 | if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 1491 | snd_m3_playback_setup(chip, s, subs); |
| 1492 | else |
| 1493 | snd_m3_capture_setup(chip, s, subs); |
| 1494 | |
| 1495 | snd_m3_pcm_setup2(chip, s, runtime); |
| 1496 | |
| 1497 | spin_unlock_irq(&chip->reg_lock); |
| 1498 | |
| 1499 | return 0; |
| 1500 | } |
| 1501 | |
| 1502 | /* |
| 1503 | * get current pointer |
| 1504 | */ |
| 1505 | static unsigned int |
| 1506 | snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) |
| 1507 | { |
| 1508 | u16 hi = 0, lo = 0; |
| 1509 | int retry = 10; |
| 1510 | u32 addr; |
| 1511 | |
| 1512 | /* |
| 1513 | * try and get a valid answer |
| 1514 | */ |
| 1515 | while (retry--) { |
| 1516 | hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, |
| 1517 | s->inst.data + CDATA_HOST_SRC_CURRENTH); |
| 1518 | |
| 1519 | lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, |
| 1520 | s->inst.data + CDATA_HOST_SRC_CURRENTL); |
| 1521 | |
| 1522 | if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, |
| 1523 | s->inst.data + CDATA_HOST_SRC_CURRENTH)) |
| 1524 | break; |
| 1525 | } |
| 1526 | addr = lo | ((u32)hi<<16); |
| 1527 | return (unsigned int)(addr - s->buffer_addr); |
| 1528 | } |
| 1529 | |
| 1530 | static snd_pcm_uframes_t |
| 1531 | snd_m3_pcm_pointer(snd_pcm_substream_t * subs) |
| 1532 | { |
| 1533 | m3_t *chip = snd_pcm_substream_chip(subs); |
| 1534 | unsigned int ptr; |
| 1535 | m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data; |
| 1536 | snd_assert(s != NULL, return 0); |
| 1537 | |
| 1538 | spin_lock(&chip->reg_lock); |
| 1539 | ptr = snd_m3_get_pointer(chip, s, subs); |
| 1540 | spin_unlock(&chip->reg_lock); |
| 1541 | return bytes_to_frames(subs->runtime, ptr); |
| 1542 | } |
| 1543 | |
| 1544 | |
| 1545 | /* update pointer */ |
| 1546 | /* spinlock held! */ |
| 1547 | static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s) |
| 1548 | { |
| 1549 | snd_pcm_substream_t *subs = s->substream; |
| 1550 | unsigned int hwptr; |
| 1551 | int diff; |
| 1552 | |
| 1553 | if (! s->running) |
| 1554 | return; |
| 1555 | |
| 1556 | hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size; |
| 1557 | diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size; |
| 1558 | s->hwptr = hwptr; |
| 1559 | s->count += diff; |
| 1560 | if (s->count >= (signed)s->period_size) { |
| 1561 | s->count %= s->period_size; |
| 1562 | spin_unlock(&chip->reg_lock); |
| 1563 | snd_pcm_period_elapsed(subs); |
| 1564 | spin_lock(&chip->reg_lock); |
| 1565 | } |
| 1566 | } |
| 1567 | |
| 1568 | static irqreturn_t |
| 1569 | snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
| 1570 | { |
| 1571 | m3_t *chip = dev_id; |
| 1572 | u8 status; |
| 1573 | int i; |
| 1574 | |
| 1575 | status = inb(chip->iobase + HOST_INT_STATUS); |
| 1576 | |
| 1577 | if (status == 0xff) |
| 1578 | return IRQ_NONE; |
| 1579 | |
| 1580 | /* |
| 1581 | * ack an assp int if its running |
| 1582 | * and has an int pending |
| 1583 | */ |
| 1584 | if (status & ASSP_INT_PENDING) { |
| 1585 | u8 ctl = inb(chip->iobase + ASSP_CONTROL_B); |
| 1586 | if (!(ctl & STOP_ASSP_CLOCK)) { |
| 1587 | ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS); |
| 1588 | if (ctl & DSP2HOST_REQ_TIMER) { |
| 1589 | outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS); |
| 1590 | /* update adc/dac info if it was a timer int */ |
| 1591 | spin_lock(&chip->reg_lock); |
| 1592 | for (i = 0; i < chip->num_substreams; i++) { |
| 1593 | m3_dma_t *s = &chip->substreams[i]; |
| 1594 | if (s->running) |
| 1595 | snd_m3_update_ptr(chip, s); |
| 1596 | } |
| 1597 | spin_unlock(&chip->reg_lock); |
| 1598 | } |
| 1599 | } |
| 1600 | } |
| 1601 | |
| 1602 | #if 0 /* TODO: not supported yet */ |
| 1603 | if ((status & MPU401_INT_PENDING) && chip->rmidi) |
| 1604 | snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs); |
| 1605 | #endif |
| 1606 | |
| 1607 | /* ack ints */ |
Ville Syrjala | 8849138 | 2005-05-12 14:14:28 +0200 | [diff] [blame^] | 1608 | outb(status, chip->iobase + HOST_INT_STATUS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1609 | |
| 1610 | return IRQ_HANDLED; |
| 1611 | } |
| 1612 | |
| 1613 | |
| 1614 | /* |
| 1615 | */ |
| 1616 | |
| 1617 | static snd_pcm_hardware_t snd_m3_playback = |
| 1618 | { |
| 1619 | .info = (SNDRV_PCM_INFO_MMAP | |
| 1620 | SNDRV_PCM_INFO_INTERLEAVED | |
| 1621 | SNDRV_PCM_INFO_MMAP_VALID | |
| 1622 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
| 1623 | /*SNDRV_PCM_INFO_PAUSE |*/ |
| 1624 | SNDRV_PCM_INFO_RESUME), |
| 1625 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, |
| 1626 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, |
| 1627 | .rate_min = 8000, |
| 1628 | .rate_max = 48000, |
| 1629 | .channels_min = 1, |
| 1630 | .channels_max = 2, |
| 1631 | .buffer_bytes_max = (512*1024), |
| 1632 | .period_bytes_min = 64, |
| 1633 | .period_bytes_max = (512*1024), |
| 1634 | .periods_min = 1, |
| 1635 | .periods_max = 1024, |
| 1636 | }; |
| 1637 | |
| 1638 | static snd_pcm_hardware_t snd_m3_capture = |
| 1639 | { |
| 1640 | .info = (SNDRV_PCM_INFO_MMAP | |
| 1641 | SNDRV_PCM_INFO_INTERLEAVED | |
| 1642 | SNDRV_PCM_INFO_MMAP_VALID | |
| 1643 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
| 1644 | /*SNDRV_PCM_INFO_PAUSE |*/ |
| 1645 | SNDRV_PCM_INFO_RESUME), |
| 1646 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, |
| 1647 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, |
| 1648 | .rate_min = 8000, |
| 1649 | .rate_max = 48000, |
| 1650 | .channels_min = 1, |
| 1651 | .channels_max = 2, |
| 1652 | .buffer_bytes_max = (512*1024), |
| 1653 | .period_bytes_min = 64, |
| 1654 | .period_bytes_max = (512*1024), |
| 1655 | .periods_min = 1, |
| 1656 | .periods_max = 1024, |
| 1657 | }; |
| 1658 | |
| 1659 | |
| 1660 | /* |
| 1661 | */ |
| 1662 | |
| 1663 | static int |
| 1664 | snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs) |
| 1665 | { |
| 1666 | int i; |
| 1667 | m3_dma_t *s; |
| 1668 | |
| 1669 | spin_lock_irq(&chip->reg_lock); |
| 1670 | for (i = 0; i < chip->num_substreams; i++) { |
| 1671 | s = &chip->substreams[i]; |
| 1672 | if (! s->opened) |
| 1673 | goto __found; |
| 1674 | } |
| 1675 | spin_unlock_irq(&chip->reg_lock); |
| 1676 | return -ENOMEM; |
| 1677 | __found: |
| 1678 | s->opened = 1; |
| 1679 | s->running = 0; |
| 1680 | spin_unlock_irq(&chip->reg_lock); |
| 1681 | |
| 1682 | subs->runtime->private_data = s; |
| 1683 | s->substream = subs; |
| 1684 | |
| 1685 | /* set list owners */ |
| 1686 | if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 1687 | s->index_list[0] = &chip->mixer_list; |
| 1688 | } else |
| 1689 | s->index_list[0] = &chip->adc1_list; |
| 1690 | s->index_list[1] = &chip->msrc_list; |
| 1691 | s->index_list[2] = &chip->dma_list; |
| 1692 | |
| 1693 | return 0; |
| 1694 | } |
| 1695 | |
| 1696 | static void |
| 1697 | snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs) |
| 1698 | { |
| 1699 | m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data; |
| 1700 | |
| 1701 | if (s == NULL) |
| 1702 | return; /* not opened properly */ |
| 1703 | |
| 1704 | spin_lock_irq(&chip->reg_lock); |
| 1705 | if (s->substream && s->running) |
| 1706 | snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */ |
| 1707 | if (s->in_lists) { |
| 1708 | snd_m3_remove_list(chip, s->index_list[0], s->index[0]); |
| 1709 | snd_m3_remove_list(chip, s->index_list[1], s->index[1]); |
| 1710 | snd_m3_remove_list(chip, s->index_list[2], s->index[2]); |
| 1711 | s->in_lists = 0; |
| 1712 | } |
| 1713 | s->running = 0; |
| 1714 | s->opened = 0; |
| 1715 | spin_unlock_irq(&chip->reg_lock); |
| 1716 | } |
| 1717 | |
| 1718 | static int |
| 1719 | snd_m3_playback_open(snd_pcm_substream_t *subs) |
| 1720 | { |
| 1721 | m3_t *chip = snd_pcm_substream_chip(subs); |
| 1722 | snd_pcm_runtime_t *runtime = subs->runtime; |
| 1723 | int err; |
| 1724 | |
| 1725 | if ((err = snd_m3_substream_open(chip, subs)) < 0) |
| 1726 | return err; |
| 1727 | |
| 1728 | runtime->hw = snd_m3_playback; |
| 1729 | snd_pcm_set_sync(subs); |
| 1730 | |
| 1731 | return 0; |
| 1732 | } |
| 1733 | |
| 1734 | static int |
| 1735 | snd_m3_playback_close(snd_pcm_substream_t *subs) |
| 1736 | { |
| 1737 | m3_t *chip = snd_pcm_substream_chip(subs); |
| 1738 | |
| 1739 | snd_m3_substream_close(chip, subs); |
| 1740 | return 0; |
| 1741 | } |
| 1742 | |
| 1743 | static int |
| 1744 | snd_m3_capture_open(snd_pcm_substream_t *subs) |
| 1745 | { |
| 1746 | m3_t *chip = snd_pcm_substream_chip(subs); |
| 1747 | snd_pcm_runtime_t *runtime = subs->runtime; |
| 1748 | int err; |
| 1749 | |
| 1750 | if ((err = snd_m3_substream_open(chip, subs)) < 0) |
| 1751 | return err; |
| 1752 | |
| 1753 | runtime->hw = snd_m3_capture; |
| 1754 | snd_pcm_set_sync(subs); |
| 1755 | |
| 1756 | return 0; |
| 1757 | } |
| 1758 | |
| 1759 | static int |
| 1760 | snd_m3_capture_close(snd_pcm_substream_t *subs) |
| 1761 | { |
| 1762 | m3_t *chip = snd_pcm_substream_chip(subs); |
| 1763 | |
| 1764 | snd_m3_substream_close(chip, subs); |
| 1765 | return 0; |
| 1766 | } |
| 1767 | |
| 1768 | /* |
| 1769 | * create pcm instance |
| 1770 | */ |
| 1771 | |
| 1772 | static snd_pcm_ops_t snd_m3_playback_ops = { |
| 1773 | .open = snd_m3_playback_open, |
| 1774 | .close = snd_m3_playback_close, |
| 1775 | .ioctl = snd_pcm_lib_ioctl, |
| 1776 | .hw_params = snd_m3_pcm_hw_params, |
| 1777 | .hw_free = snd_m3_pcm_hw_free, |
| 1778 | .prepare = snd_m3_pcm_prepare, |
| 1779 | .trigger = snd_m3_pcm_trigger, |
| 1780 | .pointer = snd_m3_pcm_pointer, |
| 1781 | }; |
| 1782 | |
| 1783 | static snd_pcm_ops_t snd_m3_capture_ops = { |
| 1784 | .open = snd_m3_capture_open, |
| 1785 | .close = snd_m3_capture_close, |
| 1786 | .ioctl = snd_pcm_lib_ioctl, |
| 1787 | .hw_params = snd_m3_pcm_hw_params, |
| 1788 | .hw_free = snd_m3_pcm_hw_free, |
| 1789 | .prepare = snd_m3_pcm_prepare, |
| 1790 | .trigger = snd_m3_pcm_trigger, |
| 1791 | .pointer = snd_m3_pcm_pointer, |
| 1792 | }; |
| 1793 | |
| 1794 | static int __devinit |
| 1795 | snd_m3_pcm(m3_t * chip, int device) |
| 1796 | { |
| 1797 | snd_pcm_t *pcm; |
| 1798 | int err; |
| 1799 | |
| 1800 | err = snd_pcm_new(chip->card, chip->card->driver, device, |
| 1801 | MAX_PLAYBACKS, MAX_CAPTURES, &pcm); |
| 1802 | if (err < 0) |
| 1803 | return err; |
| 1804 | |
| 1805 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops); |
| 1806 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops); |
| 1807 | |
| 1808 | pcm->private_data = chip; |
| 1809 | pcm->info_flags = 0; |
| 1810 | strcpy(pcm->name, chip->card->driver); |
| 1811 | chip->pcm = pcm; |
| 1812 | |
| 1813 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, |
| 1814 | snd_dma_pci_data(chip->pci), 64*1024, 64*1024); |
| 1815 | |
| 1816 | return 0; |
| 1817 | } |
| 1818 | |
| 1819 | |
| 1820 | /* |
| 1821 | * ac97 interface |
| 1822 | */ |
| 1823 | |
| 1824 | /* |
| 1825 | * Wait for the ac97 serial bus to be free. |
| 1826 | * return nonzero if the bus is still busy. |
| 1827 | */ |
| 1828 | static int snd_m3_ac97_wait(m3_t *chip) |
| 1829 | { |
| 1830 | int i = 10000; |
| 1831 | |
| 1832 | do { |
| 1833 | if (! (snd_m3_inb(chip, 0x30) & 1)) |
| 1834 | return 0; |
| 1835 | } while (i-- > 0); |
| 1836 | |
| 1837 | snd_printk("ac97 serial bus busy\n"); |
| 1838 | return 1; |
| 1839 | } |
| 1840 | |
| 1841 | static unsigned short |
| 1842 | snd_m3_ac97_read(ac97_t *ac97, unsigned short reg) |
| 1843 | { |
| 1844 | m3_t *chip = ac97->private_data; |
| 1845 | |
| 1846 | if (snd_m3_ac97_wait(chip)) |
| 1847 | return 0xffff; |
| 1848 | snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND); |
| 1849 | if (snd_m3_ac97_wait(chip)) |
| 1850 | return 0xffff; |
| 1851 | return snd_m3_inw(chip, CODEC_DATA); |
| 1852 | } |
| 1853 | |
| 1854 | static void |
| 1855 | snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val) |
| 1856 | { |
| 1857 | m3_t *chip = ac97->private_data; |
| 1858 | |
| 1859 | if (snd_m3_ac97_wait(chip)) |
| 1860 | return; |
| 1861 | snd_m3_outw(chip, val, CODEC_DATA); |
| 1862 | snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); |
| 1863 | } |
| 1864 | |
| 1865 | |
| 1866 | static void snd_m3_remote_codec_config(int io, int isremote) |
| 1867 | { |
| 1868 | isremote = isremote ? 1 : 0; |
| 1869 | |
| 1870 | outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote, |
| 1871 | io + RING_BUS_CTRL_B); |
| 1872 | outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote, |
| 1873 | io + SDO_OUT_DEST_CTRL); |
| 1874 | outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote, |
| 1875 | io + SDO_IN_DEST_CTRL); |
| 1876 | } |
| 1877 | |
| 1878 | /* |
| 1879 | * hack, returns non zero on err |
| 1880 | */ |
| 1881 | static int snd_m3_try_read_vendor(m3_t *chip) |
| 1882 | { |
| 1883 | u16 ret; |
| 1884 | |
| 1885 | if (snd_m3_ac97_wait(chip)) |
| 1886 | return 1; |
| 1887 | |
| 1888 | snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30); |
| 1889 | |
| 1890 | if (snd_m3_ac97_wait(chip)) |
| 1891 | return 1; |
| 1892 | |
| 1893 | ret = snd_m3_inw(chip, 0x32); |
| 1894 | |
| 1895 | return (ret == 0) || (ret == 0xffff); |
| 1896 | } |
| 1897 | |
| 1898 | static void snd_m3_ac97_reset(m3_t *chip) |
| 1899 | { |
| 1900 | u16 dir; |
| 1901 | int delay1 = 0, delay2 = 0, i; |
| 1902 | int io = chip->iobase; |
| 1903 | |
| 1904 | if (chip->allegro_flag) { |
| 1905 | /* |
| 1906 | * the onboard codec on the allegro seems |
| 1907 | * to want to wait a very long time before |
| 1908 | * coming back to life |
| 1909 | */ |
| 1910 | delay1 = 50; |
| 1911 | delay2 = 800; |
| 1912 | } else { |
| 1913 | /* maestro3 */ |
| 1914 | delay1 = 20; |
| 1915 | delay2 = 500; |
| 1916 | } |
| 1917 | |
| 1918 | for (i = 0; i < 5; i++) { |
| 1919 | dir = inw(io + GPIO_DIRECTION); |
| 1920 | if (! chip->quirk || ! chip->quirk->irda_workaround) |
| 1921 | dir |= 0x10; /* assuming pci bus master? */ |
| 1922 | |
| 1923 | snd_m3_remote_codec_config(io, 0); |
| 1924 | |
| 1925 | outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A); |
| 1926 | udelay(20); |
| 1927 | |
| 1928 | outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION); |
| 1929 | outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK); |
| 1930 | outw(0, io + GPIO_DATA); |
| 1931 | outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION); |
| 1932 | |
| 1933 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 1934 | schedule_timeout((delay1 * HZ) / 1000); |
| 1935 | |
| 1936 | outw(GPO_PRIMARY_AC97, io + GPIO_DATA); |
| 1937 | udelay(5); |
| 1938 | /* ok, bring back the ac-link */ |
| 1939 | outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A); |
| 1940 | outw(~0, io + GPIO_MASK); |
| 1941 | |
| 1942 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 1943 | schedule_timeout((delay2 * HZ) / 1000); |
| 1944 | |
| 1945 | if (! snd_m3_try_read_vendor(chip)) |
| 1946 | break; |
| 1947 | |
| 1948 | delay1 += 10; |
| 1949 | delay2 += 100; |
| 1950 | |
| 1951 | snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n", |
| 1952 | delay1, delay2); |
| 1953 | } |
| 1954 | |
| 1955 | #if 0 |
| 1956 | /* more gung-ho reset that doesn't |
| 1957 | * seem to work anywhere :) |
| 1958 | */ |
| 1959 | tmp = inw(io + RING_BUS_CTRL_A); |
| 1960 | outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A); |
| 1961 | big_mdelay(20); |
| 1962 | outw(tmp, io + RING_BUS_CTRL_A); |
| 1963 | big_mdelay(50); |
| 1964 | #endif |
| 1965 | } |
| 1966 | |
| 1967 | static int __devinit snd_m3_mixer(m3_t *chip) |
| 1968 | { |
| 1969 | ac97_bus_t *pbus; |
| 1970 | ac97_template_t ac97; |
| 1971 | int err; |
| 1972 | static ac97_bus_ops_t ops = { |
| 1973 | .write = snd_m3_ac97_write, |
| 1974 | .read = snd_m3_ac97_read, |
| 1975 | }; |
| 1976 | |
| 1977 | if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0) |
| 1978 | return err; |
| 1979 | |
| 1980 | memset(&ac97, 0, sizeof(ac97)); |
| 1981 | ac97.private_data = chip; |
| 1982 | if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0) |
| 1983 | return err; |
| 1984 | |
| 1985 | /* seems ac97 PCM needs initialization.. hack hack.. */ |
| 1986 | snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15); |
| 1987 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 1988 | schedule_timeout(HZ / 10); |
| 1989 | snd_ac97_write(chip->ac97, AC97_PCM, 0); |
| 1990 | |
| 1991 | return 0; |
| 1992 | } |
| 1993 | |
| 1994 | |
| 1995 | /* |
| 1996 | * DSP Code images |
| 1997 | */ |
| 1998 | |
| 1999 | static u16 assp_kernel_image[] __devinitdata = { |
| 2000 | 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4, |
| 2001 | 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, |
| 2002 | 0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, |
| 2003 | 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4, |
| 2004 | 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08, |
| 2005 | 0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909, |
| 2006 | 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41, |
| 2007 | 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308, |
| 2008 | 0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910, |
| 2009 | 0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00, |
| 2010 | 0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026, |
| 2011 | 0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0, |
| 2012 | 0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012, |
| 2013 | 0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A, |
| 2014 | 0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000, |
| 2015 | 0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05, |
| 2016 | 0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26, |
| 2017 | 0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300, |
| 2018 | 0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88, |
| 2019 | 0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008, |
| 2020 | 0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80, |
| 2021 | 0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71, |
| 2022 | 0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A, |
| 2023 | 0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100, |
| 2024 | 0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900, |
| 2025 | 0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903, |
| 2026 | 0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309, |
| 2027 | 0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B, |
| 2028 | 0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540, |
| 2029 | 0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C, |
| 2030 | 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380, |
| 2031 | 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340, |
| 2032 | 0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041, |
| 2033 | 0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18, |
| 2034 | 0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, |
| 2035 | 0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9, |
| 2036 | 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8, |
| 2037 | 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A, |
| 2038 | 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80, |
| 2039 | 0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, |
| 2040 | 0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80, |
| 2041 | 0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A, |
| 2042 | 0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F, |
| 2043 | 0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1, |
| 2044 | 0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034, |
| 2045 | 0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E, |
| 2046 | 0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977, |
| 2047 | 0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B, |
| 2048 | 0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388, |
| 2049 | 0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, |
| 2050 | 0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473, |
| 2051 | 0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473, |
| 2052 | 0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880, |
| 2053 | 0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80, |
| 2054 | 0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6, |
| 2055 | 0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909, |
| 2056 | 0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED, |
| 2057 | 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005, |
| 2058 | 0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, |
| 2059 | 0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4, |
| 2060 | 0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, |
| 2061 | 0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10, |
| 2062 | 0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070, |
| 2063 | 0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71, |
| 2064 | 0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A, |
| 2065 | 0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061, |
| 2066 | 0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A, |
| 2067 | 0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6, |
| 2068 | 0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A, |
| 2069 | 0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6, |
| 2070 | 0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358, |
| 2071 | 0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6, |
| 2072 | 0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9, |
| 2073 | 0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379, |
| 2074 | 0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6, |
| 2075 | 0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C, |
| 2076 | 0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166, |
| 2077 | 0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B, |
| 2078 | 0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A, |
| 2079 | 0xBE3A, |
| 2080 | }; |
| 2081 | |
| 2082 | /* |
| 2083 | * Mini sample rate converter code image |
| 2084 | * that is to be loaded at 0x400 on the DSP. |
| 2085 | */ |
| 2086 | static u16 assp_minisrc_image[] __devinitdata = { |
| 2087 | |
| 2088 | 0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412, |
| 2089 | 0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41, |
| 2090 | 0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907, |
| 2091 | 0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01, |
| 2092 | 0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904, |
| 2093 | 0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D, |
| 2094 | 0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD, |
| 2095 | 0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22, |
| 2096 | 0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0, |
| 2097 | 0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9, |
| 2098 | 0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89, |
| 2099 | 0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0, |
| 2100 | 0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484, |
| 2101 | 0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80, |
| 2102 | 0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624, |
| 2103 | 0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4, |
| 2104 | 0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027, |
| 2105 | 0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903, |
| 2106 | 0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809, |
| 2107 | 0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46, |
| 2108 | 0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47, |
| 2109 | 0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0, |
| 2110 | 0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516, |
| 2111 | 0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E, |
| 2112 | 0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C, |
| 2113 | 0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180, |
| 2114 | 0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E, |
| 2115 | 0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0, |
| 2116 | 0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0, |
| 2117 | 0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0, |
| 2118 | 0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F, |
| 2119 | 0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
| 2120 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
| 2121 | }; |
| 2122 | |
| 2123 | |
| 2124 | /* |
| 2125 | * initialize ASSP |
| 2126 | */ |
| 2127 | |
| 2128 | #define MINISRC_LPF_LEN 10 |
| 2129 | static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = { |
| 2130 | 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C, |
| 2131 | 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F |
| 2132 | }; |
| 2133 | |
| 2134 | static void __devinit snd_m3_assp_init(m3_t *chip) |
| 2135 | { |
| 2136 | unsigned int i; |
| 2137 | |
| 2138 | /* zero kernel data */ |
| 2139 | for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) |
| 2140 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 2141 | KDATA_BASE_ADDR + i, 0); |
| 2142 | |
| 2143 | /* zero mixer data? */ |
| 2144 | for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) |
| 2145 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 2146 | KDATA_BASE_ADDR2 + i, 0); |
| 2147 | |
| 2148 | /* init dma pointer */ |
| 2149 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 2150 | KDATA_CURRENT_DMA, |
| 2151 | KDATA_DMA_XFER0); |
| 2152 | |
| 2153 | /* write kernel into code memory.. */ |
| 2154 | for (i = 0 ; i < ARRAY_SIZE(assp_kernel_image); i++) { |
| 2155 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, |
| 2156 | REV_B_CODE_MEMORY_BEGIN + i, |
| 2157 | assp_kernel_image[i]); |
| 2158 | } |
| 2159 | |
| 2160 | /* |
| 2161 | * We only have this one client and we know that 0x400 |
| 2162 | * is free in our kernel's mem map, so lets just |
| 2163 | * drop it there. It seems that the minisrc doesn't |
| 2164 | * need vectors, so we won't bother with them.. |
| 2165 | */ |
| 2166 | for (i = 0; i < ARRAY_SIZE(assp_minisrc_image); i++) { |
| 2167 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, |
| 2168 | 0x400 + i, |
| 2169 | assp_minisrc_image[i]); |
| 2170 | } |
| 2171 | |
| 2172 | /* |
| 2173 | * write the coefficients for the low pass filter? |
| 2174 | */ |
| 2175 | for (i = 0; i < MINISRC_LPF_LEN ; i++) { |
| 2176 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, |
| 2177 | 0x400 + MINISRC_COEF_LOC + i, |
| 2178 | minisrc_lpf[i]); |
| 2179 | } |
| 2180 | |
| 2181 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, |
| 2182 | 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN, |
| 2183 | 0x8000); |
| 2184 | |
| 2185 | /* |
| 2186 | * the minisrc is the only thing on |
| 2187 | * our task list.. |
| 2188 | */ |
| 2189 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 2190 | KDATA_TASK0, |
| 2191 | 0x400); |
| 2192 | |
| 2193 | /* |
| 2194 | * init the mixer number.. |
| 2195 | */ |
| 2196 | |
| 2197 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 2198 | KDATA_MIXER_TASK_NUMBER,0); |
| 2199 | |
| 2200 | /* |
| 2201 | * EXTREME KERNEL MASTER VOLUME |
| 2202 | */ |
| 2203 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 2204 | KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); |
| 2205 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 2206 | KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); |
| 2207 | |
| 2208 | chip->mixer_list.curlen = 0; |
| 2209 | chip->mixer_list.mem_addr = KDATA_MIXER_XFER0; |
| 2210 | chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS; |
| 2211 | chip->adc1_list.curlen = 0; |
| 2212 | chip->adc1_list.mem_addr = KDATA_ADC1_XFER0; |
| 2213 | chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS; |
| 2214 | chip->dma_list.curlen = 0; |
| 2215 | chip->dma_list.mem_addr = KDATA_DMA_XFER0; |
| 2216 | chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS; |
| 2217 | chip->msrc_list.curlen = 0; |
| 2218 | chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC; |
| 2219 | chip->msrc_list.max = MAX_INSTANCE_MINISRC; |
| 2220 | } |
| 2221 | |
| 2222 | |
| 2223 | static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index) |
| 2224 | { |
| 2225 | int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 + |
| 2226 | MINISRC_IN_BUFFER_SIZE / 2 + |
| 2227 | 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 ); |
| 2228 | int address, i; |
| 2229 | |
| 2230 | /* |
| 2231 | * the revb memory map has 0x1100 through 0x1c00 |
| 2232 | * free. |
| 2233 | */ |
| 2234 | |
| 2235 | /* |
| 2236 | * align instance address to 256 bytes so that it's |
| 2237 | * shifted list address is aligned. |
| 2238 | * list address = (mem address >> 1) >> 7; |
| 2239 | */ |
| 2240 | data_bytes = (data_bytes + 255) & ~255; |
| 2241 | address = 0x1100 + ((data_bytes/2) * index); |
| 2242 | |
| 2243 | if ((address + (data_bytes/2)) >= 0x1c00) { |
| 2244 | snd_printk("no memory for %d bytes at ind %d (addr 0x%x)\n", |
| 2245 | data_bytes, index, address); |
| 2246 | return -ENOMEM; |
| 2247 | } |
| 2248 | |
| 2249 | s->number = index; |
| 2250 | s->inst.code = 0x400; |
| 2251 | s->inst.data = address; |
| 2252 | |
| 2253 | for (i = data_bytes / 2; i > 0; address++, i--) { |
| 2254 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 2255 | address, 0); |
| 2256 | } |
| 2257 | |
| 2258 | return 0; |
| 2259 | } |
| 2260 | |
| 2261 | |
| 2262 | /* |
| 2263 | * this works for the reference board, have to find |
| 2264 | * out about others |
| 2265 | * |
| 2266 | * this needs more magic for 4 speaker, but.. |
| 2267 | */ |
| 2268 | static void |
| 2269 | snd_m3_amp_enable(m3_t *chip, int enable) |
| 2270 | { |
| 2271 | int io = chip->iobase; |
| 2272 | u16 gpo, polarity; |
| 2273 | |
| 2274 | if (! chip->external_amp) |
| 2275 | return; |
| 2276 | |
| 2277 | polarity = enable ? 0 : 1; |
| 2278 | polarity = polarity << chip->amp_gpio; |
| 2279 | gpo = 1 << chip->amp_gpio; |
| 2280 | |
| 2281 | outw(~gpo, io + GPIO_MASK); |
| 2282 | |
| 2283 | outw(inw(io + GPIO_DIRECTION) | gpo, |
| 2284 | io + GPIO_DIRECTION); |
| 2285 | |
| 2286 | outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity), |
| 2287 | io + GPIO_DATA); |
| 2288 | |
| 2289 | outw(0xffff, io + GPIO_MASK); |
| 2290 | } |
| 2291 | |
| 2292 | static int |
| 2293 | snd_m3_chip_init(m3_t *chip) |
| 2294 | { |
| 2295 | struct pci_dev *pcidev = chip->pci; |
| 2296 | u32 n; |
| 2297 | u16 w; |
| 2298 | u8 t; /* makes as much sense as 'n', no? */ |
| 2299 | |
| 2300 | pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w); |
| 2301 | w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE| |
| 2302 | MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO| |
| 2303 | DISABLE_LEGACY); |
| 2304 | pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w); |
| 2305 | |
| 2306 | pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); |
| 2307 | n &= REDUCED_DEBOUNCE; |
| 2308 | n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; |
| 2309 | pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); |
| 2310 | |
| 2311 | outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B); |
| 2312 | pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); |
| 2313 | n &= ~INT_CLK_SELECT; |
| 2314 | if (!chip->allegro_flag) { |
| 2315 | n &= ~INT_CLK_MULT_ENABLE; |
| 2316 | n |= INT_CLK_SRC_NOT_PCI; |
| 2317 | } |
| 2318 | n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 ); |
| 2319 | pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); |
| 2320 | |
| 2321 | if (chip->allegro_flag) { |
| 2322 | pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n); |
| 2323 | n |= IN_CLK_12MHZ_SELECT; |
| 2324 | pci_write_config_dword(pcidev, PCI_USER_CONFIG, n); |
| 2325 | } |
| 2326 | |
| 2327 | t = inb(chip->iobase + ASSP_CONTROL_A); |
| 2328 | t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); |
| 2329 | t |= ASSP_CLK_49MHZ_SELECT; |
| 2330 | t |= ASSP_0_WS_ENABLE; |
| 2331 | outb(t, chip->iobase + ASSP_CONTROL_A); |
| 2332 | |
| 2333 | outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B); |
| 2334 | |
| 2335 | return 0; |
| 2336 | } |
| 2337 | |
| 2338 | static void |
| 2339 | snd_m3_enable_ints(m3_t *chip) |
| 2340 | { |
| 2341 | unsigned long io = chip->iobase; |
| 2342 | |
| 2343 | /* TODO: MPU401 not supported yet */ |
| 2344 | outw(ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/, io + HOST_INT_CTRL); |
| 2345 | outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE, |
| 2346 | io + ASSP_CONTROL_C); |
| 2347 | } |
| 2348 | |
| 2349 | |
| 2350 | /* |
| 2351 | */ |
| 2352 | |
| 2353 | static int snd_m3_free(m3_t *chip) |
| 2354 | { |
| 2355 | m3_dma_t *s; |
| 2356 | int i; |
| 2357 | |
| 2358 | if (chip->substreams) { |
| 2359 | spin_lock_irq(&chip->reg_lock); |
| 2360 | for (i = 0; i < chip->num_substreams; i++) { |
| 2361 | s = &chip->substreams[i]; |
| 2362 | /* check surviving pcms; this should not happen though.. */ |
| 2363 | if (s->substream && s->running) |
| 2364 | snd_m3_pcm_stop(chip, s, s->substream); |
| 2365 | } |
| 2366 | spin_unlock_irq(&chip->reg_lock); |
| 2367 | kfree(chip->substreams); |
| 2368 | } |
| 2369 | if (chip->iobase) { |
Ville Syrjala | 8849138 | 2005-05-12 14:14:28 +0200 | [diff] [blame^] | 2370 | outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2371 | } |
| 2372 | |
| 2373 | #ifdef CONFIG_PM |
| 2374 | vfree(chip->suspend_mem); |
| 2375 | #endif |
| 2376 | |
| 2377 | if (chip->irq >= 0) { |
| 2378 | synchronize_irq(chip->irq); |
| 2379 | free_irq(chip->irq, (void *)chip); |
| 2380 | } |
| 2381 | |
| 2382 | if (chip->iobase) |
| 2383 | pci_release_regions(chip->pci); |
| 2384 | |
| 2385 | pci_disable_device(chip->pci); |
| 2386 | kfree(chip); |
| 2387 | return 0; |
| 2388 | } |
| 2389 | |
| 2390 | |
| 2391 | /* |
| 2392 | * APM support |
| 2393 | */ |
| 2394 | #ifdef CONFIG_PM |
| 2395 | static int m3_suspend(snd_card_t *card, pm_message_t state) |
| 2396 | { |
| 2397 | m3_t *chip = card->pm_private_data; |
| 2398 | int i, index; |
| 2399 | |
| 2400 | if (chip->suspend_mem == NULL) |
| 2401 | return 0; |
| 2402 | |
| 2403 | snd_pcm_suspend_all(chip->pcm); |
| 2404 | snd_ac97_suspend(chip->ac97); |
| 2405 | |
| 2406 | big_mdelay(10); /* give the assp a chance to idle.. */ |
| 2407 | |
| 2408 | snd_m3_assp_halt(chip); |
| 2409 | |
| 2410 | /* save dsp image */ |
| 2411 | index = 0; |
| 2412 | for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) |
| 2413 | chip->suspend_mem[index++] = |
| 2414 | snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i); |
| 2415 | for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) |
| 2416 | chip->suspend_mem[index++] = |
| 2417 | snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i); |
| 2418 | |
| 2419 | /* power down apci registers */ |
| 2420 | snd_m3_outw(chip, 0xffff, 0x54); |
| 2421 | snd_m3_outw(chip, 0xffff, 0x56); |
| 2422 | |
| 2423 | pci_disable_device(chip->pci); |
| 2424 | return 0; |
| 2425 | } |
| 2426 | |
| 2427 | static int m3_resume(snd_card_t *card) |
| 2428 | { |
| 2429 | m3_t *chip = card->pm_private_data; |
| 2430 | int i, index; |
| 2431 | |
| 2432 | if (chip->suspend_mem == NULL) |
| 2433 | return 0; |
| 2434 | |
| 2435 | pci_enable_device(chip->pci); |
| 2436 | pci_set_master(chip->pci); |
| 2437 | |
| 2438 | /* first lets just bring everything back. .*/ |
| 2439 | snd_m3_outw(chip, 0, 0x54); |
| 2440 | snd_m3_outw(chip, 0, 0x56); |
| 2441 | |
| 2442 | snd_m3_chip_init(chip); |
| 2443 | snd_m3_assp_halt(chip); |
| 2444 | snd_m3_ac97_reset(chip); |
| 2445 | |
| 2446 | /* restore dsp image */ |
| 2447 | index = 0; |
| 2448 | for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) |
| 2449 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i, |
| 2450 | chip->suspend_mem[index++]); |
| 2451 | for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) |
| 2452 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i, |
| 2453 | chip->suspend_mem[index++]); |
| 2454 | |
| 2455 | /* tell the dma engine to restart itself */ |
| 2456 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
| 2457 | KDATA_DMA_ACTIVE, 0); |
| 2458 | |
| 2459 | /* restore ac97 registers */ |
| 2460 | snd_ac97_resume(chip->ac97); |
| 2461 | |
| 2462 | snd_m3_assp_continue(chip); |
| 2463 | snd_m3_enable_ints(chip); |
| 2464 | snd_m3_amp_enable(chip, 1); |
| 2465 | |
| 2466 | return 0; |
| 2467 | } |
| 2468 | #endif /* CONFIG_PM */ |
| 2469 | |
| 2470 | |
| 2471 | /* |
| 2472 | */ |
| 2473 | |
| 2474 | static int snd_m3_dev_free(snd_device_t *device) |
| 2475 | { |
| 2476 | m3_t *chip = device->device_data; |
| 2477 | return snd_m3_free(chip); |
| 2478 | } |
| 2479 | |
| 2480 | static int __devinit |
| 2481 | snd_m3_create(snd_card_t *card, struct pci_dev *pci, |
| 2482 | int enable_amp, |
| 2483 | int amp_gpio, |
| 2484 | m3_t **chip_ret) |
| 2485 | { |
| 2486 | m3_t *chip; |
| 2487 | int i, err; |
| 2488 | struct m3_quirk *quirk; |
| 2489 | u16 subsystem_vendor, subsystem_device; |
| 2490 | static snd_device_ops_t ops = { |
| 2491 | .dev_free = snd_m3_dev_free, |
| 2492 | }; |
| 2493 | |
| 2494 | *chip_ret = NULL; |
| 2495 | |
| 2496 | if (pci_enable_device(pci)) |
| 2497 | return -EIO; |
| 2498 | |
| 2499 | /* check, if we can restrict PCI DMA transfers to 28 bits */ |
| 2500 | if (pci_set_dma_mask(pci, 0x0fffffff) < 0 || |
| 2501 | pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) { |
| 2502 | snd_printk("architecture does not support 28bit PCI busmaster DMA\n"); |
| 2503 | pci_disable_device(pci); |
| 2504 | return -ENXIO; |
| 2505 | } |
| 2506 | |
| 2507 | chip = kcalloc(1, sizeof(*chip), GFP_KERNEL); |
| 2508 | if (chip == NULL) { |
| 2509 | pci_disable_device(pci); |
| 2510 | return -ENOMEM; |
| 2511 | } |
| 2512 | |
| 2513 | spin_lock_init(&chip->reg_lock); |
| 2514 | switch (pci->device) { |
| 2515 | case PCI_DEVICE_ID_ESS_ALLEGRO: |
| 2516 | case PCI_DEVICE_ID_ESS_ALLEGRO_1: |
| 2517 | case PCI_DEVICE_ID_ESS_CANYON3D_2LE: |
| 2518 | case PCI_DEVICE_ID_ESS_CANYON3D_2: |
| 2519 | chip->allegro_flag = 1; |
| 2520 | break; |
| 2521 | } |
| 2522 | |
| 2523 | chip->card = card; |
| 2524 | chip->pci = pci; |
| 2525 | chip->irq = -1; |
| 2526 | |
| 2527 | pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vendor); |
| 2528 | pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &subsystem_device); |
| 2529 | |
| 2530 | for (quirk = m3_quirk_list; quirk->vendor; quirk++) { |
| 2531 | if (subsystem_vendor == quirk->vendor && |
| 2532 | subsystem_device == quirk->device) { |
| 2533 | printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name); |
| 2534 | chip->quirk = quirk; |
| 2535 | break; |
| 2536 | } |
| 2537 | } |
| 2538 | |
| 2539 | chip->external_amp = enable_amp; |
| 2540 | if (amp_gpio >= 0 && amp_gpio <= 0x0f) |
| 2541 | chip->amp_gpio = amp_gpio; |
| 2542 | else if (chip->quirk && chip->quirk->amp_gpio >= 0) |
| 2543 | chip->amp_gpio = chip->quirk->amp_gpio; |
| 2544 | else if (chip->allegro_flag) |
| 2545 | chip->amp_gpio = GPO_EXT_AMP_ALLEGRO; |
| 2546 | else /* presumably this is for all 'maestro3's.. */ |
| 2547 | chip->amp_gpio = GPO_EXT_AMP_M3; |
| 2548 | |
| 2549 | chip->num_substreams = NR_DSPS; |
| 2550 | chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL); |
| 2551 | if (chip->substreams == NULL) { |
| 2552 | kfree(chip); |
| 2553 | pci_disable_device(pci); |
| 2554 | return -ENOMEM; |
| 2555 | } |
| 2556 | memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams); |
| 2557 | |
| 2558 | if ((err = pci_request_regions(pci, card->driver)) < 0) { |
| 2559 | snd_m3_free(chip); |
| 2560 | return err; |
| 2561 | } |
| 2562 | chip->iobase = pci_resource_start(pci, 0); |
| 2563 | |
| 2564 | /* just to be sure */ |
| 2565 | pci_set_master(pci); |
| 2566 | |
| 2567 | snd_m3_chip_init(chip); |
| 2568 | snd_m3_assp_halt(chip); |
| 2569 | |
| 2570 | snd_m3_ac97_reset(chip); |
| 2571 | |
| 2572 | snd_m3_assp_init(chip); |
| 2573 | snd_m3_amp_enable(chip, 1); |
| 2574 | |
| 2575 | if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ, |
| 2576 | card->driver, (void *)chip)) { |
| 2577 | snd_printk("unable to grab IRQ %d\n", pci->irq); |
| 2578 | snd_m3_free(chip); |
| 2579 | return -ENOMEM; |
| 2580 | } |
| 2581 | chip->irq = pci->irq; |
| 2582 | |
| 2583 | #ifdef CONFIG_PM |
| 2584 | chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH)); |
| 2585 | if (chip->suspend_mem == NULL) |
| 2586 | snd_printk(KERN_WARNING "can't allocate apm buffer\n"); |
| 2587 | else |
| 2588 | snd_card_set_pm_callback(card, m3_suspend, m3_resume, chip); |
| 2589 | #endif |
| 2590 | |
| 2591 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { |
| 2592 | snd_m3_free(chip); |
| 2593 | return err; |
| 2594 | } |
| 2595 | |
| 2596 | if ((err = snd_m3_mixer(chip)) < 0) |
| 2597 | return err; |
| 2598 | |
| 2599 | for (i = 0; i < chip->num_substreams; i++) { |
| 2600 | m3_dma_t *s = &chip->substreams[i]; |
| 2601 | s->chip = chip; |
| 2602 | if ((err = snd_m3_assp_client_init(chip, s, i)) < 0) |
| 2603 | return err; |
| 2604 | } |
| 2605 | |
| 2606 | if ((err = snd_m3_pcm(chip, 0)) < 0) |
| 2607 | return err; |
| 2608 | |
| 2609 | snd_m3_enable_ints(chip); |
| 2610 | snd_m3_assp_continue(chip); |
| 2611 | |
| 2612 | snd_card_set_dev(card, &pci->dev); |
| 2613 | |
| 2614 | *chip_ret = chip; |
| 2615 | |
| 2616 | return 0; |
| 2617 | } |
| 2618 | |
| 2619 | /* |
| 2620 | */ |
| 2621 | static int __devinit |
| 2622 | snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) |
| 2623 | { |
| 2624 | static int dev; |
| 2625 | snd_card_t *card; |
| 2626 | m3_t *chip; |
| 2627 | int err; |
| 2628 | |
| 2629 | /* don't pick up modems */ |
| 2630 | if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO) |
| 2631 | return -ENODEV; |
| 2632 | |
| 2633 | if (dev >= SNDRV_CARDS) |
| 2634 | return -ENODEV; |
| 2635 | if (!enable[dev]) { |
| 2636 | dev++; |
| 2637 | return -ENOENT; |
| 2638 | } |
| 2639 | |
| 2640 | card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); |
| 2641 | if (card == NULL) |
| 2642 | return -ENOMEM; |
| 2643 | |
| 2644 | switch (pci->device) { |
| 2645 | case PCI_DEVICE_ID_ESS_ALLEGRO: |
| 2646 | case PCI_DEVICE_ID_ESS_ALLEGRO_1: |
| 2647 | strcpy(card->driver, "Allegro"); |
| 2648 | break; |
| 2649 | case PCI_DEVICE_ID_ESS_CANYON3D_2LE: |
| 2650 | case PCI_DEVICE_ID_ESS_CANYON3D_2: |
| 2651 | strcpy(card->driver, "Canyon3D-2"); |
| 2652 | break; |
| 2653 | default: |
| 2654 | strcpy(card->driver, "Maestro3"); |
| 2655 | break; |
| 2656 | } |
| 2657 | |
| 2658 | if ((err = snd_m3_create(card, pci, |
| 2659 | external_amp[dev], |
| 2660 | amp_gpio[dev], |
| 2661 | &chip)) < 0) { |
| 2662 | snd_card_free(card); |
| 2663 | return err; |
| 2664 | } |
| 2665 | |
| 2666 | sprintf(card->shortname, "ESS %s PCI", card->driver); |
| 2667 | sprintf(card->longname, "%s at 0x%lx, irq %d", |
| 2668 | card->shortname, chip->iobase, chip->irq); |
| 2669 | |
| 2670 | if ((err = snd_card_register(card)) < 0) { |
| 2671 | snd_card_free(card); |
| 2672 | return err; |
| 2673 | } |
| 2674 | |
| 2675 | #if 0 /* TODO: not supported yet */ |
| 2676 | /* TODO enable midi irq and i/o */ |
| 2677 | err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401, |
| 2678 | chip->iobase + MPU401_DATA_PORT, 1, |
| 2679 | chip->irq, 0, &chip->rmidi); |
| 2680 | if (err < 0) |
| 2681 | printk(KERN_WARNING "maestro3: no midi support.\n"); |
| 2682 | #endif |
| 2683 | |
| 2684 | pci_set_drvdata(pci, card); |
| 2685 | dev++; |
| 2686 | return 0; |
| 2687 | } |
| 2688 | |
| 2689 | static void __devexit snd_m3_remove(struct pci_dev *pci) |
| 2690 | { |
| 2691 | snd_card_free(pci_get_drvdata(pci)); |
| 2692 | pci_set_drvdata(pci, NULL); |
| 2693 | } |
| 2694 | |
| 2695 | static struct pci_driver driver = { |
| 2696 | .name = "Maestro3", |
| 2697 | .id_table = snd_m3_ids, |
| 2698 | .probe = snd_m3_probe, |
| 2699 | .remove = __devexit_p(snd_m3_remove), |
| 2700 | SND_PCI_PM_CALLBACKS |
| 2701 | }; |
| 2702 | |
| 2703 | static int __init alsa_card_m3_init(void) |
| 2704 | { |
Takashi Iwai | 01d25d4 | 2005-04-11 16:58:24 +0200 | [diff] [blame] | 2705 | return pci_register_driver(&driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2706 | } |
| 2707 | |
| 2708 | static void __exit alsa_card_m3_exit(void) |
| 2709 | { |
| 2710 | pci_unregister_driver(&driver); |
| 2711 | } |
| 2712 | |
| 2713 | module_init(alsa_card_m3_init) |
| 2714 | module_exit(alsa_card_m3_exit) |