blob: bec413ba9bcabb65d97122baf928ea91a89a46db [file] [log] [blame]
Li Yangce973b12006-08-14 23:00:11 -07001/*
Kim Phillips4e19b5c2007-05-11 18:25:07 -05002 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
Li Yangce973b12006-08-14 23:00:11 -07003 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
Li Yang18a8e862006-10-19 21:07:34 -05005 * Li Yang <leoli@freescale.com>
Li Yangce973b12006-08-14 23:00:11 -07006 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
Li Yangce973b12006-08-14 23:00:11 -070010 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/slab.h>
19#include <linux/stddef.h>
20#include <linux/interrupt.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/spinlock.h>
25#include <linux/mm.h>
Li Yangce973b12006-08-14 23:00:11 -070026#include <linux/dma-mapping.h>
27#include <linux/fsl_devices.h>
Li Yangce973b12006-08-14 23:00:11 -070028#include <linux/mii.h>
Kim Phillips728de4c92007-04-13 01:26:03 -050029#include <linux/phy.h>
Timur Tabidf19b6b2007-01-09 12:31:38 -060030#include <linux/workqueue.h>
Li Yangce973b12006-08-14 23:00:11 -070031
Kim Phillipsa4f0c2c2006-11-15 12:29:35 -060032#include <asm/of_platform.h>
Li Yangce973b12006-08-14 23:00:11 -070033#include <asm/uaccess.h>
34#include <asm/irq.h>
35#include <asm/io.h>
36#include <asm/immap_qe.h>
37#include <asm/qe.h>
38#include <asm/ucc.h>
39#include <asm/ucc_fast.h>
40
41#include "ucc_geth.h"
Kim Phillips728de4c92007-04-13 01:26:03 -050042#include "ucc_geth_mii.h"
Li Yangce973b12006-08-14 23:00:11 -070043
44#undef DEBUG
45
Li Yangce973b12006-08-14 23:00:11 -070046#define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
48
49#define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51#define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53#define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55#define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
57
58#ifdef UGETH_VERBOSE_DEBUG
59#define ugeth_vdbg ugeth_dbg
60#else
61#define ugeth_vdbg(fmt, args...) do { } while (0)
62#endif /* UGETH_VERBOSE_DEBUG */
Li Yang890de952007-07-19 11:48:29 +080063#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
Li Yangce973b12006-08-14 23:00:11 -070064
Li Yangac421852007-07-19 11:47:47 +080065void uec_set_ethtool_ops(struct net_device *netdev);
Emil Medve88a15f22007-10-15 08:43:50 -050066
Li Yangce973b12006-08-14 23:00:11 -070067static DEFINE_SPINLOCK(ugeth_lock);
68
Li Yang890de952007-07-19 11:48:29 +080069static struct {
70 u32 msg_enable;
71} debug = { -1 };
72
73module_param_named(debug, debug.msg_enable, int, 0);
74MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
75
Li Yang18a8e862006-10-19 21:07:34 -050076static struct ucc_geth_info ugeth_primary_info = {
Li Yangce973b12006-08-14 23:00:11 -070077 .uf_info = {
78 .bd_mem_part = MEM_PART_SYSTEM,
79 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
80 .max_rx_buf_length = 1536,
Kim Phillips728de4c92007-04-13 01:26:03 -050081 /* adjusted at startup if max-speed 1000 */
Li Yangce973b12006-08-14 23:00:11 -070082 .urfs = UCC_GETH_URFS_INIT,
83 .urfet = UCC_GETH_URFET_INIT,
84 .urfset = UCC_GETH_URFSET_INIT,
85 .utfs = UCC_GETH_UTFS_INIT,
86 .utfet = UCC_GETH_UTFET_INIT,
87 .utftt = UCC_GETH_UTFTT_INIT,
Li Yangce973b12006-08-14 23:00:11 -070088 .ufpt = 256,
89 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
90 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
91 .tenc = UCC_FAST_TX_ENCODING_NRZ,
92 .renc = UCC_FAST_RX_ENCODING_NRZ,
93 .tcrc = UCC_FAST_16_BIT_CRC,
94 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
95 },
96 .numQueuesTx = 1,
97 .numQueuesRx = 1,
98 .extendedFilteringChainPointer = ((uint32_t) NULL),
99 .typeorlen = 3072 /*1536 */ ,
100 .nonBackToBackIfgPart1 = 0x40,
101 .nonBackToBackIfgPart2 = 0x60,
102 .miminumInterFrameGapEnforcement = 0x50,
103 .backToBackInterFrameGap = 0x60,
104 .mblinterval = 128,
105 .nortsrbytetime = 5,
106 .fracsiz = 1,
107 .strictpriorityq = 0xff,
108 .altBebTruncation = 0xa,
109 .excessDefer = 1,
110 .maxRetransmission = 0xf,
111 .collisionWindow = 0x37,
112 .receiveFlowControl = 1,
Li Yangac421852007-07-19 11:47:47 +0800113 .transmitFlowControl = 1,
Li Yangce973b12006-08-14 23:00:11 -0700114 .maxGroupAddrInHash = 4,
115 .maxIndAddrInHash = 4,
116 .prel = 7,
117 .maxFrameLength = 1518,
118 .minFrameLength = 64,
119 .maxD1Length = 1520,
120 .maxD2Length = 1520,
121 .vlantype = 0x8100,
122 .ecamptr = ((uint32_t) NULL),
123 .eventRegMask = UCCE_OTHER,
124 .pausePeriod = 0xf000,
125 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
126 .bdRingLenTx = {
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN,
134 TX_BD_RING_LEN},
135
136 .bdRingLenRx = {
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN,
144 RX_BD_RING_LEN},
145
146 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
147 .largestexternallookupkeysize =
148 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
Li Yangac421852007-07-19 11:47:47 +0800149 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
Li Yangce973b12006-08-14 23:00:11 -0700152 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
153 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
154 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
155 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
156 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
157 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_4,
158 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_4,
159 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
161};
162
Li Yang18a8e862006-10-19 21:07:34 -0500163static struct ucc_geth_info ugeth_info[8];
Li Yangce973b12006-08-14 23:00:11 -0700164
165#ifdef DEBUG
166static void mem_disp(u8 *addr, int size)
167{
168 u8 *i;
169 int size16Aling = (size >> 4) << 4;
170 int size4Aling = (size >> 2) << 2;
171 int notAlign = 0;
172 if (size % 16)
173 notAlign = 1;
174
175 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
176 printk("0x%08x: %08x %08x %08x %08x\r\n",
177 (u32) i,
178 *((u32 *) (i)),
179 *((u32 *) (i + 4)),
180 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
181 if (notAlign == 1)
182 printk("0x%08x: ", (u32) i);
183 for (; (u32) i < (u32) addr + size4Aling; i += 4)
184 printk("%08x ", *((u32 *) (i)));
185 for (; (u32) i < (u32) addr + size; i++)
186 printk("%02x", *((u8 *) (i)));
187 if (notAlign == 1)
188 printk("\r\n");
189}
190#endif /* DEBUG */
191
192#ifdef CONFIG_UGETH_FILTERING
193static void enqueue(struct list_head *node, struct list_head *lh)
194{
195 unsigned long flags;
196
Scott Wood1083cfe2006-12-07 13:31:07 -0600197 spin_lock_irqsave(&ugeth_lock, flags);
Li Yangce973b12006-08-14 23:00:11 -0700198 list_add_tail(node, lh);
Scott Wood1083cfe2006-12-07 13:31:07 -0600199 spin_unlock_irqrestore(&ugeth_lock, flags);
Li Yangce973b12006-08-14 23:00:11 -0700200}
201#endif /* CONFIG_UGETH_FILTERING */
202
203static struct list_head *dequeue(struct list_head *lh)
204{
205 unsigned long flags;
206
Scott Wood1083cfe2006-12-07 13:31:07 -0600207 spin_lock_irqsave(&ugeth_lock, flags);
Li Yangce973b12006-08-14 23:00:11 -0700208 if (!list_empty(lh)) {
209 struct list_head *node = lh->next;
210 list_del(node);
Scott Wood1083cfe2006-12-07 13:31:07 -0600211 spin_unlock_irqrestore(&ugeth_lock, flags);
Li Yangce973b12006-08-14 23:00:11 -0700212 return node;
213 } else {
Scott Wood1083cfe2006-12-07 13:31:07 -0600214 spin_unlock_irqrestore(&ugeth_lock, flags);
Li Yangce973b12006-08-14 23:00:11 -0700215 return NULL;
216 }
217}
218
Li Yang18a8e862006-10-19 21:07:34 -0500219static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd)
Li Yangce973b12006-08-14 23:00:11 -0700220{
221 struct sk_buff *skb = NULL;
222
223 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
224 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
225
226 if (skb == NULL)
227 return NULL;
228
229 /* We need the data buffer to be aligned properly. We will reserve
230 * as many bytes as needed to align the data properly
231 */
232 skb_reserve(skb,
233 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
234 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
235 1)));
236
237 skb->dev = ugeth->dev;
238
Li Yang18a8e862006-10-19 21:07:34 -0500239 out_be32(&((struct qe_bd *)bd)->buf,
Li Yangce973b12006-08-14 23:00:11 -0700240 dma_map_single(NULL,
241 skb->data,
242 ugeth->ug_info->uf_info.max_rx_buf_length +
243 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
244 DMA_FROM_DEVICE));
245
Li Yang18a8e862006-10-19 21:07:34 -0500246 out_be32((u32 *)bd, (R_E | R_I | (in_be32((u32 *)bd) & R_W)));
Li Yangce973b12006-08-14 23:00:11 -0700247
248 return skb;
249}
250
Li Yang18a8e862006-10-19 21:07:34 -0500251static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
Li Yangce973b12006-08-14 23:00:11 -0700252{
253 u8 *bd;
254 u32 bd_status;
255 struct sk_buff *skb;
256 int i;
257
258 bd = ugeth->p_rx_bd_ring[rxQ];
259 i = 0;
260
261 do {
Li Yang18a8e862006-10-19 21:07:34 -0500262 bd_status = in_be32((u32*)bd);
Li Yangce973b12006-08-14 23:00:11 -0700263 skb = get_new_skb(ugeth, bd);
264
265 if (!skb) /* If can not allocate data buffer,
266 abort. Cleanup will be elsewhere */
267 return -ENOMEM;
268
269 ugeth->rx_skbuff[rxQ][i] = skb;
270
271 /* advance the BD pointer */
Li Yang18a8e862006-10-19 21:07:34 -0500272 bd += sizeof(struct qe_bd);
Li Yangce973b12006-08-14 23:00:11 -0700273 i++;
274 } while (!(bd_status & R_W));
275
276 return 0;
277}
278
Li Yang18a8e862006-10-19 21:07:34 -0500279static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
Li Yangce973b12006-08-14 23:00:11 -0700280 volatile u32 *p_start,
281 u8 num_entries,
282 u32 thread_size,
283 u32 thread_alignment,
Li Yang18a8e862006-10-19 21:07:34 -0500284 enum qe_risc_allocation risc,
Li Yangce973b12006-08-14 23:00:11 -0700285 int skip_page_for_first_entry)
286{
287 u32 init_enet_offset;
288 u8 i;
289 int snum;
290
291 for (i = 0; i < num_entries; i++) {
292 if ((snum = qe_get_snum()) < 0) {
Li Yang890de952007-07-19 11:48:29 +0800293 if (netif_msg_ifup(ugeth))
294 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
Li Yangce973b12006-08-14 23:00:11 -0700295 return snum;
296 }
297 if ((i == 0) && skip_page_for_first_entry)
298 /* First entry of Rx does not have page */
299 init_enet_offset = 0;
300 else {
301 init_enet_offset =
302 qe_muram_alloc(thread_size, thread_alignment);
Timur Tabi4c356302007-05-08 14:46:36 -0500303 if (IS_ERR_VALUE(init_enet_offset)) {
Li Yang890de952007-07-19 11:48:29 +0800304 if (netif_msg_ifup(ugeth))
305 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
Li Yangce973b12006-08-14 23:00:11 -0700306 qe_put_snum((u8) snum);
307 return -ENOMEM;
308 }
309 }
310 *(p_start++) =
311 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
312 | risc;
313 }
314
315 return 0;
316}
317
Li Yang18a8e862006-10-19 21:07:34 -0500318static int return_init_enet_entries(struct ucc_geth_private *ugeth,
Li Yangce973b12006-08-14 23:00:11 -0700319 volatile u32 *p_start,
320 u8 num_entries,
Li Yang18a8e862006-10-19 21:07:34 -0500321 enum qe_risc_allocation risc,
Li Yangce973b12006-08-14 23:00:11 -0700322 int skip_page_for_first_entry)
323{
324 u32 init_enet_offset;
325 u8 i;
326 int snum;
327
328 for (i = 0; i < num_entries; i++) {
329 /* Check that this entry was actually valid --
330 needed in case failed in allocations */
331 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
332 snum =
333 (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
334 ENET_INIT_PARAM_SNUM_SHIFT;
335 qe_put_snum((u8) snum);
336 if (!((i == 0) && skip_page_for_first_entry)) {
337 /* First entry of Rx does not have page */
338 init_enet_offset =
339 (in_be32(p_start) &
340 ENET_INIT_PARAM_PTR_MASK);
341 qe_muram_free(init_enet_offset);
342 }
343 *(p_start++) = 0; /* Just for cosmetics */
344 }
345 }
346
347 return 0;
348}
349
350#ifdef DEBUG
Li Yang18a8e862006-10-19 21:07:34 -0500351static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
Li Yangce973b12006-08-14 23:00:11 -0700352 volatile u32 *p_start,
353 u8 num_entries,
354 u32 thread_size,
Li Yang18a8e862006-10-19 21:07:34 -0500355 enum qe_risc_allocation risc,
Li Yangce973b12006-08-14 23:00:11 -0700356 int skip_page_for_first_entry)
357{
358 u32 init_enet_offset;
359 u8 i;
360 int snum;
361
362 for (i = 0; i < num_entries; i++) {
363 /* Check that this entry was actually valid --
364 needed in case failed in allocations */
365 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
366 snum =
367 (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
368 ENET_INIT_PARAM_SNUM_SHIFT;
369 qe_put_snum((u8) snum);
370 if (!((i == 0) && skip_page_for_first_entry)) {
371 /* First entry of Rx does not have page */
372 init_enet_offset =
373 (in_be32(p_start) &
374 ENET_INIT_PARAM_PTR_MASK);
375 ugeth_info("Init enet entry %d:", i);
376 ugeth_info("Base address: 0x%08x",
377 (u32)
378 qe_muram_addr(init_enet_offset));
379 mem_disp(qe_muram_addr(init_enet_offset),
380 thread_size);
381 }
382 p_start++;
383 }
384 }
385
386 return 0;
387}
388#endif
389
390#ifdef CONFIG_UGETH_FILTERING
Li Yang18a8e862006-10-19 21:07:34 -0500391static struct enet_addr_container *get_enet_addr_container(void)
Li Yangce973b12006-08-14 23:00:11 -0700392{
Li Yang18a8e862006-10-19 21:07:34 -0500393 struct enet_addr_container *enet_addr_cont;
Li Yangce973b12006-08-14 23:00:11 -0700394
395 /* allocate memory */
Li Yang18a8e862006-10-19 21:07:34 -0500396 enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
Li Yangce973b12006-08-14 23:00:11 -0700397 if (!enet_addr_cont) {
Li Yang18a8e862006-10-19 21:07:34 -0500398 ugeth_err("%s: No memory for enet_addr_container object.",
Li Yangce973b12006-08-14 23:00:11 -0700399 __FUNCTION__);
400 return NULL;
401 }
402
403 return enet_addr_cont;
404}
405#endif /* CONFIG_UGETH_FILTERING */
406
Li Yang18a8e862006-10-19 21:07:34 -0500407static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
Li Yangce973b12006-08-14 23:00:11 -0700408{
409 kfree(enet_addr_cont);
410}
411
Timur Tabidf19b6b2007-01-09 12:31:38 -0600412static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
Li Yangce973b12006-08-14 23:00:11 -0700413{
Li Yang18a8e862006-10-19 21:07:34 -0500414 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
415 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
416 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
417}
418
419#ifdef CONFIG_UGETH_FILTERING
420static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
421 u8 *p_enet_addr, u8 paddr_num)
422{
423 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
Li Yangce973b12006-08-14 23:00:11 -0700424
425 if (!(paddr_num < NUM_OF_PADDRS)) {
Li Yang18a8e862006-10-19 21:07:34 -0500426 ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -0700427 return -EINVAL;
428 }
429
430 p_82xx_addr_filt =
Li Yang18a8e862006-10-19 21:07:34 -0500431 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
Li Yangce973b12006-08-14 23:00:11 -0700432 addressfiltering;
433
434 /* Ethernet frames are defined in Little Endian mode, */
435 /* therefore to insert the address we reverse the bytes. */
Li Yang18a8e862006-10-19 21:07:34 -0500436 set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr);
Li Yangce973b12006-08-14 23:00:11 -0700437 return 0;
438}
439#endif /* CONFIG_UGETH_FILTERING */
440
Li Yang18a8e862006-10-19 21:07:34 -0500441static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
Li Yangce973b12006-08-14 23:00:11 -0700442{
Li Yang18a8e862006-10-19 21:07:34 -0500443 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
Li Yangce973b12006-08-14 23:00:11 -0700444
445 if (!(paddr_num < NUM_OF_PADDRS)) {
446 ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
447 return -EINVAL;
448 }
449
450 p_82xx_addr_filt =
Li Yang18a8e862006-10-19 21:07:34 -0500451 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
Li Yangce973b12006-08-14 23:00:11 -0700452 addressfiltering;
453
454 /* Writing address ff.ff.ff.ff.ff.ff disables address
455 recognition for this register */
456 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
457 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
458 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
459
460 return 0;
461}
462
Li Yang18a8e862006-10-19 21:07:34 -0500463static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
464 u8 *p_enet_addr)
Li Yangce973b12006-08-14 23:00:11 -0700465{
Li Yang18a8e862006-10-19 21:07:34 -0500466 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
Li Yangce973b12006-08-14 23:00:11 -0700467 u32 cecr_subblock;
468
469 p_82xx_addr_filt =
Li Yang18a8e862006-10-19 21:07:34 -0500470 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
Li Yangce973b12006-08-14 23:00:11 -0700471 addressfiltering;
472
473 cecr_subblock =
474 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
475
476 /* Ethernet frames are defined in Little Endian mode,
477 therefor to insert */
478 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
Li Yang18a8e862006-10-19 21:07:34 -0500479
480 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
Li Yangce973b12006-08-14 23:00:11 -0700481
482 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
Li Yang18a8e862006-10-19 21:07:34 -0500483 QE_CR_PROTOCOL_ETHERNET, 0);
Li Yangce973b12006-08-14 23:00:11 -0700484}
485
486#ifdef CONFIG_UGETH_MAGIC_PACKET
Li Yang18a8e862006-10-19 21:07:34 -0500487static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -0700488{
Li Yang18a8e862006-10-19 21:07:34 -0500489 struct ucc_fast_private *uccf;
490 struct ucc_geth *ug_regs;
Li Yangce973b12006-08-14 23:00:11 -0700491 u32 maccfg2, uccm;
492
493 uccf = ugeth->uccf;
494 ug_regs = ugeth->ug_regs;
495
496 /* Enable interrupts for magic packet detection */
497 uccm = in_be32(uccf->p_uccm);
498 uccm |= UCCE_MPD;
499 out_be32(uccf->p_uccm, uccm);
500
501 /* Enable magic packet detection */
502 maccfg2 = in_be32(&ug_regs->maccfg2);
503 maccfg2 |= MACCFG2_MPE;
504 out_be32(&ug_regs->maccfg2, maccfg2);
505}
506
Li Yang18a8e862006-10-19 21:07:34 -0500507static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -0700508{
Li Yang18a8e862006-10-19 21:07:34 -0500509 struct ucc_fast_private *uccf;
510 struct ucc_geth *ug_regs;
Li Yangce973b12006-08-14 23:00:11 -0700511 u32 maccfg2, uccm;
512
513 uccf = ugeth->uccf;
514 ug_regs = ugeth->ug_regs;
515
516 /* Disable interrupts for magic packet detection */
517 uccm = in_be32(uccf->p_uccm);
518 uccm &= ~UCCE_MPD;
519 out_be32(uccf->p_uccm, uccm);
520
521 /* Disable magic packet detection */
522 maccfg2 = in_be32(&ug_regs->maccfg2);
523 maccfg2 &= ~MACCFG2_MPE;
524 out_be32(&ug_regs->maccfg2, maccfg2);
525}
526#endif /* MAGIC_PACKET */
527
Li Yang18a8e862006-10-19 21:07:34 -0500528static inline int compare_addr(u8 **addr1, u8 **addr2)
Li Yangce973b12006-08-14 23:00:11 -0700529{
530 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
531}
532
533#ifdef DEBUG
Li Yang18a8e862006-10-19 21:07:34 -0500534static void get_statistics(struct ucc_geth_private *ugeth,
535 struct ucc_geth_tx_firmware_statistics *
Li Yangce973b12006-08-14 23:00:11 -0700536 tx_firmware_statistics,
Li Yang18a8e862006-10-19 21:07:34 -0500537 struct ucc_geth_rx_firmware_statistics *
Li Yangce973b12006-08-14 23:00:11 -0700538 rx_firmware_statistics,
Li Yang18a8e862006-10-19 21:07:34 -0500539 struct ucc_geth_hardware_statistics *hardware_statistics)
Li Yangce973b12006-08-14 23:00:11 -0700540{
Li Yang18a8e862006-10-19 21:07:34 -0500541 struct ucc_fast *uf_regs;
542 struct ucc_geth *ug_regs;
543 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
544 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
Li Yangce973b12006-08-14 23:00:11 -0700545
546 ug_regs = ugeth->ug_regs;
Li Yang18a8e862006-10-19 21:07:34 -0500547 uf_regs = (struct ucc_fast *) ug_regs;
Li Yangce973b12006-08-14 23:00:11 -0700548 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
549 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
550
551 /* Tx firmware only if user handed pointer and driver actually
552 gathers Tx firmware statistics */
553 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
554 tx_firmware_statistics->sicoltx =
555 in_be32(&p_tx_fw_statistics_pram->sicoltx);
556 tx_firmware_statistics->mulcoltx =
557 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
558 tx_firmware_statistics->latecoltxfr =
559 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
560 tx_firmware_statistics->frabortduecol =
561 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
562 tx_firmware_statistics->frlostinmactxer =
563 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
564 tx_firmware_statistics->carriersenseertx =
565 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
566 tx_firmware_statistics->frtxok =
567 in_be32(&p_tx_fw_statistics_pram->frtxok);
568 tx_firmware_statistics->txfrexcessivedefer =
569 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
570 tx_firmware_statistics->txpkts256 =
571 in_be32(&p_tx_fw_statistics_pram->txpkts256);
572 tx_firmware_statistics->txpkts512 =
573 in_be32(&p_tx_fw_statistics_pram->txpkts512);
574 tx_firmware_statistics->txpkts1024 =
575 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
576 tx_firmware_statistics->txpktsjumbo =
577 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
578 }
579
580 /* Rx firmware only if user handed pointer and driver actually
581 * gathers Rx firmware statistics */
582 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
583 int i;
584 rx_firmware_statistics->frrxfcser =
585 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
586 rx_firmware_statistics->fraligner =
587 in_be32(&p_rx_fw_statistics_pram->fraligner);
588 rx_firmware_statistics->inrangelenrxer =
589 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
590 rx_firmware_statistics->outrangelenrxer =
591 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
592 rx_firmware_statistics->frtoolong =
593 in_be32(&p_rx_fw_statistics_pram->frtoolong);
594 rx_firmware_statistics->runt =
595 in_be32(&p_rx_fw_statistics_pram->runt);
596 rx_firmware_statistics->verylongevent =
597 in_be32(&p_rx_fw_statistics_pram->verylongevent);
598 rx_firmware_statistics->symbolerror =
599 in_be32(&p_rx_fw_statistics_pram->symbolerror);
600 rx_firmware_statistics->dropbsy =
601 in_be32(&p_rx_fw_statistics_pram->dropbsy);
602 for (i = 0; i < 0x8; i++)
603 rx_firmware_statistics->res0[i] =
604 p_rx_fw_statistics_pram->res0[i];
605 rx_firmware_statistics->mismatchdrop =
606 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
607 rx_firmware_statistics->underpkts =
608 in_be32(&p_rx_fw_statistics_pram->underpkts);
609 rx_firmware_statistics->pkts256 =
610 in_be32(&p_rx_fw_statistics_pram->pkts256);
611 rx_firmware_statistics->pkts512 =
612 in_be32(&p_rx_fw_statistics_pram->pkts512);
613 rx_firmware_statistics->pkts1024 =
614 in_be32(&p_rx_fw_statistics_pram->pkts1024);
615 rx_firmware_statistics->pktsjumbo =
616 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
617 rx_firmware_statistics->frlossinmacer =
618 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
619 rx_firmware_statistics->pausefr =
620 in_be32(&p_rx_fw_statistics_pram->pausefr);
621 for (i = 0; i < 0x4; i++)
622 rx_firmware_statistics->res1[i] =
623 p_rx_fw_statistics_pram->res1[i];
624 rx_firmware_statistics->removevlan =
625 in_be32(&p_rx_fw_statistics_pram->removevlan);
626 rx_firmware_statistics->replacevlan =
627 in_be32(&p_rx_fw_statistics_pram->replacevlan);
628 rx_firmware_statistics->insertvlan =
629 in_be32(&p_rx_fw_statistics_pram->insertvlan);
630 }
631
632 /* Hardware only if user handed pointer and driver actually
633 gathers hardware statistics */
634 if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
635 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
636 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
637 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
638 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
639 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
640 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
641 hardware_statistics->txok = in_be32(&ug_regs->txok);
642 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
643 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
644 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
645 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
646 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
647 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
648 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
649 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
650 }
651}
652
Li Yang18a8e862006-10-19 21:07:34 -0500653static void dump_bds(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -0700654{
655 int i;
656 int length;
657
658 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
659 if (ugeth->p_tx_bd_ring[i]) {
660 length =
661 (ugeth->ug_info->bdRingLenTx[i] *
Li Yang18a8e862006-10-19 21:07:34 -0500662 sizeof(struct qe_bd));
Li Yangce973b12006-08-14 23:00:11 -0700663 ugeth_info("TX BDs[%d]", i);
664 mem_disp(ugeth->p_tx_bd_ring[i], length);
665 }
666 }
667 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
668 if (ugeth->p_rx_bd_ring[i]) {
669 length =
670 (ugeth->ug_info->bdRingLenRx[i] *
Li Yang18a8e862006-10-19 21:07:34 -0500671 sizeof(struct qe_bd));
Li Yangce973b12006-08-14 23:00:11 -0700672 ugeth_info("RX BDs[%d]", i);
673 mem_disp(ugeth->p_rx_bd_ring[i], length);
674 }
675 }
676}
677
Li Yang18a8e862006-10-19 21:07:34 -0500678static void dump_regs(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -0700679{
680 int i;
681
682 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
683 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
684
685 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
686 (u32) & ugeth->ug_regs->maccfg1,
687 in_be32(&ugeth->ug_regs->maccfg1));
688 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
689 (u32) & ugeth->ug_regs->maccfg2,
690 in_be32(&ugeth->ug_regs->maccfg2));
691 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
692 (u32) & ugeth->ug_regs->ipgifg,
693 in_be32(&ugeth->ug_regs->ipgifg));
694 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
695 (u32) & ugeth->ug_regs->hafdup,
696 in_be32(&ugeth->ug_regs->hafdup));
Li Yangce973b12006-08-14 23:00:11 -0700697 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
698 (u32) & ugeth->ug_regs->ifctl,
699 in_be32(&ugeth->ug_regs->ifctl));
700 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
701 (u32) & ugeth->ug_regs->ifstat,
702 in_be32(&ugeth->ug_regs->ifstat));
703 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
704 (u32) & ugeth->ug_regs->macstnaddr1,
705 in_be32(&ugeth->ug_regs->macstnaddr1));
706 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
707 (u32) & ugeth->ug_regs->macstnaddr2,
708 in_be32(&ugeth->ug_regs->macstnaddr2));
709 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
710 (u32) & ugeth->ug_regs->uempr,
711 in_be32(&ugeth->ug_regs->uempr));
712 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
713 (u32) & ugeth->ug_regs->utbipar,
714 in_be32(&ugeth->ug_regs->utbipar));
715 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
716 (u32) & ugeth->ug_regs->uescr,
717 in_be16(&ugeth->ug_regs->uescr));
718 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
719 (u32) & ugeth->ug_regs->tx64,
720 in_be32(&ugeth->ug_regs->tx64));
721 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
722 (u32) & ugeth->ug_regs->tx127,
723 in_be32(&ugeth->ug_regs->tx127));
724 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
725 (u32) & ugeth->ug_regs->tx255,
726 in_be32(&ugeth->ug_regs->tx255));
727 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
728 (u32) & ugeth->ug_regs->rx64,
729 in_be32(&ugeth->ug_regs->rx64));
730 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
731 (u32) & ugeth->ug_regs->rx127,
732 in_be32(&ugeth->ug_regs->rx127));
733 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
734 (u32) & ugeth->ug_regs->rx255,
735 in_be32(&ugeth->ug_regs->rx255));
736 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
737 (u32) & ugeth->ug_regs->txok,
738 in_be32(&ugeth->ug_regs->txok));
739 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
740 (u32) & ugeth->ug_regs->txcf,
741 in_be16(&ugeth->ug_regs->txcf));
742 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
743 (u32) & ugeth->ug_regs->tmca,
744 in_be32(&ugeth->ug_regs->tmca));
745 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
746 (u32) & ugeth->ug_regs->tbca,
747 in_be32(&ugeth->ug_regs->tbca));
748 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
749 (u32) & ugeth->ug_regs->rxfok,
750 in_be32(&ugeth->ug_regs->rxfok));
751 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
752 (u32) & ugeth->ug_regs->rxbok,
753 in_be32(&ugeth->ug_regs->rxbok));
754 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
755 (u32) & ugeth->ug_regs->rbyt,
756 in_be32(&ugeth->ug_regs->rbyt));
757 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
758 (u32) & ugeth->ug_regs->rmca,
759 in_be32(&ugeth->ug_regs->rmca));
760 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
761 (u32) & ugeth->ug_regs->rbca,
762 in_be32(&ugeth->ug_regs->rbca));
763 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
764 (u32) & ugeth->ug_regs->scar,
765 in_be32(&ugeth->ug_regs->scar));
766 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
767 (u32) & ugeth->ug_regs->scam,
768 in_be32(&ugeth->ug_regs->scam));
769
770 if (ugeth->p_thread_data_tx) {
771 int numThreadsTxNumerical;
772 switch (ugeth->ug_info->numThreadsTx) {
773 case UCC_GETH_NUM_OF_THREADS_1:
774 numThreadsTxNumerical = 1;
775 break;
776 case UCC_GETH_NUM_OF_THREADS_2:
777 numThreadsTxNumerical = 2;
778 break;
779 case UCC_GETH_NUM_OF_THREADS_4:
780 numThreadsTxNumerical = 4;
781 break;
782 case UCC_GETH_NUM_OF_THREADS_6:
783 numThreadsTxNumerical = 6;
784 break;
785 case UCC_GETH_NUM_OF_THREADS_8:
786 numThreadsTxNumerical = 8;
787 break;
788 default:
789 numThreadsTxNumerical = 0;
790 break;
791 }
792
793 ugeth_info("Thread data TXs:");
794 ugeth_info("Base address: 0x%08x",
795 (u32) ugeth->p_thread_data_tx);
796 for (i = 0; i < numThreadsTxNumerical; i++) {
797 ugeth_info("Thread data TX[%d]:", i);
798 ugeth_info("Base address: 0x%08x",
799 (u32) & ugeth->p_thread_data_tx[i]);
800 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
Li Yang18a8e862006-10-19 21:07:34 -0500801 sizeof(struct ucc_geth_thread_data_tx));
Li Yangce973b12006-08-14 23:00:11 -0700802 }
803 }
804 if (ugeth->p_thread_data_rx) {
805 int numThreadsRxNumerical;
806 switch (ugeth->ug_info->numThreadsRx) {
807 case UCC_GETH_NUM_OF_THREADS_1:
808 numThreadsRxNumerical = 1;
809 break;
810 case UCC_GETH_NUM_OF_THREADS_2:
811 numThreadsRxNumerical = 2;
812 break;
813 case UCC_GETH_NUM_OF_THREADS_4:
814 numThreadsRxNumerical = 4;
815 break;
816 case UCC_GETH_NUM_OF_THREADS_6:
817 numThreadsRxNumerical = 6;
818 break;
819 case UCC_GETH_NUM_OF_THREADS_8:
820 numThreadsRxNumerical = 8;
821 break;
822 default:
823 numThreadsRxNumerical = 0;
824 break;
825 }
826
827 ugeth_info("Thread data RX:");
828 ugeth_info("Base address: 0x%08x",
829 (u32) ugeth->p_thread_data_rx);
830 for (i = 0; i < numThreadsRxNumerical; i++) {
831 ugeth_info("Thread data RX[%d]:", i);
832 ugeth_info("Base address: 0x%08x",
833 (u32) & ugeth->p_thread_data_rx[i]);
834 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
Li Yang18a8e862006-10-19 21:07:34 -0500835 sizeof(struct ucc_geth_thread_data_rx));
Li Yangce973b12006-08-14 23:00:11 -0700836 }
837 }
838 if (ugeth->p_exf_glbl_param) {
839 ugeth_info("EXF global param:");
840 ugeth_info("Base address: 0x%08x",
841 (u32) ugeth->p_exf_glbl_param);
842 mem_disp((u8 *) ugeth->p_exf_glbl_param,
843 sizeof(*ugeth->p_exf_glbl_param));
844 }
845 if (ugeth->p_tx_glbl_pram) {
846 ugeth_info("TX global param:");
847 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
848 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
849 (u32) & ugeth->p_tx_glbl_pram->temoder,
850 in_be16(&ugeth->p_tx_glbl_pram->temoder));
851 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
852 (u32) & ugeth->p_tx_glbl_pram->sqptr,
853 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
854 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
855 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
856 in_be32(&ugeth->p_tx_glbl_pram->
857 schedulerbasepointer));
858 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
859 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
860 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
861 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
862 (u32) & ugeth->p_tx_glbl_pram->tstate,
863 in_be32(&ugeth->p_tx_glbl_pram->tstate));
864 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
865 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
866 ugeth->p_tx_glbl_pram->iphoffset[0]);
867 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
868 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
869 ugeth->p_tx_glbl_pram->iphoffset[1]);
870 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
871 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
872 ugeth->p_tx_glbl_pram->iphoffset[2]);
873 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
874 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
875 ugeth->p_tx_glbl_pram->iphoffset[3]);
876 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
877 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
878 ugeth->p_tx_glbl_pram->iphoffset[4]);
879 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
880 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
881 ugeth->p_tx_glbl_pram->iphoffset[5]);
882 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
883 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
884 ugeth->p_tx_glbl_pram->iphoffset[6]);
885 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
886 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
887 ugeth->p_tx_glbl_pram->iphoffset[7]);
888 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
889 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
890 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
891 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
892 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
893 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
894 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
895 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
896 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
897 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
898 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
899 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
900 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
901 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
902 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
903 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
904 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
905 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
906 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
907 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
908 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
909 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
910 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
911 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
912 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
913 (u32) & ugeth->p_tx_glbl_pram->tqptr,
914 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
915 }
916 if (ugeth->p_rx_glbl_pram) {
917 ugeth_info("RX global param:");
918 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
919 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
920 (u32) & ugeth->p_rx_glbl_pram->remoder,
921 in_be32(&ugeth->p_rx_glbl_pram->remoder));
922 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
923 (u32) & ugeth->p_rx_glbl_pram->rqptr,
924 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
925 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
926 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
927 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
928 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
929 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
930 ugeth->p_rx_glbl_pram->rxgstpack);
931 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
932 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
933 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
934 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
935 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
936 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
937 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
938 (u32) & ugeth->p_rx_glbl_pram->rstate,
939 ugeth->p_rx_glbl_pram->rstate);
940 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
941 (u32) & ugeth->p_rx_glbl_pram->mrblr,
942 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
943 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
944 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
945 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
946 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
947 (u32) & ugeth->p_rx_glbl_pram->mflr,
948 in_be16(&ugeth->p_rx_glbl_pram->mflr));
949 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
950 (u32) & ugeth->p_rx_glbl_pram->minflr,
951 in_be16(&ugeth->p_rx_glbl_pram->minflr));
952 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
953 (u32) & ugeth->p_rx_glbl_pram->maxd1,
954 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
955 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
956 (u32) & ugeth->p_rx_glbl_pram->maxd2,
957 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
958 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
959 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
960 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
961 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
962 (u32) & ugeth->p_rx_glbl_pram->l2qt,
963 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
964 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
965 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
966 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
967 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
968 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
969 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
970 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
971 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
972 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
973 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
974 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
975 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
976 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
977 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
978 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
979 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
980 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
981 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
982 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
983 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
984 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
985 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
986 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
987 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
988 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
989 (u32) & ugeth->p_rx_glbl_pram->vlantype,
990 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
991 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
992 (u32) & ugeth->p_rx_glbl_pram->vlantci,
993 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
994 for (i = 0; i < 64; i++)
995 ugeth_info
996 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
997 i,
998 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
999 ugeth->p_rx_glbl_pram->addressfiltering[i]);
1000 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
1001 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
1002 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
1003 }
1004 if (ugeth->p_send_q_mem_reg) {
1005 ugeth_info("Send Q memory registers:");
1006 ugeth_info("Base address: 0x%08x",
1007 (u32) ugeth->p_send_q_mem_reg);
1008 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1009 ugeth_info("SQQD[%d]:", i);
1010 ugeth_info("Base address: 0x%08x",
1011 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
1012 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
Li Yang18a8e862006-10-19 21:07:34 -05001013 sizeof(struct ucc_geth_send_queue_qd));
Li Yangce973b12006-08-14 23:00:11 -07001014 }
1015 }
1016 if (ugeth->p_scheduler) {
1017 ugeth_info("Scheduler:");
1018 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
1019 mem_disp((u8 *) ugeth->p_scheduler,
1020 sizeof(*ugeth->p_scheduler));
1021 }
1022 if (ugeth->p_tx_fw_statistics_pram) {
1023 ugeth_info("TX FW statistics pram:");
1024 ugeth_info("Base address: 0x%08x",
1025 (u32) ugeth->p_tx_fw_statistics_pram);
1026 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
1027 sizeof(*ugeth->p_tx_fw_statistics_pram));
1028 }
1029 if (ugeth->p_rx_fw_statistics_pram) {
1030 ugeth_info("RX FW statistics pram:");
1031 ugeth_info("Base address: 0x%08x",
1032 (u32) ugeth->p_rx_fw_statistics_pram);
1033 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
1034 sizeof(*ugeth->p_rx_fw_statistics_pram));
1035 }
1036 if (ugeth->p_rx_irq_coalescing_tbl) {
1037 ugeth_info("RX IRQ coalescing tables:");
1038 ugeth_info("Base address: 0x%08x",
1039 (u32) ugeth->p_rx_irq_coalescing_tbl);
1040 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1041 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
1042 ugeth_info("Base address: 0x%08x",
1043 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1044 coalescingentry[i]);
1045 ugeth_info
1046 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1047 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1048 coalescingentry[i].interruptcoalescingmaxvalue,
1049 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1050 coalescingentry[i].
1051 interruptcoalescingmaxvalue));
1052 ugeth_info
1053 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1054 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1055 coalescingentry[i].interruptcoalescingcounter,
1056 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1057 coalescingentry[i].
1058 interruptcoalescingcounter));
1059 }
1060 }
1061 if (ugeth->p_rx_bd_qs_tbl) {
1062 ugeth_info("RX BD QS tables:");
1063 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1064 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1065 ugeth_info("RX BD QS table[%d]:", i);
1066 ugeth_info("Base address: 0x%08x",
1067 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1068 ugeth_info
1069 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1070 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1071 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1072 ugeth_info
1073 ("bdptr : addr - 0x%08x, val - 0x%08x",
1074 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1075 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1076 ugeth_info
1077 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1078 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1079 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1080 externalbdbaseptr));
1081 ugeth_info
1082 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1083 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1084 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1085 ugeth_info("ucode RX Prefetched BDs:");
1086 ugeth_info("Base address: 0x%08x",
1087 (u32)
1088 qe_muram_addr(in_be32
1089 (&ugeth->p_rx_bd_qs_tbl[i].
1090 bdbaseptr)));
1091 mem_disp((u8 *)
1092 qe_muram_addr(in_be32
1093 (&ugeth->p_rx_bd_qs_tbl[i].
1094 bdbaseptr)),
Li Yang18a8e862006-10-19 21:07:34 -05001095 sizeof(struct ucc_geth_rx_prefetched_bds));
Li Yangce973b12006-08-14 23:00:11 -07001096 }
1097 }
1098 if (ugeth->p_init_enet_param_shadow) {
1099 int size;
1100 ugeth_info("Init enet param shadow:");
1101 ugeth_info("Base address: 0x%08x",
1102 (u32) ugeth->p_init_enet_param_shadow);
1103 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1104 sizeof(*ugeth->p_init_enet_param_shadow));
1105
Li Yang18a8e862006-10-19 21:07:34 -05001106 size = sizeof(struct ucc_geth_thread_rx_pram);
Li Yangce973b12006-08-14 23:00:11 -07001107 if (ugeth->ug_info->rxExtendedFiltering) {
1108 size +=
1109 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1110 if (ugeth->ug_info->largestexternallookupkeysize ==
1111 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1112 size +=
1113 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1114 if (ugeth->ug_info->largestexternallookupkeysize ==
1115 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1116 size +=
1117 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1118 }
1119
1120 dump_init_enet_entries(ugeth,
1121 &(ugeth->p_init_enet_param_shadow->
1122 txthread[0]),
1123 ENET_INIT_PARAM_MAX_ENTRIES_TX,
Li Yang18a8e862006-10-19 21:07:34 -05001124 sizeof(struct ucc_geth_thread_tx_pram),
Li Yangce973b12006-08-14 23:00:11 -07001125 ugeth->ug_info->riscTx, 0);
1126 dump_init_enet_entries(ugeth,
1127 &(ugeth->p_init_enet_param_shadow->
1128 rxthread[0]),
1129 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1130 ugeth->ug_info->riscRx, 1);
1131 }
1132}
1133#endif /* DEBUG */
1134
1135static void init_default_reg_vals(volatile u32 *upsmr_register,
1136 volatile u32 *maccfg1_register,
1137 volatile u32 *maccfg2_register)
1138{
1139 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1140 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1141 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1142}
1143
1144static int init_half_duplex_params(int alt_beb,
1145 int back_pressure_no_backoff,
1146 int no_backoff,
1147 int excess_defer,
1148 u8 alt_beb_truncation,
1149 u8 max_retransmissions,
1150 u8 collision_window,
1151 volatile u32 *hafdup_register)
1152{
1153 u32 value = 0;
1154
1155 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1156 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1157 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1158 return -EINVAL;
1159
1160 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1161
1162 if (alt_beb)
1163 value |= HALFDUP_ALT_BEB;
1164 if (back_pressure_no_backoff)
1165 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1166 if (no_backoff)
1167 value |= HALFDUP_NO_BACKOFF;
1168 if (excess_defer)
1169 value |= HALFDUP_EXCESSIVE_DEFER;
1170
1171 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1172
1173 value |= collision_window;
1174
1175 out_be32(hafdup_register, value);
1176 return 0;
1177}
1178
1179static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1180 u8 non_btb_ipg,
1181 u8 min_ifg,
1182 u8 btb_ipg,
1183 volatile u32 *ipgifg_register)
1184{
1185 u32 value = 0;
1186
1187 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1188 IPG part 2 */
1189 if (non_btb_cs_ipg > non_btb_ipg)
1190 return -EINVAL;
1191
1192 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1193 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1194 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1195 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1196 return -EINVAL;
1197
1198 value |=
1199 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1200 IPGIFG_NBTB_CS_IPG_MASK);
1201 value |=
1202 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1203 IPGIFG_NBTB_IPG_MASK);
1204 value |=
1205 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1206 IPGIFG_MIN_IFG_MASK);
1207 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1208
1209 out_be32(ipgifg_register, value);
1210 return 0;
1211}
1212
Li Yangac421852007-07-19 11:47:47 +08001213int init_flow_control_params(u32 automatic_flow_control_mode,
Li Yangce973b12006-08-14 23:00:11 -07001214 int rx_flow_control_enable,
1215 int tx_flow_control_enable,
1216 u16 pause_period,
1217 u16 extension_field,
1218 volatile u32 *upsmr_register,
1219 volatile u32 *uempr_register,
1220 volatile u32 *maccfg1_register)
1221{
1222 u32 value = 0;
1223
1224 /* Set UEMPR register */
1225 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1226 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1227 out_be32(uempr_register, value);
1228
1229 /* Set UPSMR register */
1230 value = in_be32(upsmr_register);
1231 value |= automatic_flow_control_mode;
1232 out_be32(upsmr_register, value);
1233
1234 value = in_be32(maccfg1_register);
1235 if (rx_flow_control_enable)
1236 value |= MACCFG1_FLOW_RX;
1237 if (tx_flow_control_enable)
1238 value |= MACCFG1_FLOW_TX;
1239 out_be32(maccfg1_register, value);
1240
1241 return 0;
1242}
1243
1244static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1245 int auto_zero_hardware_statistics,
1246 volatile u32 *upsmr_register,
1247 volatile u16 *uescr_register)
1248{
1249 u32 upsmr_value = 0;
1250 u16 uescr_value = 0;
1251 /* Enable hardware statistics gathering if requested */
1252 if (enable_hardware_statistics) {
1253 upsmr_value = in_be32(upsmr_register);
1254 upsmr_value |= UPSMR_HSE;
1255 out_be32(upsmr_register, upsmr_value);
1256 }
1257
1258 /* Clear hardware statistics counters */
1259 uescr_value = in_be16(uescr_register);
1260 uescr_value |= UESCR_CLRCNT;
1261 /* Automatically zero hardware statistics counters on read,
1262 if requested */
1263 if (auto_zero_hardware_statistics)
1264 uescr_value |= UESCR_AUTOZ;
1265 out_be16(uescr_register, uescr_value);
1266
1267 return 0;
1268}
1269
1270static int init_firmware_statistics_gathering_mode(int
1271 enable_tx_firmware_statistics,
1272 int enable_rx_firmware_statistics,
1273 volatile u32 *tx_rmon_base_ptr,
1274 u32 tx_firmware_statistics_structure_address,
1275 volatile u32 *rx_rmon_base_ptr,
1276 u32 rx_firmware_statistics_structure_address,
1277 volatile u16 *temoder_register,
1278 volatile u32 *remoder_register)
1279{
1280 /* Note: this function does not check if */
1281 /* the parameters it receives are NULL */
1282 u16 temoder_value;
1283 u32 remoder_value;
1284
1285 if (enable_tx_firmware_statistics) {
1286 out_be32(tx_rmon_base_ptr,
1287 tx_firmware_statistics_structure_address);
1288 temoder_value = in_be16(temoder_register);
1289 temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
1290 out_be16(temoder_register, temoder_value);
1291 }
1292
1293 if (enable_rx_firmware_statistics) {
1294 out_be32(rx_rmon_base_ptr,
1295 rx_firmware_statistics_structure_address);
1296 remoder_value = in_be32(remoder_register);
1297 remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
1298 out_be32(remoder_register, remoder_value);
1299 }
1300
1301 return 0;
1302}
1303
1304static int init_mac_station_addr_regs(u8 address_byte_0,
1305 u8 address_byte_1,
1306 u8 address_byte_2,
1307 u8 address_byte_3,
1308 u8 address_byte_4,
1309 u8 address_byte_5,
1310 volatile u32 *macstnaddr1_register,
1311 volatile u32 *macstnaddr2_register)
1312{
1313 u32 value = 0;
1314
1315 /* Example: for a station address of 0x12345678ABCD, */
1316 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1317
1318 /* MACSTNADDR1 Register: */
1319
1320 /* 0 7 8 15 */
1321 /* station address byte 5 station address byte 4 */
1322 /* 16 23 24 31 */
1323 /* station address byte 3 station address byte 2 */
1324 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1325 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1326 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1327 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1328
1329 out_be32(macstnaddr1_register, value);
1330
1331 /* MACSTNADDR2 Register: */
1332
1333 /* 0 7 8 15 */
1334 /* station address byte 1 station address byte 0 */
1335 /* 16 23 24 31 */
1336 /* reserved reserved */
1337 value = 0;
1338 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1339 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1340
1341 out_be32(macstnaddr2_register, value);
1342
1343 return 0;
1344}
1345
Li Yangce973b12006-08-14 23:00:11 -07001346static int init_check_frame_length_mode(int length_check,
1347 volatile u32 *maccfg2_register)
1348{
1349 u32 value = 0;
1350
1351 value = in_be32(maccfg2_register);
1352
1353 if (length_check)
1354 value |= MACCFG2_LC;
1355 else
1356 value &= ~MACCFG2_LC;
1357
1358 out_be32(maccfg2_register, value);
1359 return 0;
1360}
1361
1362static int init_preamble_length(u8 preamble_length,
1363 volatile u32 *maccfg2_register)
1364{
1365 u32 value = 0;
1366
1367 if ((preamble_length < 3) || (preamble_length > 7))
1368 return -EINVAL;
1369
1370 value = in_be32(maccfg2_register);
1371 value &= ~MACCFG2_PREL_MASK;
1372 value |= (preamble_length << MACCFG2_PREL_SHIFT);
1373 out_be32(maccfg2_register, value);
1374 return 0;
1375}
1376
Li Yangce973b12006-08-14 23:00:11 -07001377static int init_rx_parameters(int reject_broadcast,
1378 int receive_short_frames,
1379 int promiscuous, volatile u32 *upsmr_register)
1380{
1381 u32 value = 0;
1382
1383 value = in_be32(upsmr_register);
1384
1385 if (reject_broadcast)
1386 value |= UPSMR_BRO;
1387 else
1388 value &= ~UPSMR_BRO;
1389
1390 if (receive_short_frames)
1391 value |= UPSMR_RSH;
1392 else
1393 value &= ~UPSMR_RSH;
1394
1395 if (promiscuous)
1396 value |= UPSMR_PRO;
1397 else
1398 value &= ~UPSMR_PRO;
1399
1400 out_be32(upsmr_register, value);
1401
1402 return 0;
1403}
1404
1405static int init_max_rx_buff_len(u16 max_rx_buf_len,
1406 volatile u16 *mrblr_register)
1407{
1408 /* max_rx_buf_len value must be a multiple of 128 */
1409 if ((max_rx_buf_len == 0)
1410 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1411 return -EINVAL;
1412
1413 out_be16(mrblr_register, max_rx_buf_len);
1414 return 0;
1415}
1416
1417static int init_min_frame_len(u16 min_frame_length,
1418 volatile u16 *minflr_register,
1419 volatile u16 *mrblr_register)
1420{
1421 u16 mrblr_value = 0;
1422
1423 mrblr_value = in_be16(mrblr_register);
1424 if (min_frame_length >= (mrblr_value - 4))
1425 return -EINVAL;
1426
1427 out_be16(minflr_register, min_frame_length);
1428 return 0;
1429}
1430
Li Yang18a8e862006-10-19 21:07:34 -05001431static int adjust_enet_interface(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -07001432{
Li Yang18a8e862006-10-19 21:07:34 -05001433 struct ucc_geth_info *ug_info;
1434 struct ucc_geth *ug_regs;
1435 struct ucc_fast *uf_regs;
Kim Phillips728de4c92007-04-13 01:26:03 -05001436 int ret_val;
1437 u32 upsmr, maccfg2, tbiBaseAddress;
Li Yangce973b12006-08-14 23:00:11 -07001438 u16 value;
1439
1440 ugeth_vdbg("%s: IN", __FUNCTION__);
1441
1442 ug_info = ugeth->ug_info;
1443 ug_regs = ugeth->ug_regs;
1444 uf_regs = ugeth->uccf->uf_regs;
1445
Li Yangce973b12006-08-14 23:00:11 -07001446 /* Set MACCFG2 */
1447 maccfg2 = in_be32(&ug_regs->maccfg2);
1448 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
Kim Phillips728de4c92007-04-13 01:26:03 -05001449 if ((ugeth->max_speed == SPEED_10) ||
1450 (ugeth->max_speed == SPEED_100))
Li Yangce973b12006-08-14 23:00:11 -07001451 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
Kim Phillips728de4c92007-04-13 01:26:03 -05001452 else if (ugeth->max_speed == SPEED_1000)
Li Yangce973b12006-08-14 23:00:11 -07001453 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1454 maccfg2 |= ug_info->padAndCrc;
1455 out_be32(&ug_regs->maccfg2, maccfg2);
1456
1457 /* Set UPSMR */
1458 upsmr = in_be32(&uf_regs->upsmr);
1459 upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
Kim Phillips728de4c92007-04-13 01:26:03 -05001460 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1461 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1462 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1463 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
Li Yangce973b12006-08-14 23:00:11 -07001464 upsmr |= UPSMR_RPM;
Kim Phillips728de4c92007-04-13 01:26:03 -05001465 switch (ugeth->max_speed) {
1466 case SPEED_10:
1467 upsmr |= UPSMR_R10M;
1468 /* FALLTHROUGH */
1469 case SPEED_100:
1470 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1471 upsmr |= UPSMR_RMM;
1472 }
1473 }
1474 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1475 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
Li Yangce973b12006-08-14 23:00:11 -07001476 upsmr |= UPSMR_TBIM;
Kim Phillips728de4c92007-04-13 01:26:03 -05001477 }
Li Yangce973b12006-08-14 23:00:11 -07001478 out_be32(&uf_regs->upsmr, upsmr);
1479
Li Yangce973b12006-08-14 23:00:11 -07001480 /* Disable autonegotiation in tbi mode, because by default it
1481 comes up in autonegotiation mode. */
1482 /* Note that this depends on proper setting in utbipar register. */
Kim Phillips728de4c92007-04-13 01:26:03 -05001483 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1484 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
Li Yangce973b12006-08-14 23:00:11 -07001485 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1486 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1487 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
Kim Phillips728de4c92007-04-13 01:26:03 -05001488 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1489 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
Li Yangce973b12006-08-14 23:00:11 -07001490 value &= ~0x1000; /* Turn off autonegotiation */
Kim Phillips728de4c92007-04-13 01:26:03 -05001491 ugeth->phydev->bus->write(ugeth->phydev->bus,
1492 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
Li Yangce973b12006-08-14 23:00:11 -07001493 }
1494
1495 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1496
1497 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1498 if (ret_val != 0) {
Li Yang890de952007-07-19 11:48:29 +08001499 if (netif_msg_probe(ugeth))
1500 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1501 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07001502 return ret_val;
1503 }
1504
1505 return 0;
1506}
1507
1508/* Called every time the controller might need to be made
1509 * aware of new link state. The PHY code conveys this
1510 * information through variables in the ugeth structure, and this
1511 * function converts those variables into the appropriate
1512 * register values, and can bring down the device if needed.
1513 */
Kim Phillips728de4c92007-04-13 01:26:03 -05001514
Li Yangce973b12006-08-14 23:00:11 -07001515static void adjust_link(struct net_device *dev)
1516{
Li Yang18a8e862006-10-19 21:07:34 -05001517 struct ucc_geth_private *ugeth = netdev_priv(dev);
1518 struct ucc_geth *ug_regs;
Kim Phillips728de4c92007-04-13 01:26:03 -05001519 struct ucc_fast *uf_regs;
1520 struct phy_device *phydev = ugeth->phydev;
1521 unsigned long flags;
1522 int new_state = 0;
Li Yangce973b12006-08-14 23:00:11 -07001523
1524 ug_regs = ugeth->ug_regs;
Kim Phillips728de4c92007-04-13 01:26:03 -05001525 uf_regs = ugeth->uccf->uf_regs;
Li Yangce973b12006-08-14 23:00:11 -07001526
Kim Phillips728de4c92007-04-13 01:26:03 -05001527 spin_lock_irqsave(&ugeth->lock, flags);
1528
1529 if (phydev->link) {
1530 u32 tempval = in_be32(&ug_regs->maccfg2);
1531 u32 upsmr = in_be32(&uf_regs->upsmr);
Li Yangce973b12006-08-14 23:00:11 -07001532 /* Now we make sure that we can be in full duplex mode.
1533 * If not, we operate in half-duplex mode. */
Kim Phillips728de4c92007-04-13 01:26:03 -05001534 if (phydev->duplex != ugeth->oldduplex) {
1535 new_state = 1;
1536 if (!(phydev->duplex))
Li Yangce973b12006-08-14 23:00:11 -07001537 tempval &= ~(MACCFG2_FDX);
Kim Phillips728de4c92007-04-13 01:26:03 -05001538 else
Li Yangce973b12006-08-14 23:00:11 -07001539 tempval |= MACCFG2_FDX;
Kim Phillips728de4c92007-04-13 01:26:03 -05001540 ugeth->oldduplex = phydev->duplex;
Li Yangce973b12006-08-14 23:00:11 -07001541 }
1542
Kim Phillips728de4c92007-04-13 01:26:03 -05001543 if (phydev->speed != ugeth->oldspeed) {
1544 new_state = 1;
1545 switch (phydev->speed) {
1546 case SPEED_1000:
1547 tempval = ((tempval &
1548 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1549 MACCFG2_INTERFACE_MODE_BYTE);
Li Yangce973b12006-08-14 23:00:11 -07001550 break;
Kim Phillips728de4c92007-04-13 01:26:03 -05001551 case SPEED_100:
1552 case SPEED_10:
1553 tempval = ((tempval &
1554 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1555 MACCFG2_INTERFACE_MODE_NIBBLE);
1556 /* if reduced mode, re-set UPSMR.R10M */
1557 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1558 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1559 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1560 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1561 if (phydev->speed == SPEED_10)
1562 upsmr |= UPSMR_R10M;
1563 else
1564 upsmr &= ~(UPSMR_R10M);
1565 }
Li Yangce973b12006-08-14 23:00:11 -07001566 break;
1567 default:
Kim Phillips728de4c92007-04-13 01:26:03 -05001568 if (netif_msg_link(ugeth))
1569 ugeth_warn(
1570 "%s: Ack! Speed (%d) is not 10/100/1000!",
1571 dev->name, phydev->speed);
Li Yangce973b12006-08-14 23:00:11 -07001572 break;
1573 }
Kim Phillips728de4c92007-04-13 01:26:03 -05001574 ugeth->oldspeed = phydev->speed;
Li Yangce973b12006-08-14 23:00:11 -07001575 }
1576
Kim Phillips728de4c92007-04-13 01:26:03 -05001577 out_be32(&ug_regs->maccfg2, tempval);
1578 out_be32(&uf_regs->upsmr, upsmr);
1579
Li Yangce973b12006-08-14 23:00:11 -07001580 if (!ugeth->oldlink) {
Kim Phillips728de4c92007-04-13 01:26:03 -05001581 new_state = 1;
Li Yangce973b12006-08-14 23:00:11 -07001582 ugeth->oldlink = 1;
Li Yangce973b12006-08-14 23:00:11 -07001583 netif_schedule(dev);
1584 }
Kim Phillips728de4c92007-04-13 01:26:03 -05001585 } else if (ugeth->oldlink) {
1586 new_state = 1;
Li Yangce973b12006-08-14 23:00:11 -07001587 ugeth->oldlink = 0;
1588 ugeth->oldspeed = 0;
1589 ugeth->oldduplex = -1;
Li Yangce973b12006-08-14 23:00:11 -07001590 }
Kim Phillips728de4c92007-04-13 01:26:03 -05001591
1592 if (new_state && netif_msg_link(ugeth))
1593 phy_print_status(phydev);
1594
1595 spin_unlock_irqrestore(&ugeth->lock, flags);
Li Yangce973b12006-08-14 23:00:11 -07001596}
1597
1598/* Configure the PHY for dev.
1599 * returns 0 if success. -1 if failure
1600 */
1601static int init_phy(struct net_device *dev)
1602{
Kim Phillips728de4c92007-04-13 01:26:03 -05001603 struct ucc_geth_private *priv = netdev_priv(dev);
1604 struct phy_device *phydev;
1605 char phy_id[BUS_ID_SIZE];
Li Yangce973b12006-08-14 23:00:11 -07001606
Kim Phillips728de4c92007-04-13 01:26:03 -05001607 priv->oldlink = 0;
1608 priv->oldspeed = 0;
1609 priv->oldduplex = -1;
Li Yangce973b12006-08-14 23:00:11 -07001610
Kim Phillips728de4c92007-04-13 01:26:03 -05001611 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->ug_info->mdio_bus,
1612 priv->ug_info->phy_address);
Li Yangce973b12006-08-14 23:00:11 -07001613
Kim Phillips728de4c92007-04-13 01:26:03 -05001614 phydev = phy_connect(dev, phy_id, &adjust_link, 0, priv->phy_interface);
Li Yangce973b12006-08-14 23:00:11 -07001615
Kim Phillips728de4c92007-04-13 01:26:03 -05001616 if (IS_ERR(phydev)) {
1617 printk("%s: Could not attach to PHY\n", dev->name);
1618 return PTR_ERR(phydev);
Li Yangce973b12006-08-14 23:00:11 -07001619 }
1620
Kim Phillips728de4c92007-04-13 01:26:03 -05001621 phydev->supported &= (ADVERTISED_10baseT_Half |
Li Yangce973b12006-08-14 23:00:11 -07001622 ADVERTISED_10baseT_Full |
1623 ADVERTISED_100baseT_Half |
Kim Phillips728de4c92007-04-13 01:26:03 -05001624 ADVERTISED_100baseT_Full);
Li Yangce973b12006-08-14 23:00:11 -07001625
Kim Phillips728de4c92007-04-13 01:26:03 -05001626 if (priv->max_speed == SPEED_1000)
1627 phydev->supported |= ADVERTISED_1000baseT_Full;
Li Yangce973b12006-08-14 23:00:11 -07001628
Kim Phillips728de4c92007-04-13 01:26:03 -05001629 phydev->advertising = phydev->supported;
Li Yangce973b12006-08-14 23:00:11 -07001630
Kim Phillips728de4c92007-04-13 01:26:03 -05001631 priv->phydev = phydev;
Li Yangce973b12006-08-14 23:00:11 -07001632
1633 return 0;
Li Yangce973b12006-08-14 23:00:11 -07001634}
1635
Kim Phillips728de4c92007-04-13 01:26:03 -05001636
Li Yangce973b12006-08-14 23:00:11 -07001637
Li Yang18a8e862006-10-19 21:07:34 -05001638static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -07001639{
Li Yang18a8e862006-10-19 21:07:34 -05001640 struct ucc_fast_private *uccf;
Li Yangce973b12006-08-14 23:00:11 -07001641 u32 cecr_subblock;
1642 u32 temp;
1643
1644 uccf = ugeth->uccf;
1645
1646 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1647 temp = in_be32(uccf->p_uccm);
1648 temp &= ~UCCE_GRA;
1649 out_be32(uccf->p_uccm, temp);
1650 out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */
1651
1652 /* Issue host command */
1653 cecr_subblock =
1654 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1655 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
Li Yang18a8e862006-10-19 21:07:34 -05001656 QE_CR_PROTOCOL_ETHERNET, 0);
Li Yangce973b12006-08-14 23:00:11 -07001657
1658 /* Wait for command to complete */
1659 do {
1660 temp = in_be32(uccf->p_ucce);
1661 } while (!(temp & UCCE_GRA));
1662
1663 uccf->stopped_tx = 1;
1664
1665 return 0;
1666}
1667
Li Yang18a8e862006-10-19 21:07:34 -05001668static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
Li Yangce973b12006-08-14 23:00:11 -07001669{
Li Yang18a8e862006-10-19 21:07:34 -05001670 struct ucc_fast_private *uccf;
Li Yangce973b12006-08-14 23:00:11 -07001671 u32 cecr_subblock;
1672 u8 temp;
1673
1674 uccf = ugeth->uccf;
1675
1676 /* Clear acknowledge bit */
1677 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1678 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1679 ugeth->p_rx_glbl_pram->rxgstpack = temp;
1680
1681 /* Keep issuing command and checking acknowledge bit until
1682 it is asserted, according to spec */
1683 do {
1684 /* Issue host command */
1685 cecr_subblock =
1686 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1687 ucc_num);
1688 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
Li Yang18a8e862006-10-19 21:07:34 -05001689 QE_CR_PROTOCOL_ETHERNET, 0);
Li Yangce973b12006-08-14 23:00:11 -07001690
1691 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1692 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX));
1693
1694 uccf->stopped_rx = 1;
1695
1696 return 0;
1697}
1698
Li Yang18a8e862006-10-19 21:07:34 -05001699static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -07001700{
Li Yang18a8e862006-10-19 21:07:34 -05001701 struct ucc_fast_private *uccf;
Li Yangce973b12006-08-14 23:00:11 -07001702 u32 cecr_subblock;
1703
1704 uccf = ugeth->uccf;
1705
1706 cecr_subblock =
1707 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
Li Yang18a8e862006-10-19 21:07:34 -05001708 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
Li Yangce973b12006-08-14 23:00:11 -07001709 uccf->stopped_tx = 0;
1710
1711 return 0;
1712}
1713
Li Yang18a8e862006-10-19 21:07:34 -05001714static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -07001715{
Li Yang18a8e862006-10-19 21:07:34 -05001716 struct ucc_fast_private *uccf;
Li Yangce973b12006-08-14 23:00:11 -07001717 u32 cecr_subblock;
1718
1719 uccf = ugeth->uccf;
1720
1721 cecr_subblock =
1722 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
Li Yang18a8e862006-10-19 21:07:34 -05001723 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
Li Yangce973b12006-08-14 23:00:11 -07001724 0);
1725 uccf->stopped_rx = 0;
1726
1727 return 0;
1728}
1729
Li Yang18a8e862006-10-19 21:07:34 -05001730static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
Li Yangce973b12006-08-14 23:00:11 -07001731{
Li Yang18a8e862006-10-19 21:07:34 -05001732 struct ucc_fast_private *uccf;
Li Yangce973b12006-08-14 23:00:11 -07001733 int enabled_tx, enabled_rx;
1734
1735 uccf = ugeth->uccf;
1736
1737 /* check if the UCC number is in range. */
1738 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
Li Yang890de952007-07-19 11:48:29 +08001739 if (netif_msg_probe(ugeth))
1740 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07001741 return -EINVAL;
1742 }
1743
1744 enabled_tx = uccf->enabled_tx;
1745 enabled_rx = uccf->enabled_rx;
1746
1747 /* Get Tx and Rx going again, in case this channel was actively
1748 disabled. */
1749 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1750 ugeth_restart_tx(ugeth);
1751 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1752 ugeth_restart_rx(ugeth);
1753
1754 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1755
1756 return 0;
1757
1758}
1759
Li Yang18a8e862006-10-19 21:07:34 -05001760static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
Li Yangce973b12006-08-14 23:00:11 -07001761{
Li Yang18a8e862006-10-19 21:07:34 -05001762 struct ucc_fast_private *uccf;
Li Yangce973b12006-08-14 23:00:11 -07001763
1764 uccf = ugeth->uccf;
1765
1766 /* check if the UCC number is in range. */
1767 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
Li Yang890de952007-07-19 11:48:29 +08001768 if (netif_msg_probe(ugeth))
1769 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07001770 return -EINVAL;
1771 }
1772
1773 /* Stop any transmissions */
1774 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1775 ugeth_graceful_stop_tx(ugeth);
1776
1777 /* Stop any receptions */
1778 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1779 ugeth_graceful_stop_rx(ugeth);
1780
1781 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1782
1783 return 0;
1784}
1785
Li Yang18a8e862006-10-19 21:07:34 -05001786static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -07001787{
1788#ifdef DEBUG
1789 ucc_fast_dump_regs(ugeth->uccf);
1790 dump_regs(ugeth);
1791 dump_bds(ugeth);
1792#endif
1793}
1794
1795#ifdef CONFIG_UGETH_FILTERING
Li Yang18a8e862006-10-19 21:07:34 -05001796static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
Li Yangce973b12006-08-14 23:00:11 -07001797 p_UccGethTadParams,
Li Yang18a8e862006-10-19 21:07:34 -05001798 struct qe_fltr_tad *qe_fltr_tad)
Li Yangce973b12006-08-14 23:00:11 -07001799{
1800 u16 temp;
1801
1802 /* Zero serialized TAD */
1803 memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE);
1804
1805 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V; /* Must have this */
1806 if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode ||
1807 (p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
1808 || (p_UccGethTadParams->vnontag_op !=
1809 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP)
1810 )
1811 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF;
1812 if (p_UccGethTadParams->reject_frame)
1813 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ;
1814 temp =
1815 (u16) (((u16) p_UccGethTadParams->
1816 vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT);
1817 qe_fltr_tad->serialized[0] |= (u8) (temp >> 8); /* upper bits */
1818
1819 qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff); /* lower bits */
1820 if (p_UccGethTadParams->vnontag_op ==
1821 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT)
1822 qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP;
1823 qe_fltr_tad->serialized[1] |=
1824 p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT;
1825
1826 qe_fltr_tad->serialized[2] |=
1827 p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT;
1828 /* upper bits */
1829 qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8);
1830 /* lower bits */
1831 qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff);
1832
1833 return 0;
1834}
1835
Li Yang18a8e862006-10-19 21:07:34 -05001836static struct enet_addr_container_t
1837 *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
1838 struct enet_addr *p_enet_addr)
Li Yangce973b12006-08-14 23:00:11 -07001839{
Li Yang18a8e862006-10-19 21:07:34 -05001840 struct enet_addr_container *enet_addr_cont;
Li Yangce973b12006-08-14 23:00:11 -07001841 struct list_head *p_lh;
1842 u16 i, num;
1843 int32_t j;
1844 u8 *p_counter;
1845
1846 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1847 p_lh = &ugeth->group_hash_q;
1848 p_counter = &(ugeth->numGroupAddrInHash);
1849 } else {
1850 p_lh = &ugeth->ind_hash_q;
1851 p_counter = &(ugeth->numIndAddrInHash);
1852 }
1853
1854 if (!p_lh)
1855 return NULL;
1856
1857 num = *p_counter;
1858
1859 for (i = 0; i < num; i++) {
1860 enet_addr_cont =
Li Yang18a8e862006-10-19 21:07:34 -05001861 (struct enet_addr_container *)
Li Yangce973b12006-08-14 23:00:11 -07001862 ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
1863 for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
1864 if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
1865 break;
1866 if (j == 0)
1867 return enet_addr_cont; /* Found */
1868 }
1869 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1870 }
1871 return NULL;
1872}
1873
Li Yang18a8e862006-10-19 21:07:34 -05001874static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
1875 struct enet_addr *p_enet_addr)
Li Yangce973b12006-08-14 23:00:11 -07001876{
Li Yang18a8e862006-10-19 21:07:34 -05001877 enum ucc_geth_enet_address_recognition_location location;
1878 struct enet_addr_container *enet_addr_cont;
Li Yangce973b12006-08-14 23:00:11 -07001879 struct list_head *p_lh;
1880 u8 i;
1881 u32 limit;
1882 u8 *p_counter;
1883
1884 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1885 p_lh = &ugeth->group_hash_q;
1886 limit = ugeth->ug_info->maxGroupAddrInHash;
1887 location =
1888 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH;
1889 p_counter = &(ugeth->numGroupAddrInHash);
1890 } else {
1891 p_lh = &ugeth->ind_hash_q;
1892 limit = ugeth->ug_info->maxIndAddrInHash;
1893 location =
1894 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH;
1895 p_counter = &(ugeth->numIndAddrInHash);
1896 }
1897
1898 if ((enet_addr_cont =
1899 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) {
1900 list_add(p_lh, &enet_addr_cont->node); /* Put it back */
1901 return 0;
1902 }
1903 if ((!p_lh) || (!(*p_counter < limit)))
1904 return -EBUSY;
1905 if (!(enet_addr_cont = get_enet_addr_container()))
1906 return -ENOMEM;
1907 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
1908 (enet_addr_cont->address)[i] = (*p_enet_addr)[i];
1909 enet_addr_cont->location = location;
1910 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1911 ++(*p_counter);
1912
Li Yang18a8e862006-10-19 21:07:34 -05001913 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
Li Yangce973b12006-08-14 23:00:11 -07001914 return 0;
1915}
1916
Li Yang18a8e862006-10-19 21:07:34 -05001917static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
1918 struct enet_addr *p_enet_addr)
Li Yangce973b12006-08-14 23:00:11 -07001919{
Li Yang18a8e862006-10-19 21:07:34 -05001920 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1921 struct enet_addr_container *enet_addr_cont;
1922 struct ucc_fast_private *uccf;
1923 enum comm_dir comm_dir;
Li Yangce973b12006-08-14 23:00:11 -07001924 u16 i, num;
1925 struct list_head *p_lh;
1926 u32 *addr_h, *addr_l;
1927 u8 *p_counter;
1928
1929 uccf = ugeth->uccf;
1930
1931 p_82xx_addr_filt =
Li Yang18a8e862006-10-19 21:07:34 -05001932 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
Li Yangce973b12006-08-14 23:00:11 -07001933 addressfiltering;
1934
1935 if (!
1936 (enet_addr_cont =
1937 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr)))
1938 return -ENOENT;
1939
1940 /* It's been found and removed from the CQ. */
1941 /* Now destroy its container */
1942 put_enet_addr_container(enet_addr_cont);
1943
1944 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1945 addr_h = &(p_82xx_addr_filt->gaddr_h);
1946 addr_l = &(p_82xx_addr_filt->gaddr_l);
1947 p_lh = &ugeth->group_hash_q;
1948 p_counter = &(ugeth->numGroupAddrInHash);
1949 } else {
1950 addr_h = &(p_82xx_addr_filt->iaddr_h);
1951 addr_l = &(p_82xx_addr_filt->iaddr_l);
1952 p_lh = &ugeth->ind_hash_q;
1953 p_counter = &(ugeth->numIndAddrInHash);
1954 }
1955
1956 comm_dir = 0;
1957 if (uccf->enabled_tx)
1958 comm_dir |= COMM_DIR_TX;
1959 if (uccf->enabled_rx)
1960 comm_dir |= COMM_DIR_RX;
1961 if (comm_dir)
1962 ugeth_disable(ugeth, comm_dir);
1963
1964 /* Clear the hash table. */
1965 out_be32(addr_h, 0x00000000);
1966 out_be32(addr_l, 0x00000000);
1967
1968 /* Add all remaining CQ elements back into hash */
1969 num = --(*p_counter);
1970 for (i = 0; i < num; i++) {
1971 enet_addr_cont =
Li Yang18a8e862006-10-19 21:07:34 -05001972 (struct enet_addr_container *)
Li Yangce973b12006-08-14 23:00:11 -07001973 ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
Li Yang18a8e862006-10-19 21:07:34 -05001974 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
Li Yangce973b12006-08-14 23:00:11 -07001975 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1976 }
1977
1978 if (comm_dir)
1979 ugeth_enable(ugeth, comm_dir);
1980
1981 return 0;
1982}
1983#endif /* CONFIG_UGETH_FILTERING */
1984
Li Yang18a8e862006-10-19 21:07:34 -05001985static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
Li Yangce973b12006-08-14 23:00:11 -07001986 ugeth,
Li Yang18a8e862006-10-19 21:07:34 -05001987 enum enet_addr_type
Li Yangce973b12006-08-14 23:00:11 -07001988 enet_addr_type)
1989{
Li Yang18a8e862006-10-19 21:07:34 -05001990 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1991 struct ucc_fast_private *uccf;
1992 enum comm_dir comm_dir;
Li Yangce973b12006-08-14 23:00:11 -07001993 struct list_head *p_lh;
1994 u16 i, num;
1995 u32 *addr_h, *addr_l;
1996 u8 *p_counter;
1997
1998 uccf = ugeth->uccf;
1999
2000 p_82xx_addr_filt =
Li Yang18a8e862006-10-19 21:07:34 -05002001 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
Li Yangce973b12006-08-14 23:00:11 -07002002 addressfiltering;
2003
2004 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
2005 addr_h = &(p_82xx_addr_filt->gaddr_h);
2006 addr_l = &(p_82xx_addr_filt->gaddr_l);
2007 p_lh = &ugeth->group_hash_q;
2008 p_counter = &(ugeth->numGroupAddrInHash);
2009 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
2010 addr_h = &(p_82xx_addr_filt->iaddr_h);
2011 addr_l = &(p_82xx_addr_filt->iaddr_l);
2012 p_lh = &ugeth->ind_hash_q;
2013 p_counter = &(ugeth->numIndAddrInHash);
2014 } else
2015 return -EINVAL;
2016
2017 comm_dir = 0;
2018 if (uccf->enabled_tx)
2019 comm_dir |= COMM_DIR_TX;
2020 if (uccf->enabled_rx)
2021 comm_dir |= COMM_DIR_RX;
2022 if (comm_dir)
2023 ugeth_disable(ugeth, comm_dir);
2024
2025 /* Clear the hash table. */
2026 out_be32(addr_h, 0x00000000);
2027 out_be32(addr_l, 0x00000000);
2028
2029 if (!p_lh)
2030 return 0;
2031
2032 num = *p_counter;
2033
2034 /* Delete all remaining CQ elements */
2035 for (i = 0; i < num; i++)
2036 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
2037
2038 *p_counter = 0;
2039
2040 if (comm_dir)
2041 ugeth_enable(ugeth, comm_dir);
2042
2043 return 0;
2044}
2045
2046#ifdef CONFIG_UGETH_FILTERING
Li Yang18a8e862006-10-19 21:07:34 -05002047static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
2048 struct enet_addr *p_enet_addr,
Li Yangce973b12006-08-14 23:00:11 -07002049 u8 paddr_num)
2050{
2051 int i;
2052
2053 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR)
2054 ugeth_warn
2055 ("%s: multicast address added to paddr will have no "
2056 "effect - is this what you wanted?",
2057 __FUNCTION__);
2058
2059 ugeth->indAddrRegUsed[paddr_num] = 1; /* mark this paddr as used */
2060 /* store address in our database */
2061 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
2062 ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i];
2063 /* put in hardware */
2064 return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num);
2065}
2066#endif /* CONFIG_UGETH_FILTERING */
2067
Li Yang18a8e862006-10-19 21:07:34 -05002068static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
Li Yangce973b12006-08-14 23:00:11 -07002069 u8 paddr_num)
2070{
2071 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
2072 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
2073}
2074
Li Yang18a8e862006-10-19 21:07:34 -05002075static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -07002076{
2077 u16 i, j;
2078 u8 *bd;
2079
2080 if (!ugeth)
2081 return;
2082
2083 if (ugeth->uccf)
2084 ucc_fast_free(ugeth->uccf);
2085
2086 if (ugeth->p_thread_data_tx) {
2087 qe_muram_free(ugeth->thread_dat_tx_offset);
2088 ugeth->p_thread_data_tx = NULL;
2089 }
2090 if (ugeth->p_thread_data_rx) {
2091 qe_muram_free(ugeth->thread_dat_rx_offset);
2092 ugeth->p_thread_data_rx = NULL;
2093 }
2094 if (ugeth->p_exf_glbl_param) {
2095 qe_muram_free(ugeth->exf_glbl_param_offset);
2096 ugeth->p_exf_glbl_param = NULL;
2097 }
2098 if (ugeth->p_rx_glbl_pram) {
2099 qe_muram_free(ugeth->rx_glbl_pram_offset);
2100 ugeth->p_rx_glbl_pram = NULL;
2101 }
2102 if (ugeth->p_tx_glbl_pram) {
2103 qe_muram_free(ugeth->tx_glbl_pram_offset);
2104 ugeth->p_tx_glbl_pram = NULL;
2105 }
2106 if (ugeth->p_send_q_mem_reg) {
2107 qe_muram_free(ugeth->send_q_mem_reg_offset);
2108 ugeth->p_send_q_mem_reg = NULL;
2109 }
2110 if (ugeth->p_scheduler) {
2111 qe_muram_free(ugeth->scheduler_offset);
2112 ugeth->p_scheduler = NULL;
2113 }
2114 if (ugeth->p_tx_fw_statistics_pram) {
2115 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
2116 ugeth->p_tx_fw_statistics_pram = NULL;
2117 }
2118 if (ugeth->p_rx_fw_statistics_pram) {
2119 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
2120 ugeth->p_rx_fw_statistics_pram = NULL;
2121 }
2122 if (ugeth->p_rx_irq_coalescing_tbl) {
2123 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
2124 ugeth->p_rx_irq_coalescing_tbl = NULL;
2125 }
2126 if (ugeth->p_rx_bd_qs_tbl) {
2127 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
2128 ugeth->p_rx_bd_qs_tbl = NULL;
2129 }
2130 if (ugeth->p_init_enet_param_shadow) {
2131 return_init_enet_entries(ugeth,
2132 &(ugeth->p_init_enet_param_shadow->
2133 rxthread[0]),
2134 ENET_INIT_PARAM_MAX_ENTRIES_RX,
2135 ugeth->ug_info->riscRx, 1);
2136 return_init_enet_entries(ugeth,
2137 &(ugeth->p_init_enet_param_shadow->
2138 txthread[0]),
2139 ENET_INIT_PARAM_MAX_ENTRIES_TX,
2140 ugeth->ug_info->riscTx, 0);
2141 kfree(ugeth->p_init_enet_param_shadow);
2142 ugeth->p_init_enet_param_shadow = NULL;
2143 }
2144 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
2145 bd = ugeth->p_tx_bd_ring[i];
Nicu Ioan Petru3a8205e2007-04-13 01:26:29 -05002146 if (!bd)
2147 continue;
Li Yangce973b12006-08-14 23:00:11 -07002148 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
2149 if (ugeth->tx_skbuff[i][j]) {
2150 dma_unmap_single(NULL,
Anton Vorontsov62270332007-09-13 19:23:33 +04002151 ((struct qe_bd *)bd)->buf,
Li Yang18a8e862006-10-19 21:07:34 -05002152 (in_be32((u32 *)bd) &
Li Yangce973b12006-08-14 23:00:11 -07002153 BD_LENGTH_MASK),
2154 DMA_TO_DEVICE);
2155 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
2156 ugeth->tx_skbuff[i][j] = NULL;
2157 }
2158 }
2159
2160 kfree(ugeth->tx_skbuff[i]);
2161
2162 if (ugeth->p_tx_bd_ring[i]) {
2163 if (ugeth->ug_info->uf_info.bd_mem_part ==
2164 MEM_PART_SYSTEM)
2165 kfree((void *)ugeth->tx_bd_ring_offset[i]);
2166 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2167 MEM_PART_MURAM)
2168 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
2169 ugeth->p_tx_bd_ring[i] = NULL;
2170 }
2171 }
2172 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
2173 if (ugeth->p_rx_bd_ring[i]) {
2174 /* Return existing data buffers in ring */
2175 bd = ugeth->p_rx_bd_ring[i];
2176 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
2177 if (ugeth->rx_skbuff[i][j]) {
Li Yang18a8e862006-10-19 21:07:34 -05002178 dma_unmap_single(NULL,
2179 ((struct qe_bd *)bd)->buf,
2180 ugeth->ug_info->
2181 uf_info.max_rx_buf_length +
2182 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
2183 DMA_FROM_DEVICE);
2184 dev_kfree_skb_any(
2185 ugeth->rx_skbuff[i][j]);
Li Yangce973b12006-08-14 23:00:11 -07002186 ugeth->rx_skbuff[i][j] = NULL;
2187 }
Li Yang18a8e862006-10-19 21:07:34 -05002188 bd += sizeof(struct qe_bd);
Li Yangce973b12006-08-14 23:00:11 -07002189 }
2190
2191 kfree(ugeth->rx_skbuff[i]);
2192
2193 if (ugeth->ug_info->uf_info.bd_mem_part ==
2194 MEM_PART_SYSTEM)
2195 kfree((void *)ugeth->rx_bd_ring_offset[i]);
2196 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2197 MEM_PART_MURAM)
2198 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
2199 ugeth->p_rx_bd_ring[i] = NULL;
2200 }
2201 }
2202 while (!list_empty(&ugeth->group_hash_q))
2203 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2204 (dequeue(&ugeth->group_hash_q)));
2205 while (!list_empty(&ugeth->ind_hash_q))
2206 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2207 (dequeue(&ugeth->ind_hash_q)));
2208
2209}
2210
2211static void ucc_geth_set_multi(struct net_device *dev)
2212{
Li Yang18a8e862006-10-19 21:07:34 -05002213 struct ucc_geth_private *ugeth;
Li Yangce973b12006-08-14 23:00:11 -07002214 struct dev_mc_list *dmi;
Li Yang18a8e862006-10-19 21:07:34 -05002215 struct ucc_fast *uf_regs;
2216 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2217 u8 tempaddr[6];
Li Yangce973b12006-08-14 23:00:11 -07002218 u8 *mcptr, *tdptr;
2219 int i, j;
2220
2221 ugeth = netdev_priv(dev);
2222
2223 uf_regs = ugeth->uccf->uf_regs;
2224
2225 if (dev->flags & IFF_PROMISC) {
2226
Li Yangce973b12006-08-14 23:00:11 -07002227 uf_regs->upsmr |= UPSMR_PRO;
2228
2229 } else {
2230
2231 uf_regs->upsmr &= ~UPSMR_PRO;
2232
2233 p_82xx_addr_filt =
Li Yang18a8e862006-10-19 21:07:34 -05002234 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
Li Yangce973b12006-08-14 23:00:11 -07002235 p_rx_glbl_pram->addressfiltering;
2236
2237 if (dev->flags & IFF_ALLMULTI) {
2238 /* Catch all multicast addresses, so set the
2239 * filter to all 1's.
2240 */
2241 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2242 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2243 } else {
2244 /* Clear filter and add the addresses in the list.
2245 */
2246 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2247 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2248
2249 dmi = dev->mc_list;
2250
2251 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2252
2253 /* Only support group multicast for now.
2254 */
2255 if (!(dmi->dmi_addr[0] & 1))
2256 continue;
2257
2258 /* The address in dmi_addr is LSB first,
2259 * and taddr is MSB first. We have to
2260 * copy bytes MSB first from dmi_addr.
2261 */
2262 mcptr = (u8 *) dmi->dmi_addr + 5;
Li Yang18a8e862006-10-19 21:07:34 -05002263 tdptr = (u8 *) tempaddr;
Li Yangce973b12006-08-14 23:00:11 -07002264 for (j = 0; j < 6; j++)
2265 *tdptr++ = *mcptr--;
2266
2267 /* Ask CPM to run CRC and set bit in
2268 * filter mask.
2269 */
Li Yang18a8e862006-10-19 21:07:34 -05002270 hw_add_addr_in_hash(ugeth, tempaddr);
Li Yangce973b12006-08-14 23:00:11 -07002271 }
2272 }
2273 }
2274}
2275
Li Yang18a8e862006-10-19 21:07:34 -05002276static void ucc_geth_stop(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -07002277{
Li Yang18a8e862006-10-19 21:07:34 -05002278 struct ucc_geth *ug_regs = ugeth->ug_regs;
Kim Phillips728de4c92007-04-13 01:26:03 -05002279 struct phy_device *phydev = ugeth->phydev;
Li Yangce973b12006-08-14 23:00:11 -07002280 u32 tempval;
2281
2282 ugeth_vdbg("%s: IN", __FUNCTION__);
2283
2284 /* Disable the controller */
2285 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2286
2287 /* Tell the kernel the link is down */
Kim Phillips728de4c92007-04-13 01:26:03 -05002288 phy_stop(phydev);
Li Yangce973b12006-08-14 23:00:11 -07002289
2290 /* Mask all interrupts */
Timur Tabic6f50472007-07-10 07:51:11 -05002291 out_be32(ugeth->uccf->p_uccm, 0x00000000);
Li Yangce973b12006-08-14 23:00:11 -07002292
2293 /* Clear all interrupts */
2294 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2295
2296 /* Disable Rx and Tx */
2297 tempval = in_be32(&ug_regs->maccfg1);
2298 tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2299 out_be32(&ug_regs->maccfg1, tempval);
2300
Li Yangce973b12006-08-14 23:00:11 -07002301 free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);
2302
Li Yangce973b12006-08-14 23:00:11 -07002303 ucc_geth_memclean(ugeth);
2304}
2305
Kim Phillips728de4c92007-04-13 01:26:03 -05002306static int ucc_struct_init(struct ucc_geth_private *ugeth)
Li Yangce973b12006-08-14 23:00:11 -07002307{
Li Yang18a8e862006-10-19 21:07:34 -05002308 struct ucc_geth_info *ug_info;
2309 struct ucc_fast_info *uf_info;
Kim Phillips728de4c92007-04-13 01:26:03 -05002310 int i;
Li Yangce973b12006-08-14 23:00:11 -07002311
2312 ug_info = ugeth->ug_info;
2313 uf_info = &ug_info->uf_info;
2314
Nicu Ioan Petru3a8205e2007-04-13 01:26:29 -05002315 /* Create CQs for hash tables */
2316 INIT_LIST_HEAD(&ugeth->group_hash_q);
2317 INIT_LIST_HEAD(&ugeth->ind_hash_q);
2318
Li Yangce973b12006-08-14 23:00:11 -07002319 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2320 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
Li Yang890de952007-07-19 11:48:29 +08002321 if (netif_msg_probe(ugeth))
2322 ugeth_err("%s: Bad memory partition value.",
2323 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002324 return -EINVAL;
2325 }
2326
2327 /* Rx BD lengths */
2328 for (i = 0; i < ug_info->numQueuesRx; i++) {
2329 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2330 (ug_info->bdRingLenRx[i] %
2331 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
Li Yang890de952007-07-19 11:48:29 +08002332 if (netif_msg_probe(ugeth))
2333 ugeth_err
2334 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2335 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002336 return -EINVAL;
2337 }
2338 }
2339
2340 /* Tx BD lengths */
2341 for (i = 0; i < ug_info->numQueuesTx; i++) {
2342 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
Li Yang890de952007-07-19 11:48:29 +08002343 if (netif_msg_probe(ugeth))
2344 ugeth_err
2345 ("%s: Tx BD ring length must be no smaller than 2.",
2346 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002347 return -EINVAL;
2348 }
2349 }
2350
2351 /* mrblr */
2352 if ((uf_info->max_rx_buf_length == 0) ||
2353 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
Li Yang890de952007-07-19 11:48:29 +08002354 if (netif_msg_probe(ugeth))
2355 ugeth_err
2356 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2357 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002358 return -EINVAL;
2359 }
2360
2361 /* num Tx queues */
2362 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
Li Yang890de952007-07-19 11:48:29 +08002363 if (netif_msg_probe(ugeth))
2364 ugeth_err("%s: number of tx queues too large.", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002365 return -EINVAL;
2366 }
2367
2368 /* num Rx queues */
2369 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
Li Yang890de952007-07-19 11:48:29 +08002370 if (netif_msg_probe(ugeth))
2371 ugeth_err("%s: number of rx queues too large.", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002372 return -EINVAL;
2373 }
2374
2375 /* l2qt */
2376 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2377 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
Li Yang890de952007-07-19 11:48:29 +08002378 if (netif_msg_probe(ugeth))
2379 ugeth_err
2380 ("%s: VLAN priority table entry must not be"
2381 " larger than number of Rx queues.",
2382 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002383 return -EINVAL;
2384 }
2385 }
2386
2387 /* l3qt */
2388 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2389 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
Li Yang890de952007-07-19 11:48:29 +08002390 if (netif_msg_probe(ugeth))
2391 ugeth_err
2392 ("%s: IP priority table entry must not be"
2393 " larger than number of Rx queues.",
2394 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002395 return -EINVAL;
2396 }
2397 }
2398
2399 if (ug_info->cam && !ug_info->ecamptr) {
Li Yang890de952007-07-19 11:48:29 +08002400 if (netif_msg_probe(ugeth))
2401 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2402 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002403 return -EINVAL;
2404 }
2405
2406 if ((ug_info->numStationAddresses !=
2407 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2408 && ug_info->rxExtendedFiltering) {
Li Yang890de952007-07-19 11:48:29 +08002409 if (netif_msg_probe(ugeth))
2410 ugeth_err("%s: Number of station addresses greater than 1 "
2411 "not allowed in extended parsing mode.",
2412 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002413 return -EINVAL;
2414 }
2415
2416 /* Generate uccm_mask for receive */
2417 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2418 for (i = 0; i < ug_info->numQueuesRx; i++)
2419 uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);
2420
2421 for (i = 0; i < ug_info->numQueuesTx; i++)
2422 uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
2423 /* Initialize the general fast UCC block. */
Kim Phillips728de4c92007-04-13 01:26:03 -05002424 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
Li Yang890de952007-07-19 11:48:29 +08002425 if (netif_msg_probe(ugeth))
2426 ugeth_err("%s: Failed to init uccf.", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002427 ucc_geth_memclean(ugeth);
2428 return -ENOMEM;
2429 }
Kim Phillips728de4c92007-04-13 01:26:03 -05002430
2431 ugeth->ug_regs = (struct ucc_geth *) ioremap(uf_info->regs, sizeof(struct ucc_geth));
2432
2433 return 0;
2434}
2435
2436static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2437{
2438 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2439 struct ucc_geth_init_pram *p_init_enet_pram;
2440 struct ucc_fast_private *uccf;
2441 struct ucc_geth_info *ug_info;
2442 struct ucc_fast_info *uf_info;
2443 struct ucc_fast *uf_regs;
2444 struct ucc_geth *ug_regs;
2445 int ret_val = -EINVAL;
2446 u32 remoder = UCC_GETH_REMODER_INIT;
2447 u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
2448 u32 ifstat, i, j, size, l2qt, l3qt, length;
2449 u16 temoder = UCC_GETH_TEMODER_INIT;
2450 u16 test;
2451 u8 function_code = 0;
2452 u8 *bd, *endOfRing;
2453 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2454
2455 ugeth_vdbg("%s: IN", __FUNCTION__);
2456 uccf = ugeth->uccf;
2457 ug_info = ugeth->ug_info;
2458 uf_info = &ug_info->uf_info;
2459 uf_regs = uccf->uf_regs;
2460 ug_regs = ugeth->ug_regs;
Li Yangce973b12006-08-14 23:00:11 -07002461
2462 switch (ug_info->numThreadsRx) {
2463 case UCC_GETH_NUM_OF_THREADS_1:
2464 numThreadsRxNumerical = 1;
2465 break;
2466 case UCC_GETH_NUM_OF_THREADS_2:
2467 numThreadsRxNumerical = 2;
2468 break;
2469 case UCC_GETH_NUM_OF_THREADS_4:
2470 numThreadsRxNumerical = 4;
2471 break;
2472 case UCC_GETH_NUM_OF_THREADS_6:
2473 numThreadsRxNumerical = 6;
2474 break;
2475 case UCC_GETH_NUM_OF_THREADS_8:
2476 numThreadsRxNumerical = 8;
2477 break;
2478 default:
Li Yang890de952007-07-19 11:48:29 +08002479 if (netif_msg_ifup(ugeth))
2480 ugeth_err("%s: Bad number of Rx threads value.",
2481 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002482 ucc_geth_memclean(ugeth);
2483 return -EINVAL;
2484 break;
2485 }
2486
2487 switch (ug_info->numThreadsTx) {
2488 case UCC_GETH_NUM_OF_THREADS_1:
2489 numThreadsTxNumerical = 1;
2490 break;
2491 case UCC_GETH_NUM_OF_THREADS_2:
2492 numThreadsTxNumerical = 2;
2493 break;
2494 case UCC_GETH_NUM_OF_THREADS_4:
2495 numThreadsTxNumerical = 4;
2496 break;
2497 case UCC_GETH_NUM_OF_THREADS_6:
2498 numThreadsTxNumerical = 6;
2499 break;
2500 case UCC_GETH_NUM_OF_THREADS_8:
2501 numThreadsTxNumerical = 8;
2502 break;
2503 default:
Li Yang890de952007-07-19 11:48:29 +08002504 if (netif_msg_ifup(ugeth))
2505 ugeth_err("%s: Bad number of Tx threads value.",
2506 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002507 ucc_geth_memclean(ugeth);
2508 return -EINVAL;
2509 break;
2510 }
2511
2512 /* Calculate rx_extended_features */
2513 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2514 ug_info->ipAddressAlignment ||
2515 (ug_info->numStationAddresses !=
2516 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2517
2518 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2519 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2520 || (ug_info->vlanOperationNonTagged !=
2521 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2522
Li Yangce973b12006-08-14 23:00:11 -07002523 init_default_reg_vals(&uf_regs->upsmr,
2524 &ug_regs->maccfg1, &ug_regs->maccfg2);
2525
2526 /* Set UPSMR */
2527 /* For more details see the hardware spec. */
2528 init_rx_parameters(ug_info->bro,
2529 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2530
2531 /* We're going to ignore other registers for now, */
2532 /* except as needed to get up and running */
2533
2534 /* Set MACCFG1 */
2535 /* For more details see the hardware spec. */
2536 init_flow_control_params(ug_info->aufc,
2537 ug_info->receiveFlowControl,
Li Yangac421852007-07-19 11:47:47 +08002538 ug_info->transmitFlowControl,
Li Yangce973b12006-08-14 23:00:11 -07002539 ug_info->pausePeriod,
2540 ug_info->extensionField,
2541 &uf_regs->upsmr,
2542 &ug_regs->uempr, &ug_regs->maccfg1);
2543
2544 maccfg1 = in_be32(&ug_regs->maccfg1);
2545 maccfg1 |= MACCFG1_ENABLE_RX;
2546 maccfg1 |= MACCFG1_ENABLE_TX;
2547 out_be32(&ug_regs->maccfg1, maccfg1);
2548
2549 /* Set IPGIFG */
2550 /* For more details see the hardware spec. */
2551 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2552 ug_info->nonBackToBackIfgPart2,
2553 ug_info->
2554 miminumInterFrameGapEnforcement,
2555 ug_info->backToBackInterFrameGap,
2556 &ug_regs->ipgifg);
2557 if (ret_val != 0) {
Li Yang890de952007-07-19 11:48:29 +08002558 if (netif_msg_ifup(ugeth))
2559 ugeth_err("%s: IPGIFG initialization parameter too large.",
2560 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002561 ucc_geth_memclean(ugeth);
2562 return ret_val;
2563 }
2564
2565 /* Set HAFDUP */
2566 /* For more details see the hardware spec. */
2567 ret_val = init_half_duplex_params(ug_info->altBeb,
2568 ug_info->backPressureNoBackoff,
2569 ug_info->noBackoff,
2570 ug_info->excessDefer,
2571 ug_info->altBebTruncation,
2572 ug_info->maxRetransmission,
2573 ug_info->collisionWindow,
2574 &ug_regs->hafdup);
2575 if (ret_val != 0) {
Li Yang890de952007-07-19 11:48:29 +08002576 if (netif_msg_ifup(ugeth))
2577 ugeth_err("%s: Half Duplex initialization parameter too large.",
Li Yangce973b12006-08-14 23:00:11 -07002578 __FUNCTION__);
2579 ucc_geth_memclean(ugeth);
2580 return ret_val;
2581 }
2582
2583 /* Set IFSTAT */
2584 /* For more details see the hardware spec. */
2585 /* Read only - resets upon read */
2586 ifstat = in_be32(&ug_regs->ifstat);
2587
2588 /* Clear UEMPR */
2589 /* For more details see the hardware spec. */
2590 out_be32(&ug_regs->uempr, 0);
2591
2592 /* Set UESCR */
2593 /* For more details see the hardware spec. */
2594 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2595 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2596 0, &uf_regs->upsmr, &ug_regs->uescr);
2597
2598 /* Allocate Tx bds */
2599 for (j = 0; j < ug_info->numQueuesTx; j++) {
2600 /* Allocate in multiple of
2601 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2602 according to spec */
Li Yang18a8e862006-10-19 21:07:34 -05002603 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
Li Yangce973b12006-08-14 23:00:11 -07002604 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2605 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
Li Yang18a8e862006-10-19 21:07:34 -05002606 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
Li Yangce973b12006-08-14 23:00:11 -07002607 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2608 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2609 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2610 u32 align = 4;
2611 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2612 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2613 ugeth->tx_bd_ring_offset[j] =
Ahmed S. Darwish04b588d2007-01-27 00:00:02 -08002614 kmalloc((u32) (length + align), GFP_KERNEL);
2615
Li Yangce973b12006-08-14 23:00:11 -07002616 if (ugeth->tx_bd_ring_offset[j] != 0)
2617 ugeth->p_tx_bd_ring[j] =
2618 (void*)((ugeth->tx_bd_ring_offset[j] +
2619 align) & ~(align - 1));
2620 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2621 ugeth->tx_bd_ring_offset[j] =
2622 qe_muram_alloc(length,
2623 UCC_GETH_TX_BD_RING_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05002624 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
Li Yangce973b12006-08-14 23:00:11 -07002625 ugeth->p_tx_bd_ring[j] =
2626 (u8 *) qe_muram_addr(ugeth->
2627 tx_bd_ring_offset[j]);
2628 }
2629 if (!ugeth->p_tx_bd_ring[j]) {
Li Yang890de952007-07-19 11:48:29 +08002630 if (netif_msg_ifup(ugeth))
2631 ugeth_err
2632 ("%s: Can not allocate memory for Tx bd rings.",
2633 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002634 ucc_geth_memclean(ugeth);
2635 return -ENOMEM;
2636 }
2637 /* Zero unused end of bd ring, according to spec */
2638 memset(ugeth->p_tx_bd_ring[j] +
Li Yang18a8e862006-10-19 21:07:34 -05002639 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd), 0,
2640 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
Li Yangce973b12006-08-14 23:00:11 -07002641 }
2642
2643 /* Allocate Rx bds */
2644 for (j = 0; j < ug_info->numQueuesRx; j++) {
Li Yang18a8e862006-10-19 21:07:34 -05002645 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
Li Yangce973b12006-08-14 23:00:11 -07002646 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2647 u32 align = 4;
2648 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2649 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2650 ugeth->rx_bd_ring_offset[j] =
Ahmed S. Darwish04b588d2007-01-27 00:00:02 -08002651 kmalloc((u32) (length + align), GFP_KERNEL);
Li Yangce973b12006-08-14 23:00:11 -07002652 if (ugeth->rx_bd_ring_offset[j] != 0)
2653 ugeth->p_rx_bd_ring[j] =
2654 (void*)((ugeth->rx_bd_ring_offset[j] +
2655 align) & ~(align - 1));
2656 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2657 ugeth->rx_bd_ring_offset[j] =
2658 qe_muram_alloc(length,
2659 UCC_GETH_RX_BD_RING_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05002660 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
Li Yangce973b12006-08-14 23:00:11 -07002661 ugeth->p_rx_bd_ring[j] =
2662 (u8 *) qe_muram_addr(ugeth->
2663 rx_bd_ring_offset[j]);
2664 }
2665 if (!ugeth->p_rx_bd_ring[j]) {
Li Yang890de952007-07-19 11:48:29 +08002666 if (netif_msg_ifup(ugeth))
2667 ugeth_err
2668 ("%s: Can not allocate memory for Rx bd rings.",
2669 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002670 ucc_geth_memclean(ugeth);
2671 return -ENOMEM;
2672 }
2673 }
2674
2675 /* Init Tx bds */
2676 for (j = 0; j < ug_info->numQueuesTx; j++) {
2677 /* Setup the skbuff rings */
Ahmed S. Darwish04b588d2007-01-27 00:00:02 -08002678 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2679 ugeth->ug_info->bdRingLenTx[j],
2680 GFP_KERNEL);
Li Yangce973b12006-08-14 23:00:11 -07002681
2682 if (ugeth->tx_skbuff[j] == NULL) {
Li Yang890de952007-07-19 11:48:29 +08002683 if (netif_msg_ifup(ugeth))
2684 ugeth_err("%s: Could not allocate tx_skbuff",
2685 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002686 ucc_geth_memclean(ugeth);
2687 return -ENOMEM;
2688 }
2689
2690 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2691 ugeth->tx_skbuff[j][i] = NULL;
2692
2693 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2694 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2695 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
Li Yang18a8e862006-10-19 21:07:34 -05002696 /* clear bd buffer */
2697 out_be32(&((struct qe_bd *)bd)->buf, 0);
2698 /* set bd status and length */
2699 out_be32((u32 *)bd, 0);
2700 bd += sizeof(struct qe_bd);
Li Yangce973b12006-08-14 23:00:11 -07002701 }
Li Yang18a8e862006-10-19 21:07:34 -05002702 bd -= sizeof(struct qe_bd);
2703 /* set bd status and length */
2704 out_be32((u32 *)bd, T_W); /* for last BD set Wrap bit */
Li Yangce973b12006-08-14 23:00:11 -07002705 }
2706
2707 /* Init Rx bds */
2708 for (j = 0; j < ug_info->numQueuesRx; j++) {
2709 /* Setup the skbuff rings */
Ahmed S. Darwish04b588d2007-01-27 00:00:02 -08002710 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2711 ugeth->ug_info->bdRingLenRx[j],
2712 GFP_KERNEL);
Li Yangce973b12006-08-14 23:00:11 -07002713
2714 if (ugeth->rx_skbuff[j] == NULL) {
Li Yang890de952007-07-19 11:48:29 +08002715 if (netif_msg_ifup(ugeth))
2716 ugeth_err("%s: Could not allocate rx_skbuff",
2717 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002718 ucc_geth_memclean(ugeth);
2719 return -ENOMEM;
2720 }
2721
2722 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2723 ugeth->rx_skbuff[j][i] = NULL;
2724
2725 ugeth->skb_currx[j] = 0;
2726 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2727 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
Li Yang18a8e862006-10-19 21:07:34 -05002728 /* set bd status and length */
2729 out_be32((u32 *)bd, R_I);
2730 /* clear bd buffer */
2731 out_be32(&((struct qe_bd *)bd)->buf, 0);
2732 bd += sizeof(struct qe_bd);
Li Yangce973b12006-08-14 23:00:11 -07002733 }
Li Yang18a8e862006-10-19 21:07:34 -05002734 bd -= sizeof(struct qe_bd);
2735 /* set bd status and length */
2736 out_be32((u32 *)bd, R_W); /* for last BD set Wrap bit */
Li Yangce973b12006-08-14 23:00:11 -07002737 }
2738
2739 /*
2740 * Global PRAM
2741 */
2742 /* Tx global PRAM */
2743 /* Allocate global tx parameter RAM page */
2744 ugeth->tx_glbl_pram_offset =
Li Yang18a8e862006-10-19 21:07:34 -05002745 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
Li Yangce973b12006-08-14 23:00:11 -07002746 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05002747 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
Li Yang890de952007-07-19 11:48:29 +08002748 if (netif_msg_ifup(ugeth))
2749 ugeth_err
2750 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2751 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002752 ucc_geth_memclean(ugeth);
2753 return -ENOMEM;
2754 }
2755 ugeth->p_tx_glbl_pram =
Li Yang18a8e862006-10-19 21:07:34 -05002756 (struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth->
Li Yangce973b12006-08-14 23:00:11 -07002757 tx_glbl_pram_offset);
2758 /* Zero out p_tx_glbl_pram */
Li Yang18a8e862006-10-19 21:07:34 -05002759 memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
Li Yangce973b12006-08-14 23:00:11 -07002760
2761 /* Fill global PRAM */
2762
2763 /* TQPTR */
2764 /* Size varies with number of Tx threads */
2765 ugeth->thread_dat_tx_offset =
2766 qe_muram_alloc(numThreadsTxNumerical *
Li Yang18a8e862006-10-19 21:07:34 -05002767 sizeof(struct ucc_geth_thread_data_tx) +
Li Yangce973b12006-08-14 23:00:11 -07002768 32 * (numThreadsTxNumerical == 1),
2769 UCC_GETH_THREAD_DATA_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05002770 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
Li Yang890de952007-07-19 11:48:29 +08002771 if (netif_msg_ifup(ugeth))
2772 ugeth_err
2773 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2774 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002775 ucc_geth_memclean(ugeth);
2776 return -ENOMEM;
2777 }
2778
2779 ugeth->p_thread_data_tx =
Li Yang18a8e862006-10-19 21:07:34 -05002780 (struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth->
Li Yangce973b12006-08-14 23:00:11 -07002781 thread_dat_tx_offset);
2782 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2783
2784 /* vtagtable */
2785 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2786 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2787 ug_info->vtagtable[i]);
2788
2789 /* iphoffset */
2790 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2791 ugeth->p_tx_glbl_pram->iphoffset[i] = ug_info->iphoffset[i];
2792
2793 /* SQPTR */
2794 /* Size varies with number of Tx queues */
2795 ugeth->send_q_mem_reg_offset =
2796 qe_muram_alloc(ug_info->numQueuesTx *
Li Yang18a8e862006-10-19 21:07:34 -05002797 sizeof(struct ucc_geth_send_queue_qd),
Li Yangce973b12006-08-14 23:00:11 -07002798 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05002799 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
Li Yang890de952007-07-19 11:48:29 +08002800 if (netif_msg_ifup(ugeth))
2801 ugeth_err
2802 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2803 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002804 ucc_geth_memclean(ugeth);
2805 return -ENOMEM;
2806 }
2807
2808 ugeth->p_send_q_mem_reg =
Li Yang18a8e862006-10-19 21:07:34 -05002809 (struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth->
Li Yangce973b12006-08-14 23:00:11 -07002810 send_q_mem_reg_offset);
2811 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2812
2813 /* Setup the table */
2814 /* Assume BD rings are already established */
2815 for (i = 0; i < ug_info->numQueuesTx; i++) {
2816 endOfRing =
2817 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
Li Yang18a8e862006-10-19 21:07:34 -05002818 1) * sizeof(struct qe_bd);
Li Yangce973b12006-08-14 23:00:11 -07002819 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2820 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2821 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2822 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2823 last_bd_completed_address,
2824 (u32) virt_to_phys(endOfRing));
2825 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2826 MEM_PART_MURAM) {
2827 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2828 (u32) immrbar_virt_to_phys(ugeth->
2829 p_tx_bd_ring[i]));
2830 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2831 last_bd_completed_address,
2832 (u32) immrbar_virt_to_phys(endOfRing));
2833 }
2834 }
2835
2836 /* schedulerbasepointer */
2837
2838 if (ug_info->numQueuesTx > 1) {
2839 /* scheduler exists only if more than 1 tx queue */
2840 ugeth->scheduler_offset =
Li Yang18a8e862006-10-19 21:07:34 -05002841 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
Li Yangce973b12006-08-14 23:00:11 -07002842 UCC_GETH_SCHEDULER_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05002843 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
Li Yang890de952007-07-19 11:48:29 +08002844 if (netif_msg_ifup(ugeth))
2845 ugeth_err
2846 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2847 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002848 ucc_geth_memclean(ugeth);
2849 return -ENOMEM;
2850 }
2851
2852 ugeth->p_scheduler =
Li Yang18a8e862006-10-19 21:07:34 -05002853 (struct ucc_geth_scheduler *) qe_muram_addr(ugeth->
Li Yangce973b12006-08-14 23:00:11 -07002854 scheduler_offset);
2855 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2856 ugeth->scheduler_offset);
2857 /* Zero out p_scheduler */
Li Yang18a8e862006-10-19 21:07:34 -05002858 memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
Li Yangce973b12006-08-14 23:00:11 -07002859
2860 /* Set values in scheduler */
2861 out_be32(&ugeth->p_scheduler->mblinterval,
2862 ug_info->mblinterval);
2863 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2864 ug_info->nortsrbytetime);
2865 ugeth->p_scheduler->fracsiz = ug_info->fracsiz;
2866 ugeth->p_scheduler->strictpriorityq = ug_info->strictpriorityq;
2867 ugeth->p_scheduler->txasap = ug_info->txasap;
2868 ugeth->p_scheduler->extrabw = ug_info->extrabw;
2869 for (i = 0; i < NUM_TX_QUEUES; i++)
2870 ugeth->p_scheduler->weightfactor[i] =
2871 ug_info->weightfactor[i];
2872
2873 /* Set pointers to cpucount registers in scheduler */
2874 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2875 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2876 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2877 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2878 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2879 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2880 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2881 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2882 }
2883
2884 /* schedulerbasepointer */
2885 /* TxRMON_PTR (statistics) */
2886 if (ug_info->
2887 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2888 ugeth->tx_fw_statistics_pram_offset =
2889 qe_muram_alloc(sizeof
Li Yang18a8e862006-10-19 21:07:34 -05002890 (struct ucc_geth_tx_firmware_statistics_pram),
Li Yangce973b12006-08-14 23:00:11 -07002891 UCC_GETH_TX_STATISTICS_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05002892 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
Li Yang890de952007-07-19 11:48:29 +08002893 if (netif_msg_ifup(ugeth))
2894 ugeth_err
2895 ("%s: Can not allocate DPRAM memory for"
2896 " p_tx_fw_statistics_pram.",
2897 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002898 ucc_geth_memclean(ugeth);
2899 return -ENOMEM;
2900 }
2901 ugeth->p_tx_fw_statistics_pram =
Li Yang18a8e862006-10-19 21:07:34 -05002902 (struct ucc_geth_tx_firmware_statistics_pram *)
Li Yangce973b12006-08-14 23:00:11 -07002903 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2904 /* Zero out p_tx_fw_statistics_pram */
2905 memset(ugeth->p_tx_fw_statistics_pram,
Li Yang18a8e862006-10-19 21:07:34 -05002906 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
Li Yangce973b12006-08-14 23:00:11 -07002907 }
2908
2909 /* temoder */
2910 /* Already has speed set */
2911
2912 if (ug_info->numQueuesTx > 1)
2913 temoder |= TEMODER_SCHEDULER_ENABLE;
2914 if (ug_info->ipCheckSumGenerate)
2915 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2916 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2917 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2918
2919 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2920
2921 /* Function code register value to be used later */
Timur Tabi6b0b5942007-10-03 11:34:59 -05002922 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
Li Yangce973b12006-08-14 23:00:11 -07002923 /* Required for QE */
2924
2925 /* function code register */
2926 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2927
2928 /* Rx global PRAM */
2929 /* Allocate global rx parameter RAM page */
2930 ugeth->rx_glbl_pram_offset =
Li Yang18a8e862006-10-19 21:07:34 -05002931 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
Li Yangce973b12006-08-14 23:00:11 -07002932 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05002933 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
Li Yang890de952007-07-19 11:48:29 +08002934 if (netif_msg_ifup(ugeth))
2935 ugeth_err
2936 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2937 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002938 ucc_geth_memclean(ugeth);
2939 return -ENOMEM;
2940 }
2941 ugeth->p_rx_glbl_pram =
Li Yang18a8e862006-10-19 21:07:34 -05002942 (struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth->
Li Yangce973b12006-08-14 23:00:11 -07002943 rx_glbl_pram_offset);
2944 /* Zero out p_rx_glbl_pram */
Li Yang18a8e862006-10-19 21:07:34 -05002945 memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
Li Yangce973b12006-08-14 23:00:11 -07002946
2947 /* Fill global PRAM */
2948
2949 /* RQPTR */
2950 /* Size varies with number of Rx threads */
2951 ugeth->thread_dat_rx_offset =
2952 qe_muram_alloc(numThreadsRxNumerical *
Li Yang18a8e862006-10-19 21:07:34 -05002953 sizeof(struct ucc_geth_thread_data_rx),
Li Yangce973b12006-08-14 23:00:11 -07002954 UCC_GETH_THREAD_DATA_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05002955 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
Li Yang890de952007-07-19 11:48:29 +08002956 if (netif_msg_ifup(ugeth))
2957 ugeth_err
2958 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2959 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002960 ucc_geth_memclean(ugeth);
2961 return -ENOMEM;
2962 }
2963
2964 ugeth->p_thread_data_rx =
Li Yang18a8e862006-10-19 21:07:34 -05002965 (struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth->
Li Yangce973b12006-08-14 23:00:11 -07002966 thread_dat_rx_offset);
2967 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2968
2969 /* typeorlen */
2970 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2971
2972 /* rxrmonbaseptr (statistics) */
2973 if (ug_info->
2974 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2975 ugeth->rx_fw_statistics_pram_offset =
2976 qe_muram_alloc(sizeof
Li Yang18a8e862006-10-19 21:07:34 -05002977 (struct ucc_geth_rx_firmware_statistics_pram),
Li Yangce973b12006-08-14 23:00:11 -07002978 UCC_GETH_RX_STATISTICS_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05002979 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
Li Yang890de952007-07-19 11:48:29 +08002980 if (netif_msg_ifup(ugeth))
2981 ugeth_err
2982 ("%s: Can not allocate DPRAM memory for"
2983 " p_rx_fw_statistics_pram.", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07002984 ucc_geth_memclean(ugeth);
2985 return -ENOMEM;
2986 }
2987 ugeth->p_rx_fw_statistics_pram =
Li Yang18a8e862006-10-19 21:07:34 -05002988 (struct ucc_geth_rx_firmware_statistics_pram *)
Li Yangce973b12006-08-14 23:00:11 -07002989 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2990 /* Zero out p_rx_fw_statistics_pram */
2991 memset(ugeth->p_rx_fw_statistics_pram, 0,
Li Yang18a8e862006-10-19 21:07:34 -05002992 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
Li Yangce973b12006-08-14 23:00:11 -07002993 }
2994
2995 /* intCoalescingPtr */
2996
2997 /* Size varies with number of Rx queues */
2998 ugeth->rx_irq_coalescing_tbl_offset =
2999 qe_muram_alloc(ug_info->numQueuesRx *
Michael Barkowski75639072007-04-13 01:26:15 -05003000 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
3001 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05003002 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
Li Yang890de952007-07-19 11:48:29 +08003003 if (netif_msg_ifup(ugeth))
3004 ugeth_err
3005 ("%s: Can not allocate DPRAM memory for"
3006 " p_rx_irq_coalescing_tbl.", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003007 ucc_geth_memclean(ugeth);
3008 return -ENOMEM;
3009 }
3010
3011 ugeth->p_rx_irq_coalescing_tbl =
Li Yang18a8e862006-10-19 21:07:34 -05003012 (struct ucc_geth_rx_interrupt_coalescing_table *)
Li Yangce973b12006-08-14 23:00:11 -07003013 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
3014 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
3015 ugeth->rx_irq_coalescing_tbl_offset);
3016
3017 /* Fill interrupt coalescing table */
3018 for (i = 0; i < ug_info->numQueuesRx; i++) {
3019 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
3020 interruptcoalescingmaxvalue,
3021 ug_info->interruptcoalescingmaxvalue[i]);
3022 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
3023 interruptcoalescingcounter,
3024 ug_info->interruptcoalescingmaxvalue[i]);
3025 }
3026
3027 /* MRBLR */
3028 init_max_rx_buff_len(uf_info->max_rx_buf_length,
3029 &ugeth->p_rx_glbl_pram->mrblr);
3030 /* MFLR */
3031 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
3032 /* MINFLR */
3033 init_min_frame_len(ug_info->minFrameLength,
3034 &ugeth->p_rx_glbl_pram->minflr,
3035 &ugeth->p_rx_glbl_pram->mrblr);
3036 /* MAXD1 */
3037 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
3038 /* MAXD2 */
3039 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
3040
3041 /* l2qt */
3042 l2qt = 0;
3043 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
3044 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
3045 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
3046
3047 /* l3qt */
3048 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
3049 l3qt = 0;
3050 for (i = 0; i < 8; i++)
3051 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
Li Yang18a8e862006-10-19 21:07:34 -05003052 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
Li Yangce973b12006-08-14 23:00:11 -07003053 }
3054
3055 /* vlantype */
3056 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
3057
3058 /* vlantci */
3059 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
3060
3061 /* ecamptr */
3062 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
3063
3064 /* RBDQPTR */
3065 /* Size varies with number of Rx queues */
3066 ugeth->rx_bd_qs_tbl_offset =
3067 qe_muram_alloc(ug_info->numQueuesRx *
Li Yang18a8e862006-10-19 21:07:34 -05003068 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3069 sizeof(struct ucc_geth_rx_prefetched_bds)),
Li Yangce973b12006-08-14 23:00:11 -07003070 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05003071 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
Li Yang890de952007-07-19 11:48:29 +08003072 if (netif_msg_ifup(ugeth))
3073 ugeth_err
3074 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
3075 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003076 ucc_geth_memclean(ugeth);
3077 return -ENOMEM;
3078 }
3079
3080 ugeth->p_rx_bd_qs_tbl =
Li Yang18a8e862006-10-19 21:07:34 -05003081 (struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth->
Li Yangce973b12006-08-14 23:00:11 -07003082 rx_bd_qs_tbl_offset);
3083 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
3084 /* Zero out p_rx_bd_qs_tbl */
3085 memset(ugeth->p_rx_bd_qs_tbl,
3086 0,
Li Yang18a8e862006-10-19 21:07:34 -05003087 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3088 sizeof(struct ucc_geth_rx_prefetched_bds)));
Li Yangce973b12006-08-14 23:00:11 -07003089
3090 /* Setup the table */
3091 /* Assume BD rings are already established */
3092 for (i = 0; i < ug_info->numQueuesRx; i++) {
3093 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
3094 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3095 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
3096 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
3097 MEM_PART_MURAM) {
3098 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3099 (u32) immrbar_virt_to_phys(ugeth->
3100 p_rx_bd_ring[i]));
3101 }
3102 /* rest of fields handled by QE */
3103 }
3104
3105 /* remoder */
3106 /* Already has speed set */
3107
3108 if (ugeth->rx_extended_features)
3109 remoder |= REMODER_RX_EXTENDED_FEATURES;
3110 if (ug_info->rxExtendedFiltering)
3111 remoder |= REMODER_RX_EXTENDED_FILTERING;
3112 if (ug_info->dynamicMaxFrameLength)
3113 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
3114 if (ug_info->dynamicMinFrameLength)
3115 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
3116 remoder |=
3117 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
3118 remoder |=
3119 ug_info->
3120 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
3121 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
3122 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
3123 if (ug_info->ipCheckSumCheck)
3124 remoder |= REMODER_IP_CHECKSUM_CHECK;
3125 if (ug_info->ipAddressAlignment)
3126 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
3127 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
3128
3129 /* Note that this function must be called */
3130 /* ONLY AFTER p_tx_fw_statistics_pram */
3131 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
3132 init_firmware_statistics_gathering_mode((ug_info->
3133 statisticsMode &
3134 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
3135 (ug_info->statisticsMode &
3136 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
3137 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
3138 ugeth->tx_fw_statistics_pram_offset,
3139 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
3140 ugeth->rx_fw_statistics_pram_offset,
3141 &ugeth->p_tx_glbl_pram->temoder,
3142 &ugeth->p_rx_glbl_pram->remoder);
3143
3144 /* function code register */
3145 ugeth->p_rx_glbl_pram->rstate = function_code;
3146
3147 /* initialize extended filtering */
3148 if (ug_info->rxExtendedFiltering) {
3149 if (!ug_info->extendedFilteringChainPointer) {
Li Yang890de952007-07-19 11:48:29 +08003150 if (netif_msg_ifup(ugeth))
3151 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
3152 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003153 ucc_geth_memclean(ugeth);
3154 return -EINVAL;
3155 }
3156
3157 /* Allocate memory for extended filtering Mode Global
3158 Parameters */
3159 ugeth->exf_glbl_param_offset =
Li Yang18a8e862006-10-19 21:07:34 -05003160 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
Li Yangce973b12006-08-14 23:00:11 -07003161 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
Timur Tabi4c356302007-05-08 14:46:36 -05003162 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
Li Yang890de952007-07-19 11:48:29 +08003163 if (netif_msg_ifup(ugeth))
3164 ugeth_err
3165 ("%s: Can not allocate DPRAM memory for"
3166 " p_exf_glbl_param.", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003167 ucc_geth_memclean(ugeth);
3168 return -ENOMEM;
3169 }
3170
3171 ugeth->p_exf_glbl_param =
Li Yang18a8e862006-10-19 21:07:34 -05003172 (struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth->
Li Yangce973b12006-08-14 23:00:11 -07003173 exf_glbl_param_offset);
3174 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
3175 ugeth->exf_glbl_param_offset);
3176 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
3177 (u32) ug_info->extendedFilteringChainPointer);
3178
3179 } else { /* initialize 82xx style address filtering */
3180
3181 /* Init individual address recognition registers to disabled */
3182
3183 for (j = 0; j < NUM_OF_PADDRS; j++)
3184 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
3185
Li Yangce973b12006-08-14 23:00:11 -07003186 p_82xx_addr_filt =
Li Yang18a8e862006-10-19 21:07:34 -05003187 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
Li Yangce973b12006-08-14 23:00:11 -07003188 p_rx_glbl_pram->addressfiltering;
3189
3190 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3191 ENET_ADDR_TYPE_GROUP);
3192 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3193 ENET_ADDR_TYPE_INDIVIDUAL);
3194 }
3195
3196 /*
3197 * Initialize UCC at QE level
3198 */
3199
3200 command = QE_INIT_TX_RX;
3201
3202 /* Allocate shadow InitEnet command parameter structure.
3203 * This is needed because after the InitEnet command is executed,
3204 * the structure in DPRAM is released, because DPRAM is a premium
3205 * resource.
3206 * This shadow structure keeps a copy of what was done so that the
3207 * allocated resources can be released when the channel is freed.
3208 */
3209 if (!(ugeth->p_init_enet_param_shadow =
Ahmed S. Darwish04b588d2007-01-27 00:00:02 -08003210 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
Li Yang890de952007-07-19 11:48:29 +08003211 if (netif_msg_ifup(ugeth))
3212 ugeth_err
3213 ("%s: Can not allocate memory for"
3214 " p_UccInitEnetParamShadows.", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003215 ucc_geth_memclean(ugeth);
3216 return -ENOMEM;
3217 }
3218 /* Zero out *p_init_enet_param_shadow */
3219 memset((char *)ugeth->p_init_enet_param_shadow,
Li Yang18a8e862006-10-19 21:07:34 -05003220 0, sizeof(struct ucc_geth_init_pram));
Li Yangce973b12006-08-14 23:00:11 -07003221
3222 /* Fill shadow InitEnet command parameter structure */
3223
3224 ugeth->p_init_enet_param_shadow->resinit1 =
3225 ENET_INIT_PARAM_MAGIC_RES_INIT1;
3226 ugeth->p_init_enet_param_shadow->resinit2 =
3227 ENET_INIT_PARAM_MAGIC_RES_INIT2;
3228 ugeth->p_init_enet_param_shadow->resinit3 =
3229 ENET_INIT_PARAM_MAGIC_RES_INIT3;
3230 ugeth->p_init_enet_param_shadow->resinit4 =
3231 ENET_INIT_PARAM_MAGIC_RES_INIT4;
3232 ugeth->p_init_enet_param_shadow->resinit5 =
3233 ENET_INIT_PARAM_MAGIC_RES_INIT5;
3234 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3235 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
3236 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3237 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
3238
3239 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3240 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3241 if ((ug_info->largestexternallookupkeysize !=
3242 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
3243 && (ug_info->largestexternallookupkeysize !=
3244 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3245 && (ug_info->largestexternallookupkeysize !=
3246 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
Li Yang890de952007-07-19 11:48:29 +08003247 if (netif_msg_ifup(ugeth))
3248 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3249 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003250 ucc_geth_memclean(ugeth);
3251 return -EINVAL;
3252 }
3253 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3254 ug_info->largestexternallookupkeysize;
Li Yang18a8e862006-10-19 21:07:34 -05003255 size = sizeof(struct ucc_geth_thread_rx_pram);
Li Yangce973b12006-08-14 23:00:11 -07003256 if (ug_info->rxExtendedFiltering) {
3257 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3258 if (ug_info->largestexternallookupkeysize ==
3259 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3260 size +=
3261 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3262 if (ug_info->largestexternallookupkeysize ==
3263 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3264 size +=
3265 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3266 }
3267
3268 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3269 p_init_enet_param_shadow->rxthread[0]),
3270 (u8) (numThreadsRxNumerical + 1)
3271 /* Rx needs one extra for terminator */
3272 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3273 ug_info->riscRx, 1)) != 0) {
Li Yang890de952007-07-19 11:48:29 +08003274 if (netif_msg_ifup(ugeth))
3275 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3276 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003277 ucc_geth_memclean(ugeth);
3278 return ret_val;
3279 }
3280
3281 ugeth->p_init_enet_param_shadow->txglobal =
3282 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3283 if ((ret_val =
3284 fill_init_enet_entries(ugeth,
3285 &(ugeth->p_init_enet_param_shadow->
3286 txthread[0]), numThreadsTxNumerical,
Li Yang18a8e862006-10-19 21:07:34 -05003287 sizeof(struct ucc_geth_thread_tx_pram),
Li Yangce973b12006-08-14 23:00:11 -07003288 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3289 ug_info->riscTx, 0)) != 0) {
Li Yang890de952007-07-19 11:48:29 +08003290 if (netif_msg_ifup(ugeth))
3291 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3292 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003293 ucc_geth_memclean(ugeth);
3294 return ret_val;
3295 }
3296
3297 /* Load Rx bds with buffers */
3298 for (i = 0; i < ug_info->numQueuesRx; i++) {
3299 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
Li Yang890de952007-07-19 11:48:29 +08003300 if (netif_msg_ifup(ugeth))
3301 ugeth_err("%s: Can not fill Rx bds with buffers.",
3302 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003303 ucc_geth_memclean(ugeth);
3304 return ret_val;
3305 }
3306 }
3307
3308 /* Allocate InitEnet command parameter structure */
Li Yang18a8e862006-10-19 21:07:34 -05003309 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
Timur Tabi4c356302007-05-08 14:46:36 -05003310 if (IS_ERR_VALUE(init_enet_pram_offset)) {
Li Yang890de952007-07-19 11:48:29 +08003311 if (netif_msg_ifup(ugeth))
3312 ugeth_err
3313 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3314 __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003315 ucc_geth_memclean(ugeth);
3316 return -ENOMEM;
3317 }
3318 p_init_enet_pram =
Li Yang18a8e862006-10-19 21:07:34 -05003319 (struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset);
Li Yangce973b12006-08-14 23:00:11 -07003320
3321 /* Copy shadow InitEnet command parameter structure into PRAM */
3322 p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1;
3323 p_init_enet_pram->resinit2 = ugeth->p_init_enet_param_shadow->resinit2;
3324 p_init_enet_pram->resinit3 = ugeth->p_init_enet_param_shadow->resinit3;
3325 p_init_enet_pram->resinit4 = ugeth->p_init_enet_param_shadow->resinit4;
3326 out_be16(&p_init_enet_pram->resinit5,
3327 ugeth->p_init_enet_param_shadow->resinit5);
3328 p_init_enet_pram->largestexternallookupkeysize =
3329 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize;
3330 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3331 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3332 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3333 out_be32(&p_init_enet_pram->rxthread[i],
3334 ugeth->p_init_enet_param_shadow->rxthread[i]);
3335 out_be32(&p_init_enet_pram->txglobal,
3336 ugeth->p_init_enet_param_shadow->txglobal);
3337 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3338 out_be32(&p_init_enet_pram->txthread[i],
3339 ugeth->p_init_enet_param_shadow->txthread[i]);
3340
3341 /* Issue QE command */
3342 cecr_subblock =
3343 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
Li Yang18a8e862006-10-19 21:07:34 -05003344 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
Li Yangce973b12006-08-14 23:00:11 -07003345 init_enet_pram_offset);
3346
3347 /* Free InitEnet command parameter */
3348 qe_muram_free(init_enet_pram_offset);
3349
3350 return 0;
3351}
3352
Li Yangce973b12006-08-14 23:00:11 -07003353/* ucc_geth_timeout gets called when a packet has not been
3354 * transmitted after a set amount of time.
3355 * For now, assume that clearing out all the structures, and
3356 * starting over will fix the problem. */
3357static void ucc_geth_timeout(struct net_device *dev)
3358{
Li Yang18a8e862006-10-19 21:07:34 -05003359 struct ucc_geth_private *ugeth = netdev_priv(dev);
Li Yangce973b12006-08-14 23:00:11 -07003360
3361 ugeth_vdbg("%s: IN", __FUNCTION__);
3362
Jeff Garzik09f75cd2007-10-03 17:41:50 -07003363 dev->stats.tx_errors++;
Li Yangce973b12006-08-14 23:00:11 -07003364
3365 ugeth_dump_regs(ugeth);
3366
3367 if (dev->flags & IFF_UP) {
3368 ucc_geth_stop(ugeth);
3369 ucc_geth_startup(ugeth);
3370 }
3371
3372 netif_schedule(dev);
3373}
3374
3375/* This is called by the kernel when a frame is ready for transmission. */
3376/* It is pointed to by the dev->hard_start_xmit function pointer */
3377static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3378{
Li Yang18a8e862006-10-19 21:07:34 -05003379 struct ucc_geth_private *ugeth = netdev_priv(dev);
Michael Reissd5b90492007-04-13 01:26:19 -05003380#ifdef CONFIG_UGETH_TX_ON_DEMAND
3381 struct ucc_fast_private *uccf;
3382#endif
Li Yangce973b12006-08-14 23:00:11 -07003383 u8 *bd; /* BD pointer */
3384 u32 bd_status;
3385 u8 txQ = 0;
3386
3387 ugeth_vdbg("%s: IN", __FUNCTION__);
3388
3389 spin_lock_irq(&ugeth->lock);
3390
Jeff Garzik09f75cd2007-10-03 17:41:50 -07003391 dev->stats.tx_bytes += skb->len;
Li Yangce973b12006-08-14 23:00:11 -07003392
3393 /* Start from the next BD that should be filled */
3394 bd = ugeth->txBd[txQ];
Li Yang18a8e862006-10-19 21:07:34 -05003395 bd_status = in_be32((u32 *)bd);
Li Yangce973b12006-08-14 23:00:11 -07003396 /* Save the skb pointer so we can free it later */
3397 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3398
3399 /* Update the current skb pointer (wrapping if this was the last) */
3400 ugeth->skb_curtx[txQ] =
3401 (ugeth->skb_curtx[txQ] +
3402 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3403
3404 /* set up the buffer descriptor */
Li Yang18a8e862006-10-19 21:07:34 -05003405 out_be32(&((struct qe_bd *)bd)->buf,
Li Yangce973b12006-08-14 23:00:11 -07003406 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE));
3407
Li Yang18a8e862006-10-19 21:07:34 -05003408 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
Li Yangce973b12006-08-14 23:00:11 -07003409
3410 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3411
Li Yang18a8e862006-10-19 21:07:34 -05003412 /* set bd status and length */
3413 out_be32((u32 *)bd, bd_status);
Li Yangce973b12006-08-14 23:00:11 -07003414
3415 dev->trans_start = jiffies;
3416
3417 /* Move to next BD in the ring */
3418 if (!(bd_status & T_W))
Li Yanga394f012007-03-06 16:53:46 +08003419 bd += sizeof(struct qe_bd);
Li Yangce973b12006-08-14 23:00:11 -07003420 else
Li Yanga394f012007-03-06 16:53:46 +08003421 bd = ugeth->p_tx_bd_ring[txQ];
Li Yangce973b12006-08-14 23:00:11 -07003422
3423 /* If the next BD still needs to be cleaned up, then the bds
3424 are full. We need to tell the kernel to stop sending us stuff. */
3425 if (bd == ugeth->confBd[txQ]) {
3426 if (!netif_queue_stopped(dev))
3427 netif_stop_queue(dev);
3428 }
3429
Li Yanga394f012007-03-06 16:53:46 +08003430 ugeth->txBd[txQ] = bd;
3431
Li Yangce973b12006-08-14 23:00:11 -07003432 if (ugeth->p_scheduler) {
3433 ugeth->cpucount[txQ]++;
3434 /* Indicate to QE that there are more Tx bds ready for
3435 transmission */
3436 /* This is done by writing a running counter of the bd
3437 count to the scheduler PRAM. */
3438 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3439 }
3440
Michael Reissd5b90492007-04-13 01:26:19 -05003441#ifdef CONFIG_UGETH_TX_ON_DEMAND
3442 uccf = ugeth->uccf;
3443 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3444#endif
Li Yangce973b12006-08-14 23:00:11 -07003445 spin_unlock_irq(&ugeth->lock);
3446
Li Yang6f6881b2007-03-19 11:58:02 +08003447 return 0;
Li Yangce973b12006-08-14 23:00:11 -07003448}
3449
Li Yang18a8e862006-10-19 21:07:34 -05003450static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
Li Yangce973b12006-08-14 23:00:11 -07003451{
3452 struct sk_buff *skb;
3453 u8 *bd;
3454 u16 length, howmany = 0;
3455 u32 bd_status;
3456 u8 *bdBuffer;
Emil Medve88a15f22007-10-15 08:43:50 -05003457 struct net_device * dev;
Li Yangce973b12006-08-14 23:00:11 -07003458
3459 ugeth_vdbg("%s: IN", __FUNCTION__);
3460
Emil Medve88a15f22007-10-15 08:43:50 -05003461 dev = ugeth->dev;
3462
Li Yangce973b12006-08-14 23:00:11 -07003463 /* collect received buffers */
3464 bd = ugeth->rxBd[rxQ];
3465
Li Yang18a8e862006-10-19 21:07:34 -05003466 bd_status = in_be32((u32 *)bd);
Li Yangce973b12006-08-14 23:00:11 -07003467
3468 /* while there are received buffers and BD is full (~R_E) */
3469 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
Li Yang18a8e862006-10-19 21:07:34 -05003470 bdBuffer = (u8 *) in_be32(&((struct qe_bd *)bd)->buf);
Li Yangce973b12006-08-14 23:00:11 -07003471 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3472 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3473
3474 /* determine whether buffer is first, last, first and last
3475 (single buffer frame) or middle (not first and not last) */
3476 if (!skb ||
3477 (!(bd_status & (R_F | R_L))) ||
3478 (bd_status & R_ERRORS_FATAL)) {
Li Yang890de952007-07-19 11:48:29 +08003479 if (netif_msg_rx_err(ugeth))
3480 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3481 __FUNCTION__, __LINE__, (u32) skb);
Li Yangce973b12006-08-14 23:00:11 -07003482 if (skb)
3483 dev_kfree_skb_any(skb);
3484
3485 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
Jeff Garzik09f75cd2007-10-03 17:41:50 -07003486 dev->stats.rx_dropped++;
Li Yangce973b12006-08-14 23:00:11 -07003487 } else {
Jeff Garzik09f75cd2007-10-03 17:41:50 -07003488 dev->stats.rx_packets++;
Li Yangce973b12006-08-14 23:00:11 -07003489 howmany++;
3490
3491 /* Prep the skb for the packet */
3492 skb_put(skb, length);
3493
3494 /* Tell the skb what kind of packet this is */
3495 skb->protocol = eth_type_trans(skb, ugeth->dev);
3496
Jeff Garzik09f75cd2007-10-03 17:41:50 -07003497 dev->stats.rx_bytes += length;
Li Yangce973b12006-08-14 23:00:11 -07003498 /* Send the packet up the stack */
3499#ifdef CONFIG_UGETH_NAPI
3500 netif_receive_skb(skb);
3501#else
3502 netif_rx(skb);
3503#endif /* CONFIG_UGETH_NAPI */
3504 }
3505
3506 ugeth->dev->last_rx = jiffies;
3507
3508 skb = get_new_skb(ugeth, bd);
3509 if (!skb) {
Li Yang890de952007-07-19 11:48:29 +08003510 if (netif_msg_rx_err(ugeth))
3511 ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__);
Jeff Garzik09f75cd2007-10-03 17:41:50 -07003512 dev->stats.rx_dropped++;
Li Yangce973b12006-08-14 23:00:11 -07003513 break;
3514 }
3515
3516 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3517
3518 /* update to point at the next skb */
3519 ugeth->skb_currx[rxQ] =
3520 (ugeth->skb_currx[rxQ] +
3521 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3522
3523 if (bd_status & R_W)
3524 bd = ugeth->p_rx_bd_ring[rxQ];
3525 else
Li Yang18a8e862006-10-19 21:07:34 -05003526 bd += sizeof(struct qe_bd);
Li Yangce973b12006-08-14 23:00:11 -07003527
Li Yang18a8e862006-10-19 21:07:34 -05003528 bd_status = in_be32((u32 *)bd);
Li Yangce973b12006-08-14 23:00:11 -07003529 }
3530
3531 ugeth->rxBd[rxQ] = bd;
Li Yangce973b12006-08-14 23:00:11 -07003532 return howmany;
3533}
3534
3535static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3536{
3537 /* Start from the next BD that should be filled */
Li Yang18a8e862006-10-19 21:07:34 -05003538 struct ucc_geth_private *ugeth = netdev_priv(dev);
Li Yangce973b12006-08-14 23:00:11 -07003539 u8 *bd; /* BD pointer */
3540 u32 bd_status;
3541
3542 bd = ugeth->confBd[txQ];
Li Yang18a8e862006-10-19 21:07:34 -05003543 bd_status = in_be32((u32 *)bd);
Li Yangce973b12006-08-14 23:00:11 -07003544
3545 /* Normal processing. */
3546 while ((bd_status & T_R) == 0) {
3547 /* BD contains already transmitted buffer. */
3548 /* Handle the transmitted buffer and release */
3549 /* the BD to be used with the current frame */
3550
Li Yanga394f012007-03-06 16:53:46 +08003551 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
Li Yangce973b12006-08-14 23:00:11 -07003552 break;
3553
Jeff Garzik09f75cd2007-10-03 17:41:50 -07003554 dev->stats.tx_packets++;
Li Yangce973b12006-08-14 23:00:11 -07003555
3556 /* Free the sk buffer associated with this TxBD */
3557 dev_kfree_skb_irq(ugeth->
3558 tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3559 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3560 ugeth->skb_dirtytx[txQ] =
3561 (ugeth->skb_dirtytx[txQ] +
3562 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3563
3564 /* We freed a buffer, so now we can restart transmission */
3565 if (netif_queue_stopped(dev))
3566 netif_wake_queue(dev);
3567
3568 /* Advance the confirmation BD pointer */
3569 if (!(bd_status & T_W))
Li Yanga394f012007-03-06 16:53:46 +08003570 bd += sizeof(struct qe_bd);
Li Yangce973b12006-08-14 23:00:11 -07003571 else
Li Yanga394f012007-03-06 16:53:46 +08003572 bd = ugeth->p_tx_bd_ring[txQ];
3573 bd_status = in_be32((u32 *)bd);
Li Yangce973b12006-08-14 23:00:11 -07003574 }
Li Yanga394f012007-03-06 16:53:46 +08003575 ugeth->confBd[txQ] = bd;
Li Yangce973b12006-08-14 23:00:11 -07003576 return 0;
3577}
3578
3579#ifdef CONFIG_UGETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003580static int ucc_geth_poll(struct napi_struct *napi, int budget)
Li Yangce973b12006-08-14 23:00:11 -07003581{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003582 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3583 struct net_device *dev = ugeth->dev;
Michael Reiss702ff122007-04-13 01:26:11 -05003584 struct ucc_geth_info *ug_info;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003585 int howmany, i;
Li Yangce973b12006-08-14 23:00:11 -07003586
Michael Reiss702ff122007-04-13 01:26:11 -05003587 ug_info = ugeth->ug_info;
3588
Michael Reiss702ff122007-04-13 01:26:11 -05003589 howmany = 0;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003590 for (i = 0; i < ug_info->numQueuesRx; i++)
3591 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
Michael Reiss702ff122007-04-13 01:26:11 -05003592
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003593 if (howmany < budget) {
3594 struct ucc_fast_private *uccf;
3595 u32 uccm;
Li Yangce973b12006-08-14 23:00:11 -07003596
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003597 netif_rx_complete(dev, napi);
Michael Reiss702ff122007-04-13 01:26:11 -05003598 uccf = ugeth->uccf;
3599 uccm = in_be32(uccf->p_uccm);
3600 uccm |= UCCE_RX_EVENTS;
3601 out_be32(uccf->p_uccm, uccm);
3602 }
Li Yangce973b12006-08-14 23:00:11 -07003603
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003604 return howmany;
Li Yangce973b12006-08-14 23:00:11 -07003605}
3606#endif /* CONFIG_UGETH_NAPI */
3607
David Howells7d12e782006-10-05 14:55:46 +01003608static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
Li Yangce973b12006-08-14 23:00:11 -07003609{
3610 struct net_device *dev = (struct net_device *)info;
Li Yang18a8e862006-10-19 21:07:34 -05003611 struct ucc_geth_private *ugeth = netdev_priv(dev);
3612 struct ucc_fast_private *uccf;
3613 struct ucc_geth_info *ug_info;
Michael Reiss702ff122007-04-13 01:26:11 -05003614 register u32 ucce;
3615 register u32 uccm;
3616#ifndef CONFIG_UGETH_NAPI
3617 register u32 rx_mask;
3618#endif
3619 register u32 tx_mask;
3620 u8 i;
Li Yangce973b12006-08-14 23:00:11 -07003621
3622 ugeth_vdbg("%s: IN", __FUNCTION__);
3623
3624 if (!ugeth)
3625 return IRQ_NONE;
3626
3627 uccf = ugeth->uccf;
3628 ug_info = ugeth->ug_info;
3629
Michael Reiss702ff122007-04-13 01:26:11 -05003630 /* read and clear events */
3631 ucce = (u32) in_be32(uccf->p_ucce);
3632 uccm = (u32) in_be32(uccf->p_uccm);
3633 ucce &= uccm;
3634 out_be32(uccf->p_ucce, ucce);
Li Yangce973b12006-08-14 23:00:11 -07003635
Michael Reiss702ff122007-04-13 01:26:11 -05003636 /* check for receive events that require processing */
3637 if (ucce & UCCE_RX_EVENTS) {
3638#ifdef CONFIG_UGETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003639 if (netif_rx_schedule_prep(dev, &ugeth->napi)) {
3640 uccm &= ~UCCE_RX_EVENTS;
Michael Reiss702ff122007-04-13 01:26:11 -05003641 out_be32(uccf->p_uccm, uccm);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003642 __netif_rx_schedule(dev, &ugeth->napi);
Li Yangce973b12006-08-14 23:00:11 -07003643 }
Michael Reiss702ff122007-04-13 01:26:11 -05003644#else
3645 rx_mask = UCCE_RXBF_SINGLE_MASK;
3646 for (i = 0; i < ug_info->numQueuesRx; i++) {
3647 if (ucce & rx_mask)
3648 ucc_geth_rx(ugeth, i, (int)ugeth->ug_info->bdRingLenRx[i]);
3649 ucce &= ~rx_mask;
3650 rx_mask <<= 1;
3651 }
3652#endif /* CONFIG_UGETH_NAPI */
3653 }
Li Yangce973b12006-08-14 23:00:11 -07003654
Michael Reiss702ff122007-04-13 01:26:11 -05003655 /* Tx event processing */
3656 if (ucce & UCCE_TX_EVENTS) {
3657 spin_lock(&ugeth->lock);
3658 tx_mask = UCCE_TXBF_SINGLE_MASK;
Li Yangce973b12006-08-14 23:00:11 -07003659 for (i = 0; i < ug_info->numQueuesTx; i++) {
3660 if (ucce & tx_mask)
3661 ucc_geth_tx(dev, i);
3662 ucce &= ~tx_mask;
3663 tx_mask <<= 1;
3664 }
Michael Reiss702ff122007-04-13 01:26:11 -05003665 spin_unlock(&ugeth->lock);
3666 }
Li Yangce973b12006-08-14 23:00:11 -07003667
Michael Reiss702ff122007-04-13 01:26:11 -05003668 /* Errors and other events */
3669 if (ucce & UCCE_OTHER) {
Li Yangce973b12006-08-14 23:00:11 -07003670 if (ucce & UCCE_BSY) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -07003671 dev->stats.rx_errors++;
Li Yangce973b12006-08-14 23:00:11 -07003672 }
Michael Reiss702ff122007-04-13 01:26:11 -05003673 if (ucce & UCCE_TXE) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -07003674 dev->stats.tx_errors++;
Li Yangce973b12006-08-14 23:00:11 -07003675 }
3676 }
Li Yangce973b12006-08-14 23:00:11 -07003677
3678 return IRQ_HANDLED;
3679}
3680
Li Yangce973b12006-08-14 23:00:11 -07003681/* Called when something needs to use the ethernet device */
3682/* Returns 0 for success. */
3683static int ucc_geth_open(struct net_device *dev)
3684{
Li Yang18a8e862006-10-19 21:07:34 -05003685 struct ucc_geth_private *ugeth = netdev_priv(dev);
Li Yangce973b12006-08-14 23:00:11 -07003686 int err;
3687
3688 ugeth_vdbg("%s: IN", __FUNCTION__);
3689
3690 /* Test station address */
3691 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
Li Yang890de952007-07-19 11:48:29 +08003692 if (netif_msg_ifup(ugeth))
3693 ugeth_err("%s: Multicast address used for station address"
3694 " - is this what you wanted?", __FUNCTION__);
Li Yangce973b12006-08-14 23:00:11 -07003695 return -EINVAL;
3696 }
3697
Kim Phillips728de4c92007-04-13 01:26:03 -05003698 err = ucc_struct_init(ugeth);
3699 if (err) {
Li Yang890de952007-07-19 11:48:29 +08003700 if (netif_msg_ifup(ugeth))
3701 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
Kim Phillips728de4c92007-04-13 01:26:03 -05003702 return err;
3703 }
3704
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003705#ifdef CONFIG_UGETH_NAPI
3706 napi_enable(&ugeth->napi);
3707#endif
Li Yangce973b12006-08-14 23:00:11 -07003708 err = ucc_geth_startup(ugeth);
3709 if (err) {
Li Yang890de952007-07-19 11:48:29 +08003710 if (netif_msg_ifup(ugeth))
3711 ugeth_err("%s: Cannot configure net device, aborting.",
3712 dev->name);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003713 goto out_err;
Li Yangce973b12006-08-14 23:00:11 -07003714 }
3715
3716 err = adjust_enet_interface(ugeth);
3717 if (err) {
Li Yang890de952007-07-19 11:48:29 +08003718 if (netif_msg_ifup(ugeth))
3719 ugeth_err("%s: Cannot configure net device, aborting.",
3720 dev->name);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003721 goto out_err;
Li Yangce973b12006-08-14 23:00:11 -07003722 }
3723
3724 /* Set MACSTNADDR1, MACSTNADDR2 */
3725 /* For more details see the hardware spec. */
3726 init_mac_station_addr_regs(dev->dev_addr[0],
3727 dev->dev_addr[1],
3728 dev->dev_addr[2],
3729 dev->dev_addr[3],
3730 dev->dev_addr[4],
3731 dev->dev_addr[5],
3732 &ugeth->ug_regs->macstnaddr1,
3733 &ugeth->ug_regs->macstnaddr2);
3734
3735 err = init_phy(dev);
3736 if (err) {
Li Yang890de952007-07-19 11:48:29 +08003737 if (netif_msg_ifup(ugeth))
3738 ugeth_err("%s: Cannot initialize PHY, aborting.", dev->name);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003739 goto out_err;
Li Yangce973b12006-08-14 23:00:11 -07003740 }
Kim Phillips728de4c92007-04-13 01:26:03 -05003741
3742 phy_start(ugeth->phydev);
3743
Li Yangce973b12006-08-14 23:00:11 -07003744 err =
3745 request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
3746 "UCC Geth", dev);
3747 if (err) {
Li Yang890de952007-07-19 11:48:29 +08003748 if (netif_msg_ifup(ugeth))
3749 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3750 dev->name);
Li Yangce973b12006-08-14 23:00:11 -07003751 ucc_geth_stop(ugeth);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003752 goto out_err;
Li Yangce973b12006-08-14 23:00:11 -07003753 }
Li Yangce973b12006-08-14 23:00:11 -07003754
Li Yangce973b12006-08-14 23:00:11 -07003755 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3756 if (err) {
Li Yang890de952007-07-19 11:48:29 +08003757 if (netif_msg_ifup(ugeth))
3758 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
Li Yangce973b12006-08-14 23:00:11 -07003759 ucc_geth_stop(ugeth);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003760 goto out_err;
Li Yangce973b12006-08-14 23:00:11 -07003761 }
3762
3763 netif_start_queue(dev);
3764
3765 return err;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003766
3767out_err:
3768#ifdef CONFIG_UGETH_NAPI
3769 napi_disable(&ugeth->napi);
3770#endif
3771 return err;
Li Yangce973b12006-08-14 23:00:11 -07003772}
3773
3774/* Stops the kernel queue, and halts the controller */
3775static int ucc_geth_close(struct net_device *dev)
3776{
Li Yang18a8e862006-10-19 21:07:34 -05003777 struct ucc_geth_private *ugeth = netdev_priv(dev);
Li Yangce973b12006-08-14 23:00:11 -07003778
3779 ugeth_vdbg("%s: IN", __FUNCTION__);
3780
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003781#ifdef CONFIG_UGETH_NAPI
3782 napi_disable(&ugeth->napi);
3783#endif
3784
Li Yangce973b12006-08-14 23:00:11 -07003785 ucc_geth_stop(ugeth);
3786
Kim Phillips728de4c92007-04-13 01:26:03 -05003787 phy_disconnect(ugeth->phydev);
3788 ugeth->phydev = NULL;
Li Yangce973b12006-08-14 23:00:11 -07003789
3790 netif_stop_queue(dev);
3791
3792 return 0;
3793}
3794
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003795static phy_interface_t to_phy_interface(const char *phy_connection_type)
Kim Phillips728de4c92007-04-13 01:26:03 -05003796{
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003797 if (strcasecmp(phy_connection_type, "mii") == 0)
Kim Phillips728de4c92007-04-13 01:26:03 -05003798 return PHY_INTERFACE_MODE_MII;
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003799 if (strcasecmp(phy_connection_type, "gmii") == 0)
Kim Phillips728de4c92007-04-13 01:26:03 -05003800 return PHY_INTERFACE_MODE_GMII;
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003801 if (strcasecmp(phy_connection_type, "tbi") == 0)
Kim Phillips728de4c92007-04-13 01:26:03 -05003802 return PHY_INTERFACE_MODE_TBI;
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003803 if (strcasecmp(phy_connection_type, "rmii") == 0)
Kim Phillips728de4c92007-04-13 01:26:03 -05003804 return PHY_INTERFACE_MODE_RMII;
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003805 if (strcasecmp(phy_connection_type, "rgmii") == 0)
Kim Phillips728de4c92007-04-13 01:26:03 -05003806 return PHY_INTERFACE_MODE_RGMII;
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003807 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
Kim Phillips728de4c92007-04-13 01:26:03 -05003808 return PHY_INTERFACE_MODE_RGMII_ID;
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003809 if (strcasecmp(phy_connection_type, "rtbi") == 0)
Kim Phillips728de4c92007-04-13 01:26:03 -05003810 return PHY_INTERFACE_MODE_RTBI;
3811
3812 return PHY_INTERFACE_MODE_MII;
3813}
3814
Li Yang18a8e862006-10-19 21:07:34 -05003815static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
Li Yangce973b12006-08-14 23:00:11 -07003816{
Li Yang18a8e862006-10-19 21:07:34 -05003817 struct device *device = &ofdev->dev;
3818 struct device_node *np = ofdev->node;
Kim Phillips728de4c92007-04-13 01:26:03 -05003819 struct device_node *mdio;
Li Yangce973b12006-08-14 23:00:11 -07003820 struct net_device *dev = NULL;
3821 struct ucc_geth_private *ugeth = NULL;
3822 struct ucc_geth_info *ug_info;
Li Yang18a8e862006-10-19 21:07:34 -05003823 struct resource res;
3824 struct device_node *phy;
Kim Phillips728de4c92007-04-13 01:26:03 -05003825 int err, ucc_num, max_speed = 0;
Li Yang18a8e862006-10-19 21:07:34 -05003826 const phandle *ph;
3827 const unsigned int *prop;
Li Yang9b4c7a42007-02-08 17:35:54 +08003828 const void *mac_addr;
Kim Phillips728de4c92007-04-13 01:26:03 -05003829 phy_interface_t phy_interface;
3830 static const int enet_to_speed[] = {
3831 SPEED_10, SPEED_10, SPEED_10,
3832 SPEED_100, SPEED_100, SPEED_100,
3833 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3834 };
3835 static const phy_interface_t enet_to_phy_interface[] = {
3836 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3837 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3838 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3839 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3840 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3841 };
Li Yangce973b12006-08-14 23:00:11 -07003842
3843 ugeth_vdbg("%s: IN", __FUNCTION__);
3844
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10003845 prop = of_get_property(np, "device-id", NULL);
Li Yang18a8e862006-10-19 21:07:34 -05003846 ucc_num = *prop - 1;
3847 if ((ucc_num < 0) || (ucc_num > 7))
3848 return -ENODEV;
Li Yangce973b12006-08-14 23:00:11 -07003849
Li Yang18a8e862006-10-19 21:07:34 -05003850 ug_info = &ugeth_info[ucc_num];
Li Yang890de952007-07-19 11:48:29 +08003851 if (ug_info == NULL) {
3852 if (netif_msg_probe(&debug))
3853 ugeth_err("%s: [%d] Missing additional data!",
3854 __FUNCTION__, ucc_num);
3855 return -ENODEV;
3856 }
3857
Li Yang18a8e862006-10-19 21:07:34 -05003858 ug_info->uf_info.ucc_num = ucc_num;
Kim Phillips728de4c92007-04-13 01:26:03 -05003859
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10003860 prop = of_get_property(np, "rx-clock", NULL);
Li Yang18a8e862006-10-19 21:07:34 -05003861 ug_info->uf_info.rx_clock = *prop;
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10003862 prop = of_get_property(np, "tx-clock", NULL);
Li Yang18a8e862006-10-19 21:07:34 -05003863 ug_info->uf_info.tx_clock = *prop;
3864 err = of_address_to_resource(np, 0, &res);
3865 if (err)
3866 return -EINVAL;
3867
3868 ug_info->uf_info.regs = res.start;
3869 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3870
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10003871 ph = of_get_property(np, "phy-handle", NULL);
Li Yang18a8e862006-10-19 21:07:34 -05003872 phy = of_find_node_by_phandle(*ph);
3873
3874 if (phy == NULL)
3875 return -ENODEV;
3876
Kim Phillips728de4c92007-04-13 01:26:03 -05003877 /* set the PHY address */
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10003878 prop = of_get_property(phy, "reg", NULL);
Kim Phillips728de4c92007-04-13 01:26:03 -05003879 if (prop == NULL)
3880 return -1;
Li Yang18a8e862006-10-19 21:07:34 -05003881 ug_info->phy_address = *prop;
Kim Phillips728de4c92007-04-13 01:26:03 -05003882
3883 /* get the phy interface type, or default to MII */
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003884 prop = of_get_property(np, "phy-connection-type", NULL);
Kim Phillips728de4c92007-04-13 01:26:03 -05003885 if (!prop) {
3886 /* handle interface property present in old trees */
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10003887 prop = of_get_property(phy, "interface", NULL);
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003888 if (prop != NULL) {
Kim Phillips728de4c92007-04-13 01:26:03 -05003889 phy_interface = enet_to_phy_interface[*prop];
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003890 max_speed = enet_to_speed[*prop];
3891 } else
Kim Phillips728de4c92007-04-13 01:26:03 -05003892 phy_interface = PHY_INTERFACE_MODE_MII;
3893 } else {
3894 phy_interface = to_phy_interface((const char *)prop);
3895 }
3896
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003897 /* get speed, or derive from PHY interface */
3898 if (max_speed == 0)
Kim Phillips728de4c92007-04-13 01:26:03 -05003899 switch (phy_interface) {
3900 case PHY_INTERFACE_MODE_GMII:
3901 case PHY_INTERFACE_MODE_RGMII:
3902 case PHY_INTERFACE_MODE_RGMII_ID:
3903 case PHY_INTERFACE_MODE_TBI:
3904 case PHY_INTERFACE_MODE_RTBI:
3905 max_speed = SPEED_1000;
3906 break;
3907 default:
3908 max_speed = SPEED_100;
3909 break;
3910 }
Kim Phillips728de4c92007-04-13 01:26:03 -05003911
3912 if (max_speed == SPEED_1000) {
Kim Phillips4e19b5c2007-05-11 18:25:07 -05003913 /* configure muram FIFOs for gigabit operation */
Kim Phillips728de4c92007-04-13 01:26:03 -05003914 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3915 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3916 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3917 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3918 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3919 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3920 }
3921
3922 /* Set the bus id */
3923 mdio = of_get_parent(phy);
3924
3925 if (mdio == NULL)
3926 return -1;
3927
3928 err = of_address_to_resource(mdio, 0, &res);
3929 of_node_put(mdio);
3930
3931 if (err)
3932 return -1;
3933
3934 ug_info->mdio_bus = res.start;
Li Yangce973b12006-08-14 23:00:11 -07003935
Li Yang890de952007-07-19 11:48:29 +08003936 if (netif_msg_probe(&debug))
3937 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3938 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3939 ug_info->uf_info.irq);
Li Yangce973b12006-08-14 23:00:11 -07003940
Li Yangce973b12006-08-14 23:00:11 -07003941 /* Create an ethernet device instance */
3942 dev = alloc_etherdev(sizeof(*ugeth));
3943
3944 if (dev == NULL)
3945 return -ENOMEM;
3946
3947 ugeth = netdev_priv(dev);
3948 spin_lock_init(&ugeth->lock);
3949
3950 dev_set_drvdata(device, dev);
3951
3952 /* Set the dev->base_addr to the gfar reg region */
3953 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3954
Li Yangce973b12006-08-14 23:00:11 -07003955 SET_NETDEV_DEV(dev, device);
3956
3957 /* Fill in the dev structure */
Li Yangac421852007-07-19 11:47:47 +08003958 uec_set_ethtool_ops(dev);
Li Yangce973b12006-08-14 23:00:11 -07003959 dev->open = ucc_geth_open;
3960 dev->hard_start_xmit = ucc_geth_start_xmit;
3961 dev->tx_timeout = ucc_geth_timeout;
3962 dev->watchdog_timeo = TX_TIMEOUT;
3963#ifdef CONFIG_UGETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003964 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
Li Yangce973b12006-08-14 23:00:11 -07003965#endif /* CONFIG_UGETH_NAPI */
3966 dev->stop = ucc_geth_close;
Li Yangce973b12006-08-14 23:00:11 -07003967// dev->change_mtu = ucc_geth_change_mtu;
3968 dev->mtu = 1500;
3969 dev->set_multicast_list = ucc_geth_set_multi;
Li Yangce973b12006-08-14 23:00:11 -07003970
Li Yang890de952007-07-19 11:48:29 +08003971 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
Kim Phillips728de4c92007-04-13 01:26:03 -05003972 ugeth->phy_interface = phy_interface;
3973 ugeth->max_speed = max_speed;
3974
Li Yangce973b12006-08-14 23:00:11 -07003975 err = register_netdev(dev);
3976 if (err) {
Li Yang890de952007-07-19 11:48:29 +08003977 if (netif_msg_probe(ugeth))
3978 ugeth_err("%s: Cannot register net device, aborting.",
3979 dev->name);
Li Yangce973b12006-08-14 23:00:11 -07003980 free_netdev(dev);
3981 return err;
3982 }
3983
Timur Tabie9eb70c2007-02-21 14:40:12 -06003984 mac_addr = of_get_mac_address(np);
Li Yang9b4c7a42007-02-08 17:35:54 +08003985 if (mac_addr)
3986 memcpy(dev->dev_addr, mac_addr, 6);
Li Yangce973b12006-08-14 23:00:11 -07003987
Kim Phillips728de4c92007-04-13 01:26:03 -05003988 ugeth->ug_info = ug_info;
3989 ugeth->dev = dev;
3990
Li Yangce973b12006-08-14 23:00:11 -07003991 return 0;
3992}
3993
Li Yang18a8e862006-10-19 21:07:34 -05003994static int ucc_geth_remove(struct of_device* ofdev)
Li Yangce973b12006-08-14 23:00:11 -07003995{
Li Yang18a8e862006-10-19 21:07:34 -05003996 struct device *device = &ofdev->dev;
Li Yangce973b12006-08-14 23:00:11 -07003997 struct net_device *dev = dev_get_drvdata(device);
3998 struct ucc_geth_private *ugeth = netdev_priv(dev);
3999
4000 dev_set_drvdata(device, NULL);
4001 ucc_geth_memclean(ugeth);
4002 free_netdev(dev);
4003
4004 return 0;
4005}
4006
Li Yang18a8e862006-10-19 21:07:34 -05004007static struct of_device_id ucc_geth_match[] = {
4008 {
4009 .type = "network",
4010 .compatible = "ucc_geth",
4011 },
4012 {},
4013};
4014
4015MODULE_DEVICE_TABLE(of, ucc_geth_match);
4016
4017static struct of_platform_driver ucc_geth_driver = {
4018 .name = DRV_NAME,
4019 .match_table = ucc_geth_match,
4020 .probe = ucc_geth_probe,
4021 .remove = ucc_geth_remove,
Li Yangce973b12006-08-14 23:00:11 -07004022};
4023
4024static int __init ucc_geth_init(void)
4025{
Kim Phillips728de4c92007-04-13 01:26:03 -05004026 int i, ret;
4027
4028 ret = uec_mdio_init();
4029
4030 if (ret)
4031 return ret;
Li Yang18a8e862006-10-19 21:07:34 -05004032
Li Yang890de952007-07-19 11:48:29 +08004033 if (netif_msg_drv(&debug))
4034 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
Li Yangce973b12006-08-14 23:00:11 -07004035 for (i = 0; i < 8; i++)
4036 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
4037 sizeof(ugeth_primary_info));
4038
Kim Phillips728de4c92007-04-13 01:26:03 -05004039 ret = of_register_platform_driver(&ucc_geth_driver);
4040
4041 if (ret)
4042 uec_mdio_exit();
4043
4044 return ret;
Li Yangce973b12006-08-14 23:00:11 -07004045}
4046
4047static void __exit ucc_geth_exit(void)
4048{
Kim Phillipsa4f0c2c2006-11-15 12:29:35 -06004049 of_unregister_platform_driver(&ucc_geth_driver);
Kim Phillips728de4c92007-04-13 01:26:03 -05004050 uec_mdio_exit();
Li Yangce973b12006-08-14 23:00:11 -07004051}
4052
4053module_init(ucc_geth_init);
4054module_exit(ucc_geth_exit);
4055
4056MODULE_AUTHOR("Freescale Semiconductor, Inc");
4057MODULE_DESCRIPTION(DRV_DESC);
Kim Phillipsc2bcf002007-04-13 01:26:36 -05004058MODULE_VERSION(DRV_VERSION);
Li Yangce973b12006-08-14 23:00:11 -07004059MODULE_LICENSE("GPL");