blob: d1556643a41d325abc7b7637ac94c694e778fedc [file] [log] [blame]
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +02001/*
2 * Atmel SDMMC controller driver.
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/mmc/host.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24
25#include "sdhci-pltfm.h"
26
27#define SDMMC_CACR 0x230
28#define SDMMC_CACR_CAPWREN BIT(0)
29#define SDMMC_CACR_KEY (0x46 << 8)
30
31struct sdhci_at91_priv {
32 struct clk *hclock;
33 struct clk *gck;
34 struct clk *mainck;
35};
36
37static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
38 .set_clock = sdhci_set_clock,
39 .set_bus_width = sdhci_set_bus_width,
40 .reset = sdhci_reset,
41 .set_uhs_signaling = sdhci_set_uhs_signaling,
42};
43
44static const struct sdhci_pltfm_data soc_data_sama5d2 = {
45 .ops = &sdhci_at91_sama5d2_ops,
46};
47
48static const struct of_device_id sdhci_at91_dt_match[] = {
49 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
50 {}
51};
52
53static int sdhci_at91_probe(struct platform_device *pdev)
54{
55 const struct of_device_id *match;
56 const struct sdhci_pltfm_data *soc_data;
57 struct sdhci_host *host;
58 struct sdhci_pltfm_host *pltfm_host;
59 struct sdhci_at91_priv *priv;
60 unsigned int caps0, caps1;
61 unsigned int clk_base, clk_mul;
62 unsigned int gck_rate, real_gck_rate;
63 int ret;
64
65 match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
66 if (!match)
67 return -EINVAL;
68 soc_data = match->data;
69
70 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
71 if (!priv) {
72 dev_err(&pdev->dev, "unable to allocate private data\n");
73 return -ENOMEM;
74 }
75
76 priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
77 if (IS_ERR(priv->mainck)) {
78 dev_err(&pdev->dev, "failed to get baseclk\n");
79 return PTR_ERR(priv->mainck);
80 }
81
82 priv->hclock = devm_clk_get(&pdev->dev, "hclock");
83 if (IS_ERR(priv->hclock)) {
84 dev_err(&pdev->dev, "failed to get hclock\n");
85 return PTR_ERR(priv->hclock);
86 }
87
88 priv->gck = devm_clk_get(&pdev->dev, "multclk");
89 if (IS_ERR(priv->gck)) {
90 dev_err(&pdev->dev, "failed to get multclk\n");
91 return PTR_ERR(priv->gck);
92 }
93
94 host = sdhci_pltfm_init(pdev, soc_data, 0);
95 if (IS_ERR(host))
96 return PTR_ERR(host);
97
98 /*
99 * The mult clock is provided by as a generated clock by the PMC
100 * controller. In order to set the rate of gck, we have to get the
101 * base clock rate and the clock mult from capabilities.
102 */
103 clk_prepare_enable(priv->hclock);
104 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
105 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
106 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
107 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
108 gck_rate = clk_base * 1000000 * (clk_mul + 1);
109 ret = clk_set_rate(priv->gck, gck_rate);
110 if (ret < 0) {
111 dev_err(&pdev->dev, "failed to set gck");
112 goto hclock_disable_unprepare;
113 return -EINVAL;
114 }
115 /*
116 * We need to check if we have the requested rate for gck because in
117 * some cases this rate could be not supported. If it happens, the rate
118 * is the closest one gck can provide. We have to update the value
119 * of clk mul.
120 */
121 real_gck_rate = clk_get_rate(priv->gck);
122 if (real_gck_rate != gck_rate) {
123 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
124 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
125 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK);
126 /* Set capabilities in r/w mode. */
127 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
128 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
129 /* Set capabilities in ro mode. */
130 writel(0, host->ioaddr + SDMMC_CACR);
131 dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n",
132 clk_mul, real_gck_rate);
133 }
134
135 clk_prepare_enable(priv->mainck);
136 clk_prepare_enable(priv->gck);
137
138 pltfm_host = sdhci_priv(host);
139 pltfm_host->priv = priv;
140
141 ret = mmc_of_parse(host->mmc);
142 if (ret)
143 goto clocks_disable_unprepare;
144
145 sdhci_get_of_property(pdev);
146
147 ret = sdhci_add_host(host);
148 if (ret)
149 goto clocks_disable_unprepare;
150
151 return 0;
152
153clocks_disable_unprepare:
154 clk_disable_unprepare(priv->gck);
155 clk_disable_unprepare(priv->mainck);
156hclock_disable_unprepare:
157 clk_disable_unprepare(priv->hclock);
158 sdhci_pltfm_free(pdev);
159 return ret;
160}
161
162static int sdhci_at91_remove(struct platform_device *pdev)
163{
164 struct sdhci_host *host = platform_get_drvdata(pdev);
165 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
166 struct sdhci_at91_priv *priv = pltfm_host->priv;
167
168 sdhci_pltfm_unregister(pdev);
169
170 clk_disable_unprepare(priv->gck);
171 clk_disable_unprepare(priv->hclock);
172 clk_disable_unprepare(priv->mainck);
173
174 return 0;
175}
176
177static struct platform_driver sdhci_at91_driver = {
178 .driver = {
179 .name = "sdhci-at91",
ludovic.desroches@atmel.combb5f8ea2015-07-29 16:22:47 +0200180 .of_match_table = sdhci_at91_dt_match,
181 .pm = SDHCI_PLTFM_PMOPS,
182 },
183 .probe = sdhci_at91_probe,
184 .remove = sdhci_at91_remove,
185};
186
187module_platform_driver(sdhci_at91_driver);
188
189MODULE_DESCRIPTION("SDHCI driver for at91");
190MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
191MODULE_LICENSE("GPL v2");