Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 NVIDIA Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/clk.h> |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 10 | #include <linux/debugfs.h> |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 11 | #include <linux/io.h> |
| 12 | #include <linux/platform_device.h> |
| 13 | #include <linux/reset.h> |
| 14 | #include <linux/tegra-powergate.h> |
| 15 | |
| 16 | #include <drm/drm_dp_helper.h> |
| 17 | |
| 18 | #include "dc.h" |
| 19 | #include "drm.h" |
| 20 | #include "sor.h" |
| 21 | |
| 22 | struct tegra_sor { |
| 23 | struct host1x_client client; |
| 24 | struct tegra_output output; |
| 25 | struct device *dev; |
| 26 | |
| 27 | void __iomem *regs; |
| 28 | |
| 29 | struct reset_control *rst; |
| 30 | struct clk *clk_parent; |
| 31 | struct clk *clk_safe; |
| 32 | struct clk *clk_dp; |
| 33 | struct clk *clk; |
| 34 | |
| 35 | struct tegra_dpaux *dpaux; |
| 36 | |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 37 | struct mutex lock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 38 | bool enabled; |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 39 | |
| 40 | struct dentry *debugfs; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 41 | }; |
| 42 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 43 | struct tegra_sor_config { |
| 44 | u32 bits_per_pixel; |
| 45 | |
| 46 | u32 active_polarity; |
| 47 | u32 active_count; |
| 48 | u32 tu_size; |
| 49 | u32 active_frac; |
| 50 | u32 watermark; |
Thierry Reding | 7890b57 | 2014-06-05 16:12:46 +0200 | [diff] [blame] | 51 | |
| 52 | u32 hblank_symbols; |
| 53 | u32 vblank_symbols; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 54 | }; |
| 55 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 56 | static inline struct tegra_sor * |
| 57 | host1x_client_to_sor(struct host1x_client *client) |
| 58 | { |
| 59 | return container_of(client, struct tegra_sor, client); |
| 60 | } |
| 61 | |
| 62 | static inline struct tegra_sor *to_sor(struct tegra_output *output) |
| 63 | { |
| 64 | return container_of(output, struct tegra_sor, output); |
| 65 | } |
| 66 | |
| 67 | static inline unsigned long tegra_sor_readl(struct tegra_sor *sor, |
| 68 | unsigned long offset) |
| 69 | { |
| 70 | return readl(sor->regs + (offset << 2)); |
| 71 | } |
| 72 | |
| 73 | static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value, |
| 74 | unsigned long offset) |
| 75 | { |
| 76 | writel(value, sor->regs + (offset << 2)); |
| 77 | } |
| 78 | |
| 79 | static int tegra_sor_dp_train_fast(struct tegra_sor *sor, |
| 80 | struct drm_dp_link *link) |
| 81 | { |
| 82 | unsigned long value; |
| 83 | unsigned int i; |
| 84 | u8 pattern; |
| 85 | int err; |
| 86 | |
| 87 | /* setup lane parameters */ |
| 88 | value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | |
| 89 | SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | |
| 90 | SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | |
| 91 | SOR_LANE_DRIVE_CURRENT_LANE0(0x40); |
| 92 | tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0); |
| 93 | |
| 94 | value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | |
| 95 | SOR_LANE_PREEMPHASIS_LANE2(0x0f) | |
| 96 | SOR_LANE_PREEMPHASIS_LANE1(0x0f) | |
| 97 | SOR_LANE_PREEMPHASIS_LANE0(0x0f); |
| 98 | tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0); |
| 99 | |
| 100 | value = SOR_LANE_POST_CURSOR_LANE3(0x00) | |
| 101 | SOR_LANE_POST_CURSOR_LANE2(0x00) | |
| 102 | SOR_LANE_POST_CURSOR_LANE1(0x00) | |
| 103 | SOR_LANE_POST_CURSOR_LANE0(0x00); |
| 104 | tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0); |
| 105 | |
| 106 | /* disable LVDS mode */ |
| 107 | tegra_sor_writel(sor, 0, SOR_LVDS); |
| 108 | |
| 109 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 110 | value |= SOR_DP_PADCTL_TX_PU_ENABLE; |
| 111 | value &= ~SOR_DP_PADCTL_TX_PU_MASK; |
| 112 | value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ |
| 113 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 114 | |
| 115 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 116 | value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | |
| 117 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; |
| 118 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 119 | |
| 120 | usleep_range(10, 100); |
| 121 | |
| 122 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 123 | value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | |
| 124 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); |
| 125 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 126 | |
| 127 | err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B); |
| 128 | if (err < 0) |
| 129 | return err; |
| 130 | |
| 131 | for (i = 0, value = 0; i < link->num_lanes; i++) { |
| 132 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 133 | SOR_DP_TPG_SCRAMBLER_NONE | |
| 134 | SOR_DP_TPG_PATTERN_TRAIN1; |
| 135 | value = (value << 8) | lane; |
| 136 | } |
| 137 | |
| 138 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 139 | |
| 140 | pattern = DP_TRAINING_PATTERN_1; |
| 141 | |
| 142 | err = tegra_dpaux_train(sor->dpaux, link, pattern); |
| 143 | if (err < 0) |
| 144 | return err; |
| 145 | |
| 146 | value = tegra_sor_readl(sor, SOR_DP_SPARE_0); |
| 147 | value |= SOR_DP_SPARE_SEQ_ENABLE; |
| 148 | value &= ~SOR_DP_SPARE_PANEL_INTERNAL; |
| 149 | value |= SOR_DP_SPARE_MACRO_SOR_CLK; |
| 150 | tegra_sor_writel(sor, value, SOR_DP_SPARE_0); |
| 151 | |
| 152 | for (i = 0, value = 0; i < link->num_lanes; i++) { |
| 153 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 154 | SOR_DP_TPG_SCRAMBLER_NONE | |
| 155 | SOR_DP_TPG_PATTERN_TRAIN2; |
| 156 | value = (value << 8) | lane; |
| 157 | } |
| 158 | |
| 159 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 160 | |
| 161 | pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; |
| 162 | |
| 163 | err = tegra_dpaux_train(sor->dpaux, link, pattern); |
| 164 | if (err < 0) |
| 165 | return err; |
| 166 | |
| 167 | for (i = 0, value = 0; i < link->num_lanes; i++) { |
| 168 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 169 | SOR_DP_TPG_SCRAMBLER_GALIOS | |
| 170 | SOR_DP_TPG_PATTERN_NONE; |
| 171 | value = (value << 8) | lane; |
| 172 | } |
| 173 | |
| 174 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 175 | |
| 176 | pattern = DP_TRAINING_PATTERN_DISABLE; |
| 177 | |
| 178 | err = tegra_dpaux_train(sor->dpaux, link, pattern); |
| 179 | if (err < 0) |
| 180 | return err; |
| 181 | |
| 182 | return 0; |
| 183 | } |
| 184 | |
| 185 | static void tegra_sor_super_update(struct tegra_sor *sor) |
| 186 | { |
| 187 | tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); |
| 188 | tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0); |
| 189 | tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); |
| 190 | } |
| 191 | |
| 192 | static void tegra_sor_update(struct tegra_sor *sor) |
| 193 | { |
| 194 | tegra_sor_writel(sor, 0, SOR_STATE_0); |
| 195 | tegra_sor_writel(sor, 1, SOR_STATE_0); |
| 196 | tegra_sor_writel(sor, 0, SOR_STATE_0); |
| 197 | } |
| 198 | |
| 199 | static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) |
| 200 | { |
| 201 | unsigned long value; |
| 202 | |
| 203 | value = tegra_sor_readl(sor, SOR_PWM_DIV); |
| 204 | value &= ~SOR_PWM_DIV_MASK; |
| 205 | value |= 0x400; /* period */ |
| 206 | tegra_sor_writel(sor, value, SOR_PWM_DIV); |
| 207 | |
| 208 | value = tegra_sor_readl(sor, SOR_PWM_CTL); |
| 209 | value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; |
| 210 | value |= 0x400; /* duty cycle */ |
| 211 | value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ |
| 212 | value |= SOR_PWM_CTL_TRIGGER; |
| 213 | tegra_sor_writel(sor, value, SOR_PWM_CTL); |
| 214 | |
| 215 | timeout = jiffies + msecs_to_jiffies(timeout); |
| 216 | |
| 217 | while (time_before(jiffies, timeout)) { |
| 218 | value = tegra_sor_readl(sor, SOR_PWM_CTL); |
| 219 | if ((value & SOR_PWM_CTL_TRIGGER) == 0) |
| 220 | return 0; |
| 221 | |
| 222 | usleep_range(25, 100); |
| 223 | } |
| 224 | |
| 225 | return -ETIMEDOUT; |
| 226 | } |
| 227 | |
| 228 | static int tegra_sor_attach(struct tegra_sor *sor) |
| 229 | { |
| 230 | unsigned long value, timeout; |
| 231 | |
| 232 | /* wake up in normal mode */ |
| 233 | value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); |
| 234 | value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; |
| 235 | value |= SOR_SUPER_STATE_MODE_NORMAL; |
| 236 | tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); |
| 237 | tegra_sor_super_update(sor); |
| 238 | |
| 239 | /* attach */ |
| 240 | value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); |
| 241 | value |= SOR_SUPER_STATE_ATTACHED; |
| 242 | tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); |
| 243 | tegra_sor_super_update(sor); |
| 244 | |
| 245 | timeout = jiffies + msecs_to_jiffies(250); |
| 246 | |
| 247 | while (time_before(jiffies, timeout)) { |
| 248 | value = tegra_sor_readl(sor, SOR_TEST); |
| 249 | if ((value & SOR_TEST_ATTACHED) != 0) |
| 250 | return 0; |
| 251 | |
| 252 | usleep_range(25, 100); |
| 253 | } |
| 254 | |
| 255 | return -ETIMEDOUT; |
| 256 | } |
| 257 | |
| 258 | static int tegra_sor_wakeup(struct tegra_sor *sor) |
| 259 | { |
| 260 | struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); |
| 261 | unsigned long value, timeout; |
| 262 | |
| 263 | /* enable display controller outputs */ |
| 264 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); |
| 265 | value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | |
| 266 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; |
| 267 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); |
| 268 | |
| 269 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 270 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 271 | |
| 272 | timeout = jiffies + msecs_to_jiffies(250); |
| 273 | |
| 274 | /* wait for head to wake up */ |
| 275 | while (time_before(jiffies, timeout)) { |
| 276 | value = tegra_sor_readl(sor, SOR_TEST); |
| 277 | value &= SOR_TEST_HEAD_MODE_MASK; |
| 278 | |
| 279 | if (value == SOR_TEST_HEAD_MODE_AWAKE) |
| 280 | return 0; |
| 281 | |
| 282 | usleep_range(25, 100); |
| 283 | } |
| 284 | |
| 285 | return -ETIMEDOUT; |
| 286 | } |
| 287 | |
| 288 | static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) |
| 289 | { |
| 290 | unsigned long value; |
| 291 | |
| 292 | value = tegra_sor_readl(sor, SOR_PWR); |
| 293 | value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; |
| 294 | tegra_sor_writel(sor, value, SOR_PWR); |
| 295 | |
| 296 | timeout = jiffies + msecs_to_jiffies(timeout); |
| 297 | |
| 298 | while (time_before(jiffies, timeout)) { |
| 299 | value = tegra_sor_readl(sor, SOR_PWR); |
| 300 | if ((value & SOR_PWR_TRIGGER) == 0) |
| 301 | return 0; |
| 302 | |
| 303 | usleep_range(25, 100); |
| 304 | } |
| 305 | |
| 306 | return -ETIMEDOUT; |
| 307 | } |
| 308 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 309 | struct tegra_sor_params { |
| 310 | /* number of link clocks per line */ |
| 311 | unsigned int num_clocks; |
| 312 | /* ratio between input and output */ |
| 313 | u64 ratio; |
| 314 | /* precision factor */ |
| 315 | u64 precision; |
| 316 | |
| 317 | unsigned int active_polarity; |
| 318 | unsigned int active_count; |
| 319 | unsigned int active_frac; |
| 320 | unsigned int tu_size; |
| 321 | unsigned int error; |
| 322 | }; |
| 323 | |
| 324 | static int tegra_sor_compute_params(struct tegra_sor *sor, |
| 325 | struct tegra_sor_params *params, |
| 326 | unsigned int tu_size) |
| 327 | { |
| 328 | u64 active_sym, active_count, frac, approx; |
| 329 | u32 active_polarity, active_frac = 0; |
| 330 | const u64 f = params->precision; |
| 331 | s64 error; |
| 332 | |
| 333 | active_sym = params->ratio * tu_size; |
| 334 | active_count = div_u64(active_sym, f) * f; |
| 335 | frac = active_sym - active_count; |
| 336 | |
| 337 | /* fraction < 0.5 */ |
| 338 | if (frac >= (f / 2)) { |
| 339 | active_polarity = 1; |
| 340 | frac = f - frac; |
| 341 | } else { |
| 342 | active_polarity = 0; |
| 343 | } |
| 344 | |
| 345 | if (frac != 0) { |
| 346 | frac = div_u64(f * f, frac); /* 1/fraction */ |
| 347 | if (frac <= (15 * f)) { |
| 348 | active_frac = div_u64(frac, f); |
| 349 | |
| 350 | /* round up */ |
| 351 | if (active_polarity) |
| 352 | active_frac++; |
| 353 | } else { |
| 354 | active_frac = active_polarity ? 1 : 15; |
| 355 | } |
| 356 | } |
| 357 | |
| 358 | if (active_frac == 1) |
| 359 | active_polarity = 0; |
| 360 | |
| 361 | if (active_polarity == 1) { |
| 362 | if (active_frac) { |
| 363 | approx = active_count + (active_frac * (f - 1)) * f; |
| 364 | approx = div_u64(approx, active_frac * f); |
| 365 | } else { |
| 366 | approx = active_count + f; |
| 367 | } |
| 368 | } else { |
| 369 | if (active_frac) |
| 370 | approx = active_count + div_u64(f, active_frac); |
| 371 | else |
| 372 | approx = active_count; |
| 373 | } |
| 374 | |
| 375 | error = div_s64(active_sym - approx, tu_size); |
| 376 | error *= params->num_clocks; |
| 377 | |
| 378 | if (error <= 0 && abs64(error) < params->error) { |
| 379 | params->active_count = div_u64(active_count, f); |
| 380 | params->active_polarity = active_polarity; |
| 381 | params->active_frac = active_frac; |
| 382 | params->error = abs64(error); |
| 383 | params->tu_size = tu_size; |
| 384 | |
| 385 | if (error == 0) |
| 386 | return true; |
| 387 | } |
| 388 | |
| 389 | return false; |
| 390 | } |
| 391 | |
| 392 | static int tegra_sor_calc_config(struct tegra_sor *sor, |
| 393 | struct drm_display_mode *mode, |
| 394 | struct tegra_sor_config *config, |
| 395 | struct drm_dp_link *link) |
| 396 | { |
| 397 | const u64 f = 100000, link_rate = link->rate * 1000; |
| 398 | const u64 pclk = mode->clock * 1000; |
Thierry Reding | 7890b57 | 2014-06-05 16:12:46 +0200 | [diff] [blame] | 399 | u64 input, output, watermark, num; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 400 | struct tegra_sor_params params; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 401 | u32 num_syms_per_line; |
| 402 | unsigned int i; |
| 403 | |
| 404 | if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) |
| 405 | return -EINVAL; |
| 406 | |
| 407 | output = link_rate * 8 * link->num_lanes; |
| 408 | input = pclk * config->bits_per_pixel; |
| 409 | |
| 410 | if (input >= output) |
| 411 | return -ERANGE; |
| 412 | |
| 413 | memset(¶ms, 0, sizeof(params)); |
| 414 | params.ratio = div64_u64(input * f, output); |
| 415 | params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); |
| 416 | params.precision = f; |
| 417 | params.error = 64 * f; |
| 418 | params.tu_size = 64; |
| 419 | |
| 420 | for (i = params.tu_size; i >= 32; i--) |
| 421 | if (tegra_sor_compute_params(sor, ¶ms, i)) |
| 422 | break; |
| 423 | |
| 424 | if (params.active_frac == 0) { |
| 425 | config->active_polarity = 0; |
| 426 | config->active_count = params.active_count; |
| 427 | |
| 428 | if (!params.active_polarity) |
| 429 | config->active_count--; |
| 430 | |
| 431 | config->tu_size = params.tu_size; |
| 432 | config->active_frac = 1; |
| 433 | } else { |
| 434 | config->active_polarity = params.active_polarity; |
| 435 | config->active_count = params.active_count; |
| 436 | config->active_frac = params.active_frac; |
| 437 | config->tu_size = params.tu_size; |
| 438 | } |
| 439 | |
| 440 | dev_dbg(sor->dev, |
| 441 | "polarity: %d active count: %d tu size: %d active frac: %d\n", |
| 442 | config->active_polarity, config->active_count, |
| 443 | config->tu_size, config->active_frac); |
| 444 | |
| 445 | watermark = params.ratio * config->tu_size * (f - params.ratio); |
| 446 | watermark = div_u64(watermark, f); |
| 447 | |
| 448 | watermark = div_u64(watermark + params.error, f); |
| 449 | config->watermark = watermark + (config->bits_per_pixel / 8) + 2; |
| 450 | num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * |
| 451 | (link->num_lanes * 8); |
| 452 | |
| 453 | if (config->watermark > 30) { |
| 454 | config->watermark = 30; |
| 455 | dev_err(sor->dev, |
| 456 | "unable to compute TU size, forcing watermark to %u\n", |
| 457 | config->watermark); |
| 458 | } else if (config->watermark > num_syms_per_line) { |
| 459 | config->watermark = num_syms_per_line; |
| 460 | dev_err(sor->dev, "watermark too high, forcing to %u\n", |
| 461 | config->watermark); |
| 462 | } |
| 463 | |
Thierry Reding | 7890b57 | 2014-06-05 16:12:46 +0200 | [diff] [blame] | 464 | /* compute the number of symbols per horizontal blanking interval */ |
| 465 | num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; |
| 466 | config->hblank_symbols = div_u64(num, pclk); |
| 467 | |
| 468 | if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) |
| 469 | config->hblank_symbols -= 3; |
| 470 | |
| 471 | config->hblank_symbols -= 12 / link->num_lanes; |
| 472 | |
| 473 | /* compute the number of symbols per vertical blanking interval */ |
| 474 | num = (mode->hdisplay - 25) * link_rate; |
| 475 | config->vblank_symbols = div_u64(num, pclk); |
| 476 | config->vblank_symbols -= 36 / link->num_lanes + 4; |
| 477 | |
| 478 | dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, |
| 479 | config->vblank_symbols); |
| 480 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 481 | return 0; |
| 482 | } |
| 483 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 484 | static int tegra_output_sor_enable(struct tegra_output *output) |
| 485 | { |
| 486 | struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); |
| 487 | struct drm_display_mode *mode = &dc->base.mode; |
| 488 | unsigned int vbe, vse, hbe, hse, vbs, hbs, i; |
| 489 | struct tegra_sor *sor = to_sor(output); |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 490 | struct tegra_sor_config config; |
| 491 | struct drm_dp_link link; |
| 492 | struct drm_dp_aux *aux; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 493 | unsigned long value; |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 494 | int err = 0; |
| 495 | |
| 496 | mutex_lock(&sor->lock); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 497 | |
| 498 | if (sor->enabled) |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 499 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 500 | |
| 501 | err = clk_prepare_enable(sor->clk); |
| 502 | if (err < 0) |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 503 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 504 | |
| 505 | reset_control_deassert(sor->rst); |
| 506 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 507 | /* FIXME: properly convert to struct drm_dp_aux */ |
| 508 | aux = (struct drm_dp_aux *)sor->dpaux; |
| 509 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 510 | if (sor->dpaux) { |
| 511 | err = tegra_dpaux_enable(sor->dpaux); |
| 512 | if (err < 0) |
| 513 | dev_err(sor->dev, "failed to enable DP: %d\n", err); |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 514 | |
| 515 | err = drm_dp_link_probe(aux, &link); |
| 516 | if (err < 0) { |
| 517 | dev_err(sor->dev, "failed to probe eDP link: %d\n", |
| 518 | err); |
| 519 | return err; |
| 520 | } |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 521 | } |
| 522 | |
| 523 | err = clk_set_parent(sor->clk, sor->clk_safe); |
| 524 | if (err < 0) |
| 525 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); |
| 526 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 527 | memset(&config, 0, sizeof(config)); |
| 528 | config.bits_per_pixel = 24; /* XXX: don't hardcode? */ |
| 529 | |
| 530 | err = tegra_sor_calc_config(sor, mode, &config, &link); |
| 531 | if (err < 0) |
| 532 | dev_err(sor->dev, "failed to compute link configuration: %d\n", |
| 533 | err); |
| 534 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 535 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 536 | value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; |
| 537 | value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; |
| 538 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 539 | |
| 540 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 541 | value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; |
| 542 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 543 | usleep_range(20, 100); |
| 544 | |
| 545 | value = tegra_sor_readl(sor, SOR_PLL_3); |
| 546 | value |= SOR_PLL_3_PLL_VDD_MODE_V3_3; |
| 547 | tegra_sor_writel(sor, value, SOR_PLL_3); |
| 548 | |
| 549 | value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST | |
| 550 | SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT; |
| 551 | tegra_sor_writel(sor, value, SOR_PLL_0); |
| 552 | |
| 553 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 554 | value |= SOR_PLL_2_SEQ_PLLCAPPD; |
| 555 | value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; |
| 556 | value |= SOR_PLL_2_LVDS_ENABLE; |
| 557 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 558 | |
| 559 | value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM; |
| 560 | tegra_sor_writel(sor, value, SOR_PLL_1); |
| 561 | |
| 562 | while (true) { |
| 563 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 564 | if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0) |
| 565 | break; |
| 566 | |
| 567 | usleep_range(250, 1000); |
| 568 | } |
| 569 | |
| 570 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 571 | value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE; |
| 572 | value &= ~SOR_PLL_2_PORT_POWERDOWN; |
| 573 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 574 | |
| 575 | /* |
| 576 | * power up |
| 577 | */ |
| 578 | |
| 579 | /* set safe link bandwidth (1.62 Gbps) */ |
| 580 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 581 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; |
| 582 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; |
| 583 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 584 | |
| 585 | /* step 1 */ |
| 586 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 587 | value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN | |
| 588 | SOR_PLL_2_BANDGAP_POWERDOWN; |
| 589 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 590 | |
| 591 | value = tegra_sor_readl(sor, SOR_PLL_0); |
| 592 | value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF; |
| 593 | tegra_sor_writel(sor, value, SOR_PLL_0); |
| 594 | |
| 595 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 596 | value &= ~SOR_DP_PADCTL_PAD_CAL_PD; |
| 597 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 598 | |
| 599 | /* step 2 */ |
| 600 | err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); |
| 601 | if (err < 0) { |
| 602 | dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 603 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 604 | } |
| 605 | |
| 606 | usleep_range(5, 100); |
| 607 | |
| 608 | /* step 3 */ |
| 609 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 610 | value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; |
| 611 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 612 | |
| 613 | usleep_range(20, 100); |
| 614 | |
| 615 | /* step 4 */ |
| 616 | value = tegra_sor_readl(sor, SOR_PLL_0); |
| 617 | value &= ~SOR_PLL_0_POWER_OFF; |
| 618 | value &= ~SOR_PLL_0_VCOPD; |
| 619 | tegra_sor_writel(sor, value, SOR_PLL_0); |
| 620 | |
| 621 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 622 | value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; |
| 623 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 624 | |
| 625 | usleep_range(200, 1000); |
| 626 | |
| 627 | /* step 5 */ |
| 628 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 629 | value &= ~SOR_PLL_2_PORT_POWERDOWN; |
| 630 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 631 | |
| 632 | /* switch to DP clock */ |
| 633 | err = clk_set_parent(sor->clk, sor->clk_dp); |
| 634 | if (err < 0) |
| 635 | dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); |
| 636 | |
| 637 | /* power dplanes (XXX parameterize based on link?) */ |
| 638 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 639 | value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | |
| 640 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; |
| 641 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 642 | |
| 643 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); |
| 644 | value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; |
| 645 | value |= SOR_DP_LINKCTL_LANE_COUNT(4); |
| 646 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); |
| 647 | |
| 648 | /* start lane sequencer */ |
| 649 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | |
| 650 | SOR_LANE_SEQ_CTL_POWER_STATE_UP; |
| 651 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); |
| 652 | |
| 653 | while (true) { |
| 654 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); |
| 655 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) |
| 656 | break; |
| 657 | |
| 658 | usleep_range(250, 1000); |
| 659 | } |
| 660 | |
Thierry Reding | a4263fe | 2014-06-05 16:16:23 +0200 | [diff] [blame] | 661 | /* set link bandwidth */ |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 662 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 663 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; |
Thierry Reding | a4263fe | 2014-06-05 16:16:23 +0200 | [diff] [blame] | 664 | value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 665 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 666 | |
| 667 | /* set linkctl */ |
| 668 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); |
| 669 | value |= SOR_DP_LINKCTL_ENABLE; |
| 670 | |
| 671 | value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 672 | value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 673 | |
| 674 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; |
| 675 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); |
| 676 | |
| 677 | for (i = 0, value = 0; i < 4; i++) { |
| 678 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 679 | SOR_DP_TPG_SCRAMBLER_GALIOS | |
| 680 | SOR_DP_TPG_PATTERN_NONE; |
| 681 | value = (value << 8) | lane; |
| 682 | } |
| 683 | |
| 684 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 685 | |
| 686 | value = tegra_sor_readl(sor, SOR_DP_CONFIG_0); |
| 687 | value &= ~SOR_DP_CONFIG_WATERMARK_MASK; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 688 | value |= SOR_DP_CONFIG_WATERMARK(config.watermark); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 689 | |
| 690 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 691 | value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 692 | |
| 693 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 694 | value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 695 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 696 | if (config.active_polarity) |
| 697 | value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; |
| 698 | else |
| 699 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 700 | |
| 701 | value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; |
| 702 | value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; /* XXX: don't hardcode? */ |
| 703 | tegra_sor_writel(sor, value, SOR_DP_CONFIG_0); |
| 704 | |
| 705 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); |
| 706 | value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; |
Thierry Reding | 7890b57 | 2014-06-05 16:12:46 +0200 | [diff] [blame] | 707 | value |= config.hblank_symbols & 0xffff; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 708 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); |
| 709 | |
| 710 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); |
| 711 | value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; |
Thierry Reding | 7890b57 | 2014-06-05 16:12:46 +0200 | [diff] [blame] | 712 | value |= config.vblank_symbols & 0xffff; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 713 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); |
| 714 | |
| 715 | /* enable pad calibration logic */ |
| 716 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 717 | value |= SOR_DP_PADCTL_PAD_CAL_PD; |
| 718 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 719 | |
| 720 | if (sor->dpaux) { |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 721 | u8 rate, lanes; |
| 722 | |
| 723 | err = drm_dp_link_probe(aux, &link); |
| 724 | if (err < 0) { |
| 725 | dev_err(sor->dev, "failed to probe eDP link: %d\n", |
| 726 | err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 727 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 728 | } |
| 729 | |
| 730 | err = drm_dp_link_power_up(aux, &link); |
| 731 | if (err < 0) { |
| 732 | dev_err(sor->dev, "failed to power up eDP link: %d\n", |
| 733 | err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 734 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 735 | } |
| 736 | |
| 737 | err = drm_dp_link_configure(aux, &link); |
| 738 | if (err < 0) { |
| 739 | dev_err(sor->dev, "failed to configure eDP link: %d\n", |
| 740 | err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 741 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 742 | } |
| 743 | |
| 744 | rate = drm_dp_link_rate_to_bw_code(link.rate); |
| 745 | lanes = link.num_lanes; |
| 746 | |
| 747 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 748 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; |
| 749 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); |
| 750 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 751 | |
| 752 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); |
| 753 | value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; |
| 754 | value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); |
| 755 | |
| 756 | if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) |
| 757 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; |
| 758 | |
| 759 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); |
| 760 | |
| 761 | /* disable training pattern generator */ |
| 762 | |
| 763 | for (i = 0; i < link.num_lanes; i++) { |
| 764 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 765 | SOR_DP_TPG_SCRAMBLER_GALIOS | |
| 766 | SOR_DP_TPG_PATTERN_NONE; |
| 767 | value = (value << 8) | lane; |
| 768 | } |
| 769 | |
| 770 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 771 | |
| 772 | err = tegra_sor_dp_train_fast(sor, &link); |
| 773 | if (err < 0) { |
| 774 | dev_err(sor->dev, "DP fast link training failed: %d\n", |
| 775 | err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 776 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 777 | } |
| 778 | |
| 779 | dev_dbg(sor->dev, "fast link training succeeded\n"); |
| 780 | } |
| 781 | |
| 782 | err = tegra_sor_power_up(sor, 250); |
| 783 | if (err < 0) { |
| 784 | dev_err(sor->dev, "failed to power up SOR: %d\n", err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 785 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 786 | } |
| 787 | |
| 788 | /* start display controller in continuous mode */ |
| 789 | value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); |
| 790 | value |= WRITE_MUX; |
| 791 | tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); |
| 792 | |
| 793 | tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS); |
| 794 | tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND); |
| 795 | |
| 796 | value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); |
| 797 | value &= ~WRITE_MUX; |
| 798 | tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); |
| 799 | |
| 800 | /* |
| 801 | * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete |
| 802 | * raster, associate with display controller) |
| 803 | */ |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 804 | value = SOR_STATE_ASY_VSYNCPOL | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 805 | SOR_STATE_ASY_HSYNCPOL | |
| 806 | SOR_STATE_ASY_PROTOCOL_DP_A | |
| 807 | SOR_STATE_ASY_CRC_MODE_COMPLETE | |
| 808 | SOR_STATE_ASY_OWNER(dc->pipe + 1); |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 809 | |
| 810 | switch (config.bits_per_pixel) { |
| 811 | case 24: |
| 812 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; |
| 813 | break; |
| 814 | |
| 815 | case 18: |
| 816 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; |
| 817 | break; |
| 818 | |
| 819 | default: |
| 820 | BUG(); |
| 821 | break; |
| 822 | } |
| 823 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 824 | tegra_sor_writel(sor, value, SOR_STATE_1); |
| 825 | |
| 826 | /* |
| 827 | * TODO: The video timing programming below doesn't seem to match the |
| 828 | * register definitions. |
| 829 | */ |
| 830 | |
| 831 | value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); |
| 832 | tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0)); |
| 833 | |
| 834 | vse = mode->vsync_end - mode->vsync_start - 1; |
| 835 | hse = mode->hsync_end - mode->hsync_start - 1; |
| 836 | |
| 837 | value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); |
| 838 | tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0)); |
| 839 | |
| 840 | vbe = vse + (mode->vsync_start - mode->vdisplay); |
| 841 | hbe = hse + (mode->hsync_start - mode->hdisplay); |
| 842 | |
| 843 | value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); |
| 844 | tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0)); |
| 845 | |
| 846 | vbs = vbe + mode->vdisplay; |
| 847 | hbs = hbe + mode->hdisplay; |
| 848 | |
| 849 | value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); |
| 850 | tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); |
| 851 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 852 | /* CSTM (LVDS, link A/B, upper) */ |
Stéphane Marchesin | 143b1df | 2014-05-22 20:32:47 -0700 | [diff] [blame] | 853 | value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 854 | SOR_CSTM_UPPER; |
| 855 | tegra_sor_writel(sor, value, SOR_CSTM); |
| 856 | |
| 857 | /* PWM setup */ |
| 858 | err = tegra_sor_setup_pwm(sor, 250); |
| 859 | if (err < 0) { |
| 860 | dev_err(sor->dev, "failed to setup PWM: %d\n", err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 861 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 862 | } |
| 863 | |
| 864 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 865 | value |= SOR_ENABLE; |
| 866 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 867 | |
| 868 | tegra_sor_update(sor); |
| 869 | |
| 870 | err = tegra_sor_attach(sor); |
| 871 | if (err < 0) { |
| 872 | dev_err(sor->dev, "failed to attach SOR: %d\n", err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 873 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 874 | } |
| 875 | |
| 876 | err = tegra_sor_wakeup(sor); |
| 877 | if (err < 0) { |
| 878 | dev_err(sor->dev, "failed to enable DC: %d\n", err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 879 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 880 | } |
| 881 | |
| 882 | sor->enabled = true; |
| 883 | |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 884 | unlock: |
| 885 | mutex_unlock(&sor->lock); |
| 886 | return err; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 887 | } |
| 888 | |
| 889 | static int tegra_sor_detach(struct tegra_sor *sor) |
| 890 | { |
| 891 | unsigned long value, timeout; |
| 892 | |
| 893 | /* switch to safe mode */ |
| 894 | value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); |
| 895 | value &= ~SOR_SUPER_STATE_MODE_NORMAL; |
| 896 | tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); |
| 897 | tegra_sor_super_update(sor); |
| 898 | |
| 899 | timeout = jiffies + msecs_to_jiffies(250); |
| 900 | |
| 901 | while (time_before(jiffies, timeout)) { |
| 902 | value = tegra_sor_readl(sor, SOR_PWR); |
| 903 | if (value & SOR_PWR_MODE_SAFE) |
| 904 | break; |
| 905 | } |
| 906 | |
| 907 | if ((value & SOR_PWR_MODE_SAFE) == 0) |
| 908 | return -ETIMEDOUT; |
| 909 | |
| 910 | /* go to sleep */ |
| 911 | value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); |
| 912 | value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; |
| 913 | tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); |
| 914 | tegra_sor_super_update(sor); |
| 915 | |
| 916 | /* detach */ |
| 917 | value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); |
| 918 | value &= ~SOR_SUPER_STATE_ATTACHED; |
| 919 | tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); |
| 920 | tegra_sor_super_update(sor); |
| 921 | |
| 922 | timeout = jiffies + msecs_to_jiffies(250); |
| 923 | |
| 924 | while (time_before(jiffies, timeout)) { |
| 925 | value = tegra_sor_readl(sor, SOR_TEST); |
| 926 | if ((value & SOR_TEST_ATTACHED) == 0) |
| 927 | break; |
| 928 | |
| 929 | usleep_range(25, 100); |
| 930 | } |
| 931 | |
| 932 | if ((value & SOR_TEST_ATTACHED) != 0) |
| 933 | return -ETIMEDOUT; |
| 934 | |
| 935 | return 0; |
| 936 | } |
| 937 | |
| 938 | static int tegra_sor_power_down(struct tegra_sor *sor) |
| 939 | { |
| 940 | unsigned long value, timeout; |
| 941 | int err; |
| 942 | |
| 943 | value = tegra_sor_readl(sor, SOR_PWR); |
| 944 | value &= ~SOR_PWR_NORMAL_STATE_PU; |
| 945 | value |= SOR_PWR_TRIGGER; |
| 946 | tegra_sor_writel(sor, value, SOR_PWR); |
| 947 | |
| 948 | timeout = jiffies + msecs_to_jiffies(250); |
| 949 | |
| 950 | while (time_before(jiffies, timeout)) { |
| 951 | value = tegra_sor_readl(sor, SOR_PWR); |
| 952 | if ((value & SOR_PWR_TRIGGER) == 0) |
| 953 | return 0; |
| 954 | |
| 955 | usleep_range(25, 100); |
| 956 | } |
| 957 | |
| 958 | if ((value & SOR_PWR_TRIGGER) != 0) |
| 959 | return -ETIMEDOUT; |
| 960 | |
| 961 | err = clk_set_parent(sor->clk, sor->clk_safe); |
| 962 | if (err < 0) |
| 963 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); |
| 964 | |
| 965 | value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); |
| 966 | value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | |
| 967 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); |
| 968 | tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); |
| 969 | |
| 970 | /* stop lane sequencer */ |
Stéphane Marchesin | ca185c6 | 2014-05-22 20:32:48 -0700 | [diff] [blame] | 971 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 972 | SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; |
| 973 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); |
| 974 | |
| 975 | timeout = jiffies + msecs_to_jiffies(250); |
| 976 | |
| 977 | while (time_before(jiffies, timeout)) { |
| 978 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); |
| 979 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) |
| 980 | break; |
| 981 | |
| 982 | usleep_range(25, 100); |
| 983 | } |
| 984 | |
| 985 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) |
| 986 | return -ETIMEDOUT; |
| 987 | |
| 988 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 989 | value |= SOR_PLL_2_PORT_POWERDOWN; |
| 990 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 991 | |
| 992 | usleep_range(20, 100); |
| 993 | |
| 994 | value = tegra_sor_readl(sor, SOR_PLL_0); |
| 995 | value |= SOR_PLL_0_POWER_OFF; |
| 996 | value |= SOR_PLL_0_VCOPD; |
| 997 | tegra_sor_writel(sor, value, SOR_PLL_0); |
| 998 | |
| 999 | value = tegra_sor_readl(sor, SOR_PLL_2); |
| 1000 | value |= SOR_PLL_2_SEQ_PLLCAPPD; |
| 1001 | value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; |
| 1002 | tegra_sor_writel(sor, value, SOR_PLL_2); |
| 1003 | |
| 1004 | usleep_range(20, 100); |
| 1005 | |
| 1006 | return 0; |
| 1007 | } |
| 1008 | |
| 1009 | static int tegra_output_sor_disable(struct tegra_output *output) |
| 1010 | { |
| 1011 | struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); |
| 1012 | struct tegra_sor *sor = to_sor(output); |
| 1013 | unsigned long value; |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1014 | int err = 0; |
| 1015 | |
| 1016 | mutex_lock(&sor->lock); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1017 | |
| 1018 | if (!sor->enabled) |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1019 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1020 | |
| 1021 | err = tegra_sor_detach(sor); |
| 1022 | if (err < 0) { |
| 1023 | dev_err(sor->dev, "failed to detach SOR: %d\n", err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1024 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1025 | } |
| 1026 | |
| 1027 | tegra_sor_writel(sor, 0, SOR_STATE_1); |
| 1028 | tegra_sor_update(sor); |
| 1029 | |
| 1030 | /* |
| 1031 | * The following accesses registers of the display controller, so make |
| 1032 | * sure it's only executed when the output is attached to one. |
| 1033 | */ |
| 1034 | if (dc) { |
| 1035 | /* |
| 1036 | * XXX: We can't do this here because it causes the SOR to go |
| 1037 | * into an erroneous state and the output will look scrambled |
| 1038 | * the next time it is enabled. Presumably this is because we |
| 1039 | * should be doing this only on the next VBLANK. A possible |
| 1040 | * solution would be to queue a "power-off" event to trigger |
| 1041 | * this code to be run during the next VBLANK. |
| 1042 | */ |
| 1043 | /* |
| 1044 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); |
| 1045 | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | |
| 1046 | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); |
| 1047 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); |
| 1048 | */ |
| 1049 | |
| 1050 | value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); |
| 1051 | value &= ~DISP_CTRL_MODE_MASK; |
| 1052 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); |
| 1053 | |
| 1054 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 1055 | value &= ~SOR_ENABLE; |
| 1056 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 1057 | |
| 1058 | tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); |
| 1059 | tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); |
| 1060 | } |
| 1061 | |
| 1062 | err = tegra_sor_power_down(sor); |
| 1063 | if (err < 0) { |
| 1064 | dev_err(sor->dev, "failed to power down SOR: %d\n", err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1065 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1066 | } |
| 1067 | |
| 1068 | if (sor->dpaux) { |
| 1069 | err = tegra_dpaux_disable(sor->dpaux); |
| 1070 | if (err < 0) { |
| 1071 | dev_err(sor->dev, "failed to disable DP: %d\n", err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1072 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1073 | } |
| 1074 | } |
| 1075 | |
| 1076 | err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); |
| 1077 | if (err < 0) { |
| 1078 | dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1079 | goto unlock; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1080 | } |
| 1081 | |
| 1082 | reset_control_assert(sor->rst); |
| 1083 | clk_disable_unprepare(sor->clk); |
| 1084 | |
| 1085 | sor->enabled = false; |
| 1086 | |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1087 | unlock: |
| 1088 | mutex_unlock(&sor->lock); |
| 1089 | return err; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1090 | } |
| 1091 | |
| 1092 | static int tegra_output_sor_setup_clock(struct tegra_output *output, |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 1093 | struct clk *clk, unsigned long pclk, |
| 1094 | unsigned int *div) |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1095 | { |
| 1096 | struct tegra_sor *sor = to_sor(output); |
| 1097 | int err; |
| 1098 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1099 | err = clk_set_parent(clk, sor->clk_parent); |
| 1100 | if (err < 0) { |
| 1101 | dev_err(sor->dev, "failed to set parent clock: %d\n", err); |
| 1102 | return err; |
| 1103 | } |
| 1104 | |
| 1105 | err = clk_set_rate(sor->clk_parent, pclk); |
| 1106 | if (err < 0) { |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 1107 | dev_err(sor->dev, "failed to set clock rate to %lu Hz\n", pclk); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1108 | return err; |
| 1109 | } |
| 1110 | |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 1111 | *div = 0; |
| 1112 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1113 | return 0; |
| 1114 | } |
| 1115 | |
| 1116 | static int tegra_output_sor_check_mode(struct tegra_output *output, |
| 1117 | struct drm_display_mode *mode, |
| 1118 | enum drm_mode_status *status) |
| 1119 | { |
| 1120 | /* |
| 1121 | * FIXME: For now, always assume that the mode is okay. |
| 1122 | */ |
| 1123 | |
| 1124 | *status = MODE_OK; |
| 1125 | |
| 1126 | return 0; |
| 1127 | } |
| 1128 | |
| 1129 | static enum drm_connector_status |
| 1130 | tegra_output_sor_detect(struct tegra_output *output) |
| 1131 | { |
| 1132 | struct tegra_sor *sor = to_sor(output); |
| 1133 | |
| 1134 | if (sor->dpaux) |
| 1135 | return tegra_dpaux_detect(sor->dpaux); |
| 1136 | |
| 1137 | return connector_status_unknown; |
| 1138 | } |
| 1139 | |
| 1140 | static const struct tegra_output_ops sor_ops = { |
| 1141 | .enable = tegra_output_sor_enable, |
| 1142 | .disable = tegra_output_sor_disable, |
| 1143 | .setup_clock = tegra_output_sor_setup_clock, |
| 1144 | .check_mode = tegra_output_sor_check_mode, |
| 1145 | .detect = tegra_output_sor_detect, |
| 1146 | }; |
| 1147 | |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1148 | static int tegra_sor_crc_open(struct inode *inode, struct file *file) |
| 1149 | { |
| 1150 | file->private_data = inode->i_private; |
| 1151 | |
| 1152 | return 0; |
| 1153 | } |
| 1154 | |
| 1155 | static int tegra_sor_crc_release(struct inode *inode, struct file *file) |
| 1156 | { |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
| 1160 | static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) |
| 1161 | { |
| 1162 | u32 value; |
| 1163 | |
| 1164 | timeout = jiffies + msecs_to_jiffies(timeout); |
| 1165 | |
| 1166 | while (time_before(jiffies, timeout)) { |
| 1167 | value = tegra_sor_readl(sor, SOR_CRC_A); |
| 1168 | if (value & SOR_CRC_A_VALID) |
| 1169 | return 0; |
| 1170 | |
| 1171 | usleep_range(100, 200); |
| 1172 | } |
| 1173 | |
| 1174 | return -ETIMEDOUT; |
| 1175 | } |
| 1176 | |
| 1177 | static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer, |
| 1178 | size_t size, loff_t *ppos) |
| 1179 | { |
| 1180 | struct tegra_sor *sor = file->private_data; |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1181 | ssize_t num, err; |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1182 | char buf[10]; |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1183 | u32 value; |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1184 | |
| 1185 | mutex_lock(&sor->lock); |
| 1186 | |
| 1187 | if (!sor->enabled) { |
| 1188 | err = -EAGAIN; |
| 1189 | goto unlock; |
| 1190 | } |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1191 | |
| 1192 | value = tegra_sor_readl(sor, SOR_STATE_1); |
| 1193 | value &= ~SOR_STATE_ASY_CRC_MODE_MASK; |
| 1194 | tegra_sor_writel(sor, value, SOR_STATE_1); |
| 1195 | |
| 1196 | value = tegra_sor_readl(sor, SOR_CRC_CNTRL); |
| 1197 | value |= SOR_CRC_CNTRL_ENABLE; |
| 1198 | tegra_sor_writel(sor, value, SOR_CRC_CNTRL); |
| 1199 | |
| 1200 | value = tegra_sor_readl(sor, SOR_TEST); |
| 1201 | value &= ~SOR_TEST_CRC_POST_SERIALIZE; |
| 1202 | tegra_sor_writel(sor, value, SOR_TEST); |
| 1203 | |
| 1204 | err = tegra_sor_crc_wait(sor, 100); |
| 1205 | if (err < 0) |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1206 | goto unlock; |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1207 | |
| 1208 | tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A); |
| 1209 | value = tegra_sor_readl(sor, SOR_CRC_B); |
| 1210 | |
| 1211 | num = scnprintf(buf, sizeof(buf), "%08x\n", value); |
| 1212 | |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1213 | err = simple_read_from_buffer(buffer, size, ppos, buf, num); |
| 1214 | |
| 1215 | unlock: |
| 1216 | mutex_unlock(&sor->lock); |
| 1217 | return err; |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1218 | } |
| 1219 | |
| 1220 | static const struct file_operations tegra_sor_crc_fops = { |
| 1221 | .owner = THIS_MODULE, |
| 1222 | .open = tegra_sor_crc_open, |
| 1223 | .read = tegra_sor_crc_read, |
| 1224 | .release = tegra_sor_crc_release, |
| 1225 | }; |
| 1226 | |
Thierry Reding | 1b0c7b4 | 2014-05-28 13:46:12 +0200 | [diff] [blame] | 1227 | static int tegra_sor_debugfs_init(struct tegra_sor *sor, |
| 1228 | struct drm_minor *minor) |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1229 | { |
| 1230 | struct dentry *entry; |
| 1231 | int err = 0; |
| 1232 | |
Thierry Reding | 1b0c7b4 | 2014-05-28 13:46:12 +0200 | [diff] [blame] | 1233 | sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root); |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1234 | if (!sor->debugfs) |
| 1235 | return -ENOMEM; |
| 1236 | |
| 1237 | entry = debugfs_create_file("crc", 0644, sor->debugfs, sor, |
| 1238 | &tegra_sor_crc_fops); |
| 1239 | if (!entry) { |
| 1240 | dev_err(sor->dev, |
| 1241 | "cannot create /sys/kernel/debug/dri/%s/sor/crc\n", |
Thierry Reding | 1b0c7b4 | 2014-05-28 13:46:12 +0200 | [diff] [blame] | 1242 | minor->debugfs_root->d_name.name); |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1243 | err = -ENOMEM; |
| 1244 | goto remove; |
| 1245 | } |
| 1246 | |
| 1247 | return err; |
| 1248 | |
| 1249 | remove: |
| 1250 | debugfs_remove(sor->debugfs); |
| 1251 | sor->debugfs = NULL; |
| 1252 | return err; |
| 1253 | } |
| 1254 | |
| 1255 | static int tegra_sor_debugfs_exit(struct tegra_sor *sor) |
| 1256 | { |
Thierry Reding | 9578184 | 2014-04-25 16:48:36 +0200 | [diff] [blame] | 1257 | debugfs_remove_recursive(sor->debugfs); |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1258 | sor->debugfs = NULL; |
| 1259 | |
| 1260 | return 0; |
| 1261 | } |
| 1262 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1263 | static int tegra_sor_init(struct host1x_client *client) |
| 1264 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1265 | struct drm_device *drm = dev_get_drvdata(client->parent); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1266 | struct tegra_sor *sor = host1x_client_to_sor(client); |
| 1267 | int err; |
| 1268 | |
| 1269 | if (!sor->dpaux) |
| 1270 | return -ENODEV; |
| 1271 | |
| 1272 | sor->output.type = TEGRA_OUTPUT_EDP; |
| 1273 | |
| 1274 | sor->output.dev = sor->dev; |
| 1275 | sor->output.ops = &sor_ops; |
| 1276 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1277 | err = tegra_output_init(drm, &sor->output); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1278 | if (err < 0) { |
| 1279 | dev_err(sor->dev, "output setup failed: %d\n", err); |
| 1280 | return err; |
| 1281 | } |
| 1282 | |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1283 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
Thierry Reding | 1b0c7b4 | 2014-05-28 13:46:12 +0200 | [diff] [blame] | 1284 | err = tegra_sor_debugfs_init(sor, drm->primary); |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1285 | if (err < 0) |
| 1286 | dev_err(sor->dev, "debugfs setup failed: %d\n", err); |
| 1287 | } |
| 1288 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1289 | if (sor->dpaux) { |
| 1290 | err = tegra_dpaux_attach(sor->dpaux, &sor->output); |
| 1291 | if (err < 0) { |
| 1292 | dev_err(sor->dev, "failed to attach DP: %d\n", err); |
| 1293 | return err; |
| 1294 | } |
| 1295 | } |
| 1296 | |
| 1297 | return 0; |
| 1298 | } |
| 1299 | |
| 1300 | static int tegra_sor_exit(struct host1x_client *client) |
| 1301 | { |
| 1302 | struct tegra_sor *sor = host1x_client_to_sor(client); |
| 1303 | int err; |
| 1304 | |
| 1305 | err = tegra_output_disable(&sor->output); |
| 1306 | if (err < 0) { |
| 1307 | dev_err(sor->dev, "output failed to disable: %d\n", err); |
| 1308 | return err; |
| 1309 | } |
| 1310 | |
| 1311 | if (sor->dpaux) { |
| 1312 | err = tegra_dpaux_detach(sor->dpaux); |
| 1313 | if (err < 0) { |
| 1314 | dev_err(sor->dev, "failed to detach DP: %d\n", err); |
| 1315 | return err; |
| 1316 | } |
| 1317 | } |
| 1318 | |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 1319 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
| 1320 | err = tegra_sor_debugfs_exit(sor); |
| 1321 | if (err < 0) |
| 1322 | dev_err(sor->dev, "debugfs cleanup failed: %d\n", err); |
| 1323 | } |
| 1324 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1325 | err = tegra_output_exit(&sor->output); |
| 1326 | if (err < 0) { |
| 1327 | dev_err(sor->dev, "output cleanup failed: %d\n", err); |
| 1328 | return err; |
| 1329 | } |
| 1330 | |
| 1331 | return 0; |
| 1332 | } |
| 1333 | |
| 1334 | static const struct host1x_client_ops sor_client_ops = { |
| 1335 | .init = tegra_sor_init, |
| 1336 | .exit = tegra_sor_exit, |
| 1337 | }; |
| 1338 | |
| 1339 | static int tegra_sor_probe(struct platform_device *pdev) |
| 1340 | { |
| 1341 | struct device_node *np; |
| 1342 | struct tegra_sor *sor; |
| 1343 | struct resource *regs; |
| 1344 | int err; |
| 1345 | |
| 1346 | sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); |
| 1347 | if (!sor) |
| 1348 | return -ENOMEM; |
| 1349 | |
| 1350 | sor->output.dev = sor->dev = &pdev->dev; |
| 1351 | |
| 1352 | np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); |
| 1353 | if (np) { |
| 1354 | sor->dpaux = tegra_dpaux_find_by_of_node(np); |
| 1355 | of_node_put(np); |
| 1356 | |
| 1357 | if (!sor->dpaux) |
| 1358 | return -EPROBE_DEFER; |
| 1359 | } |
| 1360 | |
| 1361 | err = tegra_output_probe(&sor->output); |
| 1362 | if (err < 0) |
| 1363 | return err; |
| 1364 | |
| 1365 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1366 | sor->regs = devm_ioremap_resource(&pdev->dev, regs); |
| 1367 | if (IS_ERR(sor->regs)) |
| 1368 | return PTR_ERR(sor->regs); |
| 1369 | |
| 1370 | sor->rst = devm_reset_control_get(&pdev->dev, "sor"); |
| 1371 | if (IS_ERR(sor->rst)) |
| 1372 | return PTR_ERR(sor->rst); |
| 1373 | |
| 1374 | sor->clk = devm_clk_get(&pdev->dev, NULL); |
| 1375 | if (IS_ERR(sor->clk)) |
| 1376 | return PTR_ERR(sor->clk); |
| 1377 | |
| 1378 | sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); |
| 1379 | if (IS_ERR(sor->clk_parent)) |
| 1380 | return PTR_ERR(sor->clk_parent); |
| 1381 | |
| 1382 | err = clk_prepare_enable(sor->clk_parent); |
| 1383 | if (err < 0) |
| 1384 | return err; |
| 1385 | |
| 1386 | sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); |
| 1387 | if (IS_ERR(sor->clk_safe)) |
| 1388 | return PTR_ERR(sor->clk_safe); |
| 1389 | |
| 1390 | err = clk_prepare_enable(sor->clk_safe); |
| 1391 | if (err < 0) |
| 1392 | return err; |
| 1393 | |
| 1394 | sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); |
| 1395 | if (IS_ERR(sor->clk_dp)) |
| 1396 | return PTR_ERR(sor->clk_dp); |
| 1397 | |
| 1398 | err = clk_prepare_enable(sor->clk_dp); |
| 1399 | if (err < 0) |
| 1400 | return err; |
| 1401 | |
| 1402 | INIT_LIST_HEAD(&sor->client.list); |
| 1403 | sor->client.ops = &sor_client_ops; |
| 1404 | sor->client.dev = &pdev->dev; |
| 1405 | |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1406 | mutex_init(&sor->lock); |
| 1407 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1408 | err = host1x_client_register(&sor->client); |
| 1409 | if (err < 0) { |
| 1410 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", |
| 1411 | err); |
| 1412 | return err; |
| 1413 | } |
| 1414 | |
| 1415 | platform_set_drvdata(pdev, sor); |
| 1416 | |
| 1417 | return 0; |
| 1418 | } |
| 1419 | |
| 1420 | static int tegra_sor_remove(struct platform_device *pdev) |
| 1421 | { |
| 1422 | struct tegra_sor *sor = platform_get_drvdata(pdev); |
| 1423 | int err; |
| 1424 | |
| 1425 | err = host1x_client_unregister(&sor->client); |
| 1426 | if (err < 0) { |
| 1427 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", |
| 1428 | err); |
| 1429 | return err; |
| 1430 | } |
| 1431 | |
| 1432 | clk_disable_unprepare(sor->clk_parent); |
| 1433 | clk_disable_unprepare(sor->clk_safe); |
| 1434 | clk_disable_unprepare(sor->clk_dp); |
| 1435 | clk_disable_unprepare(sor->clk); |
| 1436 | |
| 1437 | return 0; |
| 1438 | } |
| 1439 | |
| 1440 | static const struct of_device_id tegra_sor_of_match[] = { |
| 1441 | { .compatible = "nvidia,tegra124-sor", }, |
| 1442 | { }, |
| 1443 | }; |
| 1444 | |
| 1445 | struct platform_driver tegra_sor_driver = { |
| 1446 | .driver = { |
| 1447 | .name = "tegra-sor", |
| 1448 | .of_match_table = tegra_sor_of_match, |
| 1449 | }, |
| 1450 | .probe = tegra_sor_probe, |
| 1451 | .remove = tegra_sor_remove, |
| 1452 | }; |