Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 1 | |
| 2 | /* |
| 3 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | */ |
| 10 | |
Troy Kisky | e6117ff | 2013-11-14 14:02:10 -0700 | [diff] [blame] | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 12 | #include "imx6q-pinfunc.h" |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 13 | #include "imx6qdl.dtsi" |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 14 | |
| 15 | / { |
Sascha Hauer | a26be0f | 2014-01-16 13:44:19 +0100 | [diff] [blame] | 16 | aliases { |
| 17 | spi4 = &ecspi5; |
| 18 | }; |
| 19 | |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 20 | cpus { |
| 21 | #address-cells = <1>; |
| 22 | #size-cells = <0>; |
| 23 | |
| 24 | cpu@0 { |
| 25 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame] | 26 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 27 | reg = <0>; |
| 28 | next-level-cache = <&L2>; |
| 29 | operating-points = < |
| 30 | /* kHz uV */ |
| 31 | 1200000 1275000 |
| 32 | 996000 1250000 |
| 33 | 792000 1150000 |
Anson Huang | 26ea580 | 2013-12-16 16:07:37 -0500 | [diff] [blame] | 34 | 396000 975000 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 35 | >; |
Anson Huang | 69171ed | 2013-12-19 09:16:48 -0500 | [diff] [blame] | 36 | fsl,soc-operating-points = < |
| 37 | /* ARM kHz SOC-PU uV */ |
| 38 | 1200000 1275000 |
| 39 | 996000 1250000 |
| 40 | 792000 1175000 |
| 41 | 396000 1175000 |
| 42 | >; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 43 | clock-latency = <61036>; /* two CLK32 periods */ |
| 44 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, |
| 45 | <&clks 17>, <&clks 170>; |
| 46 | clock-names = "arm", "pll2_pfd2_396m", "step", |
| 47 | "pll1_sw", "pll1_sys"; |
| 48 | arm-supply = <®_arm>; |
| 49 | pu-supply = <®_pu>; |
| 50 | soc-supply = <®_soc>; |
| 51 | }; |
| 52 | |
| 53 | cpu@1 { |
| 54 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame] | 55 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 56 | reg = <1>; |
| 57 | next-level-cache = <&L2>; |
| 58 | }; |
| 59 | |
| 60 | cpu@2 { |
| 61 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame] | 62 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 63 | reg = <2>; |
| 64 | next-level-cache = <&L2>; |
| 65 | }; |
| 66 | |
| 67 | cpu@3 { |
| 68 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame] | 69 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 70 | reg = <3>; |
| 71 | next-level-cache = <&L2>; |
| 72 | }; |
| 73 | }; |
| 74 | |
| 75 | soc { |
Shawn Guo | 951ebf5 | 2013-07-23 15:25:13 +0800 | [diff] [blame] | 76 | ocram: sram@00900000 { |
| 77 | compatible = "mmio-sram"; |
| 78 | reg = <0x00900000 0x40000>; |
| 79 | clocks = <&clks 142>; |
| 80 | }; |
| 81 | |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 82 | aips-bus@02000000 { /* AIPS1 */ |
| 83 | spba-bus@02000000 { |
| 84 | ecspi5: ecspi@02018000 { |
| 85 | #address-cells = <1>; |
| 86 | #size-cells = <0>; |
| 87 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 88 | reg = <0x02018000 0x4000>; |
Troy Kisky | e6117ff | 2013-11-14 14:02:10 -0700 | [diff] [blame] | 89 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 90 | clocks = <&clks 116>, <&clks 116>; |
| 91 | clock-names = "ipg", "per"; |
| 92 | status = "disabled"; |
| 93 | }; |
| 94 | }; |
| 95 | |
| 96 | iomuxc: iomuxc@020e0000 { |
| 97 | compatible = "fsl,imx6q-iomuxc"; |
Shawn Guo | b72ce92 | 2013-07-12 11:38:50 +0800 | [diff] [blame] | 98 | |
| 99 | ipu2 { |
| 100 | pinctrl_ipu2_1: ipu2grp-1 { |
| 101 | fsl,pins = < |
| 102 | MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10 |
| 103 | MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10 |
| 104 | MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10 |
| 105 | MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10 |
| 106 | MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000 |
| 107 | MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10 |
| 108 | MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10 |
| 109 | MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10 |
| 110 | MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10 |
| 111 | MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10 |
| 112 | MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10 |
| 113 | MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10 |
| 114 | MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10 |
| 115 | MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10 |
| 116 | MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10 |
| 117 | MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10 |
| 118 | MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10 |
| 119 | MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10 |
| 120 | MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10 |
| 121 | MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10 |
| 122 | MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10 |
| 123 | MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10 |
| 124 | MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10 |
| 125 | MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10 |
| 126 | MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10 |
| 127 | MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10 |
| 128 | MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10 |
| 129 | MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10 |
| 130 | MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 |
| 131 | >; |
| 132 | }; |
| 133 | }; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 134 | }; |
| 135 | }; |
| 136 | |
Richard Zhu | 0fb1f80 | 2013-07-16 11:28:46 +0800 | [diff] [blame] | 137 | sata: sata@02200000 { |
| 138 | compatible = "fsl,imx6q-ahci"; |
| 139 | reg = <0x02200000 0x4000>; |
Troy Kisky | e6117ff | 2013-11-14 14:02:10 -0700 | [diff] [blame] | 140 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
Richard Zhu | 0fb1f80 | 2013-07-16 11:28:46 +0800 | [diff] [blame] | 141 | clocks = <&clks 154>, <&clks 187>, <&clks 105>; |
| 142 | clock-names = "sata", "sata_ref", "ahb"; |
| 143 | status = "disabled"; |
| 144 | }; |
| 145 | |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 146 | ipu2: ipu@02800000 { |
| 147 | #crtc-cells = <1>; |
| 148 | compatible = "fsl,imx6q-ipu"; |
| 149 | reg = <0x02800000 0x400000>; |
Troy Kisky | e6117ff | 2013-11-14 14:02:10 -0700 | [diff] [blame] | 150 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, |
| 151 | <0 7 IRQ_TYPE_LEVEL_HIGH>; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 152 | clocks = <&clks 133>, <&clks 134>, <&clks 137>; |
| 153 | clock-names = "bus", "di0", "di1"; |
Philipp Zabel | 09ebf36 | 2013-03-28 17:35:20 +0100 | [diff] [blame] | 154 | resets = <&src 4>; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 155 | }; |
| 156 | }; |
| 157 | }; |
Steffen Trumtrar | 41c0434 | 2013-03-28 16:23:35 +0100 | [diff] [blame] | 158 | |
| 159 | &ldb { |
| 160 | clocks = <&clks 33>, <&clks 34>, |
| 161 | <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>, |
| 162 | <&clks 135>, <&clks 136>; |
| 163 | clock-names = "di0_pll", "di1_pll", |
| 164 | "di0_sel", "di1_sel", "di2_sel", "di3_sel", |
| 165 | "di0", "di1"; |
| 166 | |
| 167 | lvds-channel@0 { |
| 168 | crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; |
| 169 | }; |
| 170 | |
| 171 | lvds-channel@1 { |
| 172 | crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; |
| 173 | }; |
| 174 | }; |