Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 1 | /* |
John Rigby | 5b70a09 | 2008-10-07 13:00:18 -0600 | [diff] [blame] | 2 | * MPC83xx/85xx/86xx PCI/PCIE support routing. |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 3 | * |
Prabhakar Kushwaha | f4154e1 | 2011-02-24 15:05:04 +0530 | [diff] [blame] | 4 | * Copyright 2007-2011 Freescale Semiconductor, Inc. |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 5 | * Copyright 2008-2009 MontaVista Software, Inc. |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 6 | * |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 7 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 8 | * Recode: ZHANG WEI <wei.zhang@freescale.com> |
| 9 | * Rewrite the routing for Frescale PCI and PCI Express |
| 10 | * Roy Zang <tie-fei.zang@freescale.com> |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 11 | * MPC83xx PCI-Express support: |
| 12 | * Tony Li <tony.li@freescale.com> |
| 13 | * Anton Vorontsov <avorontsov@ru.mvista.com> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify it |
| 16 | * under the terms of the GNU General Public License as published by the |
| 17 | * Free Software Foundation; either version 2 of the License, or (at your |
| 18 | * option) any later version. |
| 19 | */ |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 20 | #include <linux/kernel.h> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 21 | #include <linux/pci.h> |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 22 | #include <linux/delay.h> |
| 23 | #include <linux/string.h> |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/bootmem.h> |
Yinghai Lu | 95f72d1 | 2010-07-12 14:36:09 +1000 | [diff] [blame] | 26 | #include <linux/memblock.h> |
Kumar Gala | 54c1819 | 2009-05-08 15:05:23 -0500 | [diff] [blame] | 27 | #include <linux/log2.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 28 | #include <linux/slab.h> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 29 | |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 30 | #include <asm/io.h> |
| 31 | #include <asm/prom.h> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 32 | #include <asm/pci-bridge.h> |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 33 | #include <asm/machdep.h> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 34 | #include <sysdev/fsl_soc.h> |
Roy Zang | 55c4499 | 2007-07-10 18:44:34 +0800 | [diff] [blame] | 35 | #include <sysdev/fsl_pci.h> |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 36 | |
Kumar Gala | b8f44ec | 2010-08-05 02:45:08 -0500 | [diff] [blame] | 37 | static int fsl_pcie_bus_fixup, is_mpc83xx_pci; |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 38 | |
| 39 | static void __init quirk_fsl_pcie_header(struct pci_dev *dev) |
| 40 | { |
| 41 | /* if we aren't a PCIe don't bother */ |
| 42 | if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) |
| 43 | return; |
| 44 | |
| 45 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; |
| 46 | fsl_pcie_bus_fixup = 1; |
| 47 | return; |
| 48 | } |
| 49 | |
| 50 | static int __init fsl_pcie_check_link(struct pci_controller *hose) |
| 51 | { |
| 52 | u32 val; |
| 53 | |
| 54 | early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); |
| 55 | if (val < PCIE_LTSSM_L0) |
| 56 | return 1; |
| 57 | return 0; |
| 58 | } |
| 59 | |
Kumar Gala | 5753c08 | 2009-10-16 18:31:48 -0500 | [diff] [blame] | 60 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 61 | static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, |
| 62 | unsigned int index, const struct resource *res, |
| 63 | resource_size_t offset) |
| 64 | { |
| 65 | resource_size_t pci_addr = res->start - offset; |
| 66 | resource_size_t phys_addr = res->start; |
| 67 | resource_size_t size = res->end - res->start + 1; |
| 68 | u32 flags = 0x80044000; /* enable & mem R/W */ |
| 69 | unsigned int i; |
| 70 | |
| 71 | pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", |
| 72 | (u64)res->start, (u64)size); |
| 73 | |
Trent Piepho | 565f376 | 2008-12-17 11:43:26 -0800 | [diff] [blame] | 74 | if (res->flags & IORESOURCE_PREFETCH) |
| 75 | flags |= 0x10000000; /* enable relaxed ordering */ |
| 76 | |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 77 | for (i = 0; size > 0; i++) { |
| 78 | unsigned int bits = min(__ilog2(size), |
| 79 | __ffs(pci_addr | phys_addr)); |
| 80 | |
| 81 | if (index + i >= 5) |
| 82 | return -1; |
| 83 | |
| 84 | out_be32(&pci->pow[index + i].potar, pci_addr >> 12); |
| 85 | out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); |
| 86 | out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); |
| 87 | out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); |
| 88 | |
| 89 | pci_addr += (resource_size_t)1U << bits; |
| 90 | phys_addr += (resource_size_t)1U << bits; |
| 91 | size -= (resource_size_t)1U << bits; |
| 92 | } |
| 93 | |
| 94 | return i; |
| 95 | } |
| 96 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 97 | /* atmu setup for fsl pci/pcie controller */ |
Anton Vorontsov | c9dadff | 2008-12-29 19:40:32 +0300 | [diff] [blame] | 98 | static void __init setup_pci_atmu(struct pci_controller *hose, |
| 99 | struct resource *rsrc) |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 100 | { |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 101 | struct ccsr_pci __iomem *pci; |
Prabhakar Kushwaha | f4154e1 | 2011-02-24 15:05:04 +0530 | [diff] [blame] | 102 | int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; |
Kumar Gala | 54c1819 | 2009-05-08 15:05:23 -0500 | [diff] [blame] | 103 | u64 mem, sz, paddr_hi = 0; |
| 104 | u64 paddr_lo = ULLONG_MAX; |
| 105 | u32 pcicsrbar = 0, pcicsrbar_sz; |
| 106 | u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | |
| 107 | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; |
| 108 | char *name = hose->dn->full_name; |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 109 | |
Kumar Gala | 72b122c | 2008-01-14 17:02:19 -0600 | [diff] [blame] | 110 | pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", |
| 111 | (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); |
Prabhakar Kushwaha | f4154e1 | 2011-02-24 15:05:04 +0530 | [diff] [blame] | 112 | |
| 113 | if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) { |
| 114 | win_idx = 2; |
| 115 | start_idx = 0; |
| 116 | end_idx = 3; |
| 117 | } |
| 118 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 119 | pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 120 | if (!pci) { |
| 121 | dev_err(hose->parent, "Unable to map ATMU registers\n"); |
| 122 | return; |
| 123 | } |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 124 | |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 125 | /* Disable all windows (except powar0 since it's ignored) */ |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 126 | for(i = 1; i < 5; i++) |
| 127 | out_be32(&pci->pow[i].powar, 0); |
Prabhakar Kushwaha | f4154e1 | 2011-02-24 15:05:04 +0530 | [diff] [blame] | 128 | for (i = start_idx; i < end_idx; i++) |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 129 | out_be32(&pci->piw[i].piwar, 0); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 130 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 131 | /* Setup outbound MEM window */ |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 132 | for(i = 0, j = 1; i < 3; i++) { |
| 133 | if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) |
| 134 | continue; |
| 135 | |
Kumar Gala | 54c1819 | 2009-05-08 15:05:23 -0500 | [diff] [blame] | 136 | paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); |
| 137 | paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); |
| 138 | |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 139 | n = setup_one_atmu(pci, j, &hose->mem_resources[i], |
| 140 | hose->pci_mem_offset); |
| 141 | |
| 142 | if (n < 0 || j >= 5) { |
| 143 | pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); |
| 144 | hose->mem_resources[i].flags |= IORESOURCE_DISABLED; |
| 145 | } else |
| 146 | j += n; |
| 147 | } |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 148 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 149 | /* Setup outbound IO window */ |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 150 | if (hose->io_resource.flags & IORESOURCE_IO) { |
| 151 | if (j >= 5) { |
| 152 | pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); |
| 153 | } else { |
| 154 | pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " |
| 155 | "phy base 0x%016llx.\n", |
| 156 | (u64)hose->io_resource.start, |
| 157 | (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1, |
| 158 | (u64)hose->io_base_phys); |
| 159 | out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); |
| 160 | out_be32(&pci->pow[j].potear, 0); |
| 161 | out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); |
| 162 | /* Enable, IO R/W */ |
| 163 | out_be32(&pci->pow[j].powar, 0x80088000 |
| 164 | | (__ilog2(hose->io_resource.end |
| 165 | - hose->io_resource.start + 1) - 1)); |
| 166 | } |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 167 | } |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 168 | |
Kumar Gala | 54c1819 | 2009-05-08 15:05:23 -0500 | [diff] [blame] | 169 | /* convert to pci address space */ |
| 170 | paddr_hi -= hose->pci_mem_offset; |
| 171 | paddr_lo -= hose->pci_mem_offset; |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 172 | |
Kumar Gala | 54c1819 | 2009-05-08 15:05:23 -0500 | [diff] [blame] | 173 | if (paddr_hi == paddr_lo) { |
| 174 | pr_err("%s: No outbound window space\n", name); |
| 175 | return ; |
| 176 | } |
| 177 | |
| 178 | if (paddr_lo == 0) { |
| 179 | pr_err("%s: No space for inbound window\n", name); |
| 180 | return ; |
| 181 | } |
| 182 | |
| 183 | /* setup PCSRBAR/PEXCSRBAR */ |
| 184 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); |
| 185 | early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); |
| 186 | pcicsrbar_sz = ~pcicsrbar_sz + 1; |
| 187 | |
| 188 | if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || |
| 189 | (paddr_lo > 0x100000000ull)) |
| 190 | pcicsrbar = 0x100000000ull - pcicsrbar_sz; |
| 191 | else |
| 192 | pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; |
| 193 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); |
| 194 | |
| 195 | paddr_lo = min(paddr_lo, (u64)pcicsrbar); |
| 196 | |
| 197 | pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); |
| 198 | |
| 199 | /* Setup inbound mem window */ |
Yinghai Lu | 95f72d1 | 2010-07-12 14:36:09 +1000 | [diff] [blame] | 200 | mem = memblock_end_of_DRAM(); |
Kumar Gala | 54c1819 | 2009-05-08 15:05:23 -0500 | [diff] [blame] | 201 | sz = min(mem, paddr_lo); |
| 202 | mem_log = __ilog2_u64(sz); |
| 203 | |
| 204 | /* PCIe can overmap inbound & outbound since RX & TX are separated */ |
| 205 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
| 206 | /* Size window to exact size if power-of-two or one size up */ |
| 207 | if ((1ull << mem_log) != mem) { |
| 208 | if ((1ull << mem_log) > mem) |
| 209 | pr_info("%s: Setting PCI inbound window " |
| 210 | "greater than memory size\n", name); |
| 211 | mem_log++; |
| 212 | } |
| 213 | |
Prabhakar Kushwaha | f4154e1 | 2011-02-24 15:05:04 +0530 | [diff] [blame] | 214 | piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); |
Kumar Gala | 54c1819 | 2009-05-08 15:05:23 -0500 | [diff] [blame] | 215 | |
| 216 | /* Setup inbound memory window */ |
| 217 | out_be32(&pci->piw[win_idx].pitar, 0x00000000); |
| 218 | out_be32(&pci->piw[win_idx].piwbar, 0x00000000); |
| 219 | out_be32(&pci->piw[win_idx].piwar, piwar); |
| 220 | win_idx--; |
| 221 | |
| 222 | hose->dma_window_base_cur = 0x00000000; |
| 223 | hose->dma_window_size = (resource_size_t)sz; |
| 224 | } else { |
| 225 | u64 paddr = 0; |
| 226 | |
| 227 | /* Setup inbound memory window */ |
| 228 | out_be32(&pci->piw[win_idx].pitar, paddr >> 12); |
| 229 | out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); |
| 230 | out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); |
| 231 | win_idx--; |
| 232 | |
| 233 | paddr += 1ull << mem_log; |
| 234 | sz -= 1ull << mem_log; |
| 235 | |
| 236 | if (sz) { |
| 237 | mem_log = __ilog2_u64(sz); |
| 238 | piwar |= (mem_log - 1); |
| 239 | |
| 240 | out_be32(&pci->piw[win_idx].pitar, paddr >> 12); |
| 241 | out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); |
| 242 | out_be32(&pci->piw[win_idx].piwar, piwar); |
| 243 | win_idx--; |
| 244 | |
| 245 | paddr += 1ull << mem_log; |
| 246 | } |
| 247 | |
| 248 | hose->dma_window_base_cur = 0x00000000; |
| 249 | hose->dma_window_size = (resource_size_t)paddr; |
| 250 | } |
| 251 | |
| 252 | if (hose->dma_window_size < mem) { |
| 253 | #ifndef CONFIG_SWIOTLB |
| 254 | pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " |
| 255 | "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", |
| 256 | name); |
| 257 | #endif |
| 258 | /* adjusting outbound windows could reclaim space in mem map */ |
| 259 | if (paddr_hi < 0xffffffffull) |
| 260 | pr_warning("%s: WARNING: Outbound window cfg leaves " |
| 261 | "gaps in memory map. Adjusting the memory map " |
| 262 | "could reduce unnecessary bounce buffering.\n", |
| 263 | name); |
| 264 | |
| 265 | pr_info("%s: DMA window size is 0x%llx\n", name, |
| 266 | (u64)hose->dma_window_size); |
| 267 | } |
Becky Bruce | 89d9334 | 2009-04-20 11:26:48 -0500 | [diff] [blame] | 268 | |
Trent Piepho | a097a78 | 2009-01-06 22:37:53 -0600 | [diff] [blame] | 269 | iounmap(pci); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 270 | } |
| 271 | |
Anton Vorontsov | c9dadff | 2008-12-29 19:40:32 +0300 | [diff] [blame] | 272 | static void __init setup_pci_cmd(struct pci_controller *hose) |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 273 | { |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 274 | u16 cmd; |
Kumar Gala | eb12af4 | 2007-07-20 16:29:09 -0500 | [diff] [blame] | 275 | int cap_x; |
| 276 | |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 277 | early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); |
| 278 | cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 279 | | PCI_COMMAND_IO; |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 280 | early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); |
Kumar Gala | eb12af4 | 2007-07-20 16:29:09 -0500 | [diff] [blame] | 281 | |
| 282 | cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); |
| 283 | if (cap_x) { |
| 284 | int pci_x_cmd = cap_x + PCI_X_CMD; |
| 285 | cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
| 286 | | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; |
| 287 | early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); |
| 288 | } else { |
| 289 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); |
| 290 | } |
Kumar Gala | 9ad494f | 2006-06-28 00:37:45 -0500 | [diff] [blame] | 291 | } |
| 292 | |
Kumar Gala | 6c0a11c | 2007-07-19 15:29:53 -0500 | [diff] [blame] | 293 | void fsl_pcibios_fixup_bus(struct pci_bus *bus) |
| 294 | { |
Kumar Gala | 8206a11 | 2009-04-30 03:10:08 +0000 | [diff] [blame] | 295 | struct pci_controller *hose = pci_bus_to_host(bus); |
Kumar Gala | 6c0a11c | 2007-07-19 15:29:53 -0500 | [diff] [blame] | 296 | int i; |
| 297 | |
Kumar Gala | 72b122c | 2008-01-14 17:02:19 -0600 | [diff] [blame] | 298 | if ((bus->parent == hose->bus) && |
| 299 | ((fsl_pcie_bus_fixup && |
| 300 | early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) || |
| 301 | (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK))) |
| 302 | { |
| 303 | for (i = 0; i < 4; ++i) { |
| 304 | struct resource *res = bus->resource[i]; |
| 305 | struct resource *par = bus->parent->resource[i]; |
| 306 | if (res) { |
| 307 | res->start = 0; |
| 308 | res->end = 0; |
| 309 | res->flags = 0; |
| 310 | } |
| 311 | if (res && par) { |
| 312 | res->start = par->start; |
| 313 | res->end = par->end; |
| 314 | res->flags = par->flags; |
| 315 | } |
Kumar Gala | 6c0a11c | 2007-07-19 15:29:53 -0500 | [diff] [blame] | 316 | } |
| 317 | } |
| 318 | } |
| 319 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 320 | int __init fsl_add_bridge(struct device_node *dev, int is_primary) |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 321 | { |
| 322 | int len; |
| 323 | struct pci_controller *hose; |
| 324 | struct resource rsrc; |
Jeremy Kerr | 8efca49 | 2006-07-12 15:39:42 +1000 | [diff] [blame] | 325 | const int *bus_range; |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 326 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 327 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 328 | |
| 329 | /* Fetch host bridge registers address */ |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 330 | if (of_address_to_resource(dev, 0, &rsrc)) { |
| 331 | printk(KERN_WARNING "Can't get pci register base!"); |
| 332 | return -ENOMEM; |
| 333 | } |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 334 | |
| 335 | /* Get bus range if any */ |
Stephen Rothwell | e2eb639 | 2007-04-03 22:26:41 +1000 | [diff] [blame] | 336 | bus_range = of_get_property(dev, "bus-range", &len); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 337 | if (bus_range == NULL || len < 2 * sizeof(int)) |
| 338 | printk(KERN_WARNING "Can't get bus-range for %s, assume" |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 339 | " bus 0\n", dev->full_name); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 340 | |
Josh Boyer | 7fe519c | 2008-12-11 09:46:44 +0000 | [diff] [blame] | 341 | ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); |
Kumar Gala | dbf8471 | 2007-06-27 01:56:50 -0500 | [diff] [blame] | 342 | hose = pcibios_alloc_controller(dev); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 343 | if (!hose) |
| 344 | return -ENOMEM; |
Kumar Gala | dbf8471 | 2007-06-27 01:56:50 -0500 | [diff] [blame] | 345 | |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 346 | hose->first_busno = bus_range ? bus_range[0] : 0x0; |
Zhang Wei | bf7c036 | 2007-05-22 11:38:26 +0800 | [diff] [blame] | 347 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 348 | |
Kumar Gala | 2e56ff2 | 2007-07-19 16:07:35 -0500 | [diff] [blame] | 349 | setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, |
| 350 | PPC_INDIRECT_TYPE_BIG_ENDIAN); |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 351 | setup_pci_cmd(hose); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 352 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 353 | /* check PCI express link status */ |
Kumar Gala | 957ecff | 2007-07-11 13:31:58 -0500 | [diff] [blame] | 354 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
Kumar Gala | 7659c03 | 2007-07-25 00:29:53 -0500 | [diff] [blame] | 355 | hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | |
Kumar Gala | 957ecff | 2007-07-11 13:31:58 -0500 | [diff] [blame] | 356 | PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 357 | if (fsl_pcie_check_link(hose)) |
Kumar Gala | 957ecff | 2007-07-11 13:31:58 -0500 | [diff] [blame] | 358 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; |
| 359 | } |
Zhang Wei | e4725c2 | 2007-06-25 15:21:10 -0500 | [diff] [blame] | 360 | |
joe@perches.com | df3c901 | 2007-11-20 12:47:55 +1100 | [diff] [blame] | 361 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 362 | "Firmware bus number: %d->%d\n", |
| 363 | (unsigned long long)rsrc.start, hose->first_busno, |
| 364 | hose->last_busno); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 365 | |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 366 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 367 | hose, hose->cfg_addr, hose->cfg_data); |
| 368 | |
| 369 | /* Interpret the "ranges" property */ |
| 370 | /* This also maps the I/O region and sets isa_io/mem_base */ |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 371 | pci_process_bridge_OF_ranges(hose, dev, is_primary); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 372 | |
| 373 | /* Setup PEX window registers */ |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 374 | setup_pci_atmu(hose, &rsrc); |
Jon Loeliger | b809b3e | 2006-06-17 17:52:48 -0500 | [diff] [blame] | 375 | |
| 376 | return 0; |
| 377 | } |
Zang Roy-r61911 | 9ac4dd3 | 2007-07-10 18:46:35 +0800 | [diff] [blame] | 378 | |
Kumar Gala | 72b122c | 2008-01-14 17:02:19 -0600 | [diff] [blame] | 379 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header); |
| 380 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header); |
| 381 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header); |
| 382 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header); |
| 383 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header); |
| 384 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header); |
| 385 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header); |
Anton Vorontsov | bfa568d | 2009-05-02 06:16:47 +0400 | [diff] [blame] | 386 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header); |
| 387 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header); |
Kumar Gala | 72b122c | 2008-01-14 17:02:19 -0600 | [diff] [blame] | 388 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header); |
| 389 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header); |
| 390 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header); |
| 391 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header); |
| 392 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header); |
| 393 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header); |
| 394 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header); |
| 395 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header); |
| 396 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header); |
| 397 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header); |
Kumar Gala | 2f3804e | 2008-07-02 01:36:15 -0500 | [diff] [blame] | 398 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header); |
| 399 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header); |
Kumar Gala | 72b122c | 2008-01-14 17:02:19 -0600 | [diff] [blame] | 400 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); |
| 401 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); |
| 402 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); |
Kumar Gala | a3f62bd | 2009-10-18 13:55:55 -0500 | [diff] [blame] | 403 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header); |
| 404 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header); |
| 405 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header); |
| 406 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header); |
| 407 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header); |
| 408 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header); |
Anton Vorontsov | a28dec2 | 2010-08-08 18:03:33 +0400 | [diff] [blame] | 409 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header); |
| 410 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header); |
Kumar Gala | a3f62bd | 2009-10-18 13:55:55 -0500 | [diff] [blame] | 411 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header); |
| 412 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header); |
| 413 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header); |
| 414 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header); |
Kumar Gala | 01af950 | 2009-04-15 14:38:40 -0500 | [diff] [blame] | 415 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header); |
| 416 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header); |
Kumar Gala | 4f0e332 | 2010-09-24 13:34:42 -0500 | [diff] [blame] | 417 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040E, quirk_fsl_pcie_header); |
| 418 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040, quirk_fsl_pcie_header); |
| 419 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041E, quirk_fsl_pcie_header); |
| 420 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041, quirk_fsl_pcie_header); |
Kumar Gala | a3f62bd | 2009-10-18 13:55:55 -0500 | [diff] [blame] | 421 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header); |
| 422 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header); |
| 423 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header); |
| 424 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header); |
Kumar Gala | 4f0e332 | 2010-09-24 13:34:42 -0500 | [diff] [blame] | 425 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010E, quirk_fsl_pcie_header); |
| 426 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010, quirk_fsl_pcie_header); |
| 427 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020E, quirk_fsl_pcie_header); |
| 428 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020, quirk_fsl_pcie_header); |
Kumar Gala | 5753c08 | 2009-10-16 18:31:48 -0500 | [diff] [blame] | 429 | #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 430 | |
John Rigby | 3522580 | 2008-10-07 15:13:18 -0600 | [diff] [blame] | 431 | #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) |
Ilya Yanok | e3b5e0d | 2010-07-08 10:10:38 +0000 | [diff] [blame] | 432 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header); |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 433 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header); |
| 434 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header); |
| 435 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header); |
| 436 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header); |
| 437 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header); |
| 438 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header); |
| 439 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header); |
| 440 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header); |
| 441 | |
| 442 | struct mpc83xx_pcie_priv { |
| 443 | void __iomem *cfg_type0; |
| 444 | void __iomem *cfg_type1; |
| 445 | u32 dev_base; |
| 446 | }; |
| 447 | |
Kumar Gala | b8f44ec | 2010-08-05 02:45:08 -0500 | [diff] [blame] | 448 | struct pex_inbound_window { |
| 449 | u32 ar; |
| 450 | u32 tar; |
| 451 | u32 barl; |
| 452 | u32 barh; |
| 453 | }; |
| 454 | |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 455 | /* |
| 456 | * With the convention of u-boot, the PCIE outbound window 0 serves |
| 457 | * as configuration transactions outbound. |
| 458 | */ |
| 459 | #define PEX_OUTWIN0_BAR 0xCA4 |
| 460 | #define PEX_OUTWIN0_TAL 0xCA8 |
| 461 | #define PEX_OUTWIN0_TAH 0xCAC |
Kumar Gala | b8f44ec | 2010-08-05 02:45:08 -0500 | [diff] [blame] | 462 | #define PEX_RC_INWIN_BASE 0xE60 |
| 463 | #define PEX_RCIWARn_EN 0x1 |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 464 | |
| 465 | static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) |
| 466 | { |
Kumar Gala | 8206a11 | 2009-04-30 03:10:08 +0000 | [diff] [blame] | 467 | struct pci_controller *hose = pci_bus_to_host(bus); |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 468 | |
| 469 | if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) |
| 470 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 471 | /* |
| 472 | * Workaround for the HW bug: for Type 0 configure transactions the |
| 473 | * PCI-E controller does not check the device number bits and just |
| 474 | * assumes that the device number bits are 0. |
| 475 | */ |
| 476 | if (bus->number == hose->first_busno || |
| 477 | bus->primary == hose->first_busno) { |
| 478 | if (devfn & 0xf8) |
| 479 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 480 | } |
| 481 | |
| 482 | if (ppc_md.pci_exclude_device) { |
| 483 | if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) |
| 484 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 485 | } |
| 486 | |
| 487 | return PCIBIOS_SUCCESSFUL; |
| 488 | } |
| 489 | |
| 490 | static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, |
| 491 | unsigned int devfn, int offset) |
| 492 | { |
Kumar Gala | 8206a11 | 2009-04-30 03:10:08 +0000 | [diff] [blame] | 493 | struct pci_controller *hose = pci_bus_to_host(bus); |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 494 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; |
Anton Vorontsov | f93611f | 2009-12-08 01:54:35 +0300 | [diff] [blame] | 495 | u32 dev_base = bus->number << 24 | devfn << 16; |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 496 | int ret; |
| 497 | |
| 498 | ret = mpc83xx_pcie_exclude_device(bus, devfn); |
| 499 | if (ret) |
| 500 | return NULL; |
| 501 | |
| 502 | offset &= 0xfff; |
| 503 | |
| 504 | /* Type 0 */ |
| 505 | if (bus->number == hose->first_busno) |
| 506 | return pcie->cfg_type0 + offset; |
| 507 | |
| 508 | if (pcie->dev_base == dev_base) |
| 509 | goto mapped; |
| 510 | |
| 511 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); |
| 512 | |
| 513 | pcie->dev_base = dev_base; |
| 514 | mapped: |
| 515 | return pcie->cfg_type1 + offset; |
| 516 | } |
| 517 | |
| 518 | static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, |
| 519 | int offset, int len, u32 *val) |
| 520 | { |
| 521 | void __iomem *cfg_addr; |
| 522 | |
| 523 | cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); |
| 524 | if (!cfg_addr) |
| 525 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 526 | |
| 527 | switch (len) { |
| 528 | case 1: |
| 529 | *val = in_8(cfg_addr); |
| 530 | break; |
| 531 | case 2: |
| 532 | *val = in_le16(cfg_addr); |
| 533 | break; |
| 534 | default: |
| 535 | *val = in_le32(cfg_addr); |
| 536 | break; |
| 537 | } |
| 538 | |
| 539 | return PCIBIOS_SUCCESSFUL; |
| 540 | } |
| 541 | |
| 542 | static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, |
| 543 | int offset, int len, u32 val) |
| 544 | { |
Anton Vorontsov | f93611f | 2009-12-08 01:54:35 +0300 | [diff] [blame] | 545 | struct pci_controller *hose = pci_bus_to_host(bus); |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 546 | void __iomem *cfg_addr; |
| 547 | |
| 548 | cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); |
| 549 | if (!cfg_addr) |
| 550 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 551 | |
Anton Vorontsov | f93611f | 2009-12-08 01:54:35 +0300 | [diff] [blame] | 552 | /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ |
| 553 | if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) |
| 554 | val &= 0xffffff00; |
| 555 | |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 556 | switch (len) { |
| 557 | case 1: |
| 558 | out_8(cfg_addr, val); |
| 559 | break; |
| 560 | case 2: |
| 561 | out_le16(cfg_addr, val); |
| 562 | break; |
| 563 | default: |
| 564 | out_le32(cfg_addr, val); |
| 565 | break; |
| 566 | } |
| 567 | |
| 568 | return PCIBIOS_SUCCESSFUL; |
| 569 | } |
| 570 | |
| 571 | static struct pci_ops mpc83xx_pcie_ops = { |
| 572 | .read = mpc83xx_pcie_read_config, |
| 573 | .write = mpc83xx_pcie_write_config, |
| 574 | }; |
| 575 | |
| 576 | static int __init mpc83xx_pcie_setup(struct pci_controller *hose, |
| 577 | struct resource *reg) |
| 578 | { |
| 579 | struct mpc83xx_pcie_priv *pcie; |
| 580 | u32 cfg_bar; |
| 581 | int ret = -ENOMEM; |
| 582 | |
| 583 | pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); |
| 584 | if (!pcie) |
| 585 | return ret; |
| 586 | |
| 587 | pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); |
| 588 | if (!pcie->cfg_type0) |
| 589 | goto err0; |
| 590 | |
| 591 | cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); |
| 592 | if (!cfg_bar) { |
| 593 | /* PCI-E isn't configured. */ |
| 594 | ret = -ENODEV; |
| 595 | goto err1; |
| 596 | } |
| 597 | |
| 598 | pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); |
| 599 | if (!pcie->cfg_type1) |
| 600 | goto err1; |
| 601 | |
| 602 | WARN_ON(hose->dn->data); |
| 603 | hose->dn->data = pcie; |
| 604 | hose->ops = &mpc83xx_pcie_ops; |
| 605 | |
| 606 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); |
| 607 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); |
| 608 | |
| 609 | if (fsl_pcie_check_link(hose)) |
| 610 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; |
| 611 | |
| 612 | return 0; |
| 613 | err1: |
| 614 | iounmap(pcie->cfg_type0); |
| 615 | err0: |
| 616 | kfree(pcie); |
| 617 | return ret; |
| 618 | |
| 619 | } |
| 620 | |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 621 | int __init mpc83xx_add_bridge(struct device_node *dev) |
| 622 | { |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 623 | int ret; |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 624 | int len; |
| 625 | struct pci_controller *hose; |
John Rigby | 5b70a09 | 2008-10-07 13:00:18 -0600 | [diff] [blame] | 626 | struct resource rsrc_reg; |
| 627 | struct resource rsrc_cfg; |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 628 | const int *bus_range; |
John Rigby | 5b70a09 | 2008-10-07 13:00:18 -0600 | [diff] [blame] | 629 | int primary; |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 630 | |
Kumar Gala | b8f44ec | 2010-08-05 02:45:08 -0500 | [diff] [blame] | 631 | is_mpc83xx_pci = 1; |
| 632 | |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 633 | if (!of_device_is_available(dev)) { |
| 634 | pr_warning("%s: disabled by the firmware.\n", |
| 635 | dev->full_name); |
| 636 | return -ENODEV; |
| 637 | } |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 638 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
| 639 | |
| 640 | /* Fetch host bridge registers address */ |
John Rigby | 5b70a09 | 2008-10-07 13:00:18 -0600 | [diff] [blame] | 641 | if (of_address_to_resource(dev, 0, &rsrc_reg)) { |
| 642 | printk(KERN_WARNING "Can't get pci register base!\n"); |
| 643 | return -ENOMEM; |
| 644 | } |
| 645 | |
| 646 | memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); |
| 647 | |
| 648 | if (of_address_to_resource(dev, 1, &rsrc_cfg)) { |
| 649 | printk(KERN_WARNING |
| 650 | "No pci config register base in dev tree, " |
| 651 | "using default\n"); |
| 652 | /* |
| 653 | * MPC83xx supports up to two host controllers |
| 654 | * one at 0x8500 has config space registers at 0x8300 |
| 655 | * one at 0x8600 has config space registers at 0x8380 |
| 656 | */ |
| 657 | if ((rsrc_reg.start & 0xfffff) == 0x8500) |
| 658 | rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; |
| 659 | else if ((rsrc_reg.start & 0xfffff) == 0x8600) |
| 660 | rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; |
| 661 | } |
| 662 | /* |
| 663 | * Controller at offset 0x8500 is primary |
| 664 | */ |
| 665 | if ((rsrc_reg.start & 0xfffff) == 0x8500) |
| 666 | primary = 1; |
| 667 | else |
| 668 | primary = 0; |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 669 | |
| 670 | /* Get bus range if any */ |
| 671 | bus_range = of_get_property(dev, "bus-range", &len); |
| 672 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
| 673 | printk(KERN_WARNING "Can't get bus-range for %s, assume" |
| 674 | " bus 0\n", dev->full_name); |
| 675 | } |
| 676 | |
Josh Boyer | 7fe519c | 2008-12-11 09:46:44 +0000 | [diff] [blame] | 677 | ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 678 | hose = pcibios_alloc_controller(dev); |
| 679 | if (!hose) |
| 680 | return -ENOMEM; |
| 681 | |
| 682 | hose->first_busno = bus_range ? bus_range[0] : 0; |
| 683 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
| 684 | |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 685 | if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { |
| 686 | ret = mpc83xx_pcie_setup(hose, &rsrc_reg); |
| 687 | if (ret) |
| 688 | goto err0; |
| 689 | } else { |
| 690 | setup_indirect_pci(hose, rsrc_cfg.start, |
| 691 | rsrc_cfg.start + 4, 0); |
| 692 | } |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 693 | |
John Rigby | 3522580 | 2008-10-07 15:13:18 -0600 | [diff] [blame] | 694 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 695 | "Firmware bus number: %d->%d\n", |
John Rigby | 5b70a09 | 2008-10-07 13:00:18 -0600 | [diff] [blame] | 696 | (unsigned long long)rsrc_reg.start, hose->first_busno, |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 697 | hose->last_busno); |
| 698 | |
| 699 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
| 700 | hose, hose->cfg_addr, hose->cfg_data); |
| 701 | |
| 702 | /* Interpret the "ranges" property */ |
| 703 | /* This also maps the I/O region and sets isa_io/mem_base */ |
| 704 | pci_process_bridge_OF_ranges(hose, dev, primary); |
| 705 | |
| 706 | return 0; |
Anton Vorontsov | 598804c | 2009-01-09 00:55:39 +0300 | [diff] [blame] | 707 | err0: |
| 708 | pcibios_free_controller(hose); |
| 709 | return ret; |
John Rigby | 76fe1ff | 2008-06-26 11:07:57 -0600 | [diff] [blame] | 710 | } |
| 711 | #endif /* CONFIG_PPC_83xx */ |
Kumar Gala | b8f44ec | 2010-08-05 02:45:08 -0500 | [diff] [blame] | 712 | |
| 713 | u64 fsl_pci_immrbar_base(struct pci_controller *hose) |
| 714 | { |
| 715 | #ifdef CONFIG_PPC_83xx |
| 716 | if (is_mpc83xx_pci) { |
| 717 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; |
| 718 | struct pex_inbound_window *in; |
| 719 | int i; |
| 720 | |
| 721 | /* Walk the Root Complex Inbound windows to match IMMR base */ |
| 722 | in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; |
| 723 | for (i = 0; i < 4; i++) { |
| 724 | /* not enabled, skip */ |
| 725 | if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN) |
| 726 | continue; |
| 727 | |
| 728 | if (get_immrbase() == in_le32(&in[i].tar)) |
| 729 | return (u64)in_le32(&in[i].barh) << 32 | |
| 730 | in_le32(&in[i].barl); |
| 731 | } |
| 732 | |
| 733 | printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); |
| 734 | } |
| 735 | #endif |
| 736 | |
| 737 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) |
| 738 | if (!is_mpc83xx_pci) { |
| 739 | u32 base; |
| 740 | |
| 741 | pci_bus_read_config_dword(hose->bus, |
| 742 | PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); |
| 743 | return base; |
| 744 | } |
| 745 | #endif |
| 746 | |
| 747 | return 0; |
| 748 | } |