H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_GART_H |
| 2 | #define _ASM_X86_GART_H |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 3 | |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 4 | #include <asm/e820.h> |
| 5 | |
Rafael J. Wysocki | 6703f6d | 2008-06-10 00:10:48 +0200 | [diff] [blame] | 6 | extern void set_up_gart_resume(u32, u32); |
FUJITA Tomonori | e93be88 | 2008-07-10 08:27:49 +0900 | [diff] [blame] | 7 | |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 8 | extern int fallback_aper_order; |
| 9 | extern int fallback_aper_force; |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 10 | extern int fix_aperture; |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 11 | |
Pavel Machek | aa134f1 | 2008-04-08 10:49:03 +0200 | [diff] [blame] | 12 | /* PTE bits. */ |
| 13 | #define GPTE_VALID 1 |
| 14 | #define GPTE_COHERENT 2 |
| 15 | |
| 16 | /* Aperture control register bits. */ |
| 17 | #define GARTEN (1<<0) |
| 18 | #define DISGARTCPU (1<<4) |
| 19 | #define DISGARTIO (1<<5) |
Borislav Petkov | 260133a | 2010-09-03 18:39:40 +0200 | [diff] [blame] | 20 | #define DISTLBWALKPRB (1<<6) |
Pavel Machek | aa134f1 | 2008-04-08 10:49:03 +0200 | [diff] [blame] | 21 | |
| 22 | /* GART cache control register bits. */ |
| 23 | #define INVGART (1<<0) |
| 24 | #define GARTPTEERR (1<<1) |
| 25 | |
| 26 | /* K8 On-cpu GART registers */ |
| 27 | #define AMD64_GARTAPERTURECTL 0x90 |
| 28 | #define AMD64_GARTAPERTUREBASE 0x94 |
| 29 | #define AMD64_GARTTABLEBASE 0x98 |
| 30 | #define AMD64_GARTCACHECTL 0x9c |
Pavel Machek | aa134f1 | 2008-04-08 10:49:03 +0200 | [diff] [blame] | 31 | |
Joerg Roedel | 1d9b16d | 2008-11-27 18:39:15 +0100 | [diff] [blame] | 32 | #ifdef CONFIG_GART_IOMMU |
| 33 | extern int gart_iommu_aperture; |
| 34 | extern int gart_iommu_aperture_allowed; |
| 35 | extern int gart_iommu_aperture_disabled; |
| 36 | |
| 37 | extern void early_gart_iommu_check(void); |
FUJITA Tomonori | de95762 | 2009-11-10 19:46:14 +0900 | [diff] [blame] | 38 | extern int gart_iommu_init(void); |
Joerg Roedel | 1d9b16d | 2008-11-27 18:39:15 +0100 | [diff] [blame] | 39 | extern void __init gart_parse_options(char *); |
Konrad Rzeszutek Wilk | 480125b | 2010-08-26 13:57:57 -0400 | [diff] [blame] | 40 | extern int gart_iommu_hole_init(void); |
Joerg Roedel | 1d9b16d | 2008-11-27 18:39:15 +0100 | [diff] [blame] | 41 | |
| 42 | #else |
| 43 | #define gart_iommu_aperture 0 |
| 44 | #define gart_iommu_aperture_allowed 0 |
| 45 | #define gart_iommu_aperture_disabled 1 |
| 46 | |
| 47 | static inline void early_gart_iommu_check(void) |
| 48 | { |
| 49 | } |
Joerg Roedel | 1d9b16d | 2008-11-27 18:39:15 +0100 | [diff] [blame] | 50 | static inline void gart_parse_options(char *options) |
| 51 | { |
| 52 | } |
Konrad Rzeszutek Wilk | 480125b | 2010-08-26 13:57:57 -0400 | [diff] [blame] | 53 | static inline int gart_iommu_hole_init(void) |
Joerg Roedel | 1d9b16d | 2008-11-27 18:39:15 +0100 | [diff] [blame] | 54 | { |
Konrad Rzeszutek Wilk | 480125b | 2010-08-26 13:57:57 -0400 | [diff] [blame] | 55 | return -ENODEV; |
Joerg Roedel | 1d9b16d | 2008-11-27 18:39:15 +0100 | [diff] [blame] | 56 | } |
| 57 | #endif |
| 58 | |
Joerg Roedel | 237a622 | 2008-09-25 12:13:53 +0200 | [diff] [blame] | 59 | extern int agp_amd64_init(void); |
| 60 | |
Borislav Petkov | 260133a | 2010-09-03 18:39:40 +0200 | [diff] [blame] | 61 | static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order) |
| 62 | { |
| 63 | u32 ctl; |
| 64 | |
| 65 | /* |
| 66 | * Don't enable translation but enable GART IO and CPU accesses. |
| 67 | * Also, set DISTLBWALKPRB since GART tables memory is UC. |
| 68 | */ |
| 69 | ctl = DISTLBWALKPRB | order << 1; |
| 70 | |
| 71 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
| 72 | } |
| 73 | |
Pavel Machek | 3bb6fbf | 2008-04-15 12:43:57 +0200 | [diff] [blame] | 74 | static inline void enable_gart_translation(struct pci_dev *dev, u64 addr) |
| 75 | { |
| 76 | u32 tmp, ctl; |
| 77 | |
| 78 | /* address of the mappings table */ |
| 79 | addr >>= 12; |
| 80 | tmp = (u32) addr<<4; |
| 81 | tmp &= ~0xf; |
| 82 | pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp); |
| 83 | |
| 84 | /* Enable GART translation for this hammer. */ |
| 85 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
| 86 | ctl |= GARTEN; |
| 87 | ctl &= ~(DISGARTCPU | DISGARTIO); |
| 88 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
| 89 | } |
| 90 | |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 91 | static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size) |
| 92 | { |
| 93 | if (!aper_base) |
| 94 | return 0; |
| 95 | |
| 96 | if (aper_base + aper_size > 0x100000000ULL) { |
Adam Jackson | 9b15684 | 2008-09-29 14:52:03 -0400 | [diff] [blame] | 97 | printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n"); |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 98 | return 0; |
| 99 | } |
| 100 | if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) { |
Adam Jackson | 9b15684 | 2008-09-29 14:52:03 -0400 | [diff] [blame] | 101 | printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n"); |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 102 | return 0; |
| 103 | } |
| 104 | if (aper_size < min_size) { |
Adam Jackson | 9b15684 | 2008-09-29 14:52:03 -0400 | [diff] [blame] | 105 | printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n", |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 106 | aper_size>>20, min_size>>20); |
| 107 | return 0; |
| 108 | } |
| 109 | |
| 110 | return 1; |
| 111 | } |
| 112 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 113 | #endif /* _ASM_X86_GART_H */ |