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Linus Walleij8d318a52010-03-30 15:33:42 +02001/*
Jonas Aaberg767a9672010-08-09 12:08:34 +00002 * Copyright (C) ST-Ericsson SA 2007-2010
3 * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
Linus Walleij8d318a52010-03-30 15:33:42 +02005 * License terms: GNU General Public License (GPL) version 2
Linus Walleij8d318a52010-03-30 15:33:42 +02006 */
7#ifndef STE_DMA40_LL_H
8#define STE_DMA40_LL_H
9
10#define D40_DREG_PCBASE 0x400
11#define D40_DREG_PCDELTA (8 * 4)
12#define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */
13
Linus Walleijef1872e2010-06-20 21:24:52 +000014#define D40_LCPA_CHAN_SIZE 32
15#define D40_LCPA_CHAN_DST_DELTA 16
16
Linus Walleij8d318a52010-03-30 15:33:42 +020017#define D40_TYPE_TO_GROUP(type) (type / 16)
18#define D40_TYPE_TO_EVENT(type) (type % 16)
Narayanan G7fb3e752011-11-17 17:26:41 +053019#define D40_GROUP_SIZE 8
20#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
Linus Walleij8d318a52010-03-30 15:33:42 +020021
22/* Most bits of the CFG register are the same in log as in phy mode */
23#define D40_SREG_CFG_MST_POS 15
24#define D40_SREG_CFG_TIM_POS 14
25#define D40_SREG_CFG_EIM_POS 13
26#define D40_SREG_CFG_LOG_INCR_POS 12
27#define D40_SREG_CFG_PHY_PEN_POS 12
28#define D40_SREG_CFG_PSIZE_POS 10
29#define D40_SREG_CFG_ESIZE_POS 8
30#define D40_SREG_CFG_PRI_POS 7
31#define D40_SREG_CFG_LBE_POS 6
32#define D40_SREG_CFG_LOG_GIM_POS 5
33#define D40_SREG_CFG_LOG_MFU_POS 4
34#define D40_SREG_CFG_PHY_TM_POS 4
35#define D40_SREG_CFG_PHY_EVTL_POS 0
36
37
38/* Standard channel parameters - basic mode (element register) */
39#define D40_SREG_ELEM_PHY_ECNT_POS 16
40#define D40_SREG_ELEM_PHY_EIDX_POS 0
41
42#define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
43
44/* Standard channel parameters - basic mode (Link register) */
45#define D40_SREG_LNK_PHY_TCP_POS 0
46#define D40_SREG_LNK_PHY_LMP_POS 1
47#define D40_SREG_LNK_PHY_PRE_POS 2
48/*
49 * Source destination link address. Contains the
50 * 29-bit byte word aligned address of the reload area.
51 */
52#define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
53
54/* Standard basic channel logical mode */
55
56/* Element register */
57#define D40_SREG_ELEM_LOG_ECNT_POS 16
58#define D40_SREG_ELEM_LOG_LIDX_POS 8
59#define D40_SREG_ELEM_LOG_LOS_POS 1
60#define D40_SREG_ELEM_LOG_TCP_POS 0
61
62#define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
63
64/* Link register */
65#define D40_DEACTIVATE_EVENTLINE 0x0
66#define D40_ACTIVATE_EVENTLINE 0x1
67#define D40_EVENTLINE_POS(i) (2 * i)
68#define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
69
70/* Standard basic channel logical params in memory */
71
72/* LCSP0 */
73#define D40_MEM_LCSP0_ECNT_POS 16
74#define D40_MEM_LCSP0_SPTR_POS 0
75
76#define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
77#define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
78
79/* LCSP1 */
80#define D40_MEM_LCSP1_SPTR_POS 16
81#define D40_MEM_LCSP1_SCFG_MST_POS 15
82#define D40_MEM_LCSP1_SCFG_TIM_POS 14
83#define D40_MEM_LCSP1_SCFG_EIM_POS 13
84#define D40_MEM_LCSP1_SCFG_INCR_POS 12
85#define D40_MEM_LCSP1_SCFG_PSIZE_POS 10
86#define D40_MEM_LCSP1_SCFG_ESIZE_POS 8
87#define D40_MEM_LCSP1_SLOS_POS 1
88#define D40_MEM_LCSP1_STCP_POS 0
89
90#define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
91#define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
92#define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
93#define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
94#define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)
95#define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)
96
97/* LCSP2 */
98#define D40_MEM_LCSP2_ECNT_POS 16
99
100#define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
101
102/* LCSP3 */
103#define D40_MEM_LCSP3_DCFG_MST_POS 15
104#define D40_MEM_LCSP3_DCFG_TIM_POS 14
105#define D40_MEM_LCSP3_DCFG_EIM_POS 13
106#define D40_MEM_LCSP3_DCFG_INCR_POS 12
107#define D40_MEM_LCSP3_DCFG_PSIZE_POS 10
108#define D40_MEM_LCSP3_DCFG_ESIZE_POS 8
109#define D40_MEM_LCSP3_DLOS_POS 1
110#define D40_MEM_LCSP3_DTCP_POS 0
111
112#define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)
113#define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)
114
115
116/* Standard channel parameter register offsets */
117#define D40_CHAN_REG_SSCFG 0x00
118#define D40_CHAN_REG_SSELT 0x04
119#define D40_CHAN_REG_SSPTR 0x08
120#define D40_CHAN_REG_SSLNK 0x0C
121#define D40_CHAN_REG_SDCFG 0x10
122#define D40_CHAN_REG_SDELT 0x14
123#define D40_CHAN_REG_SDPTR 0x18
124#define D40_CHAN_REG_SDLNK 0x1C
125
126/* DMA Register Offsets */
127#define D40_DREG_GCC 0x000
Narayanan G7fb3e752011-11-17 17:26:41 +0530128#define D40_DREG_GCC_ENA 0x1
129/* This assumes that there are only 4 event groups */
130#define D40_DREG_GCC_ENABLE_ALL 0xff01
131#define D40_DREG_GCC_EVTGRP_POS 8
132#define D40_DREG_GCC_SRC 0
133#define D40_DREG_GCC_DST 1
134#define D40_DREG_GCC_EVTGRP_ENA(x, y) \
135 (1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))
136
Linus Walleij8d318a52010-03-30 15:33:42 +0200137#define D40_DREG_PRTYP 0x004
138#define D40_DREG_PRSME 0x008
139#define D40_DREG_PRSMO 0x00C
140#define D40_DREG_PRMSE 0x010
141#define D40_DREG_PRMSO 0x014
142#define D40_DREG_PRMOE 0x018
143#define D40_DREG_PRMOO 0x01C
Rabin Vincent20a5b6d2010-10-12 13:00:52 +0000144#define D40_DREG_PRMO_PCHAN_BASIC 0x1
145#define D40_DREG_PRMO_PCHAN_MODULO 0x2
146#define D40_DREG_PRMO_PCHAN_DOUBLE_DST 0x3
147#define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG 0x1
148#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY 0x2
149#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG 0x3
150
Linus Walleij8d318a52010-03-30 15:33:42 +0200151#define D40_DREG_LCPA 0x020
152#define D40_DREG_LCLA 0x024
153#define D40_DREG_ACTIVE 0x050
154#define D40_DREG_ACTIVO 0x054
155#define D40_DREG_FSEB1 0x058
156#define D40_DREG_FSEB2 0x05C
157#define D40_DREG_PCMIS 0x060
158#define D40_DREG_PCICR 0x064
159#define D40_DREG_PCTIS 0x068
160#define D40_DREG_PCEIS 0x06C
161#define D40_DREG_LCMIS0 0x080
162#define D40_DREG_LCMIS1 0x084
163#define D40_DREG_LCMIS2 0x088
164#define D40_DREG_LCMIS3 0x08C
165#define D40_DREG_LCICR0 0x090
166#define D40_DREG_LCICR1 0x094
167#define D40_DREG_LCICR2 0x098
168#define D40_DREG_LCICR3 0x09C
169#define D40_DREG_LCTIS0 0x0A0
170#define D40_DREG_LCTIS1 0x0A4
171#define D40_DREG_LCTIS2 0x0A8
172#define D40_DREG_LCTIS3 0x0AC
173#define D40_DREG_LCEIS0 0x0B0
174#define D40_DREG_LCEIS1 0x0B4
175#define D40_DREG_LCEIS2 0x0B8
176#define D40_DREG_LCEIS3 0x0BC
Rabin Vincentac2c0a32011-01-25 11:18:11 +0100177#define D40_DREG_PSEG1 0x110
178#define D40_DREG_PSEG2 0x114
179#define D40_DREG_PSEG3 0x118
180#define D40_DREG_PSEG4 0x11C
181#define D40_DREG_PCEG1 0x120
182#define D40_DREG_PCEG2 0x124
183#define D40_DREG_PCEG3 0x128
184#define D40_DREG_PCEG4 0x12C
185#define D40_DREG_RSEG1 0x130
186#define D40_DREG_RSEG2 0x134
187#define D40_DREG_RSEG3 0x138
188#define D40_DREG_RSEG4 0x13C
189#define D40_DREG_RCEG1 0x140
190#define D40_DREG_RCEG2 0x144
191#define D40_DREG_RCEG3 0x148
192#define D40_DREG_RCEG4 0x14C
Linus Walleij8d318a52010-03-30 15:33:42 +0200193#define D40_DREG_STFU 0xFC8
194#define D40_DREG_ICFG 0xFCC
195#define D40_DREG_PERIPHID0 0xFE0
196#define D40_DREG_PERIPHID1 0xFE4
197#define D40_DREG_PERIPHID2 0xFE8
198#define D40_DREG_PERIPHID3 0xFEC
199#define D40_DREG_CELLID0 0xFF0
200#define D40_DREG_CELLID1 0xFF4
201#define D40_DREG_CELLID2 0xFF8
202#define D40_DREG_CELLID3 0xFFC
203
204/* LLI related structures */
205
206/**
207 * struct d40_phy_lli - The basic configration register for each physical
208 * channel.
209 *
210 * @reg_cfg: The configuration register.
211 * @reg_elt: The element register.
212 * @reg_ptr: The pointer register.
213 * @reg_lnk: The link register.
214 *
215 * These registers are set up for both physical and logical transfers
216 * Note that the bit in each register means differently in logical and
217 * physical(standard) mode.
218 *
219 * This struct must be 16 bytes aligned, and only contain physical registers
220 * since it will be directly accessed by the DMA.
221 */
222struct d40_phy_lli {
223 u32 reg_cfg;
224 u32 reg_elt;
225 u32 reg_ptr;
226 u32 reg_lnk;
227};
228
229/**
230 * struct d40_phy_lli_bidir - struct for a transfer.
231 *
232 * @src: Register settings for src channel.
233 * @dst: Register settings for dst channel.
Linus Walleij8d318a52010-03-30 15:33:42 +0200234 *
235 * All DMA transfers have a source and a destination.
236 */
237
238struct d40_phy_lli_bidir {
239 struct d40_phy_lli *src;
240 struct d40_phy_lli *dst;
Linus Walleij8d318a52010-03-30 15:33:42 +0200241};
242
243
244/**
245 * struct d40_log_lli - logical lli configuration
246 *
247 * @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
248 * @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
249 *
250 * This struct must be 8 bytes aligned since it will be accessed directy by
251 * the DMA. Never add any none hw mapped registers to this struct.
252 */
253
254struct d40_log_lli {
255 u32 lcsp02;
256 u32 lcsp13;
257};
258
259/**
260 * struct d40_log_lli_bidir - For both src and dst
261 *
262 * @src: pointer to src lli configuration.
263 * @dst: pointer to dst lli configuration.
264 *
265 * You always have a src and a dst when doing DMA transfers.
266 */
267
268struct d40_log_lli_bidir {
269 struct d40_log_lli *src;
270 struct d40_log_lli *dst;
271};
272
273/**
274 * struct d40_log_lli_full - LCPA layout
275 *
276 * @lcsp0: Logical Channel Standard Param 0 - Src.
277 * @lcsp1: Logical Channel Standard Param 1 - Src.
278 * @lcsp2: Logical Channel Standard Param 2 - Dst.
279 * @lcsp3: Logical Channel Standard Param 3 - Dst.
280 *
281 * This struct maps to LCPA physical memory layout. Must map to
282 * the hw.
283 */
284struct d40_log_lli_full {
285 u32 lcsp0;
286 u32 lcsp1;
287 u32 lcsp2;
288 u32 lcsp3;
289};
290
291/**
292 * struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
293 *
294 * @lcsp3: The default configuration for dst.
295 * @lcsp1: The default configuration for src.
296 */
297struct d40_def_lcsp {
298 u32 lcsp3;
299 u32 lcsp1;
300};
301
Linus Walleij8d318a52010-03-30 15:33:42 +0200302/* Physical channels */
303
Rabin Vincent7f933be2011-01-25 11:18:30 +0100304enum d40_lli_flags {
305 LLI_ADDR_INC = 1 << 0,
306 LLI_TERM_INT = 1 << 1,
Rabin Vincent0c842b52011-01-25 11:18:35 +0100307 LLI_CYCLIC = 1 << 2,
308 LLI_LAST_LINK = 1 << 3,
Rabin Vincent7f933be2011-01-25 11:18:30 +0100309};
310
Linus Walleij8d318a52010-03-30 15:33:42 +0200311void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
Jonas Aaberg767a9672010-08-09 12:08:34 +0000312 u32 *src_cfg,
313 u32 *dst_cfg,
314 bool is_log);
Linus Walleij8d318a52010-03-30 15:33:42 +0200315
316void d40_log_cfg(struct stedma40_chan_cfg *cfg,
Jonas Aaberg767a9672010-08-09 12:08:34 +0000317 u32 *lcsp1,
318 u32 *lcsp2);
Linus Walleij8d318a52010-03-30 15:33:42 +0200319
320int d40_phy_sg_to_lli(struct scatterlist *sg,
321 int sg_len,
322 dma_addr_t target,
323 struct d40_phy_lli *lli,
324 dma_addr_t lli_phys,
325 u32 reg_cfg,
Rabin Vincentcc31b6f2011-01-25 11:18:27 +0100326 struct stedma40_half_channel_info *info,
Rabin Vincent0c842b52011-01-25 11:18:35 +0100327 struct stedma40_half_channel_info *otherinfo,
328 unsigned long flags);
Linus Walleij8d318a52010-03-30 15:33:42 +0200329
Linus Walleij8d318a52010-03-30 15:33:42 +0200330/* Logical channels */
331
Jonas Aaberg698e4732010-08-09 12:08:56 +0000332int d40_log_sg_to_lli(struct scatterlist *sg,
Linus Walleij8d318a52010-03-30 15:33:42 +0200333 int sg_len,
Rabin Vincent5ed04b82011-01-25 11:18:26 +0100334 dma_addr_t dev_addr,
Linus Walleij8d318a52010-03-30 15:33:42 +0200335 struct d40_log_lli *lli_sg,
336 u32 lcsp13, /* src or dst*/
Per Forlind49278e2010-12-20 18:31:38 +0100337 u32 data_width1, u32 data_width2);
Jonas Aaberg698e4732010-08-09 12:08:56 +0000338
339void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
340 struct d40_log_lli *lli_dst,
341 struct d40_log_lli *lli_src,
Rabin Vincent0c842b52011-01-25 11:18:35 +0100342 int next, unsigned int flags);
Jonas Aaberg698e4732010-08-09 12:08:56 +0000343
344void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
345 struct d40_log_lli *lli_dst,
346 struct d40_log_lli *lli_src,
Rabin Vincent0c842b52011-01-25 11:18:35 +0100347 int next, unsigned int flags);
Linus Walleij8d318a52010-03-30 15:33:42 +0200348
349#endif /* STE_DMA40_LLI_H */