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Soren Brinkmann0ee52b12013-05-13 10:46:37 -07001/*
2 * Zynq clock controller
3 *
4 * Copyright (C) 2012 - 2013 Xilinx
5 *
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License v2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/clk/zynq.h>
22#include <linux/clk-provider.h>
23#include <linux/of.h>
24#include <linux/slab.h>
25#include <linux/string.h>
26#include <linux/io.h>
27
28static void __iomem *zynq_slcr_base_priv;
29
30#define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100)
31#define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104)
32#define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108)
33#define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c)
34#define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120)
35#define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124)
36#define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128)
37#define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c)
38#define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140)
39#define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144)
40#define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148)
41#define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c)
42#define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150)
43#define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154)
44#define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158)
45#define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c)
46#define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160)
47#define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164)
48#define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168)
49#define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170)
50#define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4)
51#define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304)
52
53#define NUM_MIO_PINS 54
54
55enum zynq_clk {
56 armpll, ddrpll, iopll,
57 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
58 ddr2x, ddr3x, dci,
59 lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
60 sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
61 usb0_aper, usb1_aper, gem0_aper, gem1_aper,
62 sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
63 i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
64 smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
65
66static struct clk *ps_clk;
67static struct clk *clks[clk_max];
68static struct clk_onecell_data clk_data;
69
70static DEFINE_SPINLOCK(armpll_lock);
71static DEFINE_SPINLOCK(ddrpll_lock);
72static DEFINE_SPINLOCK(iopll_lock);
73static DEFINE_SPINLOCK(armclk_lock);
Soren Brinkmann252957c2013-06-17 15:03:46 -070074static DEFINE_SPINLOCK(swdtclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -070075static DEFINE_SPINLOCK(ddrclk_lock);
76static DEFINE_SPINLOCK(dciclk_lock);
77static DEFINE_SPINLOCK(gem0clk_lock);
78static DEFINE_SPINLOCK(gem1clk_lock);
79static DEFINE_SPINLOCK(canclk_lock);
80static DEFINE_SPINLOCK(canmioclk_lock);
81static DEFINE_SPINLOCK(dbgclk_lock);
82static DEFINE_SPINLOCK(aperclk_lock);
83
84static const char dummy_nm[] __initconst = "dummy_name";
85
86static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"};
87static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"};
88static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"};
89static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm};
90static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm};
91static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate",
92 "can0_mio_mux"};
93static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate",
94 "can1_mio_mux"};
95static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
96 dummy_nm};
97
98static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"};
99static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"};
100static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"};
101static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"};
102
103static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
104 const char *clk_name, void __iomem *fclk_ctrl_reg,
105 const char **parents)
106{
107 struct clk *clk;
108 char *mux_name;
109 char *div0_name;
110 char *div1_name;
111 spinlock_t *fclk_lock;
112 spinlock_t *fclk_gate_lock;
113 void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
114
115 fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
116 if (!fclk_lock)
117 goto err;
118 fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
119 if (!fclk_gate_lock)
120 goto err;
121 spin_lock_init(fclk_lock);
122 spin_lock_init(fclk_gate_lock);
123
124 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
125 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
126 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
127
James Hogan819c1de2013-07-29 12:25:01 +0100128 clk = clk_register_mux(NULL, mux_name, parents, 4,
129 CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
130 fclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700131
132 clk = clk_register_divider(NULL, div0_name, mux_name,
133 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
134 CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
135
136 clk = clk_register_divider(NULL, div1_name, div0_name,
137 CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
138 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
139 fclk_lock);
140
141 clks[fclk] = clk_register_gate(NULL, clk_name,
142 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
143 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
144 kfree(mux_name);
145 kfree(div0_name);
146 kfree(div1_name);
147
148 return;
149
150err:
151 clks[fclk] = ERR_PTR(-ENOMEM);
152}
153
154static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
155 enum zynq_clk clk1, const char *clk_name0,
156 const char *clk_name1, void __iomem *clk_ctrl,
157 const char **parents, unsigned int two_gates)
158{
159 struct clk *clk;
160 char *mux_name;
161 char *div_name;
162 spinlock_t *lock;
163
164 lock = kmalloc(sizeof(*lock), GFP_KERNEL);
165 if (!lock)
166 goto err;
167 spin_lock_init(lock);
168
169 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
170 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
171
James Hogan819c1de2013-07-29 12:25:01 +0100172 clk = clk_register_mux(NULL, mux_name, parents, 4,
173 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700174
175 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
176 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
177
178 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
179 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
180 if (two_gates)
181 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
182 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
183
184 kfree(mux_name);
185 kfree(div_name);
186
187 return;
188
189err:
190 clks[clk0] = ERR_PTR(-ENOMEM);
191 if (two_gates)
192 clks[clk1] = ERR_PTR(-ENOMEM);
193}
194
195static void __init zynq_clk_setup(struct device_node *np)
196{
197 int i;
198 u32 tmp;
199 int ret;
200 struct clk *clk;
201 char *clk_name;
202 const char *clk_output_name[clk_max];
203 const char *cpu_parents[4];
204 const char *periph_parents[4];
205 const char *swdt_ext_clk_mux_parents[2];
206 const char *can_mio_mux_parents[NUM_MIO_PINS];
207
208 pr_info("Zynq clock init\n");
209
210 /* get clock output names from DT */
211 for (i = 0; i < clk_max; i++) {
212 if (of_property_read_string_index(np, "clock-output-names",
213 i, &clk_output_name[i])) {
214 pr_err("%s: clock output name not in DT\n", __func__);
215 BUG();
216 }
217 }
218 cpu_parents[0] = clk_output_name[armpll];
219 cpu_parents[1] = clk_output_name[armpll];
220 cpu_parents[2] = clk_output_name[ddrpll];
221 cpu_parents[3] = clk_output_name[iopll];
222 periph_parents[0] = clk_output_name[iopll];
223 periph_parents[1] = clk_output_name[iopll];
224 periph_parents[2] = clk_output_name[armpll];
225 periph_parents[3] = clk_output_name[ddrpll];
226
227 /* ps_clk */
228 ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
229 if (ret) {
230 pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
231 tmp = 33333333;
232 }
233 ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
234 tmp);
235
236 /* PLLs */
237 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
238 SLCR_PLL_STATUS, 0, &armpll_lock);
239 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
James Hogan819c1de2013-07-29 12:25:01 +0100240 armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
241 SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700242
243 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
244 SLCR_PLL_STATUS, 1, &ddrpll_lock);
245 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
James Hogan819c1de2013-07-29 12:25:01 +0100246 ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
247 SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700248
249 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
250 SLCR_PLL_STATUS, 2, &iopll_lock);
251 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
James Hogan819c1de2013-07-29 12:25:01 +0100252 iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
253 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700254
255 /* CPU clocks */
256 tmp = readl(SLCR_621_TRUE) & 1;
James Hogan819c1de2013-07-29 12:25:01 +0100257 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
258 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
259 &armclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700260 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
261 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
262 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
263
264 clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
265 "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
266 SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
267
268 clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
269 1, 2);
270 clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
271 "cpu_3or2x_div", CLK_IGNORE_UNUSED,
272 SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
273
274 clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
275 2 + tmp);
276 clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
277 "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
278 26, 0, &armclk_lock);
279
280 clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
281 4 + 2 * tmp);
282 clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
283 "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
284 0, &armclk_lock);
285
286 /* Timers */
287 swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
288 for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
289 int idx = of_property_match_string(np, "clock-names",
290 swdt_ext_clk_input_names[i]);
291 if (idx >= 0)
292 swdt_ext_clk_mux_parents[i + 1] =
293 of_clk_get_parent_name(np, idx);
294 else
295 swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
296 }
297 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
James Hogan819c1de2013-07-29 12:25:01 +0100298 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
299 CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
Linus Torvaldsbef4a0a2013-09-09 15:49:04 -0700300 &swdtclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700301
302 /* DDR clocks */
303 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
304 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
305 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
306 clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
307 "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
308 clk_prepare_enable(clks[ddr2x]);
309 clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
310 SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
311 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
312 clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
313 "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
314 clk_prepare_enable(clks[ddr3x]);
315
316 clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
317 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
318 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
319 clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
320 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
321 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
322 &dciclk_lock);
323 clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
324 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
325 &dciclk_lock);
326 clk_prepare_enable(clks[dci]);
327
328 /* Peripheral clocks */
329 for (i = fclk0; i <= fclk3; i++)
330 zynq_clk_register_fclk(i, clk_output_name[i],
331 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
332 periph_parents);
333
334 zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
335 SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
336
337 zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
338 SLCR_SMC_CLK_CTRL, periph_parents, 0);
339
340 zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
341 SLCR_PCAP_CLK_CTRL, periph_parents, 0);
342
343 zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
344 clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
345 periph_parents, 1);
346
347 zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
348 clk_output_name[uart1], SLCR_UART_CLK_CTRL,
349 periph_parents, 1);
350
351 zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
352 clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
353 periph_parents, 1);
354
355 for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
356 int idx = of_property_match_string(np, "clock-names",
357 gem0_emio_input_names[i]);
358 if (idx >= 0)
359 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
360 idx);
361 }
James Hogan819c1de2013-07-29 12:25:01 +0100362 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
363 CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
364 &gem0clk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700365 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
366 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
367 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
368 clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
369 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
370 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
371 &gem0clk_lock);
Soren Brinkmann765b7d42013-06-17 15:47:40 -0700372 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
Linus Torvaldsbef4a0a2013-09-09 15:49:04 -0700373 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
374 SLCR_GEM0_CLK_CTRL, 6, 1, 0,
Soren Brinkmann765b7d42013-06-17 15:47:40 -0700375 &gem0clk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700376 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
377 "gem0_emio_mux", CLK_SET_RATE_PARENT,
378 SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
379
380 for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
381 int idx = of_property_match_string(np, "clock-names",
382 gem1_emio_input_names[i]);
383 if (idx >= 0)
384 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
385 idx);
386 }
James Hogan819c1de2013-07-29 12:25:01 +0100387 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
388 CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
389 &gem1clk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700390 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
391 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
392 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
393 clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
394 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
395 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
396 &gem1clk_lock);
Soren Brinkmann765b7d42013-06-17 15:47:40 -0700397 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
Linus Torvaldsbef4a0a2013-09-09 15:49:04 -0700398 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
399 SLCR_GEM1_CLK_CTRL, 6, 1, 0,
Soren Brinkmann765b7d42013-06-17 15:47:40 -0700400 &gem1clk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700401 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
402 "gem1_emio_mux", CLK_SET_RATE_PARENT,
403 SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
404
405 tmp = strlen("mio_clk_00x");
406 clk_name = kmalloc(tmp, GFP_KERNEL);
407 for (i = 0; i < NUM_MIO_PINS; i++) {
408 int idx;
409
410 snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
411 idx = of_property_match_string(np, "clock-names", clk_name);
412 if (idx >= 0)
413 can_mio_mux_parents[i] = of_clk_get_parent_name(np,
414 idx);
415 else
416 can_mio_mux_parents[i] = dummy_nm;
417 }
418 kfree(clk_name);
James Hogan819c1de2013-07-29 12:25:01 +0100419 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
420 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
421 &canclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700422 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
423 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
424 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
425 clk = clk_register_divider(NULL, "can_div1", "can_div0",
426 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
427 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
428 &canclk_lock);
429 clk = clk_register_gate(NULL, "can0_gate", "can_div1",
430 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
431 &canclk_lock);
432 clk = clk_register_gate(NULL, "can1_gate", "can_div1",
433 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
434 &canclk_lock);
435 clk = clk_register_mux(NULL, "can0_mio_mux",
James Hogan819c1de2013-07-29 12:25:01 +0100436 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
437 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
438 &canmioclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700439 clk = clk_register_mux(NULL, "can1_mio_mux",
James Hogan819c1de2013-07-29 12:25:01 +0100440 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
441 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
442 0, &canmioclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700443 clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
James Hogan819c1de2013-07-29 12:25:01 +0100444 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
445 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
446 &canmioclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700447 clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
James Hogan819c1de2013-07-29 12:25:01 +0100448 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
449 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
450 0, &canmioclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700451
452 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
453 int idx = of_property_match_string(np, "clock-names",
454 dbgtrc_emio_input_names[i]);
455 if (idx >= 0)
456 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
457 idx);
458 }
James Hogan819c1de2013-07-29 12:25:01 +0100459 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
460 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
461 &dbgclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700462 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
463 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
464 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
James Hogan819c1de2013-07-29 12:25:01 +0100465 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
466 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
467 &dbgclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700468 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
469 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
470 0, 0, &dbgclk_lock);
471 clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
472 clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
473 &dbgclk_lock);
474
475 /* One gated clock for all APER clocks. */
476 clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
477 clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
478 &aperclk_lock);
479 clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
480 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
481 &aperclk_lock);
482 clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
483 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
484 &aperclk_lock);
485 clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
486 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
487 &aperclk_lock);
488 clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
489 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
490 &aperclk_lock);
491 clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
492 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
493 &aperclk_lock);
494 clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
495 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
496 &aperclk_lock);
497 clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
498 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
499 &aperclk_lock);
500 clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
501 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
502 &aperclk_lock);
503 clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
504 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
505 &aperclk_lock);
506 clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
507 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
508 &aperclk_lock);
509 clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
510 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
511 &aperclk_lock);
512 clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
513 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
514 &aperclk_lock);
515 clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
516 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
517 &aperclk_lock);
518 clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
519 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
520 &aperclk_lock);
521 clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
522 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
523 &aperclk_lock);
524 clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
525 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
526 &aperclk_lock);
527 clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
528 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
529 &aperclk_lock);
530
531 for (i = 0; i < ARRAY_SIZE(clks); i++) {
532 if (IS_ERR(clks[i])) {
533 pr_err("Zynq clk %d: register failed with %ld\n",
534 i, PTR_ERR(clks[i]));
535 BUG();
536 }
537 }
538
539 clk_data.clks = clks;
540 clk_data.clk_num = ARRAY_SIZE(clks);
541 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
542}
543
544CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
545
546void __init zynq_clock_init(void __iomem *slcr_base)
547{
548 zynq_slcr_base_priv = slcr_base;
549 of_clk_init(NULL);
550}