Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | #include <linux/mm.h> |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/io.h> |
| 17 | |
| 18 | #include <asm/clkdev.h> |
Dinh Nguyen | 17807f9 | 2010-04-13 14:05:08 -0500 | [diff] [blame] | 19 | #include <asm/div64.h> |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 20 | |
| 21 | #include <mach/hardware.h> |
| 22 | #include <mach/common.h> |
| 23 | #include <mach/clock.h> |
| 24 | |
| 25 | #include "crm_regs.h" |
| 26 | |
| 27 | /* External clock values passed-in by the board code */ |
| 28 | static unsigned long external_high_reference, external_low_reference; |
| 29 | static unsigned long oscillator_reference, ckih2_reference; |
| 30 | |
| 31 | static struct clk osc_clk; |
| 32 | static struct clk pll1_main_clk; |
| 33 | static struct clk pll1_sw_clk; |
| 34 | static struct clk pll2_sw_clk; |
| 35 | static struct clk pll3_sw_clk; |
| 36 | static struct clk lp_apm_clk; |
| 37 | static struct clk periph_apm_clk; |
| 38 | static struct clk ahb_clk; |
| 39 | static struct clk ipg_clk; |
Dinh Nguyen | c79504e | 2010-05-10 13:45:58 -0500 | [diff] [blame] | 40 | static struct clk usboh3_clk; |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 41 | |
| 42 | #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ |
| 43 | |
Uwe Kleine-König | 7990147 | 2010-09-10 16:58:42 +0200 | [diff] [blame] | 44 | static void _clk_ccgr_setclk(struct clk *clk, unsigned mode) |
| 45 | { |
| 46 | u32 reg = __raw_readl(clk->enable_reg); |
| 47 | |
| 48 | reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); |
| 49 | reg |= mode << clk->enable_shift; |
| 50 | |
| 51 | __raw_writel(reg, clk->enable_reg); |
| 52 | } |
| 53 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 54 | static int _clk_ccgr_enable(struct clk *clk) |
| 55 | { |
Uwe Kleine-König | 7990147 | 2010-09-10 16:58:42 +0200 | [diff] [blame] | 56 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON); |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 57 | return 0; |
| 58 | } |
| 59 | |
| 60 | static void _clk_ccgr_disable(struct clk *clk) |
| 61 | { |
Uwe Kleine-König | 7990147 | 2010-09-10 16:58:42 +0200 | [diff] [blame] | 62 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF); |
| 63 | } |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 64 | |
Uwe Kleine-König | 7990147 | 2010-09-10 16:58:42 +0200 | [diff] [blame] | 65 | static int _clk_ccgr_enable_inrun(struct clk *clk) |
| 66 | { |
| 67 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); |
| 68 | return 0; |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 69 | } |
| 70 | |
| 71 | static void _clk_ccgr_disable_inwait(struct clk *clk) |
| 72 | { |
Uwe Kleine-König | 7990147 | 2010-09-10 16:58:42 +0200 | [diff] [blame] | 73 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | /* |
| 77 | * For the 4-to-1 muxed input clock |
| 78 | */ |
| 79 | static inline u32 _get_mux(struct clk *parent, struct clk *m0, |
| 80 | struct clk *m1, struct clk *m2, struct clk *m3) |
| 81 | { |
| 82 | if (parent == m0) |
| 83 | return 0; |
| 84 | else if (parent == m1) |
| 85 | return 1; |
| 86 | else if (parent == m2) |
| 87 | return 2; |
| 88 | else if (parent == m3) |
| 89 | return 3; |
| 90 | else |
| 91 | BUG(); |
| 92 | |
| 93 | return -EINVAL; |
| 94 | } |
| 95 | |
| 96 | static inline void __iomem *_get_pll_base(struct clk *pll) |
| 97 | { |
| 98 | if (pll == &pll1_main_clk) |
| 99 | return MX51_DPLL1_BASE; |
| 100 | else if (pll == &pll2_sw_clk) |
| 101 | return MX51_DPLL2_BASE; |
| 102 | else if (pll == &pll3_sw_clk) |
| 103 | return MX51_DPLL3_BASE; |
| 104 | else |
| 105 | BUG(); |
| 106 | |
| 107 | return NULL; |
| 108 | } |
| 109 | |
| 110 | static unsigned long clk_pll_get_rate(struct clk *clk) |
| 111 | { |
| 112 | long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; |
| 113 | unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; |
| 114 | void __iomem *pllbase; |
| 115 | s64 temp; |
| 116 | unsigned long parent_rate; |
| 117 | |
| 118 | parent_rate = clk_get_rate(clk->parent); |
| 119 | |
| 120 | pllbase = _get_pll_base(clk); |
| 121 | |
| 122 | dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
| 123 | pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; |
| 124 | dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; |
| 125 | |
| 126 | if (pll_hfsm == 0) { |
| 127 | dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); |
| 128 | dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); |
| 129 | dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); |
| 130 | } else { |
| 131 | dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); |
| 132 | dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); |
| 133 | dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); |
| 134 | } |
| 135 | pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; |
| 136 | mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; |
| 137 | mfi = (mfi <= 5) ? 5 : mfi; |
| 138 | mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; |
| 139 | mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; |
| 140 | /* Sign extend to 32-bits */ |
| 141 | if (mfn >= 0x04000000) { |
| 142 | mfn |= 0xFC000000; |
| 143 | mfn_abs = -mfn; |
| 144 | } |
| 145 | |
| 146 | ref_clk = 2 * parent_rate; |
| 147 | if (dbl != 0) |
| 148 | ref_clk *= 2; |
| 149 | |
| 150 | ref_clk /= (pdf + 1); |
| 151 | temp = (u64) ref_clk * mfn_abs; |
| 152 | do_div(temp, mfd + 1); |
| 153 | if (mfn < 0) |
| 154 | temp = -temp; |
| 155 | temp = (ref_clk * mfi) + temp; |
| 156 | |
| 157 | return temp; |
| 158 | } |
| 159 | |
| 160 | static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) |
| 161 | { |
| 162 | u32 reg; |
| 163 | void __iomem *pllbase; |
| 164 | |
| 165 | long mfi, pdf, mfn, mfd = 999999; |
| 166 | s64 temp64; |
| 167 | unsigned long quad_parent_rate; |
| 168 | unsigned long pll_hfsm, dp_ctl; |
| 169 | unsigned long parent_rate; |
| 170 | |
| 171 | parent_rate = clk_get_rate(clk->parent); |
| 172 | |
| 173 | pllbase = _get_pll_base(clk); |
| 174 | |
| 175 | quad_parent_rate = 4 * parent_rate; |
| 176 | pdf = mfi = -1; |
| 177 | while (++pdf < 16 && mfi < 5) |
| 178 | mfi = rate * (pdf+1) / quad_parent_rate; |
| 179 | if (mfi > 15) |
| 180 | return -EINVAL; |
| 181 | pdf--; |
| 182 | |
| 183 | temp64 = rate * (pdf+1) - quad_parent_rate * mfi; |
| 184 | do_div(temp64, quad_parent_rate/1000000); |
| 185 | mfn = (long)temp64; |
| 186 | |
| 187 | dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
| 188 | /* use dpdck0_2 */ |
| 189 | __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); |
| 190 | pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; |
| 191 | if (pll_hfsm == 0) { |
| 192 | reg = mfi << 4 | pdf; |
| 193 | __raw_writel(reg, pllbase + MXC_PLL_DP_OP); |
| 194 | __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); |
| 195 | __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); |
| 196 | } else { |
| 197 | reg = mfi << 4 | pdf; |
| 198 | __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); |
| 199 | __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); |
| 200 | __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); |
| 201 | } |
| 202 | |
| 203 | return 0; |
| 204 | } |
| 205 | |
| 206 | static int _clk_pll_enable(struct clk *clk) |
| 207 | { |
| 208 | u32 reg; |
| 209 | void __iomem *pllbase; |
| 210 | int i = 0; |
| 211 | |
| 212 | pllbase = _get_pll_base(clk); |
| 213 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; |
| 214 | __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); |
| 215 | |
| 216 | /* Wait for lock */ |
| 217 | do { |
| 218 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
| 219 | if (reg & MXC_PLL_DP_CTL_LRF) |
| 220 | break; |
| 221 | |
| 222 | udelay(1); |
| 223 | } while (++i < MAX_DPLL_WAIT_TRIES); |
| 224 | |
| 225 | if (i == MAX_DPLL_WAIT_TRIES) { |
| 226 | pr_err("MX5: pll locking failed\n"); |
| 227 | return -EINVAL; |
| 228 | } |
| 229 | |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | static void _clk_pll_disable(struct clk *clk) |
| 234 | { |
| 235 | u32 reg; |
| 236 | void __iomem *pllbase; |
| 237 | |
| 238 | pllbase = _get_pll_base(clk); |
| 239 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; |
| 240 | __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); |
| 241 | } |
| 242 | |
| 243 | static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) |
| 244 | { |
| 245 | u32 reg, step; |
| 246 | |
| 247 | reg = __raw_readl(MXC_CCM_CCSR); |
| 248 | |
| 249 | /* When switching from pll_main_clk to a bypass clock, first select a |
| 250 | * multiplexed clock in 'step_sel', then shift the glitchless mux |
| 251 | * 'pll1_sw_clk_sel'. |
| 252 | * |
| 253 | * When switching back, do it in reverse order |
| 254 | */ |
| 255 | if (parent == &pll1_main_clk) { |
| 256 | /* Switch to pll1_main_clk */ |
| 257 | reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; |
| 258 | __raw_writel(reg, MXC_CCM_CCSR); |
| 259 | /* step_clk mux switched to lp_apm, to save power. */ |
| 260 | reg = __raw_readl(MXC_CCM_CCSR); |
| 261 | reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; |
| 262 | reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM << |
| 263 | MXC_CCM_CCSR_STEP_SEL_OFFSET); |
| 264 | } else { |
| 265 | if (parent == &lp_apm_clk) { |
| 266 | step = MXC_CCM_CCSR_STEP_SEL_LP_APM; |
| 267 | } else if (parent == &pll2_sw_clk) { |
| 268 | step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED; |
| 269 | } else if (parent == &pll3_sw_clk) { |
| 270 | step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED; |
| 271 | } else |
| 272 | return -EINVAL; |
| 273 | |
| 274 | reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; |
| 275 | reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET); |
| 276 | |
| 277 | __raw_writel(reg, MXC_CCM_CCSR); |
| 278 | /* Switch to step_clk */ |
| 279 | reg = __raw_readl(MXC_CCM_CCSR); |
| 280 | reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; |
| 281 | } |
| 282 | __raw_writel(reg, MXC_CCM_CCSR); |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | static unsigned long clk_pll1_sw_get_rate(struct clk *clk) |
| 287 | { |
| 288 | u32 reg, div; |
| 289 | unsigned long parent_rate; |
| 290 | |
| 291 | parent_rate = clk_get_rate(clk->parent); |
| 292 | |
| 293 | reg = __raw_readl(MXC_CCM_CCSR); |
| 294 | |
| 295 | if (clk->parent == &pll2_sw_clk) { |
| 296 | div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> |
| 297 | MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; |
| 298 | } else if (clk->parent == &pll3_sw_clk) { |
| 299 | div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> |
| 300 | MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; |
| 301 | } else |
| 302 | div = 1; |
| 303 | return parent_rate / div; |
| 304 | } |
| 305 | |
| 306 | static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) |
| 307 | { |
| 308 | u32 reg; |
| 309 | |
| 310 | reg = __raw_readl(MXC_CCM_CCSR); |
| 311 | |
| 312 | if (parent == &pll2_sw_clk) |
| 313 | reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; |
| 314 | else |
| 315 | reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; |
| 316 | |
| 317 | __raw_writel(reg, MXC_CCM_CCSR); |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) |
| 322 | { |
| 323 | u32 reg; |
| 324 | |
| 325 | if (parent == &osc_clk) |
| 326 | reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; |
| 327 | else |
| 328 | return -EINVAL; |
| 329 | |
| 330 | __raw_writel(reg, MXC_CCM_CCSR); |
| 331 | |
| 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | static unsigned long clk_arm_get_rate(struct clk *clk) |
| 336 | { |
| 337 | u32 cacrr, div; |
| 338 | unsigned long parent_rate; |
| 339 | |
| 340 | parent_rate = clk_get_rate(clk->parent); |
| 341 | cacrr = __raw_readl(MXC_CCM_CACRR); |
| 342 | div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; |
| 343 | |
| 344 | return parent_rate / div; |
| 345 | } |
| 346 | |
| 347 | static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) |
| 348 | { |
| 349 | u32 reg, mux; |
| 350 | int i = 0; |
| 351 | |
| 352 | mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); |
| 353 | |
| 354 | reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; |
| 355 | reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; |
| 356 | __raw_writel(reg, MXC_CCM_CBCMR); |
| 357 | |
| 358 | /* Wait for lock */ |
| 359 | do { |
| 360 | reg = __raw_readl(MXC_CCM_CDHIPR); |
| 361 | if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY)) |
| 362 | break; |
| 363 | |
| 364 | udelay(1); |
| 365 | } while (++i < MAX_DPLL_WAIT_TRIES); |
| 366 | |
| 367 | if (i == MAX_DPLL_WAIT_TRIES) { |
| 368 | pr_err("MX5: Set parent for periph_apm clock failed\n"); |
| 369 | return -EINVAL; |
| 370 | } |
| 371 | |
| 372 | return 0; |
| 373 | } |
| 374 | |
| 375 | static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) |
| 376 | { |
| 377 | u32 reg; |
| 378 | |
| 379 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 380 | |
| 381 | if (parent == &pll2_sw_clk) |
| 382 | reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; |
| 383 | else if (parent == &periph_apm_clk) |
| 384 | reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; |
| 385 | else |
| 386 | return -EINVAL; |
| 387 | |
| 388 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 389 | |
| 390 | return 0; |
| 391 | } |
| 392 | |
| 393 | static struct clk main_bus_clk = { |
| 394 | .parent = &pll2_sw_clk, |
| 395 | .set_parent = _clk_main_bus_set_parent, |
| 396 | }; |
| 397 | |
| 398 | static unsigned long clk_ahb_get_rate(struct clk *clk) |
| 399 | { |
| 400 | u32 reg, div; |
| 401 | unsigned long parent_rate; |
| 402 | |
| 403 | parent_rate = clk_get_rate(clk->parent); |
| 404 | |
| 405 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 406 | div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> |
| 407 | MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; |
| 408 | return parent_rate / div; |
| 409 | } |
| 410 | |
| 411 | |
| 412 | static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) |
| 413 | { |
| 414 | u32 reg, div; |
| 415 | unsigned long parent_rate; |
| 416 | int i = 0; |
| 417 | |
| 418 | parent_rate = clk_get_rate(clk->parent); |
| 419 | |
| 420 | div = parent_rate / rate; |
| 421 | if (div > 8 || div < 1 || ((parent_rate / div) != rate)) |
| 422 | return -EINVAL; |
| 423 | |
| 424 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 425 | reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; |
| 426 | reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; |
| 427 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 428 | |
| 429 | /* Wait for lock */ |
| 430 | do { |
| 431 | reg = __raw_readl(MXC_CCM_CDHIPR); |
| 432 | if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY)) |
| 433 | break; |
| 434 | |
| 435 | udelay(1); |
| 436 | } while (++i < MAX_DPLL_WAIT_TRIES); |
| 437 | |
| 438 | if (i == MAX_DPLL_WAIT_TRIES) { |
| 439 | pr_err("MX5: clk_ahb_set_rate failed\n"); |
| 440 | return -EINVAL; |
| 441 | } |
| 442 | |
| 443 | return 0; |
| 444 | } |
| 445 | |
| 446 | static unsigned long _clk_ahb_round_rate(struct clk *clk, |
| 447 | unsigned long rate) |
| 448 | { |
| 449 | u32 div; |
| 450 | unsigned long parent_rate; |
| 451 | |
| 452 | parent_rate = clk_get_rate(clk->parent); |
| 453 | |
| 454 | div = parent_rate / rate; |
| 455 | if (div > 8) |
| 456 | div = 8; |
| 457 | else if (div == 0) |
| 458 | div++; |
| 459 | return parent_rate / div; |
| 460 | } |
| 461 | |
| 462 | |
| 463 | static int _clk_max_enable(struct clk *clk) |
| 464 | { |
| 465 | u32 reg; |
| 466 | |
| 467 | _clk_ccgr_enable(clk); |
| 468 | |
| 469 | /* Handshake with MAX when LPM is entered. */ |
| 470 | reg = __raw_readl(MXC_CCM_CLPCR); |
| 471 | reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; |
| 472 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 473 | |
| 474 | return 0; |
| 475 | } |
| 476 | |
| 477 | static void _clk_max_disable(struct clk *clk) |
| 478 | { |
| 479 | u32 reg; |
| 480 | |
| 481 | _clk_ccgr_disable_inwait(clk); |
| 482 | |
| 483 | /* No Handshake with MAX when LPM is entered as its disabled. */ |
| 484 | reg = __raw_readl(MXC_CCM_CLPCR); |
| 485 | reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; |
| 486 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 487 | } |
| 488 | |
| 489 | static unsigned long clk_ipg_get_rate(struct clk *clk) |
| 490 | { |
| 491 | u32 reg, div; |
| 492 | unsigned long parent_rate; |
| 493 | |
| 494 | parent_rate = clk_get_rate(clk->parent); |
| 495 | |
| 496 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 497 | div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> |
| 498 | MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; |
| 499 | |
| 500 | return parent_rate / div; |
| 501 | } |
| 502 | |
| 503 | static unsigned long clk_ipg_per_get_rate(struct clk *clk) |
| 504 | { |
| 505 | u32 reg, prediv1, prediv2, podf; |
| 506 | unsigned long parent_rate; |
| 507 | |
| 508 | parent_rate = clk_get_rate(clk->parent); |
| 509 | |
| 510 | if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { |
| 511 | /* the main_bus_clk is the one before the DVFS engine */ |
| 512 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 513 | prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> |
| 514 | MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; |
| 515 | prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> |
| 516 | MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; |
| 517 | podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> |
| 518 | MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; |
| 519 | return parent_rate / (prediv1 * prediv2 * podf); |
| 520 | } else if (clk->parent == &ipg_clk) |
| 521 | return parent_rate; |
| 522 | else |
| 523 | BUG(); |
| 524 | } |
| 525 | |
| 526 | static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) |
| 527 | { |
| 528 | u32 reg; |
| 529 | |
| 530 | reg = __raw_readl(MXC_CCM_CBCMR); |
| 531 | |
| 532 | reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; |
| 533 | reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; |
| 534 | |
| 535 | if (parent == &ipg_clk) |
| 536 | reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; |
| 537 | else if (parent == &lp_apm_clk) |
| 538 | reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; |
| 539 | else if (parent != &main_bus_clk) |
| 540 | return -EINVAL; |
| 541 | |
| 542 | __raw_writel(reg, MXC_CCM_CBCMR); |
| 543 | |
| 544 | return 0; |
| 545 | } |
| 546 | |
| 547 | static unsigned long clk_uart_get_rate(struct clk *clk) |
| 548 | { |
| 549 | u32 reg, prediv, podf; |
| 550 | unsigned long parent_rate; |
| 551 | |
| 552 | parent_rate = clk_get_rate(clk->parent); |
| 553 | |
| 554 | reg = __raw_readl(MXC_CCM_CSCDR1); |
| 555 | prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> |
| 556 | MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; |
| 557 | podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> |
| 558 | MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; |
| 559 | |
| 560 | return parent_rate / (prediv * podf); |
| 561 | } |
| 562 | |
| 563 | static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) |
| 564 | { |
| 565 | u32 reg, mux; |
| 566 | |
| 567 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, |
| 568 | &lp_apm_clk); |
| 569 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; |
| 570 | reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; |
| 571 | __raw_writel(reg, MXC_CCM_CSCMR1); |
| 572 | |
| 573 | return 0; |
| 574 | } |
| 575 | |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 576 | #define clk_nfc_set_parent NULL |
| 577 | |
| 578 | static unsigned long clk_nfc_get_rate(struct clk *clk) |
| 579 | { |
| 580 | unsigned long rate; |
| 581 | u32 reg, div; |
| 582 | |
| 583 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 584 | div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >> |
| 585 | MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1; |
| 586 | rate = clk_get_rate(clk->parent) / div; |
| 587 | WARN_ON(rate == 0); |
| 588 | return rate; |
| 589 | } |
| 590 | |
| 591 | static unsigned long clk_nfc_round_rate(struct clk *clk, |
| 592 | unsigned long rate) |
| 593 | { |
| 594 | u32 div; |
| 595 | unsigned long parent_rate = clk_get_rate(clk->parent); |
| 596 | |
| 597 | if (!rate) |
| 598 | return -EINVAL; |
| 599 | |
| 600 | div = parent_rate / rate; |
| 601 | |
| 602 | if (parent_rate % rate) |
| 603 | div++; |
| 604 | |
| 605 | if (div > 8) |
| 606 | return -EINVAL; |
| 607 | |
| 608 | return parent_rate / div; |
| 609 | |
| 610 | } |
| 611 | |
| 612 | static int clk_nfc_set_rate(struct clk *clk, unsigned long rate) |
| 613 | { |
| 614 | u32 reg, div; |
| 615 | |
| 616 | div = clk_get_rate(clk->parent) / rate; |
| 617 | if (div == 0) |
| 618 | div++; |
| 619 | if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8)) |
| 620 | return -EINVAL; |
| 621 | |
| 622 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 623 | reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; |
| 624 | reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; |
| 625 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 626 | |
| 627 | while (__raw_readl(MXC_CCM_CDHIPR) & |
| 628 | MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){ |
| 629 | } |
| 630 | |
| 631 | return 0; |
| 632 | } |
| 633 | |
Dinh Nguyen | c79504e | 2010-05-10 13:45:58 -0500 | [diff] [blame] | 634 | static unsigned long clk_usboh3_get_rate(struct clk *clk) |
| 635 | { |
| 636 | u32 reg, prediv, podf; |
| 637 | unsigned long parent_rate; |
| 638 | |
| 639 | parent_rate = clk_get_rate(clk->parent); |
| 640 | |
| 641 | reg = __raw_readl(MXC_CCM_CSCDR1); |
| 642 | prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >> |
| 643 | MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1; |
| 644 | podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >> |
| 645 | MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1; |
| 646 | |
| 647 | return parent_rate / (prediv * podf); |
| 648 | } |
| 649 | |
| 650 | static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent) |
| 651 | { |
| 652 | u32 reg, mux; |
| 653 | |
| 654 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, |
| 655 | &lp_apm_clk); |
| 656 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; |
| 657 | reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; |
| 658 | __raw_writel(reg, MXC_CCM_CSCMR1); |
| 659 | |
| 660 | return 0; |
| 661 | } |
| 662 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 663 | static unsigned long get_high_reference_clock_rate(struct clk *clk) |
| 664 | { |
| 665 | return external_high_reference; |
| 666 | } |
| 667 | |
| 668 | static unsigned long get_low_reference_clock_rate(struct clk *clk) |
| 669 | { |
| 670 | return external_low_reference; |
| 671 | } |
| 672 | |
| 673 | static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) |
| 674 | { |
| 675 | return oscillator_reference; |
| 676 | } |
| 677 | |
| 678 | static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) |
| 679 | { |
| 680 | return ckih2_reference; |
| 681 | } |
| 682 | |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 683 | static unsigned long clk_emi_slow_get_rate(struct clk *clk) |
| 684 | { |
| 685 | u32 reg, div; |
| 686 | |
| 687 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 688 | div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >> |
| 689 | MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1; |
| 690 | |
| 691 | return clk_get_rate(clk->parent) / div; |
| 692 | } |
| 693 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 694 | /* External high frequency clock */ |
| 695 | static struct clk ckih_clk = { |
| 696 | .get_rate = get_high_reference_clock_rate, |
| 697 | }; |
| 698 | |
| 699 | static struct clk ckih2_clk = { |
| 700 | .get_rate = get_ckih2_reference_clock_rate, |
| 701 | }; |
| 702 | |
| 703 | static struct clk osc_clk = { |
| 704 | .get_rate = get_oscillator_reference_clock_rate, |
| 705 | }; |
| 706 | |
| 707 | /* External low frequency (32kHz) clock */ |
| 708 | static struct clk ckil_clk = { |
| 709 | .get_rate = get_low_reference_clock_rate, |
| 710 | }; |
| 711 | |
| 712 | static struct clk pll1_main_clk = { |
| 713 | .parent = &osc_clk, |
| 714 | .get_rate = clk_pll_get_rate, |
| 715 | .enable = _clk_pll_enable, |
| 716 | .disable = _clk_pll_disable, |
| 717 | }; |
| 718 | |
| 719 | /* Clock tree block diagram (WIP): |
| 720 | * CCM: Clock Controller Module |
| 721 | * |
| 722 | * PLL output -> | |
| 723 | * | CCM Switcher -> CCM_CLK_ROOT_GEN -> |
| 724 | * PLL bypass -> | |
| 725 | * |
| 726 | */ |
| 727 | |
| 728 | /* PLL1 SW supplies to ARM core */ |
| 729 | static struct clk pll1_sw_clk = { |
| 730 | .parent = &pll1_main_clk, |
| 731 | .set_parent = _clk_pll1_sw_set_parent, |
| 732 | .get_rate = clk_pll1_sw_get_rate, |
| 733 | }; |
| 734 | |
| 735 | /* PLL2 SW supplies to AXI/AHB/IP buses */ |
| 736 | static struct clk pll2_sw_clk = { |
| 737 | .parent = &osc_clk, |
| 738 | .get_rate = clk_pll_get_rate, |
| 739 | .set_rate = _clk_pll_set_rate, |
| 740 | .set_parent = _clk_pll2_sw_set_parent, |
| 741 | .enable = _clk_pll_enable, |
| 742 | .disable = _clk_pll_disable, |
| 743 | }; |
| 744 | |
| 745 | /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */ |
| 746 | static struct clk pll3_sw_clk = { |
| 747 | .parent = &osc_clk, |
| 748 | .set_rate = _clk_pll_set_rate, |
| 749 | .get_rate = clk_pll_get_rate, |
| 750 | .enable = _clk_pll_enable, |
| 751 | .disable = _clk_pll_disable, |
| 752 | }; |
| 753 | |
| 754 | /* Low-power Audio Playback Mode clock */ |
| 755 | static struct clk lp_apm_clk = { |
| 756 | .parent = &osc_clk, |
| 757 | .set_parent = _clk_lp_apm_set_parent, |
| 758 | }; |
| 759 | |
| 760 | static struct clk periph_apm_clk = { |
| 761 | .parent = &pll1_sw_clk, |
| 762 | .set_parent = _clk_periph_apm_set_parent, |
| 763 | }; |
| 764 | |
| 765 | static struct clk cpu_clk = { |
| 766 | .parent = &pll1_sw_clk, |
| 767 | .get_rate = clk_arm_get_rate, |
| 768 | }; |
| 769 | |
| 770 | static struct clk ahb_clk = { |
| 771 | .parent = &main_bus_clk, |
| 772 | .get_rate = clk_ahb_get_rate, |
| 773 | .set_rate = _clk_ahb_set_rate, |
| 774 | .round_rate = _clk_ahb_round_rate, |
| 775 | }; |
| 776 | |
| 777 | /* Main IP interface clock for access to registers */ |
| 778 | static struct clk ipg_clk = { |
| 779 | .parent = &ahb_clk, |
| 780 | .get_rate = clk_ipg_get_rate, |
| 781 | }; |
| 782 | |
| 783 | static struct clk ipg_perclk = { |
| 784 | .parent = &lp_apm_clk, |
| 785 | .get_rate = clk_ipg_per_get_rate, |
| 786 | .set_parent = _clk_ipg_per_set_parent, |
| 787 | }; |
| 788 | |
| 789 | static struct clk uart_root_clk = { |
| 790 | .parent = &pll2_sw_clk, |
| 791 | .get_rate = clk_uart_get_rate, |
| 792 | .set_parent = _clk_uart_set_parent, |
| 793 | }; |
| 794 | |
Dinh Nguyen | c79504e | 2010-05-10 13:45:58 -0500 | [diff] [blame] | 795 | static struct clk usboh3_clk = { |
| 796 | .parent = &pll2_sw_clk, |
| 797 | .get_rate = clk_usboh3_get_rate, |
| 798 | .set_parent = _clk_usboh3_set_parent, |
| 799 | }; |
| 800 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 801 | static struct clk ahb_max_clk = { |
| 802 | .parent = &ahb_clk, |
| 803 | .enable_reg = MXC_CCM_CCGR0, |
| 804 | .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, |
| 805 | .enable = _clk_max_enable, |
| 806 | .disable = _clk_max_disable, |
| 807 | }; |
| 808 | |
| 809 | static struct clk aips_tz1_clk = { |
| 810 | .parent = &ahb_clk, |
| 811 | .secondary = &ahb_max_clk, |
| 812 | .enable_reg = MXC_CCM_CCGR0, |
| 813 | .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, |
| 814 | .enable = _clk_ccgr_enable, |
| 815 | .disable = _clk_ccgr_disable_inwait, |
| 816 | }; |
| 817 | |
| 818 | static struct clk aips_tz2_clk = { |
| 819 | .parent = &ahb_clk, |
| 820 | .secondary = &ahb_max_clk, |
| 821 | .enable_reg = MXC_CCM_CCGR0, |
| 822 | .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, |
| 823 | .enable = _clk_ccgr_enable, |
| 824 | .disable = _clk_ccgr_disable_inwait, |
| 825 | }; |
| 826 | |
| 827 | static struct clk gpt_32k_clk = { |
| 828 | .id = 0, |
| 829 | .parent = &ckil_clk, |
| 830 | }; |
| 831 | |
Jason Wang | a7ebd93 | 2010-07-14 21:24:53 +0800 | [diff] [blame] | 832 | static struct clk kpp_clk = { |
| 833 | .id = 0, |
| 834 | }; |
| 835 | |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 836 | static struct clk emi_slow_clk = { |
| 837 | .parent = &pll2_sw_clk, |
| 838 | .enable_reg = MXC_CCM_CCGR5, |
| 839 | .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, |
| 840 | .enable = _clk_ccgr_enable, |
| 841 | .disable = _clk_ccgr_disable_inwait, |
| 842 | .get_rate = clk_emi_slow_get_rate, |
| 843 | }; |
| 844 | |
| 845 | #define DEFINE_CLOCK1(name, i, er, es, pfx, p, s) \ |
| 846 | static struct clk name = { \ |
| 847 | .id = i, \ |
| 848 | .enable_reg = er, \ |
| 849 | .enable_shift = es, \ |
| 850 | .get_rate = pfx##_get_rate, \ |
| 851 | .set_rate = pfx##_set_rate, \ |
| 852 | .round_rate = pfx##_round_rate, \ |
| 853 | .set_parent = pfx##_set_parent, \ |
| 854 | .enable = _clk_ccgr_enable, \ |
| 855 | .disable = _clk_ccgr_disable, \ |
| 856 | .parent = p, \ |
| 857 | .secondary = s, \ |
| 858 | } |
| 859 | |
Jason Wang | 8d83db8 | 2010-09-02 15:52:00 +0800 | [diff] [blame] | 860 | /* eCSPI */ |
| 861 | static unsigned long clk_ecspi_get_rate(struct clk *clk) |
| 862 | { |
| 863 | u32 reg, pred, podf; |
| 864 | |
| 865 | reg = __raw_readl(MXC_CCM_CSCDR2); |
| 866 | |
| 867 | pred = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >> |
| 868 | MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; |
| 869 | podf = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >> |
| 870 | MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; |
| 871 | |
| 872 | return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), |
| 873 | (pred + 1) * (podf + 1)); |
| 874 | } |
| 875 | |
| 876 | static int clk_ecspi_set_parent(struct clk *clk, struct clk *parent) |
| 877 | { |
| 878 | u32 reg, mux; |
| 879 | |
| 880 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, |
| 881 | &lp_apm_clk); |
| 882 | |
| 883 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK; |
| 884 | reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; |
| 885 | __raw_writel(reg, MXC_CCM_CSCMR1); |
| 886 | |
| 887 | return 0; |
| 888 | } |
| 889 | |
| 890 | static struct clk ecspi_main_clk = { |
| 891 | .parent = &pll3_sw_clk, |
| 892 | .get_rate = clk_ecspi_get_rate, |
| 893 | .set_parent = clk_ecspi_set_parent, |
| 894 | }; |
| 895 | |
Uwe Kleine-König | 74d99f3 | 2010-09-10 17:01:26 +0200 | [diff] [blame] | 896 | #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ |
| 897 | static struct clk name = { \ |
| 898 | .id = i, \ |
| 899 | .enable_reg = er, \ |
| 900 | .enable_shift = es, \ |
| 901 | .get_rate = gr, \ |
| 902 | .set_rate = sr, \ |
| 903 | .enable = e, \ |
| 904 | .disable = d, \ |
| 905 | .parent = p, \ |
| 906 | .secondary = s, \ |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 907 | } |
| 908 | |
Uwe Kleine-König | 74d99f3 | 2010-09-10 17:01:26 +0200 | [diff] [blame] | 909 | #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ |
| 910 | DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s) |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 911 | |
| 912 | /* Shared peripheral bus arbiter */ |
| 913 | DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, |
| 914 | NULL, NULL, &ipg_clk, NULL); |
| 915 | |
| 916 | /* UART */ |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 917 | DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, |
| 918 | NULL, NULL, &ipg_clk, &aips_tz1_clk); |
| 919 | DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, |
| 920 | NULL, NULL, &ipg_clk, &aips_tz1_clk); |
| 921 | DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, |
| 922 | NULL, NULL, &ipg_clk, &spba_clk); |
Sascha Hauer | 8f6e900 | 2010-08-25 11:56:26 +0200 | [diff] [blame] | 923 | DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, |
| 924 | NULL, NULL, &uart_root_clk, &uart1_ipg_clk); |
| 925 | DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, |
| 926 | NULL, NULL, &uart_root_clk, &uart2_ipg_clk); |
| 927 | DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, |
| 928 | NULL, NULL, &uart_root_clk, &uart3_ipg_clk); |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 929 | |
| 930 | /* GPT */ |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 931 | DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, |
| 932 | NULL, NULL, &ipg_clk, NULL); |
Sascha Hauer | 8f6e900 | 2010-08-25 11:56:26 +0200 | [diff] [blame] | 933 | DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, |
| 934 | NULL, NULL, &ipg_clk, &gpt_ipg_clk); |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 935 | |
Dinh Nguyen | 71c2e51 | 2010-05-27 10:45:04 -0500 | [diff] [blame] | 936 | /* I2C */ |
| 937 | DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, |
| 938 | NULL, NULL, &ipg_clk, NULL); |
| 939 | DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET, |
| 940 | NULL, NULL, &ipg_clk, NULL); |
| 941 | DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, |
| 942 | NULL, NULL, &ipg_clk, NULL); |
| 943 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 944 | /* FEC */ |
| 945 | DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, |
| 946 | NULL, NULL, &ipg_clk, NULL); |
| 947 | |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 948 | /* NFC */ |
| 949 | DEFINE_CLOCK1(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET, |
| 950 | clk_nfc, &emi_slow_clk, NULL); |
| 951 | |
Sascha Hauer | b861866 | 2010-08-20 16:43:54 +0200 | [diff] [blame] | 952 | /* SSI */ |
| 953 | DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET, |
| 954 | NULL, NULL, &ipg_clk, NULL); |
| 955 | DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET, |
| 956 | NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk); |
| 957 | DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET, |
| 958 | NULL, NULL, &ipg_clk, NULL); |
| 959 | DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, |
| 960 | NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); |
| 961 | |
Jason Wang | 8d83db8 | 2010-09-02 15:52:00 +0800 | [diff] [blame] | 962 | /* eCSPI */ |
| 963 | DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, |
| 964 | NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, |
| 965 | &ipg_clk, &spba_clk); |
| 966 | DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET, |
| 967 | NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk); |
| 968 | DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET, |
| 969 | NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, |
| 970 | &ipg_clk, &aips_tz2_clk); |
| 971 | DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET, |
| 972 | NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk); |
| 973 | |
| 974 | /* CSPI */ |
| 975 | DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, |
| 976 | NULL, NULL, &ipg_clk, &aips_tz2_clk); |
| 977 | DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET, |
| 978 | NULL, NULL, &ipg_clk, &cspi_ipg_clk); |
| 979 | |
Uwe Kleine-König | 8a8d206 | 2010-10-08 16:00:11 +0200 | [diff] [blame^] | 980 | /* SDMA */ |
| 981 | DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET, |
| 982 | NULL, NULL, &ahb_clk, NULL); |
| 983 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 984 | #define _REGISTER_CLOCK(d, n, c) \ |
| 985 | { \ |
| 986 | .dev_id = d, \ |
| 987 | .con_id = n, \ |
| 988 | .clk = &c, \ |
| 989 | }, |
| 990 | |
| 991 | static struct clk_lookup lookups[] = { |
| 992 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) |
| 993 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) |
| 994 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
| 995 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) |
| 996 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
Dinh Nguyen | 71c2e51 | 2010-05-27 10:45:04 -0500 | [diff] [blame] | 997 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) |
| 998 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) |
| 999 | _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) |
Dinh Nguyen | c53bdf1 | 2010-04-30 15:48:24 -0500 | [diff] [blame] | 1000 | _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) |
| 1001 | _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) |
| 1002 | _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) |
| 1003 | _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) |
Dinh Nguyen | 2ba5a2c | 2010-05-10 13:45:59 -0500 | [diff] [blame] | 1004 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) |
| 1005 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) |
Jason Wang | a7ebd93 | 2010-07-14 21:24:53 +0800 | [diff] [blame] | 1006 | _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 1007 | _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) |
Sascha Hauer | b861866 | 2010-08-20 16:43:54 +0200 | [diff] [blame] | 1008 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) |
| 1009 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
Uwe Kleine-König | 8a8d206 | 2010-10-08 16:00:11 +0200 | [diff] [blame^] | 1010 | _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) |
Sascha Hauer | 8f6e900 | 2010-08-25 11:56:26 +0200 | [diff] [blame] | 1011 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk) |
| 1012 | _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) |
| 1013 | _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk) |
Jason Wang | 8d83db8 | 2010-09-02 15:52:00 +0800 | [diff] [blame] | 1014 | _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) |
| 1015 | _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) |
| 1016 | _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1017 | }; |
| 1018 | |
| 1019 | static void clk_tree_init(void) |
| 1020 | { |
| 1021 | u32 reg; |
| 1022 | |
| 1023 | ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); |
| 1024 | |
| 1025 | /* |
| 1026 | * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at |
| 1027 | * 8MHz, its derived from lp_apm. |
| 1028 | * |
| 1029 | * FIXME: Verify if true for all boards |
| 1030 | */ |
| 1031 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 1032 | reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; |
| 1033 | reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; |
| 1034 | reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; |
| 1035 | reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); |
| 1036 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 1037 | } |
| 1038 | |
| 1039 | int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, |
| 1040 | unsigned long ckih1, unsigned long ckih2) |
| 1041 | { |
| 1042 | int i; |
| 1043 | |
| 1044 | external_low_reference = ckil; |
| 1045 | external_high_reference = ckih1; |
| 1046 | ckih2_reference = ckih2; |
| 1047 | oscillator_reference = osc; |
| 1048 | |
| 1049 | for (i = 0; i < ARRAY_SIZE(lookups); i++) |
| 1050 | clkdev_add(&lookups[i]); |
| 1051 | |
| 1052 | clk_tree_init(); |
| 1053 | |
| 1054 | clk_enable(&cpu_clk); |
| 1055 | clk_enable(&main_bus_clk); |
| 1056 | |
Dinh Nguyen | c79504e | 2010-05-10 13:45:58 -0500 | [diff] [blame] | 1057 | /* set the usboh3_clk parent to pll2_sw_clk */ |
| 1058 | clk_set_parent(&usboh3_clk, &pll2_sw_clk); |
| 1059 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1060 | /* System timer */ |
| 1061 | mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), |
| 1062 | MX51_MXC_INT_GPT); |
| 1063 | return 0; |
| 1064 | } |