blob: 3b283fd898ff54c9ab7b1dbdc3a2dd3c8dff0d53 [file] [log] [blame]
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +09001/*
2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/err.h>
18#include <linux/gpio.h>
19#include <linux/device.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/pinctrl/pinconf.h>
Thomas Abraham8dc35682013-03-27 00:12:33 +090023#include <linux/interrupt.h>
24#include <linux/irqdomain.h>
25#include <linux/of_irq.h>
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +090026#include "core.h"
27
28/* EXYNOS5440 GPIO and Pinctrl register offsets */
29#define GPIO_MUX 0x00
30#define GPIO_IE 0x04
31#define GPIO_INT 0x08
32#define GPIO_TYPE 0x0C
33#define GPIO_VAL 0x10
34#define GPIO_OE 0x14
35#define GPIO_IN 0x18
36#define GPIO_PE 0x1C
37#define GPIO_PS 0x20
38#define GPIO_SR 0x24
39#define GPIO_DS0 0x28
40#define GPIO_DS1 0x2C
41
42#define EXYNOS5440_MAX_PINS 23
Thomas Abraham8dc35682013-03-27 00:12:33 +090043#define EXYNOS5440_MAX_GPIO_INT 8
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +090044#define PIN_NAME_LENGTH 10
45
46#define GROUP_SUFFIX "-grp"
47#define GSUFFIX_LEN sizeof(GROUP_SUFFIX)
48#define FUNCTION_SUFFIX "-mux"
49#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX)
50
51/*
52 * pin configuration type and its value are packed together into a 16-bits.
53 * The upper 8-bits represent the configuration type and the lower 8-bits
54 * hold the value of the configuration type.
55 */
56#define PINCFG_TYPE_MASK 0xFF
57#define PINCFG_VALUE_SHIFT 8
58#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
59#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
60#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
61#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
62 PINCFG_VALUE_SHIFT)
63
64/**
65 * enum pincfg_type - possible pin configuration types supported.
66 * @PINCFG_TYPE_PUD: Pull up/down configuration.
67 * @PINCFG_TYPE_DRV: Drive strength configuration.
68 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
69 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
70 */
71enum pincfg_type {
72 PINCFG_TYPE_PUD,
73 PINCFG_TYPE_DRV,
74 PINCFG_TYPE_SKEW_RATE,
75 PINCFG_TYPE_INPUT_TYPE
76};
77
78/**
79 * struct exynos5440_pin_group: represent group of pins for pincfg setting.
80 * @name: name of the pin group, used to lookup the group.
81 * @pins: the pins included in this group.
82 * @num_pins: number of pins included in this group.
83 */
84struct exynos5440_pin_group {
85 const char *name;
86 const unsigned int *pins;
87 u8 num_pins;
88};
89
90/**
91 * struct exynos5440_pmx_func: represent a pin function.
92 * @name: name of the pin function, used to lookup the function.
93 * @groups: one or more names of pin groups that provide this function.
94 * @num_groups: number of groups included in @groups.
95 * @function: the function number to be programmed when selected.
96 */
97struct exynos5440_pmx_func {
98 const char *name;
99 const char **groups;
100 u8 num_groups;
101 unsigned long function;
102};
103
104/**
105 * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
106 * @reg_base: ioremapped based address of the register space.
107 * @gc: gpio chip registered with gpiolib.
108 * @pin_groups: list of pin groups parsed from device tree.
109 * @nr_groups: number of pin groups available.
110 * @pmx_functions: list of pin functions parsed from device tree.
111 * @nr_functions: number of pin functions available.
112 */
113struct exynos5440_pinctrl_priv_data {
114 void __iomem *reg_base;
115 struct gpio_chip *gc;
Thomas Abraham8dc35682013-03-27 00:12:33 +0900116 struct irq_domain *irq_domain;
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900117
118 const struct exynos5440_pin_group *pin_groups;
119 unsigned int nr_groups;
120 const struct exynos5440_pmx_func *pmx_functions;
121 unsigned int nr_functions;
122};
123
Thomas Abraham8dc35682013-03-27 00:12:33 +0900124/**
125 * struct exynos5440_gpio_intr_data: private data for gpio interrupts.
126 * @priv: driver's private runtime data.
127 * @gpio_int: gpio interrupt number.
128 */
129struct exynos5440_gpio_intr_data {
130 struct exynos5440_pinctrl_priv_data *priv;
131 unsigned int gpio_int;
132};
133
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900134/* list of all possible config options supported */
Axel Lind5fd5da2012-12-10 09:54:03 +0900135static struct pin_config {
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900136 char *prop_cfg;
137 unsigned int cfg_type;
138} pcfgs[] = {
139 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
140 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
141 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
142 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
143};
144
145/* check if the selector is a valid pin group selector */
146static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
147{
148 struct exynos5440_pinctrl_priv_data *priv;
149
150 priv = pinctrl_dev_get_drvdata(pctldev);
151 return priv->nr_groups;
152}
153
154/* return the name of the group selected by the group selector */
155static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
156 unsigned selector)
157{
158 struct exynos5440_pinctrl_priv_data *priv;
159
160 priv = pinctrl_dev_get_drvdata(pctldev);
161 return priv->pin_groups[selector].name;
162}
163
164/* return the pin numbers associated with the specified group */
165static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
166 unsigned selector, const unsigned **pins, unsigned *num_pins)
167{
168 struct exynos5440_pinctrl_priv_data *priv;
169
170 priv = pinctrl_dev_get_drvdata(pctldev);
171 *pins = priv->pin_groups[selector].pins;
172 *num_pins = priv->pin_groups[selector].num_pins;
173 return 0;
174}
175
176/* create pinctrl_map entries by parsing device tree nodes */
177static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
178 struct device_node *np, struct pinctrl_map **maps,
179 unsigned *nmaps)
180{
181 struct device *dev = pctldev->dev;
182 struct pinctrl_map *map;
183 unsigned long *cfg = NULL;
184 char *gname, *fname;
185 int cfg_cnt = 0, map_cnt = 0, idx = 0;
186
187 /* count the number of config options specfied in the node */
188 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
189 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
190 cfg_cnt++;
191
192 /*
193 * Find out the number of map entries to create. All the config options
194 * can be accomadated into a single config map entry.
195 */
196 if (cfg_cnt)
197 map_cnt = 1;
198 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
199 map_cnt++;
200 if (!map_cnt) {
201 dev_err(dev, "node %s does not have either config or function "
202 "configurations\n", np->name);
203 return -EINVAL;
204 }
205
206 /* Allocate memory for pin-map entries */
207 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
208 if (!map) {
209 dev_err(dev, "could not alloc memory for pin-maps\n");
210 return -ENOMEM;
211 }
212 *nmaps = 0;
213
214 /*
215 * Allocate memory for pin group name. The pin group name is derived
216 * from the node name from which these map entries are be created.
217 */
218 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
219 if (!gname) {
220 dev_err(dev, "failed to alloc memory for group name\n");
221 goto free_map;
222 }
Thomas Abraham79bae272013-06-06 10:22:03 +0900223 snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX);
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900224
225 /*
226 * don't have config options? then skip over to creating function
227 * map entries.
228 */
229 if (!cfg_cnt)
230 goto skip_cfgs;
231
232 /* Allocate memory for config entries */
233 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
234 if (!cfg) {
235 dev_err(dev, "failed to alloc memory for configs\n");
236 goto free_gname;
237 }
238
239 /* Prepare a list of config settings */
240 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
241 u32 value;
242 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
243 cfg[cfg_cnt++] =
244 PINCFG_PACK(pcfgs[idx].cfg_type, value);
245 }
246
247 /* create the config map entry */
248 map[*nmaps].data.configs.group_or_pin = gname;
249 map[*nmaps].data.configs.configs = cfg;
250 map[*nmaps].data.configs.num_configs = cfg_cnt;
251 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
252 *nmaps += 1;
253
254skip_cfgs:
255 /* create the function map entry */
256 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
257 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL);
258 if (!fname) {
259 dev_err(dev, "failed to alloc memory for func name\n");
260 goto free_cfg;
261 }
Thomas Abraham79bae272013-06-06 10:22:03 +0900262 snprintf(fname, strlen(np->name) + 4, "%s%s", np->name,
263 FUNCTION_SUFFIX);
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900264
265 map[*nmaps].data.mux.group = gname;
266 map[*nmaps].data.mux.function = fname;
267 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
268 *nmaps += 1;
269 }
270
271 *maps = map;
272 return 0;
273
274free_cfg:
275 kfree(cfg);
276free_gname:
277 kfree(gname);
278free_map:
279 kfree(map);
280 return -ENOMEM;
281}
282
283/* free the memory allocated to hold the pin-map table */
284static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
285 struct pinctrl_map *map, unsigned num_maps)
286{
287 int idx;
288
289 for (idx = 0; idx < num_maps; idx++) {
290 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
291 kfree(map[idx].data.mux.function);
292 if (!idx)
293 kfree(map[idx].data.mux.group);
294 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
295 kfree(map[idx].data.configs.configs);
296 if (!idx)
297 kfree(map[idx].data.configs.group_or_pin);
298 }
299 };
300
301 kfree(map);
302}
303
304/* list of pinctrl callbacks for the pinctrl core */
Laurent Pinchart022ab142013-02-16 10:25:07 +0100305static const struct pinctrl_ops exynos5440_pctrl_ops = {
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900306 .get_groups_count = exynos5440_get_group_count,
307 .get_group_name = exynos5440_get_group_name,
308 .get_group_pins = exynos5440_get_group_pins,
309 .dt_node_to_map = exynos5440_dt_node_to_map,
310 .dt_free_map = exynos5440_dt_free_map,
311};
312
313/* check if the selector is a valid pin function selector */
314static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
315{
316 struct exynos5440_pinctrl_priv_data *priv;
317
318 priv = pinctrl_dev_get_drvdata(pctldev);
319 return priv->nr_functions;
320}
321
322/* return the name of the pin function specified */
323static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
324 unsigned selector)
325{
326 struct exynos5440_pinctrl_priv_data *priv;
327
328 priv = pinctrl_dev_get_drvdata(pctldev);
329 return priv->pmx_functions[selector].name;
330}
331
332/* return the groups associated for the specified function selector */
333static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
334 unsigned selector, const char * const **groups,
335 unsigned * const num_groups)
336{
337 struct exynos5440_pinctrl_priv_data *priv;
338
339 priv = pinctrl_dev_get_drvdata(pctldev);
340 *groups = priv->pmx_functions[selector].groups;
341 *num_groups = priv->pmx_functions[selector].num_groups;
342 return 0;
343}
344
345/* enable or disable a pinmux function */
346static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
347 unsigned group, bool enable)
348{
349 struct exynos5440_pinctrl_priv_data *priv;
350 void __iomem *base;
351 u32 function;
352 u32 data;
353
354 priv = pinctrl_dev_get_drvdata(pctldev);
355 base = priv->reg_base;
356 function = priv->pmx_functions[selector].function;
357
358 data = readl(base + GPIO_MUX);
359 if (enable)
360 data |= (1 << function);
361 else
362 data &= ~(1 << function);
363 writel(data, base + GPIO_MUX);
364}
365
366/* enable a specified pinmux by writing to registers */
367static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
368 unsigned group)
369{
370 exynos5440_pinmux_setup(pctldev, selector, group, true);
371 return 0;
372}
373
374/* disable a specified pinmux by writing to registers */
375static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
376 unsigned selector, unsigned group)
377{
378 exynos5440_pinmux_setup(pctldev, selector, group, false);
379}
380
381/*
382 * The calls to gpio_direction_output() and gpio_direction_input()
383 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
384 * function called from the gpiolib interface).
385 */
386static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
387 struct pinctrl_gpio_range *range, unsigned offset, bool input)
388{
389 return 0;
390}
391
392/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
Laurent Pinchart022ab142013-02-16 10:25:07 +0100393static const struct pinmux_ops exynos5440_pinmux_ops = {
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900394 .get_functions_count = exynos5440_get_functions_count,
395 .get_function_name = exynos5440_pinmux_get_fname,
396 .get_function_groups = exynos5440_pinmux_get_groups,
397 .enable = exynos5440_pinmux_enable,
398 .disable = exynos5440_pinmux_disable,
399 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
400};
401
402/* set the pin config settings for a specified pin */
403static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
404 unsigned long config)
405{
406 struct exynos5440_pinctrl_priv_data *priv;
407 void __iomem *base;
408 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config);
409 u32 cfg_value = PINCFG_UNPACK_VALUE(config);
410 u32 data;
411
412 priv = pinctrl_dev_get_drvdata(pctldev);
413 base = priv->reg_base;
414
415 switch (cfg_type) {
416 case PINCFG_TYPE_PUD:
417 /* first set pull enable/disable bit */
418 data = readl(base + GPIO_PE);
419 data &= ~(1 << pin);
420 if (cfg_value)
421 data |= (1 << pin);
422 writel(data, base + GPIO_PE);
423
424 /* then set pull up/down bit */
425 data = readl(base + GPIO_PS);
426 data &= ~(1 << pin);
427 if (cfg_value == 2)
428 data |= (1 << pin);
429 writel(data, base + GPIO_PS);
430 break;
431
432 case PINCFG_TYPE_DRV:
433 /* set the first bit of the drive strength */
434 data = readl(base + GPIO_DS0);
435 data &= ~(1 << pin);
436 data |= ((cfg_value & 1) << pin);
437 writel(data, base + GPIO_DS0);
438 cfg_value >>= 1;
439
440 /* set the second bit of the driver strength */
441 data = readl(base + GPIO_DS1);
442 data &= ~(1 << pin);
443 data |= ((cfg_value & 1) << pin);
444 writel(data, base + GPIO_DS1);
445 break;
446 case PINCFG_TYPE_SKEW_RATE:
447 data = readl(base + GPIO_SR);
448 data &= ~(1 << pin);
449 data |= ((cfg_value & 1) << pin);
450 writel(data, base + GPIO_SR);
451 break;
452 case PINCFG_TYPE_INPUT_TYPE:
453 data = readl(base + GPIO_TYPE);
454 data &= ~(1 << pin);
455 data |= ((cfg_value & 1) << pin);
456 writel(data, base + GPIO_TYPE);
457 break;
458 default:
459 WARN_ON(1);
460 return -EINVAL;
461 }
462
463 return 0;
464}
465
466/* get the pin config settings for a specified pin */
467static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
468 unsigned long *config)
469{
470 struct exynos5440_pinctrl_priv_data *priv;
471 void __iomem *base;
472 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
473 u32 data;
474
475 priv = pinctrl_dev_get_drvdata(pctldev);
476 base = priv->reg_base;
477
478 switch (cfg_type) {
479 case PINCFG_TYPE_PUD:
480 data = readl(base + GPIO_PE);
481 data = (data >> pin) & 1;
482 if (!data)
483 *config = 0;
484 else
485 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
486 break;
487 case PINCFG_TYPE_DRV:
488 data = readl(base + GPIO_DS0);
489 data = (data >> pin) & 1;
490 *config = data;
491 data = readl(base + GPIO_DS1);
492 data = (data >> pin) & 1;
493 *config |= (data << 1);
494 break;
495 case PINCFG_TYPE_SKEW_RATE:
496 data = readl(base + GPIO_SR);
497 *config = (data >> pin) & 1;
498 break;
499 case PINCFG_TYPE_INPUT_TYPE:
500 data = readl(base + GPIO_TYPE);
501 *config = (data >> pin) & 1;
502 break;
503 default:
504 WARN_ON(1);
505 return -EINVAL;
506 }
507
508 return 0;
509}
510
511/* set the pin config settings for a specified pin group */
512static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
513 unsigned group, unsigned long config)
514{
515 struct exynos5440_pinctrl_priv_data *priv;
516 const unsigned int *pins;
517 unsigned int cnt;
518
519 priv = pinctrl_dev_get_drvdata(pctldev);
520 pins = priv->pin_groups[group].pins;
521
522 for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
523 exynos5440_pinconf_set(pctldev, pins[cnt], config);
524
525 return 0;
526}
527
528/* get the pin config settings for a specified pin group */
529static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
530 unsigned int group, unsigned long *config)
531{
532 struct exynos5440_pinctrl_priv_data *priv;
533 const unsigned int *pins;
534
535 priv = pinctrl_dev_get_drvdata(pctldev);
536 pins = priv->pin_groups[group].pins;
537 exynos5440_pinconf_get(pctldev, pins[0], config);
538 return 0;
539}
540
541/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
Laurent Pinchart022ab142013-02-16 10:25:07 +0100542static const struct pinconf_ops exynos5440_pinconf_ops = {
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900543 .pin_config_get = exynos5440_pinconf_get,
544 .pin_config_set = exynos5440_pinconf_set,
545 .pin_config_group_get = exynos5440_pinconf_group_get,
546 .pin_config_group_set = exynos5440_pinconf_group_set,
547};
548
549/* gpiolib gpio_set callback function */
550static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
551{
552 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
553 void __iomem *base = priv->reg_base;
554 u32 data;
555
556 data = readl(base + GPIO_VAL);
557 data &= ~(1 << offset);
558 if (value)
559 data |= 1 << offset;
560 writel(data, base + GPIO_VAL);
561}
562
563/* gpiolib gpio_get callback function */
564static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
565{
566 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
567 void __iomem *base = priv->reg_base;
568 u32 data;
569
570 data = readl(base + GPIO_IN);
571 data >>= offset;
572 data &= 1;
573 return data;
574}
575
576/* gpiolib gpio_direction_input callback function */
577static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
578{
579 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
580 void __iomem *base = priv->reg_base;
581 u32 data;
582
583 /* first disable the data output enable on this pin */
584 data = readl(base + GPIO_OE);
585 data &= ~(1 << offset);
586 writel(data, base + GPIO_OE);
587
588 /* now enable input on this pin */
589 data = readl(base + GPIO_IE);
590 data |= 1 << offset;
591 writel(data, base + GPIO_IE);
592 return 0;
593}
594
595/* gpiolib gpio_direction_output callback function */
596static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
597 int value)
598{
599 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
600 void __iomem *base = priv->reg_base;
601 u32 data;
602
603 exynos5440_gpio_set(gc, offset, value);
604
605 /* first disable the data input enable on this pin */
606 data = readl(base + GPIO_IE);
607 data &= ~(1 << offset);
608 writel(data, base + GPIO_IE);
609
610 /* now enable output on this pin */
611 data = readl(base + GPIO_OE);
612 data |= 1 << offset;
613 writel(data, base + GPIO_OE);
614 return 0;
615}
616
Thomas Abraham8dc35682013-03-27 00:12:33 +0900617/* gpiolib gpio_to_irq callback function */
618static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
619{
620 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
621 unsigned int virq;
622
623 if (offset < 16 || offset > 23)
624 return -ENXIO;
625
626 if (!priv->irq_domain)
627 return -ENXIO;
628
629 virq = irq_create_mapping(priv->irq_domain, offset - 16);
630 return virq ? : -ENXIO;
631}
632
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900633/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
Arnd Bergmann312b00e52013-01-25 14:14:29 +0000634static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900635 struct device_node *cfg_np, unsigned int **pin_list,
636 unsigned int *npins)
637{
638 struct device *dev = &pdev->dev;
639 struct property *prop;
640
641 prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
642 if (!prop)
643 return -ENOENT;
644
645 *npins = prop->length / sizeof(unsigned long);
646 if (!*npins) {
647 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
648 return -EINVAL;
649 }
650
651 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
652 if (!*pin_list) {
653 dev_err(dev, "failed to allocate memory for pin list\n");
654 return -ENOMEM;
655 }
656
657 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
658 *pin_list, *npins);
659}
660
661/*
662 * Parse the information about all the available pin groups and pin functions
663 * from device node of the pin-controller.
664 */
Arnd Bergmann312b00e52013-01-25 14:14:29 +0000665static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900666 struct exynos5440_pinctrl_priv_data *priv)
667{
668 struct device *dev = &pdev->dev;
669 struct device_node *dev_np = dev->of_node;
670 struct device_node *cfg_np;
671 struct exynos5440_pin_group *groups, *grp;
672 struct exynos5440_pmx_func *functions, *func;
673 unsigned *pin_list;
674 unsigned int npins, grp_cnt, func_idx = 0;
675 char *gname, *fname;
676 int ret;
677
678 grp_cnt = of_get_child_count(dev_np);
679 if (!grp_cnt)
680 return -EINVAL;
681
682 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
683 if (!groups) {
684 dev_err(dev, "failed allocate memory for ping group list\n");
685 return -EINVAL;
686 }
687 grp = groups;
688
689 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
690 if (!functions) {
691 dev_err(dev, "failed to allocate memory for function list\n");
692 return -EINVAL;
693 }
694 func = functions;
695
696 /*
697 * Iterate over all the child nodes of the pin controller node
698 * and create pin groups and pin function lists.
699 */
700 for_each_child_of_node(dev_np, cfg_np) {
701 u32 function;
702
703 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
704 &pin_list, &npins);
Thomas Abrahamf9819732013-03-27 00:12:32 +0900705 if (ret) {
706 gname = NULL;
707 goto skip_to_pin_function;
708 }
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900709
710 /* derive pin group name from the node name */
711 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
712 GFP_KERNEL);
713 if (!gname) {
714 dev_err(dev, "failed to alloc memory for group name\n");
715 return -ENOMEM;
716 }
Thomas Abraham79bae272013-06-06 10:22:03 +0900717 snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name,
718 GROUP_SUFFIX);
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900719
720 grp->name = gname;
721 grp->pins = pin_list;
722 grp->num_pins = npins;
723 grp++;
724
Thomas Abrahamf9819732013-03-27 00:12:32 +0900725skip_to_pin_function:
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900726 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
727 &function);
728 if (ret)
729 continue;
730
731 /* derive function name from the node name */
732 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
733 GFP_KERNEL);
734 if (!fname) {
735 dev_err(dev, "failed to alloc memory for func name\n");
736 return -ENOMEM;
737 }
Thomas Abraham79bae272013-06-06 10:22:03 +0900738 snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name,
739 FUNCTION_SUFFIX);
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900740
741 func->name = fname;
742 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
743 if (!func->groups) {
744 dev_err(dev, "failed to alloc memory for group list "
745 "in pin function");
746 return -ENOMEM;
747 }
748 func->groups[0] = gname;
Thomas Abrahamf9819732013-03-27 00:12:32 +0900749 func->num_groups = gname ? 1 : 0;
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900750 func->function = function;
751 func++;
752 func_idx++;
753 }
754
755 priv->pin_groups = groups;
756 priv->nr_groups = grp_cnt;
757 priv->pmx_functions = functions;
758 priv->nr_functions = func_idx;
759 return 0;
760}
761
762/* register the pinctrl interface with the pinctrl subsystem */
Arnd Bergmann312b00e52013-01-25 14:14:29 +0000763static int exynos5440_pinctrl_register(struct platform_device *pdev,
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900764 struct exynos5440_pinctrl_priv_data *priv)
765{
766 struct device *dev = &pdev->dev;
767 struct pinctrl_desc *ctrldesc;
768 struct pinctrl_dev *pctl_dev;
769 struct pinctrl_pin_desc *pindesc, *pdesc;
770 struct pinctrl_gpio_range grange;
771 char *pin_names;
772 int pin, ret;
773
774 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
775 if (!ctrldesc) {
776 dev_err(dev, "could not allocate memory for pinctrl desc\n");
777 return -ENOMEM;
778 }
779
780 ctrldesc->name = "exynos5440-pinctrl";
781 ctrldesc->owner = THIS_MODULE;
782 ctrldesc->pctlops = &exynos5440_pctrl_ops;
783 ctrldesc->pmxops = &exynos5440_pinmux_ops;
784 ctrldesc->confops = &exynos5440_pinconf_ops;
785
786 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
787 EXYNOS5440_MAX_PINS, GFP_KERNEL);
788 if (!pindesc) {
789 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
790 return -ENOMEM;
791 }
792 ctrldesc->pins = pindesc;
793 ctrldesc->npins = EXYNOS5440_MAX_PINS;
794
795 /* dynamically populate the pin number and pin name for pindesc */
796 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
797 pdesc->number = pin;
798
799 /*
800 * allocate space for storing the dynamically generated names for all
801 * the pins which belong to this pin-controller.
802 */
803 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
804 ctrldesc->npins, GFP_KERNEL);
805 if (!pin_names) {
806 dev_err(&pdev->dev, "mem alloc for pin names failed\n");
807 return -ENOMEM;
808 }
809
810 /* for each pin, set the name of the pin */
811 for (pin = 0; pin < ctrldesc->npins; pin++) {
Thomas Abraham79bae272013-06-06 10:22:03 +0900812 snprintf(pin_names, 6, "gpio%02d", pin);
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900813 pdesc = pindesc + pin;
814 pdesc->name = pin_names;
815 pin_names += PIN_NAME_LENGTH;
816 }
817
818 ret = exynos5440_pinctrl_parse_dt(pdev, priv);
819 if (ret)
820 return ret;
821
822 pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
823 if (!pctl_dev) {
824 dev_err(&pdev->dev, "could not register pinctrl driver\n");
825 return -EINVAL;
826 }
827
828 grange.name = "exynos5440-pctrl-gpio-range";
829 grange.id = 0;
830 grange.base = 0;
831 grange.npins = EXYNOS5440_MAX_PINS;
832 grange.gc = priv->gc;
833 pinctrl_add_gpio_range(pctl_dev, &grange);
834 return 0;
835}
836
837/* register the gpiolib interface with the gpiolib subsystem */
Arnd Bergmann312b00e52013-01-25 14:14:29 +0000838static int exynos5440_gpiolib_register(struct platform_device *pdev,
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900839 struct exynos5440_pinctrl_priv_data *priv)
840{
841 struct gpio_chip *gc;
842 int ret;
843
844 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
845 if (!gc) {
846 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
847 return -ENOMEM;
848 }
849
850 priv->gc = gc;
851 gc->base = 0;
852 gc->ngpio = EXYNOS5440_MAX_PINS;
853 gc->dev = &pdev->dev;
854 gc->set = exynos5440_gpio_set;
855 gc->get = exynos5440_gpio_get;
856 gc->direction_input = exynos5440_gpio_direction_input;
857 gc->direction_output = exynos5440_gpio_direction_output;
Thomas Abraham8dc35682013-03-27 00:12:33 +0900858 gc->to_irq = exynos5440_gpio_to_irq;
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900859 gc->label = "gpiolib-exynos5440";
860 gc->owner = THIS_MODULE;
861 ret = gpiochip_add(gc);
862 if (ret) {
863 dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
864 "code: %d\n", gc->label, ret);
865 return ret;
866 }
867
868 return 0;
869}
870
871/* unregister the gpiolib interface with the gpiolib subsystem */
Arnd Bergmann312b00e52013-01-25 14:14:29 +0000872static int exynos5440_gpiolib_unregister(struct platform_device *pdev,
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900873 struct exynos5440_pinctrl_priv_data *priv)
874{
875 int ret = gpiochip_remove(priv->gc);
876 if (ret) {
877 dev_err(&pdev->dev, "gpio chip remove failed\n");
878 return ret;
879 }
880 return 0;
881}
882
Thomas Abraham8dc35682013-03-27 00:12:33 +0900883static void exynos5440_gpio_irq_unmask(struct irq_data *irqd)
884{
885 struct exynos5440_pinctrl_priv_data *d;
886 unsigned long gpio_int;
887
888 d = irq_data_get_irq_chip_data(irqd);
889 gpio_int = readl(d->reg_base + GPIO_INT);
890 gpio_int |= 1 << irqd->hwirq;
891 writel(gpio_int, d->reg_base + GPIO_INT);
892}
893
894static void exynos5440_gpio_irq_mask(struct irq_data *irqd)
895{
896 struct exynos5440_pinctrl_priv_data *d;
897 unsigned long gpio_int;
898
899 d = irq_data_get_irq_chip_data(irqd);
900 gpio_int = readl(d->reg_base + GPIO_INT);
901 gpio_int &= ~(1 << irqd->hwirq);
902 writel(gpio_int, d->reg_base + GPIO_INT);
903}
904
905/* irq_chip for gpio interrupts */
906static struct irq_chip exynos5440_gpio_irq_chip = {
907 .name = "exynos5440_gpio_irq_chip",
908 .irq_unmask = exynos5440_gpio_irq_unmask,
909 .irq_mask = exynos5440_gpio_irq_mask,
910};
911
912/* interrupt handler for GPIO interrupts 0..7 */
913static irqreturn_t exynos5440_gpio_irq(int irq, void *data)
914{
915 struct exynos5440_gpio_intr_data *intd = data;
916 struct exynos5440_pinctrl_priv_data *d = intd->priv;
917 int virq;
918
919 virq = irq_linear_revmap(d->irq_domain, intd->gpio_int);
920 if (!virq)
921 return IRQ_NONE;
922 generic_handle_irq(virq);
923 return IRQ_HANDLED;
924}
925
926static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq,
927 irq_hw_number_t hw)
928{
929 struct exynos5440_pinctrl_priv_data *d = h->host_data;
930
931 irq_set_chip_data(virq, d);
932 irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip,
933 handle_level_irq);
934 set_irq_flags(virq, IRQF_VALID);
935 return 0;
936}
937
938/* irq domain callbacks for gpio interrupt controller */
939static const struct irq_domain_ops exynos5440_gpio_irqd_ops = {
940 .map = exynos5440_gpio_irq_map,
941 .xlate = irq_domain_xlate_twocell,
942};
943
944/* setup handling of gpio interrupts */
945static int exynos5440_gpio_irq_init(struct platform_device *pdev,
946 struct exynos5440_pinctrl_priv_data *priv)
947{
948 struct device *dev = &pdev->dev;
949 struct exynos5440_gpio_intr_data *intd;
950 int i, irq, ret;
951
952 intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT,
953 GFP_KERNEL);
954 if (!intd) {
955 dev_err(dev, "failed to allocate memory for gpio intr data\n");
956 return -ENOMEM;
957 }
958
959 for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) {
960 irq = irq_of_parse_and_map(dev->of_node, i);
961 if (irq <= 0) {
962 dev_err(dev, "irq parsing failed\n");
963 return -EINVAL;
964 }
965
966 intd->gpio_int = i;
967 intd->priv = priv;
968 ret = devm_request_irq(dev, irq, exynos5440_gpio_irq,
969 0, dev_name(dev), intd++);
970 if (ret) {
971 dev_err(dev, "irq request failed\n");
972 return -ENXIO;
973 }
974 }
975
976 priv->irq_domain = irq_domain_add_linear(dev->of_node,
977 EXYNOS5440_MAX_GPIO_INT,
978 &exynos5440_gpio_irqd_ops, priv);
979 if (!priv->irq_domain) {
980 dev_err(dev, "failed to create irq domain\n");
981 return -ENXIO;
982 }
983
984 return 0;
985}
986
Greg Kroah-Hartman150632b2012-12-21 13:10:23 -0800987static int exynos5440_pinctrl_probe(struct platform_device *pdev)
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +0900988{
989 struct device *dev = &pdev->dev;
990 struct exynos5440_pinctrl_priv_data *priv;
991 struct resource *res;
992 int ret;
993
994 if (!dev->of_node) {
995 dev_err(dev, "device tree node not found\n");
996 return -ENODEV;
997 }
998
Wei Yongjunc078d782013-03-14 21:59:38 +0800999 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +09001000 if (!priv) {
1001 dev_err(dev, "could not allocate memory for private data\n");
1002 return -ENOMEM;
1003 }
1004
1005 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding9e0c1fb2013-01-21 11:09:14 +01001006 priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
1007 if (IS_ERR(priv->reg_base))
1008 return PTR_ERR(priv->reg_base);
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +09001009
1010 ret = exynos5440_gpiolib_register(pdev, priv);
1011 if (ret)
1012 return ret;
1013
1014 ret = exynos5440_pinctrl_register(pdev, priv);
1015 if (ret) {
1016 exynos5440_gpiolib_unregister(pdev, priv);
1017 return ret;
1018 }
1019
Thomas Abraham8dc35682013-03-27 00:12:33 +09001020 ret = exynos5440_gpio_irq_init(pdev, priv);
1021 if (ret) {
1022 dev_err(dev, "failed to setup gpio interrupts\n");
1023 return ret;
1024 }
1025
Thomas Abrahamf0b9a7e2012-10-10 09:41:12 +09001026 platform_set_drvdata(pdev, priv);
1027 dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
1028 return 0;
1029}
1030
1031static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
1032 { .compatible = "samsung,exynos5440-pinctrl" },
1033 {},
1034};
1035MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
1036
1037static struct platform_driver exynos5440_pinctrl_driver = {
1038 .probe = exynos5440_pinctrl_probe,
1039 .driver = {
1040 .name = "exynos5440-pinctrl",
1041 .owner = THIS_MODULE,
1042 .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match),
1043 },
1044};
1045
1046static int __init exynos5440_pinctrl_drv_register(void)
1047{
1048 return platform_driver_register(&exynos5440_pinctrl_driver);
1049}
1050postcore_initcall(exynos5440_pinctrl_drv_register);
1051
1052static void __exit exynos5440_pinctrl_drv_unregister(void)
1053{
1054 platform_driver_unregister(&exynos5440_pinctrl_driver);
1055}
1056module_exit(exynos5440_pinctrl_drv_unregister);
1057
1058MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1059MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
1060MODULE_LICENSE("GPL v2");