Colin Cross | ce1e326 | 2010-05-24 17:07:46 -0700 | [diff] [blame] | 1 | /* |
Colin Cross | ce1e326 | 2010-05-24 17:07:46 -0700 | [diff] [blame] | 2 | * Copyright (c) 2010 Google, Inc |
| 3 | * |
| 4 | * Author: |
| 5 | * Colin Cross <ccross@google.com> |
| 6 | * |
| 7 | * This software is licensed under the terms of the GNU General Public |
| 8 | * License version 2, as published by the Free Software Foundation, and |
| 9 | * may be copied, distributed, and modified under those terms. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #ifndef _MACH_TEGRA_POWERGATE_H_ |
| 19 | #define _MACH_TEGRA_POWERGATE_H_ |
| 20 | |
Stephen Warren | a25186e | 2012-10-04 13:50:56 -0600 | [diff] [blame] | 21 | struct clk; |
| 22 | |
Colin Cross | ce1e326 | 2010-05-24 17:07:46 -0700 | [diff] [blame] | 23 | #define TEGRA_POWERGATE_CPU 0 |
| 24 | #define TEGRA_POWERGATE_3D 1 |
| 25 | #define TEGRA_POWERGATE_VENC 2 |
| 26 | #define TEGRA_POWERGATE_PCIE 3 |
| 27 | #define TEGRA_POWERGATE_VDEC 4 |
| 28 | #define TEGRA_POWERGATE_L2 5 |
| 29 | #define TEGRA_POWERGATE_MPE 6 |
Peter De Schrijver | 6cafa97 | 2012-02-10 01:47:48 +0200 | [diff] [blame] | 30 | #define TEGRA_POWERGATE_HEG 7 |
| 31 | #define TEGRA_POWERGATE_SATA 8 |
| 32 | #define TEGRA_POWERGATE_CPU1 9 |
| 33 | #define TEGRA_POWERGATE_CPU2 10 |
| 34 | #define TEGRA_POWERGATE_CPU3 11 |
| 35 | #define TEGRA_POWERGATE_CELP 12 |
| 36 | #define TEGRA_POWERGATE_3D1 13 |
Thierry Reding | bd6a9dd | 2013-10-16 19:19:02 +0200 | [diff] [blame] | 37 | #define TEGRA_POWERGATE_CPU0 14 |
| 38 | #define TEGRA_POWERGATE_C0NC 15 |
| 39 | #define TEGRA_POWERGATE_C1NC 16 |
| 40 | #define TEGRA_POWERGATE_DIS 18 |
| 41 | #define TEGRA_POWERGATE_DISB 19 |
| 42 | #define TEGRA_POWERGATE_XUSBA 20 |
| 43 | #define TEGRA_POWERGATE_XUSBB 21 |
| 44 | #define TEGRA_POWERGATE_XUSBC 22 |
Peter De Schrijver | 6cafa97 | 2012-02-10 01:47:48 +0200 | [diff] [blame] | 45 | |
Peter De Schrijver | 6cafa97 | 2012-02-10 01:47:48 +0200 | [diff] [blame] | 46 | #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D |
Colin Cross | ce1e326 | 2010-05-24 17:07:46 -0700 | [diff] [blame] | 47 | |
Thierry Reding | 9886e1f | 2013-11-25 11:49:47 -0700 | [diff] [blame] | 48 | #ifdef CONFIG_ARCH_TEGRA |
Peter De Schrijver | 6ac8cb5 | 2012-02-10 01:47:47 +0200 | [diff] [blame] | 49 | int tegra_powergate_is_powered(int id); |
Colin Cross | ce1e326 | 2010-05-24 17:07:46 -0700 | [diff] [blame] | 50 | int tegra_powergate_power_on(int id); |
| 51 | int tegra_powergate_power_off(int id); |
Colin Cross | ce1e326 | 2010-05-24 17:07:46 -0700 | [diff] [blame] | 52 | int tegra_powergate_remove_clamping(int id); |
| 53 | |
| 54 | /* Must be called with clk disabled, and returns with clk enabled */ |
| 55 | int tegra_powergate_sequence_power_up(int id, struct clk *clk); |
Thierry Reding | 9886e1f | 2013-11-25 11:49:47 -0700 | [diff] [blame] | 56 | #else |
| 57 | static inline int tegra_powergate_is_powered(int id) |
| 58 | { |
| 59 | return -ENOSYS; |
| 60 | } |
| 61 | |
| 62 | static inline int tegra_powergate_power_on(int id) |
| 63 | { |
| 64 | return -ENOSYS; |
| 65 | } |
| 66 | |
| 67 | static inline int tegra_powergate_power_off(int id) |
| 68 | { |
| 69 | return -ENOSYS; |
| 70 | } |
| 71 | |
| 72 | static inline int tegra_powergate_remove_clamping(int id) |
| 73 | { |
| 74 | return -ENOSYS; |
| 75 | } |
| 76 | |
| 77 | static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk) |
| 78 | { |
| 79 | return -ENOSYS; |
| 80 | } |
| 81 | #endif |
Colin Cross | ce1e326 | 2010-05-24 17:07:46 -0700 | [diff] [blame] | 82 | |
| 83 | #endif /* _MACH_TEGRA_POWERGATE_H_ */ |