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Mattias Wallin489bcce2011-05-27 10:30:12 +02001/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
6 * Author: Sundar Iyer for ST-Ericsson
7 * sched_clock implementation is based on:
8 * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
9 *
10 * DBx500-PRCMU Timer
11 * The PRCMU has 5 timers which are available in a always-on
12 * power domain. We use the Timer 4 for our always-on clock
Fabio Baltieri807eba52013-01-21 13:09:32 +010013 * source on DB8500.
Mattias Wallin489bcce2011-05-27 10:30:12 +020014 */
15#include <linux/clockchips.h>
16#include <linux/clksrc-dbx500-prcmu.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070017#include <linux/sched_clock.h>
Mattias Wallin489bcce2011-05-27 10:30:12 +020018
Mattias Wallin489bcce2011-05-27 10:30:12 +020019#define RATE_32K 32768
20
21#define TIMER_MODE_CONTINOUS 0x1
22#define TIMER_DOWNCOUNT_VAL 0xffffffff
23
24#define PRCMU_TIMER_REF 0
25#define PRCMU_TIMER_DOWNCOUNT 0x4
26#define PRCMU_TIMER_MODE 0x8
27
28#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */
29
Linus Walleijb1e3be062011-10-03 09:30:20 +020030static void __iomem *clksrc_dbx500_timer_base;
Mattias Wallin489bcce2011-05-27 10:30:12 +020031
Rabin Vincent53028222013-01-21 13:09:31 +010032static cycle_t notrace clksrc_dbx500_prcmu_read(struct clocksource *cs)
Mattias Wallin489bcce2011-05-27 10:30:12 +020033{
Rabin Vincent53028222013-01-21 13:09:31 +010034 void __iomem *base = clksrc_dbx500_timer_base;
Mattias Wallin489bcce2011-05-27 10:30:12 +020035 u32 count, count2;
36
37 do {
Rabin Vincent53028222013-01-21 13:09:31 +010038 count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
39 count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
Mattias Wallin489bcce2011-05-27 10:30:12 +020040 } while (count2 != count);
41
42 /* Negate because the timer is a decrementing counter */
43 return ~count;
44}
45
46static struct clocksource clocksource_dbx500_prcmu = {
47 .name = "dbx500-prcmu-timer",
48 .rating = 300,
49 .read = clksrc_dbx500_prcmu_read,
Mattias Wallin489bcce2011-05-27 10:30:12 +020050 .mask = CLOCKSOURCE_MASK(32),
51 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
52};
53
54#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
Mattias Wallin489bcce2011-05-27 10:30:12 +020055
Linus Walleijcfef0322012-01-02 14:50:15 +010056static u32 notrace dbx500_prcmu_sched_clock_read(void)
Mattias Wallin489bcce2011-05-27 10:30:12 +020057{
Mattias Wallin489bcce2011-05-27 10:30:12 +020058 if (unlikely(!clksrc_dbx500_timer_base))
59 return 0;
60
Linus Walleijcfef0322012-01-02 14:50:15 +010061 return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
Mattias Wallin489bcce2011-05-27 10:30:12 +020062}
63
Mattias Wallin489bcce2011-05-27 10:30:12 +020064#endif
65
Linus Walleijb1e3be062011-10-03 09:30:20 +020066void __init clksrc_dbx500_prcmu_init(void __iomem *base)
Mattias Wallin489bcce2011-05-27 10:30:12 +020067{
Linus Walleijb1e3be062011-10-03 09:30:20 +020068 clksrc_dbx500_timer_base = base;
69
Mattias Wallin489bcce2011-05-27 10:30:12 +020070 /*
71 * The A9 sub system expects the timer to be configured as
72 * a continous looping timer.
73 * The PRCMU should configure it but if it for some reason
74 * don't we do it here.
75 */
76 if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
77 TIMER_MODE_CONTINOUS) {
78 writel(TIMER_MODE_CONTINOUS,
79 clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
80 writel(TIMER_DOWNCOUNT_VAL,
81 clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
82 }
83#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
Linus Walleijcfef0322012-01-02 14:50:15 +010084 setup_sched_clock(dbx500_prcmu_sched_clock_read,
Mattias Wallin489bcce2011-05-27 10:30:12 +020085 32, RATE_32K);
86#endif
Yong Zhang13f0f032011-12-01 15:20:15 +080087 clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
Mattias Wallin489bcce2011-05-27 10:30:12 +020088}