Kumar Gala | e5aae72 | 2011-06-27 07:53:24 -0500 | [diff] [blame] | 1 | /* |
| 2 | * P3041 Silicon Device Tree Source |
| 3 | * |
| 4 | * Copyright 2010-2011 Freescale Semiconductor Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions are met: |
| 8 | * * Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * * Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in the |
| 12 | * documentation and/or other materials provided with the distribution. |
| 13 | * * Neither the name of Freescale Semiconductor nor the |
| 14 | * names of its contributors may be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
| 16 | * |
| 17 | * |
| 18 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 19 | * GNU General Public License ("GPL") as published by the Free Software |
| 20 | * Foundation, either version 2 of that License or (at your option) any |
| 21 | * later version. |
| 22 | * |
| 23 | * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
| 24 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 25 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 26 | * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
| 27 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 28 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 29 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 30 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 33 | */ |
| 34 | |
| 35 | /dts-v1/; |
| 36 | |
| 37 | / { |
| 38 | compatible = "fsl,P3041"; |
| 39 | #address-cells = <2>; |
| 40 | #size-cells = <2>; |
| 41 | interrupt-parent = <&mpic>; |
| 42 | |
| 43 | aliases { |
| 44 | ccsr = &soc; |
Stephen George | b9df022 | 2011-09-16 10:36:34 -0500 | [diff] [blame] | 45 | dcsr = &dcsr; |
Kumar Gala | e5aae72 | 2011-06-27 07:53:24 -0500 | [diff] [blame] | 46 | |
| 47 | serial0 = &serial0; |
| 48 | serial1 = &serial1; |
| 49 | serial2 = &serial2; |
| 50 | serial3 = &serial3; |
| 51 | pci0 = &pci0; |
| 52 | pci1 = &pci1; |
| 53 | pci2 = &pci2; |
| 54 | pci3 = &pci3; |
| 55 | usb0 = &usb0; |
| 56 | usb1 = &usb1; |
| 57 | dma0 = &dma0; |
| 58 | dma1 = &dma1; |
| 59 | sdhc = &sdhc; |
| 60 | msi0 = &msi0; |
| 61 | msi1 = &msi1; |
| 62 | msi2 = &msi2; |
| 63 | |
| 64 | crypto = &crypto; |
| 65 | sec_jr0 = &sec_jr0; |
| 66 | sec_jr1 = &sec_jr1; |
| 67 | sec_jr2 = &sec_jr2; |
| 68 | sec_jr3 = &sec_jr3; |
| 69 | rtic_a = &rtic_a; |
| 70 | rtic_b = &rtic_b; |
| 71 | rtic_c = &rtic_c; |
| 72 | rtic_d = &rtic_d; |
| 73 | sec_mon = &sec_mon; |
| 74 | |
| 75 | /* |
| 76 | rio0 = &rapidio0; |
| 77 | */ |
| 78 | }; |
| 79 | |
| 80 | cpus { |
| 81 | #address-cells = <1>; |
| 82 | #size-cells = <0>; |
| 83 | |
| 84 | cpu0: PowerPC,e500mc@0 { |
| 85 | device_type = "cpu"; |
| 86 | reg = <0>; |
| 87 | next-level-cache = <&L2_0>; |
| 88 | L2_0: l2-cache { |
| 89 | next-level-cache = <&cpc>; |
| 90 | }; |
| 91 | }; |
| 92 | cpu1: PowerPC,e500mc@1 { |
| 93 | device_type = "cpu"; |
| 94 | reg = <1>; |
| 95 | next-level-cache = <&L2_1>; |
| 96 | L2_1: l2-cache { |
| 97 | next-level-cache = <&cpc>; |
| 98 | }; |
| 99 | }; |
| 100 | cpu2: PowerPC,e500mc@2 { |
| 101 | device_type = "cpu"; |
| 102 | reg = <2>; |
| 103 | next-level-cache = <&L2_2>; |
| 104 | L2_2: l2-cache { |
| 105 | next-level-cache = <&cpc>; |
| 106 | }; |
| 107 | }; |
| 108 | cpu3: PowerPC,e500mc@3 { |
| 109 | device_type = "cpu"; |
| 110 | reg = <3>; |
| 111 | next-level-cache = <&L2_3>; |
| 112 | L2_3: l2-cache { |
| 113 | next-level-cache = <&cpc>; |
| 114 | }; |
| 115 | }; |
| 116 | }; |
| 117 | |
Stephen George | b9df022 | 2011-09-16 10:36:34 -0500 | [diff] [blame] | 118 | dcsr: dcsr@f00000000 { |
| 119 | #address-cells = <1>; |
| 120 | #size-cells = <1>; |
| 121 | compatible = "fsl,dcsr", "simple-bus"; |
| 122 | |
| 123 | dcsr-epu@0 { |
| 124 | compatible = "fsl,dcsr-epu"; |
| 125 | interrupts = <52 2 0 0 |
| 126 | 84 2 0 0 |
| 127 | 85 2 0 0>; |
| 128 | interrupt-parent = <&mpic>; |
| 129 | reg = <0x0 0x1000>; |
| 130 | }; |
| 131 | dcsr-npc { |
| 132 | compatible = "fsl,dcsr-npc"; |
| 133 | reg = <0x1000 0x1000 0x1000000 0x8000>; |
| 134 | }; |
| 135 | dcsr-nxc@2000 { |
| 136 | compatible = "fsl,dcsr-nxc"; |
| 137 | reg = <0x2000 0x1000>; |
| 138 | }; |
| 139 | dcsr-corenet { |
| 140 | compatible = "fsl,dcsr-corenet"; |
| 141 | reg = <0x8000 0x1000 0xB0000 0x1000>; |
| 142 | }; |
| 143 | dcsr-dpaa@9000 { |
| 144 | compatible = "fsl,p43041-dcsr-dpaa", "fsl,dcsr-dpaa"; |
| 145 | reg = <0x9000 0x1000>; |
| 146 | }; |
| 147 | dcsr-ocn@11000 { |
| 148 | compatible = "fsl,p43041-dcsr-ocn", "fsl,dcsr-ocn"; |
| 149 | reg = <0x11000 0x1000>; |
| 150 | }; |
| 151 | dcsr-ddr@12000 { |
| 152 | compatible = "fsl,dcsr-ddr"; |
| 153 | dev-handle = <&ddr>; |
| 154 | reg = <0x12000 0x1000>; |
| 155 | }; |
| 156 | dcsr-nal@18000 { |
| 157 | compatible = "fsl,p43041-dcsr-nal", "fsl,dcsr-nal"; |
| 158 | reg = <0x18000 0x1000>; |
| 159 | }; |
| 160 | dcsr-rcpm@22000 { |
| 161 | compatible = "fsl,p43041-dcsr-rcpm", "fsl,dcsr-rcpm"; |
| 162 | reg = <0x22000 0x1000>; |
| 163 | }; |
| 164 | dcsr-cpu-sb-proxy@40000 { |
| 165 | compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| 166 | cpu-handle = <&cpu0>; |
| 167 | reg = <0x40000 0x1000>; |
| 168 | }; |
| 169 | dcsr-cpu-sb-proxy@41000 { |
| 170 | compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| 171 | cpu-handle = <&cpu1>; |
| 172 | reg = <0x41000 0x1000>; |
| 173 | }; |
| 174 | dcsr-cpu-sb-proxy@42000 { |
| 175 | compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| 176 | cpu-handle = <&cpu2>; |
| 177 | reg = <0x42000 0x1000>; |
| 178 | }; |
| 179 | dcsr-cpu-sb-proxy@43000 { |
| 180 | compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| 181 | cpu-handle = <&cpu3>; |
| 182 | reg = <0x43000 0x1000>; |
| 183 | }; |
| 184 | }; |
| 185 | |
Kumar Gala | e5aae72 | 2011-06-27 07:53:24 -0500 | [diff] [blame] | 186 | soc: soc@ffe000000 { |
| 187 | #address-cells = <1>; |
| 188 | #size-cells = <1>; |
| 189 | device_type = "soc"; |
| 190 | compatible = "simple-bus"; |
| 191 | ranges = <0x00000000 0xf 0xfe000000 0x1000000>; |
| 192 | reg = <0xf 0xfe000000 0 0x00001000>; |
| 193 | |
| 194 | soc-sram-error { |
| 195 | compatible = "fsl,soc-sram-error"; |
| 196 | interrupts = <16 2 1 29>; |
| 197 | }; |
| 198 | |
| 199 | corenet-law@0 { |
| 200 | compatible = "fsl,corenet-law"; |
| 201 | reg = <0x0 0x1000>; |
| 202 | fsl,num-laws = <32>; |
| 203 | }; |
| 204 | |
Stephen George | b9df022 | 2011-09-16 10:36:34 -0500 | [diff] [blame] | 205 | ddr: memory-controller@8000 { |
Kumar Gala | e5aae72 | 2011-06-27 07:53:24 -0500 | [diff] [blame] | 206 | compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; |
| 207 | reg = <0x8000 0x1000>; |
| 208 | interrupts = <16 2 1 23>; |
| 209 | }; |
| 210 | |
| 211 | cpc: l3-cache-controller@10000 { |
| 212 | compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; |
| 213 | reg = <0x10000 0x1000>; |
| 214 | interrupts = <16 2 1 27>; |
| 215 | }; |
| 216 | |
| 217 | corenet-cf@18000 { |
| 218 | compatible = "fsl,corenet-cf"; |
| 219 | reg = <0x18000 0x1000>; |
| 220 | interrupts = <16 2 1 31>; |
| 221 | fsl,ccf-num-csdids = <32>; |
| 222 | fsl,ccf-num-snoopids = <32>; |
| 223 | }; |
| 224 | |
| 225 | iommu@20000 { |
| 226 | compatible = "fsl,pamu-v1.0", "fsl,pamu"; |
| 227 | reg = <0x20000 0x4000>; |
| 228 | interrupts = < |
| 229 | 24 2 0 0 |
| 230 | 16 2 1 30>; |
| 231 | }; |
| 232 | |
| 233 | mpic: pic@40000 { |
| 234 | clock-frequency = <0>; |
| 235 | interrupt-controller; |
| 236 | #address-cells = <0>; |
| 237 | #interrupt-cells = <4>; |
| 238 | reg = <0x40000 0x40000>; |
| 239 | compatible = "fsl,mpic", "chrp,open-pic"; |
| 240 | device_type = "open-pic"; |
| 241 | }; |
| 242 | |
| 243 | msi0: msi@41600 { |
| 244 | compatible = "fsl,mpic-msi"; |
| 245 | reg = <0x41600 0x200>; |
| 246 | msi-available-ranges = <0 0x100>; |
| 247 | interrupts = < |
| 248 | 0xe0 0 0 0 |
| 249 | 0xe1 0 0 0 |
| 250 | 0xe2 0 0 0 |
| 251 | 0xe3 0 0 0 |
| 252 | 0xe4 0 0 0 |
| 253 | 0xe5 0 0 0 |
| 254 | 0xe6 0 0 0 |
| 255 | 0xe7 0 0 0>; |
| 256 | }; |
| 257 | |
| 258 | msi1: msi@41800 { |
| 259 | compatible = "fsl,mpic-msi"; |
| 260 | reg = <0x41800 0x200>; |
| 261 | msi-available-ranges = <0 0x100>; |
| 262 | interrupts = < |
| 263 | 0xe8 0 0 0 |
| 264 | 0xe9 0 0 0 |
| 265 | 0xea 0 0 0 |
| 266 | 0xeb 0 0 0 |
| 267 | 0xec 0 0 0 |
| 268 | 0xed 0 0 0 |
| 269 | 0xee 0 0 0 |
| 270 | 0xef 0 0 0>; |
| 271 | }; |
| 272 | |
| 273 | msi2: msi@41a00 { |
| 274 | compatible = "fsl,mpic-msi"; |
| 275 | reg = <0x41a00 0x200>; |
| 276 | msi-available-ranges = <0 0x100>; |
| 277 | interrupts = < |
| 278 | 0xf0 0 0 0 |
| 279 | 0xf1 0 0 0 |
| 280 | 0xf2 0 0 0 |
| 281 | 0xf3 0 0 0 |
| 282 | 0xf4 0 0 0 |
| 283 | 0xf5 0 0 0 |
| 284 | 0xf6 0 0 0 |
| 285 | 0xf7 0 0 0>; |
| 286 | }; |
| 287 | |
| 288 | guts: global-utilities@e0000 { |
| 289 | compatible = "fsl,qoriq-device-config-1.0"; |
| 290 | reg = <0xe0000 0xe00>; |
| 291 | fsl,has-rstcr; |
| 292 | #sleep-cells = <1>; |
| 293 | fsl,liodn-bits = <12>; |
| 294 | }; |
| 295 | |
| 296 | pins: global-utilities@e0e00 { |
| 297 | compatible = "fsl,qoriq-pin-control-1.0"; |
| 298 | reg = <0xe0e00 0x200>; |
| 299 | #sleep-cells = <2>; |
| 300 | }; |
| 301 | |
| 302 | clockgen: global-utilities@e1000 { |
| 303 | compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; |
| 304 | reg = <0xe1000 0x1000>; |
| 305 | clock-frequency = <0>; |
| 306 | }; |
| 307 | |
| 308 | rcpm: global-utilities@e2000 { |
| 309 | compatible = "fsl,qoriq-rcpm-1.0"; |
| 310 | reg = <0xe2000 0x1000>; |
| 311 | #sleep-cells = <1>; |
| 312 | }; |
| 313 | |
| 314 | sfp: sfp@e8000 { |
| 315 | compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0"; |
| 316 | reg = <0xe8000 0x1000>; |
| 317 | }; |
| 318 | |
| 319 | serdes: serdes@ea000 { |
| 320 | compatible = "fsl,p3041-serdes"; |
| 321 | reg = <0xea000 0x1000>; |
| 322 | }; |
| 323 | |
| 324 | dma0: dma@100300 { |
| 325 | #address-cells = <1>; |
| 326 | #size-cells = <1>; |
| 327 | compatible = "fsl,p3041-dma", "fsl,eloplus-dma"; |
| 328 | reg = <0x100300 0x4>; |
| 329 | ranges = <0x0 0x100100 0x200>; |
| 330 | cell-index = <0>; |
| 331 | dma-channel@0 { |
| 332 | compatible = "fsl,p3041-dma-channel", |
| 333 | "fsl,eloplus-dma-channel"; |
| 334 | reg = <0x0 0x80>; |
| 335 | cell-index = <0>; |
| 336 | interrupts = <28 2 0 0>; |
| 337 | }; |
| 338 | dma-channel@80 { |
| 339 | compatible = "fsl,p3041-dma-channel", |
| 340 | "fsl,eloplus-dma-channel"; |
| 341 | reg = <0x80 0x80>; |
| 342 | cell-index = <1>; |
| 343 | interrupts = <29 2 0 0>; |
| 344 | }; |
| 345 | dma-channel@100 { |
| 346 | compatible = "fsl,p3041-dma-channel", |
| 347 | "fsl,eloplus-dma-channel"; |
| 348 | reg = <0x100 0x80>; |
| 349 | cell-index = <2>; |
| 350 | interrupts = <30 2 0 0>; |
| 351 | }; |
| 352 | dma-channel@180 { |
| 353 | compatible = "fsl,p3041-dma-channel", |
| 354 | "fsl,eloplus-dma-channel"; |
| 355 | reg = <0x180 0x80>; |
| 356 | cell-index = <3>; |
| 357 | interrupts = <31 2 0 0>; |
| 358 | }; |
| 359 | }; |
| 360 | |
| 361 | dma1: dma@101300 { |
| 362 | #address-cells = <1>; |
| 363 | #size-cells = <1>; |
| 364 | compatible = "fsl,p3041-dma", "fsl,eloplus-dma"; |
| 365 | reg = <0x101300 0x4>; |
| 366 | ranges = <0x0 0x101100 0x200>; |
| 367 | cell-index = <1>; |
| 368 | dma-channel@0 { |
| 369 | compatible = "fsl,p3041-dma-channel", |
| 370 | "fsl,eloplus-dma-channel"; |
| 371 | reg = <0x0 0x80>; |
| 372 | cell-index = <0>; |
| 373 | interrupts = <32 2 0 0>; |
| 374 | }; |
| 375 | dma-channel@80 { |
| 376 | compatible = "fsl,p3041-dma-channel", |
| 377 | "fsl,eloplus-dma-channel"; |
| 378 | reg = <0x80 0x80>; |
| 379 | cell-index = <1>; |
| 380 | interrupts = <33 2 0 0>; |
| 381 | }; |
| 382 | dma-channel@100 { |
| 383 | compatible = "fsl,p3041-dma-channel", |
| 384 | "fsl,eloplus-dma-channel"; |
| 385 | reg = <0x100 0x80>; |
| 386 | cell-index = <2>; |
| 387 | interrupts = <34 2 0 0>; |
| 388 | }; |
| 389 | dma-channel@180 { |
| 390 | compatible = "fsl,p3041-dma-channel", |
| 391 | "fsl,eloplus-dma-channel"; |
| 392 | reg = <0x180 0x80>; |
| 393 | cell-index = <3>; |
| 394 | interrupts = <35 2 0 0>; |
| 395 | }; |
| 396 | }; |
| 397 | |
| 398 | spi@110000 { |
| 399 | #address-cells = <1>; |
| 400 | #size-cells = <0>; |
| 401 | compatible = "fsl,p3041-espi", "fsl,mpc8536-espi"; |
| 402 | reg = <0x110000 0x1000>; |
| 403 | interrupts = <53 0x2 0 0>; |
| 404 | fsl,espi-num-chipselects = <4>; |
| 405 | }; |
| 406 | |
| 407 | sdhc: sdhc@114000 { |
| 408 | compatible = "fsl,p3041-esdhc", "fsl,esdhc"; |
| 409 | reg = <0x114000 0x1000>; |
| 410 | interrupts = <48 2 0 0>; |
| 411 | sdhci,auto-cmd12; |
| 412 | clock-frequency = <0>; |
| 413 | }; |
| 414 | |
| 415 | i2c@118000 { |
| 416 | #address-cells = <1>; |
| 417 | #size-cells = <0>; |
| 418 | cell-index = <0>; |
| 419 | compatible = "fsl-i2c"; |
| 420 | reg = <0x118000 0x100>; |
| 421 | interrupts = <38 2 0 0>; |
| 422 | dfsrr; |
| 423 | }; |
| 424 | |
| 425 | i2c@118100 { |
| 426 | #address-cells = <1>; |
| 427 | #size-cells = <0>; |
| 428 | cell-index = <1>; |
| 429 | compatible = "fsl-i2c"; |
| 430 | reg = <0x118100 0x100>; |
| 431 | interrupts = <38 2 0 0>; |
| 432 | dfsrr; |
| 433 | }; |
| 434 | |
| 435 | i2c@119000 { |
| 436 | #address-cells = <1>; |
| 437 | #size-cells = <0>; |
| 438 | cell-index = <2>; |
| 439 | compatible = "fsl-i2c"; |
| 440 | reg = <0x119000 0x100>; |
| 441 | interrupts = <39 2 0 0>; |
| 442 | dfsrr; |
| 443 | }; |
| 444 | |
| 445 | i2c@119100 { |
| 446 | #address-cells = <1>; |
| 447 | #size-cells = <0>; |
| 448 | cell-index = <3>; |
| 449 | compatible = "fsl-i2c"; |
| 450 | reg = <0x119100 0x100>; |
| 451 | interrupts = <39 2 0 0>; |
| 452 | dfsrr; |
| 453 | }; |
| 454 | |
| 455 | serial0: serial@11c500 { |
| 456 | cell-index = <0>; |
| 457 | device_type = "serial"; |
| 458 | compatible = "ns16550"; |
| 459 | reg = <0x11c500 0x100>; |
| 460 | clock-frequency = <0>; |
| 461 | interrupts = <36 2 0 0>; |
| 462 | }; |
| 463 | |
| 464 | serial1: serial@11c600 { |
| 465 | cell-index = <1>; |
| 466 | device_type = "serial"; |
| 467 | compatible = "ns16550"; |
| 468 | reg = <0x11c600 0x100>; |
| 469 | clock-frequency = <0>; |
| 470 | interrupts = <36 2 0 0>; |
| 471 | }; |
| 472 | |
| 473 | serial2: serial@11d500 { |
| 474 | cell-index = <2>; |
| 475 | device_type = "serial"; |
| 476 | compatible = "ns16550"; |
| 477 | reg = <0x11d500 0x100>; |
| 478 | clock-frequency = <0>; |
| 479 | interrupts = <37 2 0 0>; |
| 480 | }; |
| 481 | |
| 482 | serial3: serial@11d600 { |
| 483 | cell-index = <3>; |
| 484 | device_type = "serial"; |
| 485 | compatible = "ns16550"; |
| 486 | reg = <0x11d600 0x100>; |
| 487 | clock-frequency = <0>; |
| 488 | interrupts = <37 2 0 0>; |
| 489 | }; |
| 490 | |
| 491 | gpio0: gpio@130000 { |
| 492 | compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio"; |
| 493 | reg = <0x130000 0x1000>; |
| 494 | interrupts = <55 2 0 0>; |
| 495 | #gpio-cells = <2>; |
| 496 | gpio-controller; |
| 497 | }; |
| 498 | |
| 499 | usb0: usb@210000 { |
| 500 | compatible = "fsl,p3041-usb2-mph", |
| 501 | "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; |
| 502 | reg = <0x210000 0x1000>; |
| 503 | #address-cells = <1>; |
| 504 | #size-cells = <0>; |
| 505 | interrupts = <44 0x2 0 0>; |
| 506 | phy_type = "utmi"; |
| 507 | port0; |
| 508 | }; |
| 509 | |
| 510 | usb1: usb@211000 { |
| 511 | compatible = "fsl,p3041-usb2-dr", |
| 512 | "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; |
| 513 | reg = <0x211000 0x1000>; |
| 514 | #address-cells = <1>; |
| 515 | #size-cells = <0>; |
| 516 | interrupts = <45 0x2 0 0>; |
| 517 | dr_mode = "host"; |
| 518 | phy_type = "utmi"; |
| 519 | }; |
| 520 | |
| 521 | sata@220000 { |
| 522 | compatible = "fsl,p3041-sata", "fsl,pq-sata-v2"; |
| 523 | reg = <0x220000 0x1000>; |
| 524 | interrupts = <68 0x2 0 0>; |
| 525 | }; |
| 526 | |
| 527 | sata@221000 { |
| 528 | compatible = "fsl,p3041-sata", "fsl,pq-sata-v2"; |
| 529 | reg = <0x221000 0x1000>; |
| 530 | interrupts = <69 0x2 0 0>; |
| 531 | }; |
| 532 | |
| 533 | crypto: crypto@300000 { |
| 534 | compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; |
| 535 | #address-cells = <1>; |
| 536 | #size-cells = <1>; |
| 537 | reg = <0x300000 0x10000>; |
| 538 | ranges = <0 0x300000 0x10000>; |
| 539 | interrupts = <92 2 0 0>; |
| 540 | |
| 541 | sec_jr0: jr@1000 { |
| 542 | compatible = "fsl,sec-v4.2-job-ring", |
| 543 | "fsl,sec-v4.0-job-ring"; |
| 544 | reg = <0x1000 0x1000>; |
| 545 | interrupts = <88 2 0 0>; |
| 546 | }; |
| 547 | |
| 548 | sec_jr1: jr@2000 { |
| 549 | compatible = "fsl,sec-v4.2-job-ring", |
| 550 | "fsl,sec-v4.0-job-ring"; |
| 551 | reg = <0x2000 0x1000>; |
| 552 | interrupts = <89 2 0 0>; |
| 553 | }; |
| 554 | |
| 555 | sec_jr2: jr@3000 { |
| 556 | compatible = "fsl,sec-v4.2-job-ring", |
| 557 | "fsl,sec-v4.0-job-ring"; |
| 558 | reg = <0x3000 0x1000>; |
| 559 | interrupts = <90 2 0 0>; |
| 560 | }; |
| 561 | |
| 562 | sec_jr3: jr@4000 { |
| 563 | compatible = "fsl,sec-v4.2-job-ring", |
| 564 | "fsl,sec-v4.0-job-ring"; |
| 565 | reg = <0x4000 0x1000>; |
| 566 | interrupts = <91 2 0 0>; |
| 567 | }; |
| 568 | |
| 569 | rtic@6000 { |
| 570 | compatible = "fsl,sec-v4.2-rtic", |
| 571 | "fsl,sec-v4.0-rtic"; |
| 572 | #address-cells = <1>; |
| 573 | #size-cells = <1>; |
| 574 | reg = <0x6000 0x100>; |
| 575 | ranges = <0x0 0x6100 0xe00>; |
| 576 | |
| 577 | rtic_a: rtic-a@0 { |
| 578 | compatible = "fsl,sec-v4.2-rtic-memory", |
| 579 | "fsl,sec-v4.0-rtic-memory"; |
| 580 | reg = <0x00 0x20 0x100 0x80>; |
| 581 | }; |
| 582 | |
| 583 | rtic_b: rtic-b@20 { |
| 584 | compatible = "fsl,sec-v4.2-rtic-memory", |
| 585 | "fsl,sec-v4.0-rtic-memory"; |
| 586 | reg = <0x20 0x20 0x200 0x80>; |
| 587 | }; |
| 588 | |
| 589 | rtic_c: rtic-c@40 { |
| 590 | compatible = "fsl,sec-v4.2-rtic-memory", |
| 591 | "fsl,sec-v4.0-rtic-memory"; |
| 592 | reg = <0x40 0x20 0x300 0x80>; |
| 593 | }; |
| 594 | |
| 595 | rtic_d: rtic-d@60 { |
| 596 | compatible = "fsl,sec-v4.2-rtic-memory", |
| 597 | "fsl,sec-v4.0-rtic-memory"; |
| 598 | reg = <0x60 0x20 0x500 0x80>; |
| 599 | }; |
| 600 | }; |
| 601 | }; |
| 602 | |
| 603 | sec_mon: sec_mon@314000 { |
| 604 | compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon"; |
| 605 | reg = <0x314000 0x1000>; |
| 606 | interrupts = <93 2 0 0>; |
| 607 | }; |
| 608 | }; |
| 609 | |
| 610 | /* |
| 611 | rapidio0: rapidio@ffe0c0000 |
| 612 | */ |
| 613 | |
| 614 | localbus@ffe124000 { |
| 615 | compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus"; |
| 616 | interrupts = <25 2 0 0>; |
| 617 | #address-cells = <2>; |
| 618 | #size-cells = <1>; |
| 619 | }; |
| 620 | |
| 621 | pci0: pcie@ffe200000 { |
| 622 | compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; |
| 623 | device_type = "pci"; |
| 624 | #size-cells = <2>; |
| 625 | #address-cells = <3>; |
| 626 | bus-range = <0x0 0xff>; |
| 627 | clock-frequency = <0x1fca055>; |
| 628 | fsl,msi = <&msi0>; |
| 629 | interrupts = <16 2 1 15>; |
| 630 | |
| 631 | pcie@0 { |
| 632 | reg = <0 0 0 0 0>; |
| 633 | #interrupt-cells = <1>; |
| 634 | #size-cells = <2>; |
| 635 | #address-cells = <3>; |
| 636 | device_type = "pci"; |
| 637 | interrupts = <16 2 1 15>; |
| 638 | interrupt-map-mask = <0xf800 0 0 7>; |
| 639 | interrupt-map = < |
| 640 | /* IDSEL 0x0 */ |
| 641 | 0000 0 0 1 &mpic 40 1 0 0 |
| 642 | 0000 0 0 2 &mpic 1 1 0 0 |
| 643 | 0000 0 0 3 &mpic 2 1 0 0 |
| 644 | 0000 0 0 4 &mpic 3 1 0 0 |
| 645 | >; |
| 646 | }; |
| 647 | }; |
| 648 | |
| 649 | pci1: pcie@ffe201000 { |
| 650 | compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; |
| 651 | device_type = "pci"; |
| 652 | #size-cells = <2>; |
| 653 | #address-cells = <3>; |
| 654 | bus-range = <0 0xff>; |
| 655 | clock-frequency = <0x1fca055>; |
| 656 | fsl,msi = <&msi1>; |
| 657 | interrupts = <16 2 1 14>; |
| 658 | pcie@0 { |
| 659 | reg = <0 0 0 0 0>; |
| 660 | #interrupt-cells = <1>; |
| 661 | #size-cells = <2>; |
| 662 | #address-cells = <3>; |
| 663 | device_type = "pci"; |
| 664 | interrupts = <16 2 1 14>; |
| 665 | interrupt-map-mask = <0xf800 0 0 7>; |
| 666 | interrupt-map = < |
| 667 | /* IDSEL 0x0 */ |
| 668 | 0000 0 0 1 &mpic 41 1 0 0 |
| 669 | 0000 0 0 2 &mpic 5 1 0 0 |
| 670 | 0000 0 0 3 &mpic 6 1 0 0 |
| 671 | 0000 0 0 4 &mpic 7 1 0 0 |
| 672 | >; |
| 673 | }; |
| 674 | }; |
| 675 | |
| 676 | pci2: pcie@ffe202000 { |
| 677 | compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; |
| 678 | device_type = "pci"; |
| 679 | #size-cells = <2>; |
| 680 | #address-cells = <3>; |
| 681 | bus-range = <0x0 0xff>; |
| 682 | clock-frequency = <0x1fca055>; |
| 683 | fsl,msi = <&msi2>; |
| 684 | interrupts = <16 2 1 13>; |
| 685 | pcie@0 { |
| 686 | reg = <0 0 0 0 0>; |
| 687 | #interrupt-cells = <1>; |
| 688 | #size-cells = <2>; |
| 689 | #address-cells = <3>; |
| 690 | device_type = "pci"; |
| 691 | interrupts = <16 2 1 13>; |
| 692 | interrupt-map-mask = <0xf800 0 0 7>; |
| 693 | interrupt-map = < |
| 694 | /* IDSEL 0x0 */ |
| 695 | 0000 0 0 1 &mpic 42 1 0 0 |
| 696 | 0000 0 0 2 &mpic 9 1 0 0 |
| 697 | 0000 0 0 3 &mpic 10 1 0 0 |
| 698 | 0000 0 0 4 &mpic 11 1 0 0 |
| 699 | >; |
| 700 | }; |
| 701 | }; |
| 702 | |
| 703 | pci3: pcie@ffe203000 { |
| 704 | compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; |
| 705 | device_type = "pci"; |
| 706 | #size-cells = <2>; |
| 707 | #address-cells = <3>; |
| 708 | bus-range = <0x0 0xff>; |
| 709 | clock-frequency = <0x1fca055>; |
| 710 | fsl,msi = <&msi2>; |
| 711 | interrupts = <16 2 1 12>; |
| 712 | pcie@0 { |
| 713 | reg = <0 0 0 0 0>; |
| 714 | #interrupt-cells = <1>; |
| 715 | #size-cells = <2>; |
| 716 | #address-cells = <3>; |
| 717 | device_type = "pci"; |
| 718 | interrupts = <16 2 1 12>; |
| 719 | interrupt-map-mask = <0xf800 0 0 7>; |
| 720 | interrupt-map = < |
| 721 | /* IDSEL 0x0 */ |
| 722 | 0000 0 0 1 &mpic 43 1 0 0 |
| 723 | 0000 0 0 2 &mpic 0 1 0 0 |
| 724 | 0000 0 0 3 &mpic 4 1 0 0 |
| 725 | 0000 0 0 4 &mpic 8 1 0 0 |
| 726 | >; |
| 727 | }; |
| 728 | }; |
| 729 | }; |