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Paul Walmsley69d88a02008-03-18 10:02:50 +02001#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
2#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
3
4/*
5 * OMAP2/3 PRCM base and module definitions
6 *
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17
18/* Module offsets from both CM_BASE & PRM_BASE */
19
20/*
21 * Offsets that are the same on 24xx and 34xx
22 *
23 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
24 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
25 */
26#define OCP_MOD 0x000
27#define MPU_MOD 0x100
28#define CORE_MOD 0x200
29#define GFX_MOD 0x300
30#define WKUP_MOD 0x400
31#define PLL_MOD 0x500
32
33
34/* Chip-specific module offsets */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +030035#define OMAP24XX_GR_MOD OCP_MOD
Paul Walmsley69d88a02008-03-18 10:02:50 +020036#define OMAP24XX_DSP_MOD 0x800
37
38#define OMAP2430_MDM_MOD 0xc00
39
40/* IVA2 module is < base on 3430 */
41#define OMAP3430_IVA2_MOD -0x800
42#define OMAP3430ES2_SGX_MOD GFX_MOD
43#define OMAP3430_CCR_MOD PLL_MOD
44#define OMAP3430_DSS_MOD 0x600
45#define OMAP3430_CAM_MOD 0x700
46#define OMAP3430_PER_MOD 0x800
47#define OMAP3430_EMU_MOD 0x900
48#define OMAP3430_GR_MOD 0xa00
49#define OMAP3430_NEON_MOD 0xb00
50#define OMAP3430ES2_USBHOST_MOD 0xc00
51
52
53/* 24XX register bits shared between CM & PRM registers */
54
55/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
56#define OMAP2420_EN_MMC_SHIFT 26
57#define OMAP2420_EN_MMC (1 << 26)
58#define OMAP24XX_EN_UART2_SHIFT 22
59#define OMAP24XX_EN_UART2 (1 << 22)
60#define OMAP24XX_EN_UART1_SHIFT 21
61#define OMAP24XX_EN_UART1 (1 << 21)
62#define OMAP24XX_EN_MCSPI2_SHIFT 18
63#define OMAP24XX_EN_MCSPI2 (1 << 18)
64#define OMAP24XX_EN_MCSPI1_SHIFT 17
65#define OMAP24XX_EN_MCSPI1 (1 << 17)
66#define OMAP24XX_EN_MCBSP2_SHIFT 16
67#define OMAP24XX_EN_MCBSP2 (1 << 16)
68#define OMAP24XX_EN_MCBSP1_SHIFT 15
69#define OMAP24XX_EN_MCBSP1 (1 << 15)
70#define OMAP24XX_EN_GPT12_SHIFT 14
71#define OMAP24XX_EN_GPT12 (1 << 14)
72#define OMAP24XX_EN_GPT11_SHIFT 13
73#define OMAP24XX_EN_GPT11 (1 << 13)
74#define OMAP24XX_EN_GPT10_SHIFT 12
75#define OMAP24XX_EN_GPT10 (1 << 12)
76#define OMAP24XX_EN_GPT9_SHIFT 11
77#define OMAP24XX_EN_GPT9 (1 << 11)
78#define OMAP24XX_EN_GPT8_SHIFT 10
79#define OMAP24XX_EN_GPT8 (1 << 10)
80#define OMAP24XX_EN_GPT7_SHIFT 9
81#define OMAP24XX_EN_GPT7 (1 << 9)
82#define OMAP24XX_EN_GPT6_SHIFT 8
83#define OMAP24XX_EN_GPT6 (1 << 8)
84#define OMAP24XX_EN_GPT5_SHIFT 7
85#define OMAP24XX_EN_GPT5 (1 << 7)
86#define OMAP24XX_EN_GPT4_SHIFT 6
87#define OMAP24XX_EN_GPT4 (1 << 6)
88#define OMAP24XX_EN_GPT3_SHIFT 5
89#define OMAP24XX_EN_GPT3 (1 << 5)
90#define OMAP24XX_EN_GPT2_SHIFT 4
91#define OMAP24XX_EN_GPT2 (1 << 4)
92#define OMAP2420_EN_VLYNQ_SHIFT 3
93#define OMAP2420_EN_VLYNQ (1 << 3)
94
95/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
96#define OMAP2430_EN_GPIO5_SHIFT 10
97#define OMAP2430_EN_GPIO5 (1 << 10)
98#define OMAP2430_EN_MCSPI3_SHIFT 9
99#define OMAP2430_EN_MCSPI3 (1 << 9)
100#define OMAP2430_EN_MMCHS2_SHIFT 8
101#define OMAP2430_EN_MMCHS2 (1 << 8)
102#define OMAP2430_EN_MMCHS1_SHIFT 7
103#define OMAP2430_EN_MMCHS1 (1 << 7)
104#define OMAP24XX_EN_UART3_SHIFT 2
105#define OMAP24XX_EN_UART3 (1 << 2)
106#define OMAP24XX_EN_USB_SHIFT 0
107#define OMAP24XX_EN_USB (1 << 0)
108
109/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
110#define OMAP2430_EN_MDM_INTC_SHIFT 11
111#define OMAP2430_EN_MDM_INTC (1 << 11)
112#define OMAP2430_EN_USBHS_SHIFT 6
113#define OMAP2430_EN_USBHS (1 << 6)
114
115/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700116#define OMAP2420_ST_MMC_SHIFT 26
117#define OMAP2420_ST_MMC_MASK (1 << 26)
118#define OMAP24XX_ST_UART2_SHIFT 22
119#define OMAP24XX_ST_UART2_MASK (1 << 22)
120#define OMAP24XX_ST_UART1_SHIFT 21
121#define OMAP24XX_ST_UART1_MASK (1 << 21)
122#define OMAP24XX_ST_MCSPI2_SHIFT 18
123#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
124#define OMAP24XX_ST_MCSPI1_SHIFT 17
125#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
126#define OMAP24XX_ST_GPT12_SHIFT 14
127#define OMAP24XX_ST_GPT12_MASK (1 << 14)
128#define OMAP24XX_ST_GPT11_SHIFT 13
129#define OMAP24XX_ST_GPT11_MASK (1 << 13)
130#define OMAP24XX_ST_GPT10_SHIFT 12
131#define OMAP24XX_ST_GPT10_MASK (1 << 12)
132#define OMAP24XX_ST_GPT9_SHIFT 11
133#define OMAP24XX_ST_GPT9_MASK (1 << 11)
134#define OMAP24XX_ST_GPT8_SHIFT 10
135#define OMAP24XX_ST_GPT8_MASK (1 << 10)
136#define OMAP24XX_ST_GPT7_SHIFT 9
137#define OMAP24XX_ST_GPT7_MASK (1 << 9)
138#define OMAP24XX_ST_GPT6_SHIFT 8
139#define OMAP24XX_ST_GPT6_MASK (1 << 8)
140#define OMAP24XX_ST_GPT5_SHIFT 7
141#define OMAP24XX_ST_GPT5_MASK (1 << 7)
142#define OMAP24XX_ST_GPT4_SHIFT 6
143#define OMAP24XX_ST_GPT4_MASK (1 << 6)
144#define OMAP24XX_ST_GPT3_SHIFT 5
145#define OMAP24XX_ST_GPT3_MASK (1 << 5)
146#define OMAP24XX_ST_GPT2_SHIFT 4
147#define OMAP24XX_ST_GPT2_MASK (1 << 4)
148#define OMAP2420_ST_VLYNQ_SHIFT 3
149#define OMAP2420_ST_VLYNQ_MASK (1 << 3)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200150
151/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700152#define OMAP2430_ST_MDM_INTC_SHIFT 11
153#define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
154#define OMAP2430_ST_GPIO5_SHIFT 10
155#define OMAP2430_ST_GPIO5_MASK (1 << 10)
156#define OMAP2430_ST_MCSPI3_SHIFT 9
157#define OMAP2430_ST_MCSPI3_MASK (1 << 9)
158#define OMAP2430_ST_MMCHS2_SHIFT 8
159#define OMAP2430_ST_MMCHS2_MASK (1 << 8)
160#define OMAP2430_ST_MMCHS1_SHIFT 7
161#define OMAP2430_ST_MMCHS1_MASK (1 << 7)
162#define OMAP2430_ST_USBHS_SHIFT 6
163#define OMAP2430_ST_USBHS_MASK (1 << 6)
164#define OMAP24XX_ST_UART3_SHIFT 2
165#define OMAP24XX_ST_UART3_MASK (1 << 2)
166#define OMAP24XX_ST_USB_SHIFT 0
167#define OMAP24XX_ST_USB_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200168
169/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
170#define OMAP24XX_EN_GPIOS_SHIFT 2
171#define OMAP24XX_EN_GPIOS (1 << 2)
172#define OMAP24XX_EN_GPT1_SHIFT 0
173#define OMAP24XX_EN_GPT1 (1 << 0)
174
175/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700176#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
177#define OMAP24XX_ST_GPIOS_MASK 2
178#define OMAP24XX_ST_GPT1_SHIFT (1 << 0)
179#define OMAP24XX_ST_GPT1_MASK 0
Paul Walmsley69d88a02008-03-18 10:02:50 +0200180
181/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700182#define OMAP2430_ST_MDM_SHIFT (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200183
184
185/* 3430 register bits shared between CM & PRM registers */
186
187/* CM_REVISION, PRM_REVISION shared bits */
188#define OMAP3430_REV_SHIFT 0
189#define OMAP3430_REV_MASK (0xff << 0)
190
191/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
192#define OMAP3430_AUTOIDLE (1 << 0)
193
194/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
195#define OMAP3430_EN_MMC2 (1 << 25)
196#define OMAP3430_EN_MMC2_SHIFT 25
197#define OMAP3430_EN_MMC1 (1 << 24)
198#define OMAP3430_EN_MMC1_SHIFT 24
199#define OMAP3430_EN_MCSPI4 (1 << 21)
200#define OMAP3430_EN_MCSPI4_SHIFT 21
201#define OMAP3430_EN_MCSPI3 (1 << 20)
202#define OMAP3430_EN_MCSPI3_SHIFT 20
203#define OMAP3430_EN_MCSPI2 (1 << 19)
204#define OMAP3430_EN_MCSPI2_SHIFT 19
205#define OMAP3430_EN_MCSPI1 (1 << 18)
206#define OMAP3430_EN_MCSPI1_SHIFT 18
207#define OMAP3430_EN_I2C3 (1 << 17)
208#define OMAP3430_EN_I2C3_SHIFT 17
209#define OMAP3430_EN_I2C2 (1 << 16)
210#define OMAP3430_EN_I2C2_SHIFT 16
211#define OMAP3430_EN_I2C1 (1 << 15)
212#define OMAP3430_EN_I2C1_SHIFT 15
213#define OMAP3430_EN_UART2 (1 << 14)
214#define OMAP3430_EN_UART2_SHIFT 14
215#define OMAP3430_EN_UART1 (1 << 13)
216#define OMAP3430_EN_UART1_SHIFT 13
217#define OMAP3430_EN_GPT11 (1 << 12)
218#define OMAP3430_EN_GPT11_SHIFT 12
219#define OMAP3430_EN_GPT10 (1 << 11)
220#define OMAP3430_EN_GPT10_SHIFT 11
221#define OMAP3430_EN_MCBSP5 (1 << 10)
222#define OMAP3430_EN_MCBSP5_SHIFT 10
223#define OMAP3430_EN_MCBSP1 (1 << 9)
224#define OMAP3430_EN_MCBSP1_SHIFT 9
225#define OMAP3430_EN_FSHOSTUSB (1 << 5)
226#define OMAP3430_EN_FSHOSTUSB_SHIFT 5
227#define OMAP3430_EN_D2D (1 << 3)
228#define OMAP3430_EN_D2D_SHIFT 3
229
230/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
231#define OMAP3430_EN_HSOTGUSB (1 << 4)
232#define OMAP3430_EN_HSOTGUSB_SHIFT 4
233
234/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700235#define OMAP3430_ST_MMC2_SHIFT 25
236#define OMAP3430_ST_MMC2_MASK (1 << 25)
237#define OMAP3430_ST_MMC1_SHIFT 24
238#define OMAP3430_ST_MMC1_MASK (1 << 24)
239#define OMAP3430_ST_MCSPI4_SHIFT 21
240#define OMAP3430_ST_MCSPI4_MASK (1 << 21)
241#define OMAP3430_ST_MCSPI3_SHIFT 20
242#define OMAP3430_ST_MCSPI3_MASK (1 << 20)
243#define OMAP3430_ST_MCSPI2_SHIFT 19
244#define OMAP3430_ST_MCSPI2_MASK (1 << 19)
245#define OMAP3430_ST_MCSPI1_SHIFT 18
246#define OMAP3430_ST_MCSPI1_MASK (1 << 18)
247#define OMAP3430_ST_I2C3_SHIFT 17
248#define OMAP3430_ST_I2C3_MASK (1 << 17)
249#define OMAP3430_ST_I2C2_SHIFT 16
250#define OMAP3430_ST_I2C2_MASK (1 << 16)
251#define OMAP3430_ST_I2C1_SHIFT 15
252#define OMAP3430_ST_I2C1_MASK (1 << 15)
253#define OMAP3430_ST_UART2_SHIFT 14
254#define OMAP3430_ST_UART2_MASK (1 << 14)
255#define OMAP3430_ST_UART1_SHIFT 13
256#define OMAP3430_ST_UART1_MASK (1 << 13)
257#define OMAP3430_ST_GPT11_SHIFT 12
258#define OMAP3430_ST_GPT11_MASK (1 << 12)
259#define OMAP3430_ST_GPT10_SHIFT 11
260#define OMAP3430_ST_GPT10_MASK (1 << 11)
261#define OMAP3430_ST_MCBSP5_SHIFT 10
262#define OMAP3430_ST_MCBSP5_MASK (1 << 10)
263#define OMAP3430_ST_MCBSP1_SHIFT 9
264#define OMAP3430_ST_MCBSP1_MASK (1 << 9)
265#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5
266#define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5)
267#define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4
268#define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4)
269#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
270#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5)
271#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4
272#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4)
273#define OMAP3430_ST_D2D_SHIFT 3
274#define OMAP3430_ST_D2D_MASK (1 << 3)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200275
276/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
277#define OMAP3430_EN_GPIO1 (1 << 3)
278#define OMAP3430_EN_GPIO1_SHIFT 3
Kevin Hilman8bd22942009-05-28 10:56:16 -0700279#define OMAP3430_EN_GPT12 (1 << 1)
280#define OMAP3430_EN_GPT12_SHIFT 1
Paul Walmsley69d88a02008-03-18 10:02:50 +0200281#define OMAP3430_EN_GPT1 (1 << 0)
282#define OMAP3430_EN_GPT1_SHIFT 0
283
284/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
285#define OMAP3430_EN_SR2 (1 << 7)
286#define OMAP3430_EN_SR2_SHIFT 7
287#define OMAP3430_EN_SR1 (1 << 6)
288#define OMAP3430_EN_SR1_SHIFT 6
289
290/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
291#define OMAP3430_EN_GPT12 (1 << 1)
292#define OMAP3430_EN_GPT12_SHIFT 1
293
294/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700295#define OMAP3430_ST_SR2_SHIFT 7
296#define OMAP3430_ST_SR2_MASK (1 << 7)
297#define OMAP3430_ST_SR1_SHIFT 6
298#define OMAP3430_ST_SR1_MASK (1 << 6)
299#define OMAP3430_ST_GPIO1_SHIFT 3
300#define OMAP3430_ST_GPIO1_MASK (1 << 3)
301#define OMAP3430_ST_GPT12_SHIFT 1
302#define OMAP3430_ST_GPT12_MASK (1 << 1)
303#define OMAP3430_ST_GPT1_SHIFT 0
304#define OMAP3430_ST_GPT1_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200305
306/*
307 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
308 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
309 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
310 */
311#define OMAP3430_EN_MPU (1 << 1)
312#define OMAP3430_EN_MPU_SHIFT 1
313
314/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
315#define OMAP3430_EN_GPIO6 (1 << 17)
316#define OMAP3430_EN_GPIO6_SHIFT 17
317#define OMAP3430_EN_GPIO5 (1 << 16)
318#define OMAP3430_EN_GPIO5_SHIFT 16
319#define OMAP3430_EN_GPIO4 (1 << 15)
320#define OMAP3430_EN_GPIO4_SHIFT 15
321#define OMAP3430_EN_GPIO3 (1 << 14)
322#define OMAP3430_EN_GPIO3_SHIFT 14
323#define OMAP3430_EN_GPIO2 (1 << 13)
324#define OMAP3430_EN_GPIO2_SHIFT 13
325#define OMAP3430_EN_UART3 (1 << 11)
326#define OMAP3430_EN_UART3_SHIFT 11
327#define OMAP3430_EN_GPT9 (1 << 10)
328#define OMAP3430_EN_GPT9_SHIFT 10
329#define OMAP3430_EN_GPT8 (1 << 9)
330#define OMAP3430_EN_GPT8_SHIFT 9
331#define OMAP3430_EN_GPT7 (1 << 8)
332#define OMAP3430_EN_GPT7_SHIFT 8
333#define OMAP3430_EN_GPT6 (1 << 7)
334#define OMAP3430_EN_GPT6_SHIFT 7
335#define OMAP3430_EN_GPT5 (1 << 6)
336#define OMAP3430_EN_GPT5_SHIFT 6
337#define OMAP3430_EN_GPT4 (1 << 5)
338#define OMAP3430_EN_GPT4_SHIFT 5
339#define OMAP3430_EN_GPT3 (1 << 4)
340#define OMAP3430_EN_GPT3_SHIFT 4
341#define OMAP3430_EN_GPT2 (1 << 3)
342#define OMAP3430_EN_GPT2_SHIFT 3
343
344/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
345/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
346 * be ST_* bits instead? */
347#define OMAP3430_EN_MCBSP4 (1 << 2)
348#define OMAP3430_EN_MCBSP4_SHIFT 2
349#define OMAP3430_EN_MCBSP3 (1 << 1)
350#define OMAP3430_EN_MCBSP3_SHIFT 1
351#define OMAP3430_EN_MCBSP2 (1 << 0)
352#define OMAP3430_EN_MCBSP2_SHIFT 0
353
354/* CM_IDLEST_PER, PM_WKST_PER shared bits */
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700355#define OMAP3430_ST_GPIO6_SHIFT 17
356#define OMAP3430_ST_GPIO6_MASK (1 << 17)
357#define OMAP3430_ST_GPIO5_SHIFT 16
358#define OMAP3430_ST_GPIO5_MASK (1 << 16)
359#define OMAP3430_ST_GPIO4_SHIFT 15
360#define OMAP3430_ST_GPIO4_MASK (1 << 15)
361#define OMAP3430_ST_GPIO3_SHIFT 14
362#define OMAP3430_ST_GPIO3_MASK (1 << 14)
363#define OMAP3430_ST_GPIO2_SHIFT 13
364#define OMAP3430_ST_GPIO2_MASK (1 << 13)
365#define OMAP3430_ST_UART3_SHIFT 11
366#define OMAP3430_ST_UART3_MASK (1 << 11)
367#define OMAP3430_ST_GPT9_SHIFT 10
368#define OMAP3430_ST_GPT9_MASK (1 << 10)
369#define OMAP3430_ST_GPT8_SHIFT 9
370#define OMAP3430_ST_GPT8_MASK (1 << 9)
371#define OMAP3430_ST_GPT7_SHIFT 8
372#define OMAP3430_ST_GPT7_MASK (1 << 8)
373#define OMAP3430_ST_GPT6_SHIFT 7
374#define OMAP3430_ST_GPT6_MASK (1 << 7)
375#define OMAP3430_ST_GPT5_SHIFT 6
376#define OMAP3430_ST_GPT5_MASK (1 << 6)
377#define OMAP3430_ST_GPT4_SHIFT 5
378#define OMAP3430_ST_GPT4_MASK (1 << 5)
379#define OMAP3430_ST_GPT3_SHIFT 4
380#define OMAP3430_ST_GPT3_MASK (1 << 4)
381#define OMAP3430_ST_GPT2_SHIFT 3
382#define OMAP3430_ST_GPT2_MASK (1 << 3)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200383
384/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300385#define OMAP3430_EN_CORE_SHIFT 0
386#define OMAP3430_EN_CORE_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200387
388#endif
389