blob: 5e8cbf5b799fe233a0a6f1da9a7d5f17b018a207 [file] [log] [blame]
Joseph Lo0b25e252012-10-31 17:41:15 +08001/*
2 * CPU idle driver for Tegra CPUs
3 *
4 * Copyright (c) 2010-2012, NVIDIA Corporation.
5 * Copyright (c) 2011 Google, Inc.
6 * Author: Colin Cross <ccross@android.com>
7 * Gary King <gking@nvidia.com>
8 *
9 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/cpuidle.h>
Joseph Lod457ef352012-10-31 17:41:17 +080025#include <linux/cpu_pm.h>
26#include <linux/clockchips.h>
Joseph Lo0b25e252012-10-31 17:41:15 +080027
28#include <asm/cpuidle.h>
Joseph Lod457ef352012-10-31 17:41:17 +080029#include <asm/proc-fns.h>
30#include <asm/suspend.h>
31#include <asm/smp_plat.h>
32
33#include "pm.h"
34#include "sleep.h"
Joseph Lod5529202012-10-31 17:41:21 +080035#include "tegra_cpu_car.h"
Joseph Lod457ef352012-10-31 17:41:17 +080036
37#ifdef CONFIG_PM_SLEEP
38static int tegra30_idle_lp2(struct cpuidle_device *dev,
39 struct cpuidle_driver *drv,
40 int index);
41#endif
Joseph Lo0b25e252012-10-31 17:41:15 +080042
43static struct cpuidle_driver tegra_idle_driver = {
44 .name = "tegra_idle",
45 .owner = THIS_MODULE,
46 .en_core_tk_irqen = 1,
Joseph Lod457ef352012-10-31 17:41:17 +080047#ifdef CONFIG_PM_SLEEP
48 .state_count = 2,
49#else
Joseph Lo0b25e252012-10-31 17:41:15 +080050 .state_count = 1,
Joseph Lod457ef352012-10-31 17:41:17 +080051#endif
Joseph Lo0b25e252012-10-31 17:41:15 +080052 .states = {
53 [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
Joseph Lod457ef352012-10-31 17:41:17 +080054#ifdef CONFIG_PM_SLEEP
55 [1] = {
56 .enter = tegra30_idle_lp2,
57 .exit_latency = 2000,
58 .target_residency = 2200,
59 .power_usage = 0,
60 .flags = CPUIDLE_FLAG_TIME_VALID,
61 .name = "powered-down",
62 .desc = "CPU power gated",
63 },
64#endif
Joseph Lo0b25e252012-10-31 17:41:15 +080065 },
66};
67
68static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
69
Joseph Lod457ef352012-10-31 17:41:17 +080070#ifdef CONFIG_PM_SLEEP
Joseph Lod5529202012-10-31 17:41:21 +080071static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
72 struct cpuidle_driver *drv,
73 int index)
74{
75 struct cpuidle_state *state = &drv->states[index];
76 u32 cpu_on_time = state->exit_latency;
77 u32 cpu_off_time = state->target_residency - state->exit_latency;
78
79 /* All CPUs entering LP2 is not working.
80 * Don't let CPU0 enter LP2 when any secondary CPU is online.
81 */
82 if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
83 cpu_do_idle();
84 return false;
85 }
86
87 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
88
89 tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
90
91 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
92
93 return true;
94}
95
Joseph Lod457ef352012-10-31 17:41:17 +080096#ifdef CONFIG_SMP
97static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
98 struct cpuidle_driver *drv,
99 int index)
100{
101 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
102
103 smp_wmb();
104
105 save_cpu_arch_register();
106
107 cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
108
109 restore_cpu_arch_register();
110
111 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
112
113 return true;
114}
115#else
116static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
117 struct cpuidle_driver *drv,
118 int index)
119{
120 return true;
121}
122#endif
123
124static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
125 struct cpuidle_driver *drv,
126 int index)
127{
128 u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
129 bool entered_lp2 = false;
Joseph Lod5529202012-10-31 17:41:21 +0800130 bool last_cpu;
Joseph Lod457ef352012-10-31 17:41:17 +0800131
132 local_fiq_disable();
133
Joseph Lod5529202012-10-31 17:41:21 +0800134 last_cpu = tegra_set_cpu_in_lp2(cpu);
Joseph Lod457ef352012-10-31 17:41:17 +0800135 cpu_pm_enter();
136
Joseph Lod5529202012-10-31 17:41:21 +0800137 if (cpu == 0) {
138 if (last_cpu)
139 entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
140 index);
141 else
142 cpu_do_idle();
143 } else {
Joseph Lod457ef352012-10-31 17:41:17 +0800144 entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
Joseph Lod5529202012-10-31 17:41:21 +0800145 }
Joseph Lod457ef352012-10-31 17:41:17 +0800146
147 cpu_pm_exit();
148 tegra_clear_cpu_in_lp2(cpu);
149
150 local_fiq_enable();
151
152 smp_rmb();
153
154 return (entered_lp2) ? index : 0;
155}
156#endif
157
Joseph Lo0b25e252012-10-31 17:41:15 +0800158int __init tegra30_cpuidle_init(void)
159{
160 int ret;
161 unsigned int cpu;
162 struct cpuidle_device *dev;
163 struct cpuidle_driver *drv = &tegra_idle_driver;
164
Joseph Lod5529202012-10-31 17:41:21 +0800165#ifdef CONFIG_PM_SLEEP
166 tegra_tear_down_cpu = tegra30_tear_down_cpu;
167#endif
168
Joseph Lo0b25e252012-10-31 17:41:15 +0800169 ret = cpuidle_register_driver(&tegra_idle_driver);
170 if (ret) {
171 pr_err("CPUidle driver registration failed\n");
172 return ret;
173 }
174
175 for_each_possible_cpu(cpu) {
176 dev = &per_cpu(tegra_idle_device, cpu);
177 dev->cpu = cpu;
178
179 dev->state_count = drv->state_count;
180 ret = cpuidle_register_device(dev);
181 if (ret) {
182 pr_err("CPU%u: CPUidle device registration failed\n",
183 cpu);
184 return ret;
185 }
186 }
187 return 0;
188}