Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.h |
| 3 | * |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
Paul Walmsley | 530e544 | 2011-02-25 15:39:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2004-2011 Nokia Corporation |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 6 | * |
| 7 | * Contacts: |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
| 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 18 | |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 19 | #include <linux/kernel.h> |
Paul Walmsley | a135eaa | 2012-09-27 10:33:34 -0600 | [diff] [blame] | 20 | #include <linux/list.h> |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 21 | |
Paul Walmsley | e10dd62 | 2012-09-27 10:33:35 -0600 | [diff] [blame] | 22 | #include <linux/clkdev.h> |
| 23 | |
| 24 | struct omap_clk { |
| 25 | u16 cpu; |
| 26 | struct clk_lookup lk; |
| 27 | }; |
| 28 | |
| 29 | #define CLK(dev, con, ck, cp) \ |
| 30 | { \ |
| 31 | .cpu = cp, \ |
| 32 | .lk = { \ |
| 33 | .dev_id = dev, \ |
| 34 | .con_id = con, \ |
| 35 | .clk = ck, \ |
| 36 | }, \ |
| 37 | } |
| 38 | |
| 39 | /* Platform flags for the clkdev-OMAP integration code */ |
| 40 | #define CK_242X (1 << 0) |
| 41 | #define CK_243X (1 << 1) /* 243x, 253x */ |
| 42 | #define CK_3430ES1 (1 << 2) /* 34xxES1 only */ |
| 43 | #define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */ |
| 44 | #define CK_AM35XX (1 << 4) /* Sitara AM35xx */ |
| 45 | #define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */ |
| 46 | #define CK_443X (1 << 6) |
| 47 | #define CK_TI816X (1 << 7) |
| 48 | #define CK_446X (1 << 8) |
| 49 | #define CK_AM33XX (1 << 9) /* AM33xx specific clocks */ |
| 50 | |
| 51 | |
| 52 | #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) |
| 53 | #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) |
| 54 | |
Rajendra Nayak | b5a2366 | 2012-11-10 16:58:40 -0700 | [diff] [blame] | 55 | #ifdef CONFIG_COMMON_CLK |
| 56 | #include <linux/clk-provider.h> |
| 57 | |
| 58 | struct clockdomain; |
| 59 | #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) |
| 60 | |
Paul Walmsley | 8c725dc | 2012-09-16 10:45:54 -0600 | [diff] [blame^] | 61 | #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ |
| 62 | static struct clk _name = { \ |
| 63 | .name = #_name, \ |
| 64 | .hw = &_name##_hw.hw, \ |
| 65 | .parent_names = _parent_array_name, \ |
| 66 | .num_parents = ARRAY_SIZE(_parent_array_name), \ |
| 67 | .ops = &_clkops_name, \ |
| 68 | }; |
| 69 | |
| 70 | #define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ |
| 71 | static struct clk_hw_omap _name##_hw = { \ |
| 72 | .hw = { \ |
| 73 | .clk = &_name, \ |
| 74 | }, \ |
| 75 | .clkdm_name = _clkdm_name, \ |
| 76 | }; |
| 77 | |
| 78 | #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ |
| 79 | _clksel_reg, _clksel_mask, \ |
| 80 | _parent_names, _ops) \ |
| 81 | static struct clk _name; \ |
| 82 | static struct clk_hw_omap _name##_hw = { \ |
| 83 | .hw = { \ |
| 84 | .clk = &_name, \ |
| 85 | }, \ |
| 86 | .clksel = _clksel, \ |
| 87 | .clksel_reg = _clksel_reg, \ |
| 88 | .clksel_mask = _clksel_mask, \ |
| 89 | .clkdm_name = _clkdm_name, \ |
| 90 | }; \ |
| 91 | DEFINE_STRUCT_CLK(_name, _parent_names, _ops); |
| 92 | |
| 93 | #define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \ |
| 94 | _clksel_reg, _clksel_mask, \ |
| 95 | _enable_reg, _enable_bit, \ |
| 96 | _hwops, _parent_names, _ops) \ |
| 97 | static struct clk _name; \ |
| 98 | static struct clk_hw_omap _name##_hw = { \ |
| 99 | .hw = { \ |
| 100 | .clk = &_name, \ |
| 101 | }, \ |
| 102 | .ops = _hwops, \ |
| 103 | .enable_reg = _enable_reg, \ |
| 104 | .enable_bit = _enable_bit, \ |
| 105 | .clksel = _clksel, \ |
| 106 | .clksel_reg = _clksel_reg, \ |
| 107 | .clksel_mask = _clksel_mask, \ |
| 108 | .clkdm_name = _clkdm_name, \ |
| 109 | }; \ |
| 110 | DEFINE_STRUCT_CLK(_name, _parent_names, _ops); |
| 111 | |
| 112 | #define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ |
| 113 | _parent_ptr, _flags, \ |
| 114 | _clksel_reg, _clksel_mask) \ |
| 115 | static const struct clksel _name##_div[] = { \ |
| 116 | { \ |
| 117 | .parent = _parent_ptr, \ |
| 118 | .rates = div31_1to31_rates \ |
| 119 | }, \ |
| 120 | { .parent = NULL }, \ |
| 121 | }; \ |
| 122 | static struct clk _name; \ |
| 123 | static const char *_name##_parent_names[] = { \ |
| 124 | _parent_name, \ |
| 125 | }; \ |
| 126 | static struct clk_hw_omap _name##_hw = { \ |
| 127 | .hw = { \ |
| 128 | .clk = &_name, \ |
| 129 | }, \ |
| 130 | .clksel = _name##_div, \ |
| 131 | .clksel_reg = _clksel_reg, \ |
| 132 | .clksel_mask = _clksel_mask, \ |
| 133 | .ops = &clkhwops_omap4_dpllmx, \ |
| 134 | }; \ |
| 135 | DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); |
| 136 | |
| 137 | |
Rajendra Nayak | b5a2366 | 2012-11-10 16:58:40 -0700 | [diff] [blame] | 138 | #else |
| 139 | |
Paul Walmsley | a135eaa | 2012-09-27 10:33:34 -0600 | [diff] [blame] | 140 | struct module; |
| 141 | struct clk; |
| 142 | struct clockdomain; |
| 143 | |
| 144 | /* Temporary, needed during the common clock framework conversion */ |
| 145 | #define __clk_get_name(clk) (clk->name) |
| 146 | #define __clk_get_parent(clk) (clk->parent) |
| 147 | #define __clk_get_rate(clk) (clk->rate) |
| 148 | |
| 149 | /** |
| 150 | * struct clkops - some clock function pointers |
| 151 | * @enable: fn ptr that enables the current clock in hardware |
| 152 | * @disable: fn ptr that enables the current clock in hardware |
| 153 | * @find_idlest: function returning the IDLEST register for the clock's IP blk |
| 154 | * @find_companion: function returning the "companion" clk reg for the clock |
| 155 | * @allow_idle: fn ptr that enables autoidle for the current clock in hardware |
| 156 | * @deny_idle: fn ptr that disables autoidle for the current clock in hardware |
| 157 | * |
| 158 | * A "companion" clk is an accompanying clock to the one being queried |
| 159 | * that must be enabled for the IP module connected to the clock to |
| 160 | * become accessible by the hardware. Neither @find_idlest nor |
| 161 | * @find_companion should be needed; that information is IP |
| 162 | * block-specific; the hwmod code has been created to handle this, but |
| 163 | * until hwmod data is ready and drivers have been converted to use PM |
| 164 | * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and |
| 165 | * @find_companion must, unfortunately, remain. |
| 166 | */ |
| 167 | struct clkops { |
| 168 | int (*enable)(struct clk *); |
| 169 | void (*disable)(struct clk *); |
| 170 | void (*find_idlest)(struct clk *, void __iomem **, |
| 171 | u8 *, u8 *); |
| 172 | void (*find_companion)(struct clk *, void __iomem **, |
| 173 | u8 *); |
| 174 | void (*allow_idle)(struct clk *); |
| 175 | void (*deny_idle)(struct clk *); |
| 176 | }; |
Rajendra Nayak | b5a2366 | 2012-11-10 16:58:40 -0700 | [diff] [blame] | 177 | #endif |
Paul Walmsley | a135eaa | 2012-09-27 10:33:34 -0600 | [diff] [blame] | 178 | |
| 179 | /* struct clksel_rate.flags possibilities */ |
| 180 | #define RATE_IN_242X (1 << 0) |
| 181 | #define RATE_IN_243X (1 << 1) |
| 182 | #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ |
| 183 | #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ |
| 184 | #define RATE_IN_36XX (1 << 4) |
| 185 | #define RATE_IN_4430 (1 << 5) |
| 186 | #define RATE_IN_TI816X (1 << 6) |
| 187 | #define RATE_IN_4460 (1 << 7) |
| 188 | #define RATE_IN_AM33XX (1 << 8) |
| 189 | #define RATE_IN_TI814X (1 << 9) |
| 190 | |
| 191 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) |
| 192 | #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) |
| 193 | #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) |
| 194 | #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460) |
| 195 | |
| 196 | /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ |
| 197 | #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) |
| 198 | |
| 199 | |
| 200 | /** |
| 201 | * struct clksel_rate - register bitfield values corresponding to clk divisors |
| 202 | * @val: register bitfield value (shifted to bit 0) |
| 203 | * @div: clock divisor corresponding to @val |
| 204 | * @flags: (see "struct clksel_rate.flags possibilities" above) |
| 205 | * |
| 206 | * @val should match the value of a read from struct clk.clksel_reg |
| 207 | * AND'ed with struct clk.clksel_mask, shifted right to bit 0. |
| 208 | * |
| 209 | * @div is the divisor that should be applied to the parent clock's rate |
| 210 | * to produce the current clock's rate. |
| 211 | */ |
| 212 | struct clksel_rate { |
| 213 | u32 val; |
| 214 | u8 div; |
| 215 | u16 flags; |
| 216 | }; |
| 217 | |
| 218 | /** |
| 219 | * struct clksel - available parent clocks, and a pointer to their divisors |
| 220 | * @parent: struct clk * to a possible parent clock |
| 221 | * @rates: available divisors for this parent clock |
| 222 | * |
| 223 | * A struct clksel is always associated with one or more struct clks |
| 224 | * and one or more struct clksel_rates. |
| 225 | */ |
| 226 | struct clksel { |
| 227 | struct clk *parent; |
| 228 | const struct clksel_rate *rates; |
| 229 | }; |
| 230 | |
| 231 | /** |
| 232 | * struct dpll_data - DPLL registers and integration data |
| 233 | * @mult_div1_reg: register containing the DPLL M and N bitfields |
| 234 | * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg |
| 235 | * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg |
| 236 | * @clk_bypass: struct clk pointer to the clock's bypass clock input |
| 237 | * @clk_ref: struct clk pointer to the clock's reference clock input |
| 238 | * @control_reg: register containing the DPLL mode bitfield |
| 239 | * @enable_mask: mask of the DPLL mode bitfield in @control_reg |
| 240 | * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() |
| 241 | * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() |
| 242 | * @max_multiplier: maximum valid non-bypass multiplier value (actual) |
| 243 | * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() |
| 244 | * @min_divider: minimum valid non-bypass divider value (actual) |
| 245 | * @max_divider: maximum valid non-bypass divider value (actual) |
| 246 | * @modes: possible values of @enable_mask |
| 247 | * @autoidle_reg: register containing the DPLL autoidle mode bitfield |
| 248 | * @idlest_reg: register containing the DPLL idle status bitfield |
| 249 | * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg |
| 250 | * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg |
| 251 | * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg |
| 252 | * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg |
| 253 | * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs |
| 254 | * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs |
| 255 | * @flags: DPLL type/features (see below) |
| 256 | * |
| 257 | * Possible values for @flags: |
| 258 | * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) |
| 259 | * |
| 260 | * @freqsel_mask is only used on the OMAP34xx family and AM35xx. |
| 261 | * |
| 262 | * XXX Some DPLLs have multiple bypass inputs, so it's not technically |
| 263 | * correct to only have one @clk_bypass pointer. |
| 264 | * |
| 265 | * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, |
| 266 | * @last_rounded_n) should be separated from the runtime-fixed fields |
| 267 | * and placed into a different structure, so that the runtime-fixed data |
| 268 | * can be placed into read-only space. |
| 269 | */ |
| 270 | struct dpll_data { |
| 271 | void __iomem *mult_div1_reg; |
| 272 | u32 mult_mask; |
| 273 | u32 div1_mask; |
| 274 | struct clk *clk_bypass; |
| 275 | struct clk *clk_ref; |
| 276 | void __iomem *control_reg; |
| 277 | u32 enable_mask; |
| 278 | unsigned long last_rounded_rate; |
| 279 | u16 last_rounded_m; |
| 280 | u16 max_multiplier; |
| 281 | u8 last_rounded_n; |
| 282 | u8 min_divider; |
| 283 | u16 max_divider; |
| 284 | u8 modes; |
| 285 | void __iomem *autoidle_reg; |
| 286 | void __iomem *idlest_reg; |
| 287 | u32 autoidle_mask; |
| 288 | u32 freqsel_mask; |
| 289 | u32 idlest_mask; |
| 290 | u32 dco_mask; |
| 291 | u32 sddiv_mask; |
| 292 | u8 auto_recal_bit; |
| 293 | u8 recal_en_bit; |
| 294 | u8 recal_st_bit; |
| 295 | u8 flags; |
| 296 | }; |
| 297 | |
| 298 | /* |
| 299 | * struct clk.flags possibilities |
| 300 | * |
| 301 | * XXX document the rest of the clock flags here |
| 302 | * |
| 303 | * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL |
| 304 | * bits share the same register. This flag allows the |
| 305 | * omap4_dpllmx*() code to determine which GATE_CTRL bit field |
| 306 | * should be used. This is a temporary solution - a better approach |
| 307 | * would be to associate clock type-specific data with the clock, |
| 308 | * similar to the struct dpll_data approach. |
| 309 | */ |
| 310 | #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ |
| 311 | #define CLOCK_IDLE_CONTROL (1 << 1) |
| 312 | #define CLOCK_NO_IDLE_PARENT (1 << 2) |
| 313 | #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ |
| 314 | #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ |
| 315 | #define CLOCK_CLKOUTX2 (1 << 5) |
| 316 | |
Rajendra Nayak | b5a2366 | 2012-11-10 16:58:40 -0700 | [diff] [blame] | 317 | #ifdef CONFIG_COMMON_CLK |
| 318 | /** |
| 319 | * struct clk_hw_omap - OMAP struct clk |
| 320 | * @node: list_head connecting this clock into the full clock list |
| 321 | * @enable_reg: register to write to enable the clock (see @enable_bit) |
| 322 | * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) |
| 323 | * @flags: see "struct clk.flags possibilities" above |
| 324 | * @clksel_reg: for clksel clks, register va containing src/divisor select |
| 325 | * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector |
| 326 | * @clksel: for clksel clks, pointer to struct clksel for this clock |
| 327 | * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock |
| 328 | * @clkdm_name: clockdomain name that this clock is contained in |
| 329 | * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime |
| 330 | * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) |
| 331 | * @src_offset: bitshift for source selection bitfield (OMAP1 only) |
| 332 | * |
| 333 | * XXX @rate_offset, @src_offset should probably be removed and OMAP1 |
| 334 | * clock code converted to use clksel. |
| 335 | * |
| 336 | */ |
| 337 | |
| 338 | struct clk_hw_omap_ops; |
| 339 | |
| 340 | struct clk_hw_omap { |
| 341 | struct clk_hw hw; |
| 342 | struct list_head node; |
| 343 | unsigned long fixed_rate; |
| 344 | u8 fixed_div; |
| 345 | void __iomem *enable_reg; |
| 346 | u8 enable_bit; |
| 347 | u8 flags; |
| 348 | void __iomem *clksel_reg; |
| 349 | u32 clksel_mask; |
| 350 | const struct clksel *clksel; |
| 351 | struct dpll_data *dpll_data; |
| 352 | const char *clkdm_name; |
| 353 | struct clockdomain *clkdm; |
| 354 | const struct clk_hw_omap_ops *ops; |
| 355 | }; |
| 356 | |
| 357 | struct clk_hw_omap_ops { |
| 358 | void (*find_idlest)(struct clk_hw_omap *oclk, |
| 359 | void __iomem **idlest_reg, |
| 360 | u8 *idlest_bit, u8 *idlest_val); |
| 361 | void (*find_companion)(struct clk_hw_omap *oclk, |
| 362 | void __iomem **other_reg, |
| 363 | u8 *other_bit); |
| 364 | void (*allow_idle)(struct clk_hw_omap *oclk); |
| 365 | void (*deny_idle)(struct clk_hw_omap *oclk); |
| 366 | }; |
| 367 | |
| 368 | unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, |
| 369 | unsigned long parent_rate); |
| 370 | #else |
Paul Walmsley | a135eaa | 2012-09-27 10:33:34 -0600 | [diff] [blame] | 371 | /** |
| 372 | * struct clk - OMAP struct clk |
| 373 | * @node: list_head connecting this clock into the full clock list |
| 374 | * @ops: struct clkops * for this clock |
| 375 | * @name: the name of the clock in the hardware (used in hwmod data and debug) |
| 376 | * @parent: pointer to this clock's parent struct clk |
| 377 | * @children: list_head connecting to the child clks' @sibling list_heads |
| 378 | * @sibling: list_head connecting this clk to its parent clk's @children |
| 379 | * @rate: current clock rate |
| 380 | * @enable_reg: register to write to enable the clock (see @enable_bit) |
| 381 | * @recalc: fn ptr that returns the clock's current rate |
| 382 | * @set_rate: fn ptr that can change the clock's current rate |
| 383 | * @round_rate: fn ptr that can round the clock's current rate |
| 384 | * @init: fn ptr to do clock-specific initialization |
| 385 | * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) |
| 386 | * @usecount: number of users that have requested this clock to be enabled |
| 387 | * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div |
| 388 | * @flags: see "struct clk.flags possibilities" above |
| 389 | * @clksel_reg: for clksel clks, register va containing src/divisor select |
| 390 | * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector |
| 391 | * @clksel: for clksel clks, pointer to struct clksel for this clock |
| 392 | * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock |
| 393 | * @clkdm_name: clockdomain name that this clock is contained in |
| 394 | * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime |
| 395 | * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) |
| 396 | * @src_offset: bitshift for source selection bitfield (OMAP1 only) |
| 397 | * |
| 398 | * XXX @rate_offset, @src_offset should probably be removed and OMAP1 |
| 399 | * clock code converted to use clksel. |
| 400 | * |
| 401 | * XXX @usecount is poorly named. It should be "enable_count" or |
| 402 | * something similar. "users" in the description refers to kernel |
| 403 | * code (core code or drivers) that have called clk_enable() and not |
| 404 | * yet called clk_disable(); the usecount of parent clocks is also |
| 405 | * incremented by the clock code when clk_enable() is called on child |
| 406 | * clocks and decremented by the clock code when clk_disable() is |
| 407 | * called on child clocks. |
| 408 | * |
| 409 | * XXX @clkdm, @usecount, @children, @sibling should be marked for |
| 410 | * internal use only. |
| 411 | * |
| 412 | * @children and @sibling are used to optimize parent-to-child clock |
| 413 | * tree traversals. (child-to-parent traversals use @parent.) |
| 414 | * |
| 415 | * XXX The notion of the clock's current rate probably needs to be |
| 416 | * separated from the clock's target rate. |
| 417 | */ |
| 418 | struct clk { |
| 419 | struct list_head node; |
| 420 | const struct clkops *ops; |
| 421 | const char *name; |
| 422 | struct clk *parent; |
| 423 | struct list_head children; |
| 424 | struct list_head sibling; /* node for children */ |
| 425 | unsigned long rate; |
| 426 | void __iomem *enable_reg; |
| 427 | unsigned long (*recalc)(struct clk *); |
| 428 | int (*set_rate)(struct clk *, unsigned long); |
| 429 | long (*round_rate)(struct clk *, unsigned long); |
| 430 | void (*init)(struct clk *); |
| 431 | u8 enable_bit; |
| 432 | s8 usecount; |
| 433 | u8 fixed_div; |
| 434 | u8 flags; |
| 435 | void __iomem *clksel_reg; |
| 436 | u32 clksel_mask; |
| 437 | const struct clksel *clksel; |
| 438 | struct dpll_data *dpll_data; |
| 439 | const char *clkdm_name; |
| 440 | struct clockdomain *clkdm; |
| 441 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
| 442 | struct dentry *dent; /* For visible tree hierarchy */ |
| 443 | #endif |
| 444 | }; |
| 445 | |
| 446 | struct clk_functions { |
| 447 | int (*clk_enable)(struct clk *clk); |
| 448 | void (*clk_disable)(struct clk *clk); |
| 449 | long (*clk_round_rate)(struct clk *clk, unsigned long rate); |
| 450 | int (*clk_set_rate)(struct clk *clk, unsigned long rate); |
| 451 | int (*clk_set_parent)(struct clk *clk, struct clk *parent); |
| 452 | void (*clk_allow_idle)(struct clk *clk); |
| 453 | void (*clk_deny_idle)(struct clk *clk); |
| 454 | void (*clk_disable_unused)(struct clk *clk); |
| 455 | }; |
| 456 | |
| 457 | extern int mpurate; |
| 458 | |
| 459 | extern int clk_init(struct clk_functions *custom_clocks); |
| 460 | extern void clk_preinit(struct clk *clk); |
| 461 | extern int clk_register(struct clk *clk); |
| 462 | extern void clk_reparent(struct clk *child, struct clk *parent); |
| 463 | extern void clk_unregister(struct clk *clk); |
| 464 | extern void propagate_rate(struct clk *clk); |
| 465 | extern void recalculate_root_clocks(void); |
| 466 | extern unsigned long followparent_recalc(struct clk *clk); |
| 467 | extern void clk_enable_init_clocks(void); |
| 468 | unsigned long omap_fixed_divisor_recalc(struct clk *clk); |
| 469 | extern struct clk *omap_clk_get_by_name(const char *name); |
| 470 | extern int omap_clk_enable_autoidle_all(void); |
| 471 | extern int omap_clk_disable_autoidle_all(void); |
| 472 | |
| 473 | extern const struct clkops clkops_null; |
| 474 | |
| 475 | extern struct clk dummy_ck; |
| 476 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 477 | #endif /* CONFIG_COMMON_CLK */ |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 478 | |
Russell King | c0bf313 | 2009-02-19 13:29:22 +0000 | [diff] [blame] | 479 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ |
| 480 | #define CORE_CLK_SRC_32K 0x0 |
| 481 | #define CORE_CLK_SRC_DPLL 0x1 |
| 482 | #define CORE_CLK_SRC_DPLL_X2 0x2 |
| 483 | |
| 484 | /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ |
| 485 | #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 |
| 486 | #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 |
| 487 | #define OMAP2XXX_EN_DPLL_LOCKED 0x3 |
| 488 | |
| 489 | /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
| 490 | #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 |
| 491 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 |
| 492 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 |
| 493 | |
Rajendra Nayak | 16975a7 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 494 | /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
| 495 | #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 |
| 496 | #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 |
| 497 | #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 |
| 498 | #define OMAP4XXX_EN_DPLL_LOCKED 0x7 |
| 499 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 500 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
| 501 | #define DPLL_LOW_POWER_STOP 0x1 |
| 502 | #define DPLL_LOW_POWER_BYPASS 0x5 |
| 503 | #define DPLL_LOCKED 0x7 |
| 504 | |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 505 | /* DPLL Type and DCO Selection Flags */ |
| 506 | #define DPLL_J_TYPE 0x1 |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 507 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 508 | #ifndef CONFIG_COMMON_CLK |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 509 | int omap2_clk_enable(struct clk *clk); |
| 510 | void omap2_clk_disable(struct clk *clk); |
| 511 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); |
| 512 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); |
| 513 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 514 | #endif /* CONFIG_COMMON_CLK */ |
| 515 | |
| 516 | #ifdef CONFIG_COMMON_CLK |
| 517 | long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, |
| 518 | unsigned long *parent_rate); |
| 519 | unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); |
| 520 | int omap3_noncore_dpll_enable(struct clk_hw *hw); |
| 521 | void omap3_noncore_dpll_disable(struct clk_hw *hw); |
| 522 | int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, |
| 523 | unsigned long parent_rate); |
| 524 | u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); |
| 525 | void omap3_dpll_allow_idle(struct clk_hw_omap *clk); |
| 526 | void omap3_dpll_deny_idle(struct clk_hw_omap *clk); |
| 527 | unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, |
| 528 | unsigned long parent_rate); |
| 529 | int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); |
| 530 | void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); |
| 531 | void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); |
| 532 | unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, |
| 533 | unsigned long parent_rate); |
| 534 | long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, |
| 535 | unsigned long target_rate, |
| 536 | unsigned long *parent_rate); |
| 537 | #else |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 538 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 539 | unsigned long omap3_dpll_recalc(struct clk *clk); |
| 540 | unsigned long omap3_clkoutx2_recalc(struct clk *clk); |
| 541 | void omap3_dpll_allow_idle(struct clk *clk); |
| 542 | void omap3_dpll_deny_idle(struct clk *clk); |
| 543 | u32 omap3_dpll_autoidle_read(struct clk *clk); |
| 544 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); |
| 545 | int omap3_noncore_dpll_enable(struct clk *clk); |
| 546 | void omap3_noncore_dpll_disable(struct clk *clk); |
Rajendra Nayak | 97f6789 | 2011-02-25 15:49:01 -0700 | [diff] [blame] | 547 | int omap4_dpllmx_gatectrl_read(struct clk *clk); |
| 548 | void omap4_dpllmx_allow_gatectrl(struct clk *clk); |
| 549 | void omap4_dpllmx_deny_gatectrl(struct clk *clk); |
Mike Turquette | a1900f2 | 2011-10-07 00:52:58 -0600 | [diff] [blame] | 550 | long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); |
| 551 | unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 552 | #endif |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 553 | |
| 554 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| 555 | void omap2_clk_disable_unused(struct clk *clk); |
| 556 | #else |
| 557 | #define omap2_clk_disable_unused NULL |
| 558 | #endif |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 559 | #ifdef CONFIG_COMMON_CLK |
| 560 | void omap2_init_clk_clkdm(struct clk_hw *clk); |
| 561 | #else |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 562 | void omap2_init_clk_clkdm(struct clk *clk); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 563 | #endif |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 564 | void __init omap2_clk_disable_clkdm_control(void); |
Paul Walmsley | 435699d | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 565 | |
| 566 | /* clkt_clksel.c public functions */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 567 | #ifdef CONFIG_COMMON_CLK |
| 568 | u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, |
| 569 | unsigned long target_rate, |
| 570 | u32 *new_div); |
| 571 | u8 omap2_clksel_find_parent_index(struct clk_hw *hw); |
| 572 | unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate); |
| 573 | long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, |
| 574 | unsigned long *parent_rate); |
| 575 | int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, |
| 576 | unsigned long parent_rate); |
| 577 | int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); |
| 578 | #else |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 579 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, |
| 580 | u32 *new_div); |
Paul Walmsley | 435699d | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 581 | void omap2_init_clksel_parent(struct clk *clk); |
| 582 | unsigned long omap2_clksel_recalc(struct clk *clk); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 583 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
| 584 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); |
Paul Walmsley | df791b3 | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 585 | int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 586 | #endif |
Paul Walmsley | 435699d | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 587 | |
Paul Walmsley | 530e544 | 2011-02-25 15:39:28 -0700 | [diff] [blame] | 588 | /* clkt_iclk.c public functions */ |
Rajendra Nayak | b4777a2 | 2012-04-27 15:53:48 +0530 | [diff] [blame] | 589 | #ifdef CONFIG_COMMON_CLK |
| 590 | extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); |
| 591 | extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); |
| 592 | #else |
Paul Walmsley | 530e544 | 2011-02-25 15:39:28 -0700 | [diff] [blame] | 593 | extern void omap2_clkt_iclk_allow_idle(struct clk *clk); |
| 594 | extern void omap2_clkt_iclk_deny_idle(struct clk *clk); |
Rajendra Nayak | b4777a2 | 2012-04-27 15:53:48 +0530 | [diff] [blame] | 595 | #endif |
Paul Walmsley | 530e544 | 2011-02-25 15:39:28 -0700 | [diff] [blame] | 596 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 597 | #ifdef CONFIG_COMMON_CLK |
| 598 | u8 omap2_init_dpll_parent(struct clk_hw *hw); |
| 599 | unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); |
| 600 | #else |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 601 | u32 omap2_get_dpll_rate(struct clk *clk); |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 602 | void omap2_init_dpll_parent(struct clk *clk); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 603 | #endif |
Paul Walmsley | 435699d | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 604 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 605 | #ifdef CONFIG_COMMON_CLK |
| 606 | int omap2_dflt_clk_enable(struct clk_hw *hw); |
| 607 | void omap2_dflt_clk_disable(struct clk_hw *hw); |
| 608 | int omap2_dflt_clk_is_enabled(struct clk_hw *hw); |
| 609 | void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, |
| 610 | void __iomem **other_reg, |
| 611 | u8 *other_bit); |
| 612 | void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, |
| 613 | void __iomem **idlest_reg, |
| 614 | u8 *idlest_bit, u8 *idlest_val); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 615 | void omap2_init_clk_hw_omap_clocks(struct clk *clk); |
| 616 | int omap2_clk_enable_autoidle_all(void); |
| 617 | int omap2_clk_disable_autoidle_all(void); |
Rajendra Nayak | 8577413 | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 618 | void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 619 | #else |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 620 | int omap2_dflt_clk_enable(struct clk *clk); |
| 621 | void omap2_dflt_clk_disable(struct clk *clk); |
| 622 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
| 623 | u8 *other_bit); |
| 624 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
Ranjith Lohithakshan | 419cc97 | 2010-02-24 12:05:54 -0700 | [diff] [blame] | 625 | u8 *idlest_bit, u8 *idlest_val); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 626 | #endif |
Paul Walmsley | 4d30e82 | 2010-02-22 22:09:36 -0700 | [diff] [blame] | 627 | int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); |
| 628 | void omap2_clk_print_new_rates(const char *hfclkin_ck_name, |
| 629 | const char *core_ck_name, |
| 630 | const char *mpu_ck_name); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 631 | |
Afzal Mohammed | 9954119 | 2011-12-13 10:46:43 -0800 | [diff] [blame] | 632 | extern u16 cpu_mask; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 633 | |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 634 | extern const struct clkops clkops_omap2_dflt_wait; |
Santosh Shilimkar | 7c43d54 | 2010-02-22 22:09:40 -0700 | [diff] [blame] | 635 | extern const struct clkops clkops_dummy; |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 636 | extern const struct clkops clkops_omap2_dflt; |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 637 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 638 | extern struct clk_functions omap2_clk_functions; |
| 639 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 640 | extern const struct clksel_rate gpt_32k_rates[]; |
| 641 | extern const struct clksel_rate gpt_sys_rates[]; |
| 642 | extern const struct clksel_rate gfx_l3_rates[]; |
Paul Walmsley | 2241139 | 2011-02-25 15:52:04 -0700 | [diff] [blame] | 643 | extern const struct clksel_rate dsp_ick_rates[]; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 644 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 645 | #ifdef CONFIG_COMMON_CLK |
| 646 | extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; |
| 647 | extern const struct clk_hw_omap_ops clkhwops_iclk_wait; |
| 648 | extern const struct clk_hw_omap_ops clkhwops_wait; |
| 649 | extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; |
Rajendra Nayak | b4777a2 | 2012-04-27 15:53:48 +0530 | [diff] [blame] | 650 | extern const struct clk_hw_omap_ops clkhwops_iclk; |
| 651 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; |
| 652 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; |
| 653 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; |
| 654 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; |
| 655 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; |
| 656 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; |
| 657 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; |
| 658 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; |
| 659 | extern const struct clk_hw_omap_ops clkhwops_apll54; |
| 660 | extern const struct clk_hw_omap_ops clkhwops_apll96; |
| 661 | extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; |
| 662 | extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; |
| 663 | #else |
Paul Walmsley | 530e544 | 2011-02-25 15:39:28 -0700 | [diff] [blame] | 664 | extern const struct clkops clkops_omap2_iclk_dflt_wait; |
| 665 | extern const struct clkops clkops_omap2_iclk_dflt; |
| 666 | extern const struct clkops clkops_omap2_iclk_idle_only; |
Paul Walmsley | e892b25 | 2011-02-25 15:39:29 -0700 | [diff] [blame] | 667 | extern const struct clkops clkops_omap2_mdmclk_dflt_wait; |
Paul Walmsley | 0fd0c21 | 2011-02-25 15:49:53 -0700 | [diff] [blame] | 668 | extern const struct clkops clkops_omap2xxx_dpll_ops; |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 669 | extern const struct clkops clkops_omap3_noncore_dpll_ops; |
Rajendra Nayak | 6c6f5a7 | 2011-02-25 15:49:00 -0700 | [diff] [blame] | 670 | extern const struct clkops clkops_omap3_core_dpll_ops; |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 671 | extern const struct clkops clkops_omap4_dpllmx_ops; |
Rajendra Nayak | b4777a2 | 2012-04-27 15:53:48 +0530 | [diff] [blame] | 672 | #endif /* CONFIG_COMMON_CLK */ |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 673 | |
Paul Walmsley | 571efa0 | 2012-05-29 15:26:40 +0530 | [diff] [blame] | 674 | /* clksel_rate blocks shared between OMAP44xx and AM33xx */ |
| 675 | extern const struct clksel_rate div_1_0_rates[]; |
| 676 | extern const struct clksel_rate div_1_1_rates[]; |
| 677 | extern const struct clksel_rate div_1_2_rates[]; |
| 678 | extern const struct clksel_rate div_1_3_rates[]; |
| 679 | extern const struct clksel_rate div_1_4_rates[]; |
| 680 | extern const struct clksel_rate div31_1to31_rates[]; |
| 681 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 682 | #ifndef CONFIG_COMMON_CLK |
Paul Walmsley | 571efa0 | 2012-05-29 15:26:40 +0530 | [diff] [blame] | 683 | /* clocks shared between various OMAP SoCs */ |
| 684 | extern struct clk virt_19200000_ck; |
| 685 | extern struct clk virt_26000000_ck; |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 686 | #endif |
Paul Walmsley | 571efa0 | 2012-05-29 15:26:40 +0530 | [diff] [blame] | 687 | |
Vaibhav Hiremath | e30384a | 2012-05-29 15:26:41 +0530 | [diff] [blame] | 688 | extern int am33xx_clk_init(void); |
| 689 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 690 | #ifdef CONFIG_COMMON_CLK |
| 691 | extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); |
| 692 | extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); |
| 693 | #endif |
| 694 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 695 | #endif |