blob: 1fd50dcfe47c629b75e9d8cfe855cad3aba8a1fa [file] [log] [blame]
Patil, Rachna01636eb2012-10-16 12:55:43 +05301#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
2#define __LINUX_TI_AM335X_TSCADC_MFD_H
3
4/*
5 * TI Touch Screen / ADC MFD driver
6 *
7 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mfd/core.h>
20
21#define REG_RAWIRQSTATUS 0x024
22#define REG_IRQSTATUS 0x028
23#define REG_IRQENABLE 0x02C
24#define REG_IRQCLR 0x030
25#define REG_IRQWAKEUP 0x034
26#define REG_CTRL 0x040
27#define REG_ADCFSM 0x044
28#define REG_CLKDIV 0x04C
29#define REG_SE 0x054
30#define REG_IDLECONFIG 0x058
31#define REG_CHARGECONFIG 0x05C
32#define REG_CHARGEDELAY 0x060
Sebastian Andrzej Siewior8c896302013-05-29 14:46:21 +020033#define REG_STEPCONFIG(n) (0x64 + ((n) * 8))
34#define REG_STEPDELAY(n) (0x68 + ((n) * 8))
Patil, Rachna01636eb2012-10-16 12:55:43 +053035#define REG_FIFO0CNT 0xE4
36#define REG_FIFO0THR 0xE8
37#define REG_FIFO1CNT 0xF0
38#define REG_FIFO1THR 0xF4
39#define REG_FIFO0 0x100
40#define REG_FIFO1 0x200
41
42/* Register Bitfields */
43/* IRQ wakeup enable */
44#define IRQWKUP_ENB BIT(0)
45
46/* Step Enable */
47#define STEPENB_MASK (0x1FFFF << 0)
48#define STEPENB(val) ((val) << 0)
Zubair Lutfullahca9a5632013-09-19 07:24:00 +010049#define ENB(val) (1 << (val))
50#define STPENB_STEPENB STEPENB(0x1FFFF)
51#define STPENB_STEPENB_TC STEPENB(0x1FFF)
Patil, Rachna01636eb2012-10-16 12:55:43 +053052
53/* IRQ enable */
54#define IRQENB_HW_PEN BIT(0)
Brad Griffis344d6352015-02-03 11:44:12 -080055#define IRQENB_EOS BIT(1)
Patil, Rachna01636eb2012-10-16 12:55:43 +053056#define IRQENB_FIFO0THRES BIT(2)
Zubair Lutfullahca9a5632013-09-19 07:24:00 +010057#define IRQENB_FIFO0OVRRUN BIT(3)
58#define IRQENB_FIFO0UNDRFLW BIT(4)
Patil, Rachna01636eb2012-10-16 12:55:43 +053059#define IRQENB_FIFO1THRES BIT(5)
Zubair Lutfullahca9a5632013-09-19 07:24:00 +010060#define IRQENB_FIFO1OVRRUN BIT(6)
61#define IRQENB_FIFO1UNDRFLW BIT(7)
Patil, Rachna01636eb2012-10-16 12:55:43 +053062#define IRQENB_PENUP BIT(9)
63
64/* Step Configuration */
65#define STEPCONFIG_MODE_MASK (3 << 0)
66#define STEPCONFIG_MODE(val) ((val) << 0)
Zubair Lutfullahca9a5632013-09-19 07:24:00 +010067#define STEPCONFIG_MODE_SWCNT STEPCONFIG_MODE(1)
Patil, Rachna01636eb2012-10-16 12:55:43 +053068#define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
69#define STEPCONFIG_AVG_MASK (7 << 2)
70#define STEPCONFIG_AVG(val) ((val) << 2)
71#define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4)
72#define STEPCONFIG_XPP BIT(5)
73#define STEPCONFIG_XNN BIT(6)
74#define STEPCONFIG_YPP BIT(7)
75#define STEPCONFIG_YNN BIT(8)
76#define STEPCONFIG_XNP BIT(9)
77#define STEPCONFIG_YPN BIT(10)
78#define STEPCONFIG_INM_MASK (0xF << 15)
79#define STEPCONFIG_INM(val) ((val) << 15)
80#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
81#define STEPCONFIG_INP_MASK (0xF << 19)
82#define STEPCONFIG_INP(val) ((val) << 19)
Patil, Rachna01636eb2012-10-16 12:55:43 +053083#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
84#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
85#define STEPCONFIG_FIFO1 BIT(26)
86
87/* Delay register */
88#define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
89#define STEPDELAY_OPEN(val) ((val) << 0)
90#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
91#define STEPDELAY_SAMPLE_MASK (0xFF << 24)
92#define STEPDELAY_SAMPLE(val) ((val) << 24)
93#define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0)
94
95/* Charge Config */
96#define STEPCHARGE_RFP_MASK (7 << 12)
97#define STEPCHARGE_RFP(val) ((val) << 12)
98#define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
99#define STEPCHARGE_INM_MASK (0xF << 15)
100#define STEPCHARGE_INM(val) ((val) << 15)
101#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
102#define STEPCHARGE_INP_MASK (0xF << 19)
103#define STEPCHARGE_INP(val) ((val) << 19)
Patil, Rachna01636eb2012-10-16 12:55:43 +0530104#define STEPCHARGE_RFM_MASK (3 << 23)
105#define STEPCHARGE_RFM(val) ((val) << 23)
106#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
107
108/* Charge delay */
109#define CHARGEDLY_OPEN_MASK (0x3FFFF << 0)
110#define CHARGEDLY_OPEN(val) ((val) << 0)
Brad Griffis344d6352015-02-03 11:44:12 -0800111#define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(0x400)
Patil, Rachna01636eb2012-10-16 12:55:43 +0530112
113/* Control register */
114#define CNTRLREG_TSCSSENB BIT(0)
115#define CNTRLREG_STEPID BIT(1)
116#define CNTRLREG_STEPCONFIGWRT BIT(2)
117#define CNTRLREG_POWERDOWN BIT(4)
118#define CNTRLREG_AFE_CTRL_MASK (3 << 5)
119#define CNTRLREG_AFE_CTRL(val) ((val) << 5)
120#define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1)
121#define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2)
122#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
123#define CNTRLREG_TSCENB BIT(7)
124
Patil, Rachnab1451e52013-07-20 17:27:00 +0100125/* FIFO READ Register */
126#define FIFOREAD_DATA_MASK (0xfff << 0)
127#define FIFOREAD_CHNLID_MASK (0xf << 16)
128
129/* Sequencer Status */
130#define SEQ_STATUS BIT(5)
Vignesh Rb10848e2015-01-07 11:19:36 +0530131#define CHARGE_STEP 0x11
Patil, Rachnab1451e52013-07-20 17:27:00 +0100132
Patil, Rachna01636eb2012-10-16 12:55:43 +0530133#define ADC_CLK 3000000
Patil, Rachna5e53a692012-10-16 12:55:45 +0530134#define TOTAL_STEPS 16
135#define TOTAL_CHANNELS 8
Zubair Lutfullahca9a5632013-09-19 07:24:00 +0100136#define FIFO1_THRESHOLD 19
Patil, Rachna01636eb2012-10-16 12:55:43 +0530137
Patil, Rachnab1451e52013-07-20 17:27:00 +0100138/*
Matthias Kaehlcke1a54b7d2013-09-10 23:02:18 +0200139 * time in us for processing a single channel, calculated as follows:
140 *
141 * num cycles = open delay + (sample delay + conv time) * averaging
142 *
143 * num cycles: 152 + (1 + 13) * 16 = 376
144 *
145 * clock frequency: 26MHz / 8 = 3.25MHz
146 * clock period: 1 / 3.25MHz = 308ns
147 *
148 * processing time: 376 * 308ns = 116us
149 */
150#define IDLE_TIMEOUT 116 /* microsec */
Patil, Rachnab1451e52013-07-20 17:27:00 +0100151
Patil, Rachna5e53a692012-10-16 12:55:45 +0530152#define TSCADC_CELLS 2
Patil, Rachna2b99baf2012-10-16 12:55:44 +0530153
Patil, Rachna01636eb2012-10-16 12:55:43 +0530154struct ti_tscadc_dev {
155 struct device *dev;
156 struct regmap *regmap_tscadc;
157 void __iomem *tscadc_base;
158 int irq;
Pantelis Antoniou24d5c822012-10-13 16:37:24 +0300159 int used_cells; /* 1-2 */
Jeff Lancef0933a62014-09-04 19:01:57 +0200160 int tsc_wires;
Pantelis Antoniou24d5c822012-10-13 16:37:24 +0300161 int tsc_cell; /* -1 if not used */
162 int adc_cell; /* -1 if not used */
Patil, Rachna01636eb2012-10-16 12:55:43 +0530163 struct mfd_cell cells[TSCADC_CELLS];
Patil, Rachnaabeccee2013-01-24 03:45:05 +0000164 u32 reg_se_cache;
Sebastian Andrzej Siewior7ca67402013-12-19 16:28:31 +0100165 bool adc_waiting;
166 bool adc_in_use;
167 wait_queue_head_t reg_se_wait;
Patil, Rachnaabeccee2013-01-24 03:45:05 +0000168 spinlock_t reg_lock;
Matthias Kaehlckee90f8752013-09-23 22:43:29 +0200169 unsigned int clk_div;
Patil, Rachna2b99baf2012-10-16 12:55:44 +0530170
171 /* tsc device */
172 struct titsc *tsc;
Patil, Rachna5e53a692012-10-16 12:55:45 +0530173
174 /* adc device */
175 struct adc_device *adc;
Patil, Rachna01636eb2012-10-16 12:55:43 +0530176};
177
Sebastian Andrzej Siewiora9bce1b2013-06-05 16:13:47 +0200178static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
179{
180 struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;
181
182 return *tscadc_dev;
183}
184
Sebastian Andrzej Siewior7e170c62013-12-19 16:28:29 +0100185void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
186void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
Patil, Rachnaabeccee2013-01-24 03:45:05 +0000187void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
Sebastian Andrzej Siewior7ca67402013-12-19 16:28:31 +0100188void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc);
Patil, Rachnaabeccee2013-01-24 03:45:05 +0000189
Patil, Rachna01636eb2012-10-16 12:55:43 +0530190#endif