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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
2 * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 *
31 * Rewritten by:
32 * Gareth Hughes <gareth@valinux.com>
33 */
34
35#ifndef __MGA_DRM_H__
36#define __MGA_DRM_H__
37
38/* WARNING: If you change any of these defines, make sure to change the
39 * defines in the Xserver file (mga_sarea.h)
40 */
41
42#ifndef __MGA_SAREA_DEFINES__
43#define __MGA_SAREA_DEFINES__
44
45/* WARP pipe flags
46 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +100047#define MGA_F 0x1 /* fog */
48#define MGA_A 0x2 /* alpha */
49#define MGA_S 0x4 /* specular */
50#define MGA_T2 0x8 /* multitexture */
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
52#define MGA_WARP_TGZ 0
53#define MGA_WARP_TGZF (MGA_F)
54#define MGA_WARP_TGZA (MGA_A)
55#define MGA_WARP_TGZAF (MGA_F|MGA_A)
56#define MGA_WARP_TGZS (MGA_S)
57#define MGA_WARP_TGZSF (MGA_S|MGA_F)
58#define MGA_WARP_TGZSA (MGA_S|MGA_A)
59#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
60#define MGA_WARP_T2GZ (MGA_T2)
61#define MGA_WARP_T2GZF (MGA_T2|MGA_F)
62#define MGA_WARP_T2GZA (MGA_T2|MGA_A)
63#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
64#define MGA_WARP_T2GZS (MGA_T2|MGA_S)
65#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
66#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
67#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
68
Dave Airlieb5e89ed2005-09-25 14:28:13 +100069#define MGA_MAX_G200_PIPES 8 /* no multitex */
Linus Torvalds1da177e2005-04-16 15:20:36 -070070#define MGA_MAX_G400_PIPES 16
71#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
Dave Airlieb5e89ed2005-09-25 14:28:13 +100072#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
74#define MGA_CARD_TYPE_G200 1
75#define MGA_CARD_TYPE_G400 2
Dave Airlieb5e89ed2005-09-25 14:28:13 +100076#define MGA_CARD_TYPE_G450 3 /* not currently used */
Dave Airlie93f453f2005-07-10 17:45:34 +100077#define MGA_CARD_TYPE_G550 4
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
79#define MGA_FRONT 0x1
80#define MGA_BACK 0x2
81#define MGA_DEPTH 0x4
82
83/* What needs to be changed for the current vertex dma buffer?
84 */
85#define MGA_UPLOAD_CONTEXT 0x1
86#define MGA_UPLOAD_TEX0 0x2
87#define MGA_UPLOAD_TEX1 0x4
88#define MGA_UPLOAD_PIPE 0x8
Dave Airlieb5e89ed2005-09-25 14:28:13 +100089#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
90#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
Linus Torvalds1da177e2005-04-16 15:20:36 -070091#define MGA_UPLOAD_2D 0x40
Dave Airlieb5e89ed2005-09-25 14:28:13 +100092#define MGA_WAIT_AGE 0x80 /* handled client-side */
93#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
Linus Torvalds1da177e2005-04-16 15:20:36 -070094#if 0
Dave Airlieb5e89ed2005-09-25 14:28:13 +100095#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
96 quiescent */
Linus Torvalds1da177e2005-04-16 15:20:36 -070097#endif
98
99/* 32 buffers of 64k each, total 2 meg.
100 */
101#define MGA_BUFFER_SIZE (1 << 16)
102#define MGA_NUM_BUFFERS 128
103
104/* Keep these small for testing.
105 */
106#define MGA_NR_SAREA_CLIPRECTS 8
107
108/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
109 * regions, subject to a minimum region size of (1<<16) == 64k.
110 *
111 * Clients may subdivide regions internally, but when sharing between
112 * clients, the region size is the minimum granularity.
113 */
114
115#define MGA_CARD_HEAP 0
116#define MGA_AGP_HEAP 1
117#define MGA_NR_TEX_HEAPS 2
118#define MGA_NR_TEX_REGIONS 16
119#define MGA_LOG_MIN_TEX_REGION_SIZE 16
120
121#define DRM_MGA_IDLE_RETRY 2048
122
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000123#endif /* __MGA_SAREA_DEFINES__ */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124
125/* Setup registers for 3D context
126 */
127typedef struct {
128 unsigned int dstorg;
129 unsigned int maccess;
130 unsigned int plnwt;
131 unsigned int dwgctl;
132 unsigned int alphactrl;
133 unsigned int fogcolor;
134 unsigned int wflag;
135 unsigned int tdualstage0;
136 unsigned int tdualstage1;
137 unsigned int fcol;
138 unsigned int stencil;
139 unsigned int stencilctl;
140} drm_mga_context_regs_t;
141
142/* Setup registers for 2D, X server
143 */
144typedef struct {
145 unsigned int pitch;
146} drm_mga_server_regs_t;
147
148/* Setup registers for each texture unit
149 */
150typedef struct {
151 unsigned int texctl;
152 unsigned int texctl2;
153 unsigned int texfilter;
154 unsigned int texbordercol;
155 unsigned int texorg;
156 unsigned int texwidth;
157 unsigned int texheight;
158 unsigned int texorg1;
159 unsigned int texorg2;
160 unsigned int texorg3;
161 unsigned int texorg4;
162} drm_mga_texture_regs_t;
163
164/* General aging mechanism
165 */
166typedef struct {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000167 unsigned int head; /* Position of head pointer */
168 unsigned int wrap; /* Primary DMA wrap count */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169} drm_mga_age_t;
170
171typedef struct _drm_mga_sarea {
172 /* The channel for communication of state information to the kernel
173 * on firing a vertex dma buffer.
174 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000175 drm_mga_context_regs_t context_state;
176 drm_mga_server_regs_t server_state;
177 drm_mga_texture_regs_t tex_state[2];
178 unsigned int warp_pipe;
179 unsigned int dirty;
180 unsigned int vertsize;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181
182 /* The current cliprects, or a subset thereof.
183 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000184 drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
185 unsigned int nbox;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186
187 /* Information about the most recently used 3d drawable. The
188 * client fills in the req_* fields, the server fills in the
189 * exported_ fields and puts the cliprects into boxes, above.
190 *
191 * The client clears the exported_drawable field before
192 * clobbering the boxes data.
193 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000194 unsigned int req_drawable; /* the X drawable id */
195 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000197 unsigned int exported_drawable;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198 unsigned int exported_index;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000199 unsigned int exported_stamp;
200 unsigned int exported_buffers;
201 unsigned int exported_nfront;
202 unsigned int exported_nback;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 int exported_back_x, exported_front_x, exported_w;
204 int exported_back_y, exported_front_y, exported_h;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000205 drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206
207 /* Counters for aging textures and for client-side throttling.
208 */
209 unsigned int status[4];
210 unsigned int last_wrap;
211
212 drm_mga_age_t last_frame;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000213 unsigned int last_enqueue; /* last time a buffer was enqueued */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 unsigned int last_dispatch; /* age of the most recently dispatched buffer */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000215 unsigned int last_quiescent; /* */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216
217 /* LRU lists for texture memory in agp space and on the card.
218 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000219 drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 unsigned int texAge[MGA_NR_TEX_HEAPS];
221
222 /* Mechanism to validate card state.
223 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000224 int ctxOwner;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225} drm_mga_sarea_t;
226
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227/* MGA specific ioctls
228 * The device specific ioctl range is 0x40 to 0x79.
229 */
230#define DRM_MGA_INIT 0x00
231#define DRM_MGA_FLUSH 0x01
232#define DRM_MGA_RESET 0x02
233#define DRM_MGA_SWAP 0x03
234#define DRM_MGA_CLEAR 0x04
235#define DRM_MGA_VERTEX 0x05
236#define DRM_MGA_INDICES 0x06
237#define DRM_MGA_ILOAD 0x07
238#define DRM_MGA_BLIT 0x08
239#define DRM_MGA_GETPARAM 0x09
240
Dave Airlie6795c982005-07-10 18:20:09 +1000241/* 3.2:
242 * ioctls for operating on fences.
243 */
244#define DRM_MGA_SET_FENCE 0x0a
245#define DRM_MGA_WAIT_FENCE 0x0b
246#define DRM_MGA_DMA_BOOTSTRAP 0x0c
247
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
249#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
250#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
251#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
252#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
253#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
254#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
255#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
256#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
257#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
Dave Airlie6795c982005-07-10 18:20:09 +1000258#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t)
259#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t)
260#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261
262typedef struct _drm_mga_warp_index {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000263 int installed;
264 unsigned long phys_addr;
265 int size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266} drm_mga_warp_index_t;
267
268typedef struct drm_mga_init {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000269 enum {
270 MGA_INIT_DMA = 0x01,
271 MGA_CLEANUP_DMA = 0x02
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 } func;
273
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000274 unsigned long sarea_priv_offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275
276 int chipset;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000277 int sgram;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278
279 unsigned int maccess;
280
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000281 unsigned int fb_cpp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 unsigned int front_offset, front_pitch;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000283 unsigned int back_offset, back_pitch;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000285 unsigned int depth_cpp;
286 unsigned int depth_offset, depth_pitch;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000288 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
289 unsigned int texture_size[MGA_NR_TEX_HEAPS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290
291 unsigned long fb_offset;
292 unsigned long mmio_offset;
293 unsigned long status_offset;
294 unsigned long warp_offset;
295 unsigned long primary_offset;
296 unsigned long buffers_offset;
297} drm_mga_init_t;
298
Dave Airlie6795c982005-07-10 18:20:09 +1000299typedef struct drm_mga_dma_bootstrap {
300 /**
301 * \name AGP texture region
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000302 *
Dave Airlie6795c982005-07-10 18:20:09 +1000303 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
304 * be filled in with the actual AGP texture settings.
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000305 *
Dave Airlie6795c982005-07-10 18:20:09 +1000306 * \warning
307 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
308 * is zero, it means that PCI memory (most likely through the use of
309 * an IOMMU) is being used for "AGP" textures.
310 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000311 /*@{ */
Dave Airlied1f2b552005-08-05 22:11:22 +1000312 unsigned long texture_handle; /**< Handle used to map AGP textures. */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000313 uint32_t texture_size; /**< Size of the AGP texture region. */
314 /*@} */
Dave Airlie6795c982005-07-10 18:20:09 +1000315
316 /**
317 * Requested size of the primary DMA region.
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000318 *
Dave Airlie6795c982005-07-10 18:20:09 +1000319 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
320 * filled in with the actual AGP mode. If AGP was not available
321 */
322 uint32_t primary_size;
323
Dave Airlie6795c982005-07-10 18:20:09 +1000324 /**
325 * Requested number of secondary DMA buffers.
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000326 *
Dave Airlie6795c982005-07-10 18:20:09 +1000327 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
328 * filled in with the actual number of secondary DMA buffers
329 * allocated. Particularly when PCI DMA is used, this may be
330 * (subtantially) less than the number requested.
331 */
332 uint32_t secondary_bin_count;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000333
Dave Airlie6795c982005-07-10 18:20:09 +1000334 /**
335 * Requested size of each secondary DMA buffer.
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000336 *
Dave Airlie6795c982005-07-10 18:20:09 +1000337 * While the kernel \b is free to reduce
338 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
339 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
340 */
341 uint32_t secondary_bin_size;
342
Dave Airlie6795c982005-07-10 18:20:09 +1000343 /**
344 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
345 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
346 * zero, it means that PCI DMA should be used, even if AGP is
347 * possible.
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000348 *
Dave Airlie6795c982005-07-10 18:20:09 +1000349 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
350 * filled in with the actual AGP mode. If AGP was not available
351 * (i.e., PCI DMA was used), this value will be zero.
352 */
353 uint32_t agp_mode;
354
Dave Airlie6795c982005-07-10 18:20:09 +1000355 /**
356 * Desired AGP GART size, measured in megabytes.
357 */
358 uint8_t agp_size;
359} drm_mga_dma_bootstrap_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360
361typedef struct drm_mga_clear {
362 unsigned int flags;
363 unsigned int clear_color;
364 unsigned int clear_depth;
365 unsigned int color_mask;
366 unsigned int depth_mask;
367} drm_mga_clear_t;
368
369typedef struct drm_mga_vertex {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000370 int idx; /* buffer to queue */
371 int used; /* bytes in use */
372 int discard; /* client finished with buffer? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373} drm_mga_vertex_t;
374
375typedef struct drm_mga_indices {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000376 int idx; /* buffer to queue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 unsigned int start;
378 unsigned int end;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000379 int discard; /* client finished with buffer? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380} drm_mga_indices_t;
381
382typedef struct drm_mga_iload {
383 int idx;
384 unsigned int dstorg;
385 unsigned int length;
386} drm_mga_iload_t;
387
388typedef struct _drm_mga_blit {
389 unsigned int planemask;
390 unsigned int srcorg;
391 unsigned int dstorg;
392 int src_pitch, dst_pitch;
393 int delta_sx, delta_sy;
394 int delta_dx, delta_dy;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000395 int height, ydir; /* flip image vertically */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 int source_pitch, dest_pitch;
397} drm_mga_blit_t;
398
399/* 3.1: An ioctl to get parameters that aren't available to the 3d
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000400 * client any other way.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 */
402#define MGA_PARAM_IRQ_NR 1
403
Dave Airlie6795c982005-07-10 18:20:09 +1000404/* 3.2: Query the actual card type. The DDX only distinguishes between
405 * G200 chips and non-G200 chips, which it calls G400. It turns out that
406 * there are some very sublte differences between the G4x0 chips and the G550
407 * chips. Using this parameter query, a client-side driver can detect the
408 * difference between a G4x0 and a G550.
409 */
410#define MGA_PARAM_CARD_TYPE 2
411
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412typedef struct drm_mga_getparam {
413 int param;
414 void __user *value;
415} drm_mga_getparam_t;
416
417#endif