Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * dim2_hal.h - DIM2 HAL interface |
| 3 | * (MediaLB, Device Interface Macro IP, OS62420) |
| 4 | * |
| 5 | * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | * This file is licensed under GPLv2. |
| 13 | */ |
| 14 | |
| 15 | #ifndef _DIM2_HAL_H |
| 16 | #define _DIM2_HAL_H |
| 17 | |
| 18 | #include <linux/types.h> |
Hugo Camboulive | 092c78f | 2016-01-02 22:33:26 +0000 | [diff] [blame] | 19 | #include "dim2_reg.h" |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 20 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 21 | /* |
| 22 | * The values below are specified in the hardware specification. |
| 23 | * So, they should not be changed until the hardware specification changes. |
| 24 | */ |
| 25 | enum mlb_clk_speed { |
| 26 | CLK_256FS = 0, |
| 27 | CLK_512FS = 1, |
| 28 | CLK_1024FS = 2, |
| 29 | CLK_2048FS = 3, |
| 30 | CLK_3072FS = 4, |
| 31 | CLK_4096FS = 5, |
| 32 | CLK_6144FS = 6, |
| 33 | CLK_8192FS = 7, |
| 34 | }; |
| 35 | |
| 36 | struct dim_ch_state_t { |
| 37 | bool ready; /* Shows readiness to enqueue next buffer */ |
| 38 | u16 done_buffers; /* Number of completed buffers */ |
| 39 | }; |
| 40 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 41 | struct int_ch_state { |
| 42 | /* changed only in interrupt context */ |
PrasannaKumar Muralidharan | afb1055 | 2016-03-12 14:03:09 +0530 | [diff] [blame] | 43 | volatile int request_counter; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 44 | |
| 45 | /* changed only in task context */ |
PrasannaKumar Muralidharan | afb1055 | 2016-03-12 14:03:09 +0530 | [diff] [blame] | 46 | volatile int service_counter; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 47 | |
| 48 | u8 idx1; |
| 49 | u8 idx2; |
| 50 | u8 level; /* [0..2], buffering level */ |
| 51 | }; |
| 52 | |
| 53 | struct dim_channel { |
| 54 | struct int_ch_state state; |
| 55 | u8 addr; |
| 56 | u16 dbr_addr; |
| 57 | u16 dbr_size; |
| 58 | u16 packet_length; /*< Isochronous packet length in bytes. */ |
| 59 | u16 bytes_per_frame; /*< Synchronous bytes per frame. */ |
| 60 | u16 done_sw_buffers_number; /*< Done software buffers number. */ |
| 61 | }; |
| 62 | |
Christian Gromm | 63c8766 | 2016-06-13 16:24:24 +0200 | [diff] [blame] | 63 | u8 dim_startup(struct dim2_regs __iomem *dim_base_address, u32 mlb_clock, |
| 64 | u32 fcnt); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 65 | |
Chaehyun Lim | 50a45b1 | 2015-10-29 16:44:12 +0900 | [diff] [blame] | 66 | void dim_shutdown(void); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 67 | |
Chaehyun Lim | b724207 | 2015-11-02 22:59:01 +0900 | [diff] [blame] | 68 | bool dim_get_lock_state(void); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 69 | |
Chaehyun Lim | c64c6073 | 2015-11-02 22:59:05 +0900 | [diff] [blame] | 70 | u16 dim_norm_ctrl_async_buffer_size(u16 buf_size); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 71 | |
Chaehyun Lim | e302ca4 | 2015-11-02 22:59:06 +0900 | [diff] [blame] | 72 | u16 dim_norm_isoc_buffer_size(u16 buf_size, u16 packet_length); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 73 | |
Chaehyun Lim | aff1924 | 2015-11-02 22:59:07 +0900 | [diff] [blame] | 74 | u16 dim_norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 75 | |
Chaehyun Lim | a3f3e92 | 2015-11-02 22:59:08 +0900 | [diff] [blame] | 76 | u8 dim_init_control(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
| 77 | u16 max_buffer_size); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 78 | |
Chaehyun Lim | 2630315 | 2015-11-02 22:59:09 +0900 | [diff] [blame] | 79 | u8 dim_init_async(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
| 80 | u16 max_buffer_size); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 81 | |
Chaehyun Lim | f138317 | 2015-11-02 22:59:10 +0900 | [diff] [blame] | 82 | u8 dim_init_isoc(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
| 83 | u16 packet_length); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 84 | |
Chaehyun Lim | 10e5efb | 2015-11-02 22:59:11 +0900 | [diff] [blame] | 85 | u8 dim_init_sync(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
| 86 | u16 bytes_per_frame); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 87 | |
Chaehyun Lim | a5e4d89 | 2015-11-02 22:59:12 +0900 | [diff] [blame] | 88 | u8 dim_destroy_channel(struct dim_channel *ch); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 89 | |
Andrey Shvetsov | 8f53346 | 2016-09-15 16:19:13 +0200 | [diff] [blame] | 90 | void dim_service_mlb_int_irq(void); |
| 91 | |
Andrey Shvetsov | 055f1d1 | 2016-09-15 16:19:09 +0200 | [diff] [blame] | 92 | void dim_service_ahb_int_irq(struct dim_channel *const *channels); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 93 | |
Chaehyun Lim | 0d08d54 | 2015-11-02 22:59:14 +0900 | [diff] [blame] | 94 | u8 dim_service_channel(struct dim_channel *ch); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 95 | |
Chaehyun Lim | 60d5f66 | 2015-11-02 22:59:16 +0900 | [diff] [blame] | 96 | struct dim_ch_state_t *dim_get_channel_state(struct dim_channel *ch, |
| 97 | struct dim_ch_state_t *state_ptr); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 98 | |
Andrey Shvetsov | 8f53346 | 2016-09-15 16:19:13 +0200 | [diff] [blame] | 99 | u16 dim_dbr_space(struct dim_channel *ch); |
| 100 | |
Chaehyun Lim | c904ffd | 2015-11-02 22:59:17 +0900 | [diff] [blame] | 101 | bool dim_enqueue_buffer(struct dim_channel *ch, u32 buffer_addr, |
| 102 | u16 buffer_size); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 103 | |
Chaehyun Lim | 38c3854 | 2015-10-29 16:44:13 +0900 | [diff] [blame] | 104 | bool dim_detach_buffers(struct dim_channel *ch, u16 buffers_number); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 105 | |
Hugo Camboulive | 092c78f | 2016-01-02 22:33:26 +0000 | [diff] [blame] | 106 | u32 dimcb_io_read(u32 __iomem *ptr32); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 107 | |
Hugo Camboulive | 092c78f | 2016-01-02 22:33:26 +0000 | [diff] [blame] | 108 | void dimcb_io_write(u32 __iomem *ptr32, u32 value); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 109 | |
Chaehyun Lim | de66873 | 2015-11-02 22:59:02 +0900 | [diff] [blame] | 110 | void dimcb_on_error(u8 error_id, const char *error_message); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 111 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 112 | #endif /* _DIM2_HAL_H */ |