Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 1 | #ifndef __ASM_SH_IRQ_SH7343_H |
| 2 | #define __ASM_SH_IRQ_SH7343_H |
| 3 | |
| 4 | /* |
| 5 | * linux/include/asm-sh/irq-sh7343.h |
| 6 | * |
| 7 | * Copyright (C) 2006 Kenati Technologies Inc. |
| 8 | * Andre Mccurdy <andre@kenati.com> |
| 9 | * Ranjit Deshpande <ranjit@kenati.com> |
| 10 | */ |
| 11 | |
| 12 | #undef INTC_IPRA |
| 13 | #undef INTC_IPRB |
| 14 | #undef INTC_IPRC |
| 15 | #undef INTC_IPRD |
| 16 | |
| 17 | #undef DMTE0_IRQ |
| 18 | #undef DMTE1_IRQ |
| 19 | #undef DMTE2_IRQ |
| 20 | #undef DMTE3_IRQ |
| 21 | #undef DMTE4_IRQ |
| 22 | #undef DMTE5_IRQ |
| 23 | #undef DMTE6_IRQ |
| 24 | #undef DMTE7_IRQ |
| 25 | #undef DMAE_IRQ |
| 26 | #undef DMA_IPR_ADDR |
| 27 | #undef DMA_IPR_POS |
| 28 | #undef DMA_PRIORITY |
| 29 | |
| 30 | #undef INTC_IMCR0 |
| 31 | #undef INTC_IMCR1 |
| 32 | #undef INTC_IMCR2 |
| 33 | #undef INTC_IMCR3 |
| 34 | #undef INTC_IMCR4 |
| 35 | #undef INTC_IMCR5 |
| 36 | #undef INTC_IMCR6 |
| 37 | #undef INTC_IMCR7 |
| 38 | #undef INTC_IMCR8 |
| 39 | #undef INTC_IMCR9 |
| 40 | #undef INTC_IMCR10 |
| 41 | |
| 42 | |
| 43 | #define INTC_IPRA 0xA4080000UL |
| 44 | #define INTC_IPRB 0xA4080004UL |
| 45 | #define INTC_IPRC 0xA4080008UL |
| 46 | #define INTC_IPRD 0xA408000CUL |
| 47 | #define INTC_IPRE 0xA4080010UL |
| 48 | #define INTC_IPRF 0xA4080014UL |
| 49 | #define INTC_IPRG 0xA4080018UL |
| 50 | #define INTC_IPRH 0xA408001CUL |
| 51 | #define INTC_IPRI 0xA4080020UL |
| 52 | #define INTC_IPRJ 0xA4080024UL |
| 53 | #define INTC_IPRK 0xA4080028UL |
| 54 | #define INTC_IPRL 0xA408002CUL |
| 55 | |
| 56 | #define INTC_IMR0 0xA4080080UL |
| 57 | #define INTC_IMR1 0xA4080084UL |
| 58 | #define INTC_IMR2 0xA4080088UL |
| 59 | #define INTC_IMR3 0xA408008CUL |
| 60 | #define INTC_IMR4 0xA4080090UL |
| 61 | #define INTC_IMR5 0xA4080094UL |
| 62 | #define INTC_IMR6 0xA4080098UL |
| 63 | #define INTC_IMR7 0xA408009CUL |
| 64 | #define INTC_IMR8 0xA40800A0UL |
| 65 | #define INTC_IMR9 0xA40800A4UL |
| 66 | #define INTC_IMR10 0xA40800A8UL |
| 67 | #define INTC_IMR11 0xA40800ACUL |
| 68 | |
| 69 | #define INTC_IMCR0 0xA40800C0UL |
| 70 | #define INTC_IMCR1 0xA40800C4UL |
| 71 | #define INTC_IMCR2 0xA40800C8UL |
| 72 | #define INTC_IMCR3 0xA40800CCUL |
| 73 | #define INTC_IMCR4 0xA40800D0UL |
| 74 | #define INTC_IMCR5 0xA40800D4UL |
| 75 | #define INTC_IMCR6 0xA40800D8UL |
| 76 | #define INTC_IMCR7 0xA40800DCUL |
| 77 | #define INTC_IMCR8 0xA40800E0UL |
| 78 | #define INTC_IMCR9 0xA40800E4UL |
| 79 | #define INTC_IMCR10 0xA40800E8UL |
| 80 | #define INTC_IMCR11 0xA40800ECUL |
| 81 | |
| 82 | #define INTC_ICR0 0xA4140000UL |
| 83 | #define INTC_ICR1 0xA414001CUL |
| 84 | |
| 85 | #define INTMSK0 0xa4140044 |
| 86 | #define INTMSKCLR0 0xa4140064 |
| 87 | #define INTC_INTPRI0 0xa4140010 |
| 88 | |
| 89 | /* |
| 90 | NOTE: |
| 91 | |
| 92 | *_IRQ = (INTEVT2 - 0x200)/0x20 |
| 93 | */ |
| 94 | |
| 95 | /* TMU0 */ |
| 96 | #define TMU0_IRQ 16 |
| 97 | #define TMU0_IPR_ADDR INTC_IPRA |
| 98 | #define TMU0_IPR_POS 3 |
| 99 | #define TMU0_PRIORITY 2 |
| 100 | |
| 101 | #define TIMER_IRQ 16 |
| 102 | #define TIMER_IPR_ADDR INTC_IPRA |
| 103 | #define TIMER_IPR_POS 3 |
| 104 | #define TIMER_PRIORITY 2 |
| 105 | |
| 106 | /* TMU1 */ |
| 107 | #define TMU1_IRQ 17 |
| 108 | #define TMU1_IPR_ADDR INTC_IPRA |
| 109 | #define TMU1_IPR_POS 2 |
| 110 | #define TMU1_PRIORITY 2 |
| 111 | |
| 112 | /* TMU2 */ |
| 113 | #define TMU2_IRQ 18 |
| 114 | #define TMU2_IPR_ADDR INTC_IPRA |
| 115 | #define TMU2_IPR_POS 1 |
| 116 | #define TMU2_PRIORITY 2 |
| 117 | |
| 118 | /* LCDC */ |
| 119 | #define LCDC_IRQ 28 |
| 120 | #define LCDC_IPR_ADDR INTC_IPRB |
| 121 | #define LCDC_IPR_POS 2 |
| 122 | #define LCDC_PRIORITY 2 |
| 123 | |
| 124 | /* VIO (Video I/O) */ |
| 125 | #define CEU_IRQ 52 |
| 126 | #define BEU_IRQ 53 |
| 127 | #define VEU_IRQ 54 |
| 128 | #define VOU_IRQ 55 |
| 129 | #define VIO_IPR_ADDR INTC_IPRE |
| 130 | #define VIO_IPR_POS 2 |
| 131 | #define VIO_PRIORITY 2 |
| 132 | |
| 133 | /* MFI (Multi Functional Interface) */ |
| 134 | #define MFI_IRQ 56 |
| 135 | #define MFI_IPR_ADDR INTC_IPRE |
| 136 | #define MFI_IPR_POS 1 |
| 137 | #define MFI_PRIORITY 2 |
| 138 | |
| 139 | /* VPU (Video Processing Unit) */ |
| 140 | #define VPU_IRQ 60 |
| 141 | #define VPU_IPR_ADDR INTC_IPRE |
| 142 | #define VPU_IPR_POS 0 |
| 143 | #define VPU_PRIORITY 2 |
| 144 | |
| 145 | /* 3DG */ |
| 146 | #define TDG_IRQ 63 |
| 147 | #define TDG_IPR_ADDR INTC_IPRJ |
| 148 | #define TDG_IPR_POS 2 |
| 149 | #define TDG_PRIORITY 2 |
| 150 | |
| 151 | /* DMAC(1) */ |
| 152 | #define DMTE0_IRQ 48 |
| 153 | #define DMTE1_IRQ 49 |
| 154 | #define DMTE2_IRQ 50 |
| 155 | #define DMTE3_IRQ 51 |
| 156 | #define DMA1_IPR_ADDR INTC_IPRE |
| 157 | #define DMA1_IPR_POS 3 |
| 158 | #define DMA1_PRIORITY 7 |
| 159 | |
| 160 | /* DMAC(2) */ |
| 161 | #define DMTE4_IRQ 76 |
| 162 | #define DMTE5_IRQ 77 |
| 163 | #define DMA2_IPR_ADDR INTC_IPRF |
| 164 | #define DMA2_IPR_POS 2 |
| 165 | #define DMA2_PRIORITY 7 |
| 166 | |
| 167 | /* SCIF0 */ |
| 168 | #define SCIF_ERI_IRQ 80 |
| 169 | #define SCIF_RXI_IRQ 81 |
| 170 | #define SCIF_BRI_IRQ 82 |
| 171 | #define SCIF_TXI_IRQ 83 |
| 172 | #define SCIF_IPR_ADDR INTC_IPRG |
| 173 | #define SCIF_IPR_POS 3 |
| 174 | #define SCIF_PRIORITY 3 |
| 175 | |
| 176 | /* SIOF0 */ |
| 177 | #define SIOF0_IRQ 84 |
| 178 | #define SIOF0_IPR_ADDR INTC_IPRH |
| 179 | #define SIOF0_IPR_POS 3 |
| 180 | #define SIOF0_PRIORITY 3 |
| 181 | |
| 182 | /* FLCTL (Flash Memory Controller) */ |
| 183 | #define FLSTE_IRQ 92 |
| 184 | #define FLTEND_IRQ 93 |
| 185 | #define FLTRQ0_IRQ 94 |
| 186 | #define FLTRQ1_IRQ 95 |
| 187 | #define FLCTL_IPR_ADDR INTC_IPRH |
| 188 | #define FLCTL_IPR_POS 1 |
| 189 | #define FLCTL_PRIORITY 3 |
| 190 | |
| 191 | /* IIC(0) (IIC Bus Interface) */ |
| 192 | #define IIC0_ALI_IRQ 96 |
| 193 | #define IIC0_TACKI_IRQ 97 |
| 194 | #define IIC0_WAITI_IRQ 98 |
| 195 | #define IIC0_DTEI_IRQ 99 |
| 196 | #define IIC0_IPR_ADDR INTC_IPRH |
| 197 | #define IIC0_IPR_POS 0 |
| 198 | #define IIC0_PRIORITY 3 |
| 199 | |
| 200 | /* IIC(1) (IIC Bus Interface) */ |
| 201 | #define IIC1_ALI_IRQ 44 |
| 202 | #define IIC1_TACKI_IRQ 45 |
| 203 | #define IIC1_WAITI_IRQ 46 |
| 204 | #define IIC1_DTEI_IRQ 47 |
| 205 | #define IIC1_IPR_ADDR INTC_IPRI |
| 206 | #define IIC1_IPR_POS 0 |
| 207 | #define IIC1_PRIORITY 3 |
| 208 | |
| 209 | /* SIO0 */ |
| 210 | #define SIO0_IRQ 88 |
| 211 | #define SIO0_IPR_ADDR INTC_IPRI |
| 212 | #define SIO0_IPR_POS 3 |
| 213 | #define SIO0_PRIORITY 3 |
| 214 | |
| 215 | /* SDHI */ |
| 216 | #define SDHI_SDHII0_IRQ 100 |
| 217 | #define SDHI_SDHII1_IRQ 101 |
| 218 | #define SDHI_SDHII2_IRQ 102 |
| 219 | #define SDHI_SDHII3_IRQ 103 |
| 220 | #define SDHI_IPR_ADDR INTC_IPRK |
| 221 | #define SDHI_IPR_POS 0 |
| 222 | #define SDHI_PRIORITY 3 |
| 223 | |
| 224 | /* SIU (Sound Interface Unit) */ |
| 225 | #define SIU_IRQ 108 |
| 226 | #define SIU_IPR_ADDR INTC_IPRJ |
| 227 | #define SIU_IPR_POS 1 |
| 228 | #define SIU_PRIORITY 3 |
| 229 | |
| 230 | #define PORT_PACR 0xA4050100UL |
| 231 | #define PORT_PBCR 0xA4050102UL |
| 232 | #define PORT_PCCR 0xA4050104UL |
| 233 | #define PORT_PDCR 0xA4050106UL |
| 234 | #define PORT_PECR 0xA4050108UL |
| 235 | #define PORT_PFCR 0xA405010AUL |
| 236 | #define PORT_PGCR 0xA405010CUL |
| 237 | #define PORT_PHCR 0xA405010EUL |
| 238 | #define PORT_PJCR 0xA4050110UL |
| 239 | #define PORT_PKCR 0xA4050112UL |
| 240 | #define PORT_PLCR 0xA4050114UL |
| 241 | #define PORT_SCPCR 0xA4050116UL |
| 242 | #define PORT_PMCR 0xA4050118UL |
| 243 | #define PORT_PNCR 0xA405011AUL |
| 244 | #define PORT_PQCR 0xA405011CUL |
| 245 | #define PORT_PRCR 0xA405011EUL |
| 246 | #define PORT_PTCR 0xA405014CUL |
| 247 | #define PORT_PUCR 0xA405014EUL |
| 248 | #define PORT_PVCR 0xA4050150UL |
| 249 | |
| 250 | #define PORT_PSELA 0xA4050140UL |
| 251 | #define PORT_PSELB 0xA4050142UL |
| 252 | #define PORT_PSELC 0xA4050144UL |
| 253 | #define PORT_PSELE 0xA4050158UL |
| 254 | |
| 255 | #define PORT_HIZCRA 0xA4050146UL |
| 256 | #define PORT_HIZCRB 0xA4050148UL |
| 257 | #define PORT_DRVCR 0xA405014AUL |
| 258 | |
| 259 | #define PORT_PADR 0xA4050120UL |
| 260 | #define PORT_PBDR 0xA4050122UL |
| 261 | #define PORT_PCDR 0xA4050124UL |
| 262 | #define PORT_PDDR 0xA4050126UL |
| 263 | #define PORT_PEDR 0xA4050128UL |
| 264 | #define PORT_PFDR 0xA405012AUL |
| 265 | #define PORT_PGDR 0xA405012CUL |
| 266 | #define PORT_PHDR 0xA405012EUL |
| 267 | #define PORT_PJDR 0xA4050130UL |
| 268 | #define PORT_PKDR 0xA4050132UL |
| 269 | #define PORT_PLDR 0xA4050134UL |
| 270 | #define PORT_SCPDR 0xA4050136UL |
| 271 | #define PORT_PMDR 0xA4050138UL |
| 272 | #define PORT_PNDR 0xA405013AUL |
| 273 | #define PORT_PQDR 0xA405013CUL |
| 274 | #define PORT_PRDR 0xA405013EUL |
| 275 | #define PORT_PTDR 0xA405016CUL |
| 276 | #define PORT_PUDR 0xA405016EUL |
| 277 | #define PORT_PVDR 0xA4050170UL |
| 278 | |
| 279 | #define IRQ0_IRQ 32 |
| 280 | #define IRQ1_IRQ 33 |
| 281 | #define IRQ2_IRQ 34 |
| 282 | #define IRQ3_IRQ 35 |
| 283 | #define IRQ4_IRQ 36 |
| 284 | #define IRQ5_IRQ 37 |
| 285 | #define IRQ6_IRQ 38 |
| 286 | #define IRQ7_IRQ 39 |
| 287 | |
| 288 | #define INTPRI00 0xA4140010UL |
| 289 | |
| 290 | #define IRQ0_IPR_ADDR INTPRI00 |
| 291 | #define IRQ1_IPR_ADDR INTPRI00 |
| 292 | #define IRQ2_IPR_ADDR INTPRI00 |
| 293 | #define IRQ3_IPR_ADDR INTPRI00 |
| 294 | #define IRQ4_IPR_ADDR INTPRI00 |
| 295 | #define IRQ5_IPR_ADDR INTPRI00 |
| 296 | #define IRQ6_IPR_ADDR INTPRI00 |
| 297 | #define IRQ7_IPR_ADDR INTPRI00 |
| 298 | |
| 299 | #define IRQ0_IPR_POS 7 |
| 300 | #define IRQ1_IPR_POS 6 |
| 301 | #define IRQ2_IPR_POS 5 |
| 302 | #define IRQ3_IPR_POS 4 |
| 303 | #define IRQ4_IPR_POS 3 |
| 304 | #define IRQ5_IPR_POS 2 |
| 305 | #define IRQ6_IPR_POS 1 |
| 306 | #define IRQ7_IPR_POS 0 |
| 307 | |
| 308 | #define IRQ0_PRIORITY 1 |
| 309 | #define IRQ1_PRIORITY 1 |
| 310 | #define IRQ2_PRIORITY 1 |
| 311 | #define IRQ3_PRIORITY 1 |
| 312 | #define IRQ4_PRIORITY 1 |
| 313 | #define IRQ5_PRIORITY 1 |
| 314 | #define IRQ6_PRIORITY 1 |
| 315 | #define IRQ7_PRIORITY 1 |
| 316 | |
| 317 | #endif /* __ASM_SH_IRQ_SH7343_H */ |