blob: a5df24c578fc8b65b8945781a0cacb6e6bb33977 [file] [log] [blame]
Alexander Shishkine443b332012-05-11 17:25:46 +03001/*
2 * core.c - ChipIdea USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * Description: ChipIdea USB IP core family device controller
15 *
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
19 * - UTIL: utilities
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
24 *
25 * Compile Options
26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
29 * => case 4: Hi > Dn
30 * => case 5: Hi > Di
31 * => case 8: Hi <> Do
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
34 *
35 * Main Features
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
39 *
40 * USBTEST Report
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
43 *
44 * TODO List
45 * - OTG
Michael Grzeschike4ce4ec2013-06-13 17:59:47 +030046 * - Interrupt Traffic
Alexander Shishkine443b332012-05-11 17:25:46 +030047 * - GET_STATUS(device) - always reports 0
48 * - Gadget API (majority of optional features)
49 * - Suspend & Remote Wakeup
50 */
51#include <linux/delay.h>
52#include <linux/device.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030053#include <linux/dma-mapping.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030054#include <linux/platform_device.h>
55#include <linux/module.h>
Richard Zhaofe6e1252012-07-07 22:56:42 +080056#include <linux/idr.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030057#include <linux/interrupt.h>
58#include <linux/io.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030059#include <linux/kernel.h>
60#include <linux/slab.h>
61#include <linux/pm_runtime.h>
62#include <linux/usb/ch9.h>
63#include <linux/usb/gadget.h>
64#include <linux/usb/otg.h>
65#include <linux/usb/chipidea.h>
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +030066#include <linux/usb/of.h>
67#include <linux/phy.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030068
69#include "ci.h"
70#include "udc.h"
71#include "bits.h"
Alexander Shishkineb70e5a2012-05-11 17:25:54 +030072#include "host.h"
Alexander Shishkine443b332012-05-11 17:25:46 +030073#include "debug.h"
74
Alexander Shishkin5f36e232012-05-11 17:25:47 +030075/* Controller register map */
Alexander Shishkine443b332012-05-11 17:25:46 +030076static uintptr_t ci_regs_nolpm[] = {
77 [CAP_CAPLENGTH] = 0x000UL,
78 [CAP_HCCPARAMS] = 0x008UL,
79 [CAP_DCCPARAMS] = 0x024UL,
80 [CAP_TESTMODE] = 0x038UL,
81 [OP_USBCMD] = 0x000UL,
82 [OP_USBSTS] = 0x004UL,
83 [OP_USBINTR] = 0x008UL,
84 [OP_DEVICEADDR] = 0x014UL,
85 [OP_ENDPTLISTADDR] = 0x018UL,
86 [OP_PORTSC] = 0x044UL,
87 [OP_DEVLC] = 0x084UL,
Alexander Shishkin5f36e232012-05-11 17:25:47 +030088 [OP_OTGSC] = 0x064UL,
Alexander Shishkine443b332012-05-11 17:25:46 +030089 [OP_USBMODE] = 0x068UL,
90 [OP_ENDPTSETUPSTAT] = 0x06CUL,
91 [OP_ENDPTPRIME] = 0x070UL,
92 [OP_ENDPTFLUSH] = 0x074UL,
93 [OP_ENDPTSTAT] = 0x078UL,
94 [OP_ENDPTCOMPLETE] = 0x07CUL,
95 [OP_ENDPTCTRL] = 0x080UL,
96};
97
98static uintptr_t ci_regs_lpm[] = {
99 [CAP_CAPLENGTH] = 0x000UL,
100 [CAP_HCCPARAMS] = 0x008UL,
101 [CAP_DCCPARAMS] = 0x024UL,
102 [CAP_TESTMODE] = 0x0FCUL,
103 [OP_USBCMD] = 0x000UL,
104 [OP_USBSTS] = 0x004UL,
105 [OP_USBINTR] = 0x008UL,
106 [OP_DEVICEADDR] = 0x014UL,
107 [OP_ENDPTLISTADDR] = 0x018UL,
108 [OP_PORTSC] = 0x044UL,
109 [OP_DEVLC] = 0x084UL,
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300110 [OP_OTGSC] = 0x0C4UL,
Alexander Shishkine443b332012-05-11 17:25:46 +0300111 [OP_USBMODE] = 0x0C8UL,
112 [OP_ENDPTSETUPSTAT] = 0x0D8UL,
113 [OP_ENDPTPRIME] = 0x0DCUL,
114 [OP_ENDPTFLUSH] = 0x0E0UL,
115 [OP_ENDPTSTAT] = 0x0E4UL,
116 [OP_ENDPTCOMPLETE] = 0x0E8UL,
117 [OP_ENDPTCTRL] = 0x0ECUL,
118};
119
Alexander Shishkin8e229782013-06-24 14:46:36 +0300120static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
Alexander Shishkine443b332012-05-11 17:25:46 +0300121{
122 int i;
123
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300124 kfree(ci->hw_bank.regmap);
Alexander Shishkine443b332012-05-11 17:25:46 +0300125
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300126 ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
127 GFP_KERNEL);
128 if (!ci->hw_bank.regmap)
Alexander Shishkine443b332012-05-11 17:25:46 +0300129 return -ENOMEM;
130
131 for (i = 0; i < OP_ENDPTCTRL; i++)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300132 ci->hw_bank.regmap[i] =
133 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
Alexander Shishkine443b332012-05-11 17:25:46 +0300134 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
135
136 for (; i <= OP_LAST; i++)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300137 ci->hw_bank.regmap[i] = ci->hw_bank.op +
Alexander Shishkine443b332012-05-11 17:25:46 +0300138 4 * (i - OP_ENDPTCTRL) +
139 (is_lpm
140 ? ci_regs_lpm[OP_ENDPTCTRL]
141 : ci_regs_nolpm[OP_ENDPTCTRL]);
142
143 return 0;
144}
145
146/**
147 * hw_port_test_set: writes port test mode (execute without interruption)
148 * @mode: new value
149 *
150 * This function returns an error code
151 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300152int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
Alexander Shishkine443b332012-05-11 17:25:46 +0300153{
154 const u8 TEST_MODE_MAX = 7;
155
156 if (mode > TEST_MODE_MAX)
157 return -EINVAL;
158
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200159 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
Alexander Shishkine443b332012-05-11 17:25:46 +0300160 return 0;
161}
162
163/**
164 * hw_port_test_get: reads port test mode value
165 *
166 * This function returns port test mode value
167 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300168u8 hw_port_test_get(struct ci_hdrc *ci)
Alexander Shishkine443b332012-05-11 17:25:46 +0300169{
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200170 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
Alexander Shishkine443b332012-05-11 17:25:46 +0300171}
172
Alexander Shishkin8e229782013-06-24 14:46:36 +0300173static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
Alexander Shishkine443b332012-05-11 17:25:46 +0300174{
175 u32 reg;
176
177 /* bank is a module variable */
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300178 ci->hw_bank.abs = base;
Alexander Shishkine443b332012-05-11 17:25:46 +0300179
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300180 ci->hw_bank.cap = ci->hw_bank.abs;
Richard Zhao77c44002012-06-29 17:48:53 +0800181 ci->hw_bank.cap += ci->platdata->capoffset;
Svetoslav Neykov938d3232013-03-30 12:54:03 +0200182 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
Alexander Shishkine443b332012-05-11 17:25:46 +0300183
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300184 hw_alloc_regmap(ci, false);
185 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200186 __ffs(HCCPARAMS_LEN);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300187 ci->hw_bank.lpm = reg;
188 hw_alloc_regmap(ci, !!reg);
189 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
190 ci->hw_bank.size += OP_LAST;
191 ci->hw_bank.size /= sizeof(u32);
Alexander Shishkine443b332012-05-11 17:25:46 +0300192
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300193 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200194 __ffs(DCCPARAMS_DEN);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300195 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
Alexander Shishkine443b332012-05-11 17:25:46 +0300196
Richard Zhao09c94e62012-05-15 21:58:18 +0800197 if (ci->hw_ep_max > ENDPT_MAX)
Alexander Shishkine443b332012-05-11 17:25:46 +0300198 return -ENODEV;
199
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300200 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
201 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
Alexander Shishkine443b332012-05-11 17:25:46 +0300202
203 /* setup lock mode ? */
204
205 /* ENDPTSETUPSTAT is '0' by default */
206
207 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
208
209 return 0;
210}
211
Alexander Shishkin8e229782013-06-24 14:46:36 +0300212static void hw_phymode_configure(struct ci_hdrc *ci)
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300213{
214 u32 portsc, lpm, sts;
215
216 switch (ci->platdata->phy_mode) {
217 case USBPHY_INTERFACE_MODE_UTMI:
218 portsc = PORTSC_PTS(PTS_UTMI);
219 lpm = DEVLC_PTS(PTS_UTMI);
220 break;
221 case USBPHY_INTERFACE_MODE_UTMIW:
222 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
223 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
224 break;
225 case USBPHY_INTERFACE_MODE_ULPI:
226 portsc = PORTSC_PTS(PTS_ULPI);
227 lpm = DEVLC_PTS(PTS_ULPI);
228 break;
229 case USBPHY_INTERFACE_MODE_SERIAL:
230 portsc = PORTSC_PTS(PTS_SERIAL);
231 lpm = DEVLC_PTS(PTS_SERIAL);
232 sts = 1;
233 break;
234 case USBPHY_INTERFACE_MODE_HSIC:
235 portsc = PORTSC_PTS(PTS_HSIC);
236 lpm = DEVLC_PTS(PTS_HSIC);
237 break;
238 default:
239 return;
240 }
241
242 if (ci->hw_bank.lpm) {
243 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
244 hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
245 } else {
246 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
247 hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
248 }
249}
250
Alexander Shishkine443b332012-05-11 17:25:46 +0300251/**
252 * hw_device_reset: resets chip (execute without interruption)
253 * @ci: the controller
254 *
255 * This function returns an error code
256 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300257int hw_device_reset(struct ci_hdrc *ci, u32 mode)
Alexander Shishkine443b332012-05-11 17:25:46 +0300258{
259 /* should flush & stop before reset */
260 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
261 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
262
263 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
264 while (hw_read(ci, OP_USBCMD, USBCMD_RST))
265 udelay(10); /* not RTOS friendly */
266
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300267 hw_phymode_configure(ci);
Alexander Shishkine443b332012-05-11 17:25:46 +0300268
Richard Zhao77c44002012-06-29 17:48:53 +0800269 if (ci->platdata->notify_event)
270 ci->platdata->notify_event(ci,
Alexander Shishkin8e229782013-06-24 14:46:36 +0300271 CI_HDRC_CONTROLLER_RESET_EVENT);
Alexander Shishkine443b332012-05-11 17:25:46 +0300272
Alexander Shishkin8e229782013-06-24 14:46:36 +0300273 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
Alexander Shishkin758fc982012-05-11 17:25:53 +0300274 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
Alexander Shishkine443b332012-05-11 17:25:46 +0300275
276 /* USBMODE should be configured step by step */
277 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300278 hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
Alexander Shishkine443b332012-05-11 17:25:46 +0300279 /* HW >= 2.3 */
280 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
281
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300282 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
283 pr_err("cannot enter in %s mode", ci_role(ci)->name);
Alexander Shishkine443b332012-05-11 17:25:46 +0300284 pr_err("lpm = %i", ci->hw_bank.lpm);
285 return -ENODEV;
286 }
287
288 return 0;
289}
290
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300291/**
292 * ci_otg_role - pick role based on ID pin state
293 * @ci: the controller
294 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300295static enum ci_role ci_otg_role(struct ci_hdrc *ci)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300296{
297 u32 sts = hw_read(ci, OP_OTGSC, ~0);
298 enum ci_role role = sts & OTGSC_ID
299 ? CI_ROLE_GADGET
300 : CI_ROLE_HOST;
301
302 return role;
303}
304
305/**
306 * ci_role_work - perform role changing based on ID pin
307 * @work: work struct
308 */
309static void ci_role_work(struct work_struct *work)
310{
Alexander Shishkin8e229782013-06-24 14:46:36 +0300311 struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300312 enum ci_role role = ci_otg_role(ci);
313
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300314 if (role != ci->role) {
315 dev_dbg(ci->dev, "switching from %s to %s\n",
316 ci_role(ci)->name, ci->roles[role]->name);
317
318 ci_role_stop(ci);
319 ci_role_start(ci, role);
320 }
Alexander Shishkin0c3f3dc2013-06-11 13:41:48 +0300321
322 enable_irq(ci->irq);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300323}
324
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300325static irqreturn_t ci_irq(int irq, void *data)
326{
Alexander Shishkin8e229782013-06-24 14:46:36 +0300327 struct ci_hdrc *ci = data;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300328 irqreturn_t ret = IRQ_NONE;
Richard Zhaob183c192012-09-12 14:58:11 +0300329 u32 otgsc = 0;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300330
Richard Zhaob183c192012-09-12 14:58:11 +0300331 if (ci->is_otg)
332 otgsc = hw_read(ci, OP_OTGSC, ~0);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300333
Richard Zhaob183c192012-09-12 14:58:11 +0300334 if (ci->role != CI_ROLE_END)
335 ret = ci_role(ci)->irq(ci);
336
337 if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
338 hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
339 disable_irq_nosync(ci->irq);
340 queue_work(ci->wq, &ci->work);
341 ret = IRQ_HANDLED;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300342 }
343
Richard Zhaob183c192012-09-12 14:58:11 +0300344 return ret;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300345}
346
Richard Zhaofe6e1252012-07-07 22:56:42 +0800347static DEFINE_IDA(ci_ida);
348
Alexander Shishkin8e229782013-06-24 14:46:36 +0300349struct platform_device *ci_hdrc_add_device(struct device *dev,
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800350 struct resource *res, int nres,
Alexander Shishkin8e229782013-06-24 14:46:36 +0300351 struct ci_hdrc_platform_data *platdata)
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800352{
353 struct platform_device *pdev;
Richard Zhaofe6e1252012-07-07 22:56:42 +0800354 int id, ret;
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800355
Richard Zhaofe6e1252012-07-07 22:56:42 +0800356 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
357 if (id < 0)
358 return ERR_PTR(id);
359
360 pdev = platform_device_alloc("ci_hdrc", id);
361 if (!pdev) {
362 ret = -ENOMEM;
363 goto put_id;
364 }
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800365
366 pdev->dev.parent = dev;
367 pdev->dev.dma_mask = dev->dma_mask;
368 pdev->dev.dma_parms = dev->dma_parms;
369 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
370
371 ret = platform_device_add_resources(pdev, res, nres);
372 if (ret)
373 goto err;
374
375 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
376 if (ret)
377 goto err;
378
379 ret = platform_device_add(pdev);
380 if (ret)
381 goto err;
382
383 return pdev;
384
385err:
386 platform_device_put(pdev);
Richard Zhaofe6e1252012-07-07 22:56:42 +0800387put_id:
388 ida_simple_remove(&ci_ida, id);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800389 return ERR_PTR(ret);
390}
Alexander Shishkin8e229782013-06-24 14:46:36 +0300391EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800392
Alexander Shishkin8e229782013-06-24 14:46:36 +0300393void ci_hdrc_remove_device(struct platform_device *pdev)
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800394{
Lothar Waßmann98c35532012-11-22 10:11:25 +0100395 int id = pdev->id;
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800396 platform_device_unregister(pdev);
Lothar Waßmann98c35532012-11-22 10:11:25 +0100397 ida_simple_remove(&ci_ida, id);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800398}
Alexander Shishkin8e229782013-06-24 14:46:36 +0300399EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800400
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500401static int ci_hdrc_probe(struct platform_device *pdev)
Alexander Shishkine443b332012-05-11 17:25:46 +0300402{
403 struct device *dev = &pdev->dev;
Alexander Shishkin8e229782013-06-24 14:46:36 +0300404 struct ci_hdrc *ci;
Alexander Shishkine443b332012-05-11 17:25:46 +0300405 struct resource *res;
406 void __iomem *base;
407 int ret;
Sascha Hauer691962d2013-06-13 17:59:57 +0300408 enum usb_dr_mode dr_mode;
Alexander Shishkine443b332012-05-11 17:25:46 +0300409
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300410 if (!dev->platform_data) {
Alexander Shishkine443b332012-05-11 17:25:46 +0300411 dev_err(dev, "platform data missing\n");
412 return -ENODEV;
413 }
414
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300415 if (!dev->of_node && dev->parent)
416 dev->of_node = dev->parent->of_node;
417
Alexander Shishkine443b332012-05-11 17:25:46 +0300418 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Felipe Balbi19290812013-03-30 02:46:27 +0200419 base = devm_ioremap_resource(dev, res);
420 if (IS_ERR(base))
421 return PTR_ERR(base);
Alexander Shishkine443b332012-05-11 17:25:46 +0300422
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300423 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
424 if (!ci) {
425 dev_err(dev, "can't allocate device\n");
426 return -ENOMEM;
Alexander Shishkine443b332012-05-11 17:25:46 +0300427 }
428
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300429 ci->dev = dev;
Richard Zhao77c44002012-06-29 17:48:53 +0800430 ci->platdata = dev->platform_data;
Richard Zhaoa2c3d692012-07-07 22:56:46 +0800431 if (ci->platdata->phy)
432 ci->transceiver = ci->platdata->phy;
433 else
434 ci->global_phy = true;
Alexander Shishkine443b332012-05-11 17:25:46 +0300435
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300436 ret = hw_device_init(ci, base);
437 if (ret < 0) {
438 dev_err(dev, "can't initialize hardware\n");
439 return -ENODEV;
440 }
441
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300442 ci->hw_bank.phys = res->start;
443
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300444 ci->irq = platform_get_irq(pdev, 0);
445 if (ci->irq < 0) {
446 dev_err(dev, "missing IRQ\n");
447 return -ENODEV;
448 }
449
450 INIT_WORK(&ci->work, ci_role_work);
451 ci->wq = create_singlethread_workqueue("ci_otg");
452 if (!ci->wq) {
453 dev_err(dev, "can't create workqueue\n");
454 return -ENODEV;
455 }
456
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300457 if (!ci->platdata->phy_mode)
458 ci->platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
459
Sascha Hauer691962d2013-06-13 17:59:57 +0300460 if (!ci->platdata->dr_mode)
461 ci->platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300462
Sascha Hauer691962d2013-06-13 17:59:57 +0300463 if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
464 ci->platdata->dr_mode = USB_DR_MODE_OTG;
465
466 dr_mode = ci->platdata->dr_mode;
467 /* initialize role(s) before the interrupt is requested */
468 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
469 ret = ci_hdrc_host_init(ci);
470 if (ret)
471 dev_info(dev, "doesn't support host\n");
472 }
473
474 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
475 ret = ci_hdrc_gadget_init(ci);
476 if (ret)
477 dev_info(dev, "doesn't support gadget\n");
478 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300479
480 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
481 dev_err(dev, "no supported roles\n");
482 ret = -ENODEV;
483 goto rm_wq;
484 }
485
486 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
487 ci->is_otg = true;
Richard Zhao86ad01a2012-09-12 14:58:07 +0300488 /* ID pin needs 1ms debouce time, we delay 2ms for safe */
489 mdelay(2);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300490 ci->role = ci_otg_role(ci);
491 } else {
492 ci->role = ci->roles[CI_ROLE_HOST]
493 ? CI_ROLE_HOST
494 : CI_ROLE_GADGET;
495 }
496
497 ret = ci_role_start(ci, ci->role);
498 if (ret) {
499 dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
500 ret = -ENODEV;
501 goto rm_wq;
502 }
503
504 platform_set_drvdata(pdev, ci);
Richard Zhao77c44002012-06-29 17:48:53 +0800505 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300506 ci);
507 if (ret)
508 goto stop;
509
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300510 if (ci->is_otg)
511 hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);
512
Alexander Shishkinadf0f732013-03-30 12:53:53 +0200513 ret = dbg_create_files(ci);
514 if (!ret)
515 return 0;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300516
Alexander Shishkinadf0f732013-03-30 12:53:53 +0200517 free_irq(ci->irq, ci);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300518stop:
519 ci_role_stop(ci);
520rm_wq:
521 flush_workqueue(ci->wq);
522 destroy_workqueue(ci->wq);
Alexander Shishkine443b332012-05-11 17:25:46 +0300523
524 return ret;
525}
526
Bill Pembertonfb4e98a2012-11-19 13:26:20 -0500527static int ci_hdrc_remove(struct platform_device *pdev)
Alexander Shishkine443b332012-05-11 17:25:46 +0300528{
Alexander Shishkin8e229782013-06-24 14:46:36 +0300529 struct ci_hdrc *ci = platform_get_drvdata(pdev);
Alexander Shishkine443b332012-05-11 17:25:46 +0300530
Alexander Shishkinadf0f732013-03-30 12:53:53 +0200531 dbg_remove_files(ci);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300532 flush_workqueue(ci->wq);
533 destroy_workqueue(ci->wq);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300534 free_irq(ci->irq, ci);
535 ci_role_stop(ci);
Alexander Shishkine443b332012-05-11 17:25:46 +0300536
537 return 0;
538}
539
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300540static struct platform_driver ci_hdrc_driver = {
541 .probe = ci_hdrc_probe,
Bill Pemberton76904172012-11-19 13:21:08 -0500542 .remove = ci_hdrc_remove,
Alexander Shishkine443b332012-05-11 17:25:46 +0300543 .driver = {
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300544 .name = "ci_hdrc",
Alexander Shishkine443b332012-05-11 17:25:46 +0300545 },
546};
547
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300548module_platform_driver(ci_hdrc_driver);
Alexander Shishkine443b332012-05-11 17:25:46 +0300549
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300550MODULE_ALIAS("platform:ci_hdrc");
Alexander Shishkine443b332012-05-11 17:25:46 +0300551MODULE_ALIAS("platform:ci13xxx");
552MODULE_LICENSE("GPL v2");
553MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300554MODULE_DESCRIPTION("ChipIdea HDRC Driver");