blob: be53d98fa38466992e762ca029d7c32007998d88 [file] [log] [blame]
Shaohua Li7d715a62008-02-25 09:46:41 +08001/*
2 * File: drivers/pci/pcie/aspm.c
Stefan Assmann45e829e2009-12-03 06:49:24 -05003 * Enabling PCIe link L0s/L1 state and Clock Power Management
Shaohua Li7d715a62008-02-25 09:46:41 +08004 *
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/pci_regs.h>
15#include <linux/errno.h>
16#include <linux/pm.h>
17#include <linux/init.h>
18#include <linux/slab.h>
Thomas Renninger2a42d9d2008-12-09 13:05:09 +010019#include <linux/jiffies.h>
Andrew Patterson987a4c72009-01-05 16:21:04 -070020#include <linux/delay.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080021#include <linux/pci-aspm.h>
22#include "../pci.h"
23
24#ifdef MODULE_PARAM_PREFIX
25#undef MODULE_PARAM_PREFIX
26#endif
27#define MODULE_PARAM_PREFIX "pcie_aspm."
28
Kenji Kaneshigeac180182009-08-19 11:02:13 +090029/* Note: those are not register definitions */
30#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32#define ASPM_STATE_L1 (4) /* L1 state */
33#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
34#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1)
35
Kenji Kaneshigeb6c2e542009-05-13 12:14:58 +090036struct aspm_latency {
37 u32 l0s; /* L0s latency (nsec) */
38 u32 l1; /* L1 latency (nsec) */
Shaohua Li7d715a62008-02-25 09:46:41 +080039};
40
41struct pcie_link_state {
Kenji Kaneshige5cde89d2009-05-13 12:17:04 +090042 struct pci_dev *pdev; /* Upstream component of the Link */
Kenji Kaneshige5c92ffb2009-05-13 12:23:57 +090043 struct pcie_link_state *root; /* pointer to the root port link */
Kenji Kaneshige5cde89d2009-05-13 12:17:04 +090044 struct pcie_link_state *parent; /* pointer to the parent Link state */
45 struct list_head sibling; /* node in link_list */
46 struct list_head children; /* list of child link states */
47 struct list_head link; /* node in parent's children list */
Shaohua Li7d715a62008-02-25 09:46:41 +080048
49 /* ASPM state */
Kenji Kaneshigeac180182009-08-19 11:02:13 +090050 u32 aspm_support:3; /* Supported ASPM state */
51 u32 aspm_enabled:3; /* Enabled ASPM state */
52 u32 aspm_capable:3; /* Capable ASPM state with latency */
53 u32 aspm_default:3; /* Default ASPM state by BIOS */
54 u32 aspm_disable:3; /* Disabled ASPM state */
Kenji Kaneshige80bfdbe2009-05-13 12:12:43 +090055
Kenji Kaneshige4d246e42009-05-13 12:15:38 +090056 /* Clock PM state */
57 u32 clkpm_capable:1; /* Clock PM capable? */
58 u32 clkpm_enabled:1; /* Current Clock PM state */
59 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
60
Kenji Kaneshigeac180182009-08-19 11:02:13 +090061 /* Exit latencies */
62 struct aspm_latency latency_up; /* Upstream direction exit latency */
63 struct aspm_latency latency_dw; /* Downstream direction exit latency */
Shaohua Li7d715a62008-02-25 09:46:41 +080064 /*
Kenji Kaneshigeb6c2e542009-05-13 12:14:58 +090065 * Endpoint acceptable latencies. A pcie downstream port only
66 * has one slot under it, so at most there are 8 functions.
Shaohua Li7d715a62008-02-25 09:46:41 +080067 */
Kenji Kaneshigeb6c2e542009-05-13 12:14:58 +090068 struct aspm_latency acceptable[8];
Shaohua Li7d715a62008-02-25 09:46:41 +080069};
70
Shaohua Lid6d38572008-07-23 10:32:42 +080071static int aspm_disabled, aspm_force;
Shaohua Li7d715a62008-02-25 09:46:41 +080072static DEFINE_MUTEX(aspm_lock);
73static LIST_HEAD(link_list);
74
75#define POLICY_DEFAULT 0 /* BIOS default setting */
76#define POLICY_PERFORMANCE 1 /* high performance */
77#define POLICY_POWERSAVE 2 /* high power saving */
78static int aspm_policy;
79static const char *policy_str[] = {
80 [POLICY_DEFAULT] = "default",
81 [POLICY_PERFORMANCE] = "performance",
82 [POLICY_POWERSAVE] = "powersave"
83};
84
Andrew Patterson987a4c72009-01-05 16:21:04 -070085#define LINK_RETRAIN_TIMEOUT HZ
86
Kenji Kaneshige5aa63582009-05-13 12:17:44 +090087static int policy_to_aspm_state(struct pcie_link_state *link)
Shaohua Li7d715a62008-02-25 09:46:41 +080088{
Shaohua Li7d715a62008-02-25 09:46:41 +080089 switch (aspm_policy) {
90 case POLICY_PERFORMANCE:
91 /* Disable ASPM and Clock PM */
92 return 0;
93 case POLICY_POWERSAVE:
94 /* Enable ASPM L0s/L1 */
Kenji Kaneshigeac180182009-08-19 11:02:13 +090095 return ASPM_STATE_ALL;
Shaohua Li7d715a62008-02-25 09:46:41 +080096 case POLICY_DEFAULT:
Kenji Kaneshige5aa63582009-05-13 12:17:44 +090097 return link->aspm_default;
Shaohua Li7d715a62008-02-25 09:46:41 +080098 }
99 return 0;
100}
101
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900102static int policy_to_clkpm_state(struct pcie_link_state *link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800103{
Shaohua Li7d715a62008-02-25 09:46:41 +0800104 switch (aspm_policy) {
105 case POLICY_PERFORMANCE:
106 /* Disable ASPM and Clock PM */
107 return 0;
108 case POLICY_POWERSAVE:
109 /* Disable Clock PM */
110 return 1;
111 case POLICY_DEFAULT:
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900112 return link->clkpm_default;
Shaohua Li7d715a62008-02-25 09:46:41 +0800113 }
114 return 0;
115}
116
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900117static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
Shaohua Li7d715a62008-02-25 09:46:41 +0800118{
Shaohua Li7d715a62008-02-25 09:46:41 +0800119 int pos;
120 u16 reg16;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900121 struct pci_dev *child;
122 struct pci_bus *linkbus = link->pdev->subordinate;
Shaohua Li7d715a62008-02-25 09:46:41 +0800123
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900124 list_for_each_entry(child, &linkbus->devices, bus_list) {
Kenji Kaneshigedb9538a2009-11-11 14:33:30 +0900125 pos = pci_pcie_cap(child);
Shaohua Li7d715a62008-02-25 09:46:41 +0800126 if (!pos)
127 return;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900128 pci_read_config_word(child, pos + PCI_EXP_LNKCTL, &reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800129 if (enable)
130 reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
131 else
132 reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900133 pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800134 }
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900135 link->clkpm_enabled = !!enable;
Shaohua Li7d715a62008-02-25 09:46:41 +0800136}
137
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900138static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
139{
140 /* Don't enable Clock PM if the link is not Clock PM capable */
141 if (!link->clkpm_capable && enable)
142 return;
143 /* Need nothing if the specified equals to current state */
144 if (link->clkpm_enabled == enable)
145 return;
146 pcie_set_clkpm_nocheck(link, enable);
147}
148
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900149static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
Shaohua Li7d715a62008-02-25 09:46:41 +0800150{
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900151 int pos, capable = 1, enabled = 1;
Shaohua Li7d715a62008-02-25 09:46:41 +0800152 u32 reg32;
153 u16 reg16;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900154 struct pci_dev *child;
155 struct pci_bus *linkbus = link->pdev->subordinate;
Shaohua Li7d715a62008-02-25 09:46:41 +0800156
157 /* All functions should have the same cap and state, take the worst */
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900158 list_for_each_entry(child, &linkbus->devices, bus_list) {
Kenji Kaneshigedb9538a2009-11-11 14:33:30 +0900159 pos = pci_pcie_cap(child);
Shaohua Li7d715a62008-02-25 09:46:41 +0800160 if (!pos)
161 return;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900162 pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, &reg32);
Shaohua Li7d715a62008-02-25 09:46:41 +0800163 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
164 capable = 0;
165 enabled = 0;
166 break;
167 }
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900168 pci_read_config_word(child, pos + PCI_EXP_LNKCTL, &reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800169 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
170 enabled = 0;
171 }
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900172 link->clkpm_enabled = enabled;
173 link->clkpm_default = enabled;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900174 link->clkpm_capable = (blacklist) ? 0 : capable;
Shaohua Li46bbdfa2008-12-19 09:27:42 +0800175}
176
Shaohua Li7d715a62008-02-25 09:46:41 +0800177/*
178 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
179 * could use common clock. If they are, configure them to use the
180 * common clock. That will reduce the ASPM state exit latency.
181 */
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900182static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800183{
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900184 int ppos, cpos, same_clock = 1;
185 u16 reg16, parent_reg, child_reg[8];
Thomas Renninger2a42d9d2008-12-09 13:05:09 +0100186 unsigned long start_jiffies;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900187 struct pci_dev *child, *parent = link->pdev;
188 struct pci_bus *linkbus = parent->subordinate;
Shaohua Li7d715a62008-02-25 09:46:41 +0800189 /*
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900190 * All functions of a slot should have the same Slot Clock
Shaohua Li7d715a62008-02-25 09:46:41 +0800191 * Configuration, so just check one function
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900192 */
193 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
Kenji Kaneshige8b064772009-11-11 14:36:52 +0900194 BUG_ON(!pci_is_pcie(child));
Shaohua Li7d715a62008-02-25 09:46:41 +0800195
196 /* Check downstream component if bit Slot Clock Configuration is 1 */
Kenji Kaneshigedb9538a2009-11-11 14:33:30 +0900197 cpos = pci_pcie_cap(child);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900198 pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, &reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800199 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
200 same_clock = 0;
201
202 /* Check upstream component if bit Slot Clock Configuration is 1 */
Kenji Kaneshigedb9538a2009-11-11 14:33:30 +0900203 ppos = pci_pcie_cap(parent);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900204 pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, &reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800205 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
206 same_clock = 0;
207
208 /* Configure downstream component, all functions */
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900209 list_for_each_entry(child, &linkbus->devices, bus_list) {
Kenji Kaneshigedb9538a2009-11-11 14:33:30 +0900210 cpos = pci_pcie_cap(child);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900211 pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, &reg16);
212 child_reg[PCI_FUNC(child->devfn)] = reg16;
Shaohua Li7d715a62008-02-25 09:46:41 +0800213 if (same_clock)
214 reg16 |= PCI_EXP_LNKCTL_CCC;
215 else
216 reg16 &= ~PCI_EXP_LNKCTL_CCC;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900217 pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800218 }
219
220 /* Configure upstream component */
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900221 pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, &reg16);
Thomas Renninger2a42d9d2008-12-09 13:05:09 +0100222 parent_reg = reg16;
Shaohua Li7d715a62008-02-25 09:46:41 +0800223 if (same_clock)
224 reg16 |= PCI_EXP_LNKCTL_CCC;
225 else
226 reg16 &= ~PCI_EXP_LNKCTL_CCC;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900227 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800228
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900229 /* Retrain link */
Shaohua Li7d715a62008-02-25 09:46:41 +0800230 reg16 |= PCI_EXP_LNKCTL_RL;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900231 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800232
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900233 /* Wait for link training end. Break out after waiting for timeout */
Thomas Renninger2a42d9d2008-12-09 13:05:09 +0100234 start_jiffies = jiffies;
Andrew Patterson987a4c72009-01-05 16:21:04 -0700235 for (;;) {
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900236 pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, &reg16);
Shaohua Li7d715a62008-02-25 09:46:41 +0800237 if (!(reg16 & PCI_EXP_LNKSTA_LT))
238 break;
Andrew Patterson987a4c72009-01-05 16:21:04 -0700239 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
240 break;
241 msleep(1);
Shaohua Li7d715a62008-02-25 09:46:41 +0800242 }
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900243 if (!(reg16 & PCI_EXP_LNKSTA_LT))
244 return;
245
246 /* Training failed. Restore common clock configurations */
247 dev_printk(KERN_ERR, &parent->dev,
248 "ASPM: Could not configure common clock\n");
249 list_for_each_entry(child, &linkbus->devices, bus_list) {
Kenji Kaneshigedb9538a2009-11-11 14:33:30 +0900250 cpos = pci_pcie_cap(child);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900251 pci_write_config_word(child, cpos + PCI_EXP_LNKCTL,
252 child_reg[PCI_FUNC(child->devfn)]);
Thomas Renninger2a42d9d2008-12-09 13:05:09 +0100253 }
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900254 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg);
Shaohua Li7d715a62008-02-25 09:46:41 +0800255}
256
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900257/* Convert L0s latency encoding to ns */
258static u32 calc_l0s_latency(u32 encoding)
Shaohua Li7d715a62008-02-25 09:46:41 +0800259{
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900260 if (encoding == 0x7)
261 return (5 * 1000); /* > 4us */
262 return (64 << encoding);
Shaohua Li7d715a62008-02-25 09:46:41 +0800263}
264
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900265/* Convert L0s acceptable latency encoding to ns */
266static u32 calc_l0s_acceptable(u32 encoding)
Shaohua Li7d715a62008-02-25 09:46:41 +0800267{
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900268 if (encoding == 0x7)
269 return -1U;
270 return (64 << encoding);
271}
Shaohua Li7d715a62008-02-25 09:46:41 +0800272
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900273/* Convert L1 latency encoding to ns */
274static u32 calc_l1_latency(u32 encoding)
275{
276 if (encoding == 0x7)
277 return (65 * 1000); /* > 64us */
278 return (1000 << encoding);
279}
280
281/* Convert L1 acceptable latency encoding to ns */
282static u32 calc_l1_acceptable(u32 encoding)
283{
284 if (encoding == 0x7)
285 return -1U;
286 return (1000 << encoding);
Shaohua Li7d715a62008-02-25 09:46:41 +0800287}
288
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900289struct aspm_register_info {
290 u32 support:2;
291 u32 enabled:2;
292 u32 latency_encoding_l0s;
293 u32 latency_encoding_l1;
294};
295
296static void pcie_get_aspm_reg(struct pci_dev *pdev,
297 struct aspm_register_info *info)
Shaohua Li7d715a62008-02-25 09:46:41 +0800298{
299 int pos;
300 u16 reg16;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900301 u32 reg32;
Shaohua Li7d715a62008-02-25 09:46:41 +0800302
Kenji Kaneshigedb9538a2009-11-11 14:33:30 +0900303 pos = pci_pcie_cap(pdev);
Shaohua Li7d715a62008-02-25 09:46:41 +0800304 pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, &reg32);
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900305 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900306 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
307 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
Shaohua Li7d715a62008-02-25 09:46:41 +0800308 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900309 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
Shaohua Li7d715a62008-02-25 09:46:41 +0800310}
311
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900312static void pcie_aspm_check_latency(struct pci_dev *endpoint)
313{
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900314 u32 latency, l1_switch_latency = 0;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900315 struct aspm_latency *acceptable;
316 struct pcie_link_state *link;
317
318 /* Device not in D0 doesn't need latency check */
319 if ((endpoint->current_state != PCI_D0) &&
320 (endpoint->current_state != PCI_UNKNOWN))
321 return;
322
323 link = endpoint->bus->self->link_state;
324 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
325
326 while (link) {
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900327 /* Check upstream direction L0s latency */
328 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
329 (link->latency_up.l0s > acceptable->l0s))
330 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
331
332 /* Check downstream direction L0s latency */
333 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
334 (link->latency_dw.l0s > acceptable->l0s))
335 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900336 /*
337 * Check L1 latency.
338 * Every switch on the path to root complex need 1
339 * more microsecond for L1. Spec doesn't mention L0s.
340 */
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900341 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
342 if ((link->aspm_capable & ASPM_STATE_L1) &&
343 (latency + l1_switch_latency > acceptable->l1))
344 link->aspm_capable &= ~ASPM_STATE_L1;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900345 l1_switch_latency += 1000;
346
347 link = link->parent;
348 }
349}
350
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900351static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
Shaohua Li7d715a62008-02-25 09:46:41 +0800352{
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900353 struct pci_dev *child, *parent = link->pdev;
354 struct pci_bus *linkbus = parent->subordinate;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900355 struct aspm_register_info upreg, dwreg;
Shaohua Li7d715a62008-02-25 09:46:41 +0800356
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900357 if (blacklist) {
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900358 /* Set enabled/disable so that we will disable ASPM later */
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900359 link->aspm_enabled = ASPM_STATE_ALL;
360 link->aspm_disable = ASPM_STATE_ALL;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900361 return;
362 }
363
364 /* Configure common clock before checking latencies */
365 pcie_aspm_configure_common_clock(link);
366
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900367 /* Get upstream/downstream components' register state */
368 pcie_get_aspm_reg(parent, &upreg);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900369 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900370 pcie_get_aspm_reg(child, &dwreg);
371
372 /*
373 * Setup L0s state
374 *
375 * Note that we must not enable L0s in either direction on a
376 * given link unless components on both sides of the link each
377 * support L0s.
378 */
379 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
380 link->aspm_support |= ASPM_STATE_L0S;
381 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
382 link->aspm_enabled |= ASPM_STATE_L0S_UP;
383 if (upreg.enabled & PCIE_LINK_STATE_L0S)
384 link->aspm_enabled |= ASPM_STATE_L0S_DW;
385 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
386 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
387
388 /* Setup L1 state */
389 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
390 link->aspm_support |= ASPM_STATE_L1;
391 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
392 link->aspm_enabled |= ASPM_STATE_L1;
393 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
394 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
Kenji Kaneshige80bfdbe2009-05-13 12:12:43 +0900395
Kenji Kaneshigeb127bd52009-08-19 10:57:31 +0900396 /* Save default state */
397 link->aspm_default = link->aspm_enabled;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900398
399 /* Setup initial capable state. Will be updated later */
400 link->aspm_capable = link->aspm_support;
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900401 /*
402 * If the downstream component has pci bridge function, don't
403 * do ASPM for now.
404 */
405 list_for_each_entry(child, &linkbus->devices, bus_list) {
406 if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900407 link->aspm_disable = ASPM_STATE_ALL;
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900408 break;
409 }
410 }
Kenji Kaneshigeb127bd52009-08-19 10:57:31 +0900411
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900412 /* Get and check endpoint acceptable latencies */
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900413 list_for_each_entry(child, &linkbus->devices, bus_list) {
Shaohua Li7d715a62008-02-25 09:46:41 +0800414 int pos;
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900415 u32 reg32, encoding;
Kenji Kaneshigeb6c2e542009-05-13 12:14:58 +0900416 struct aspm_latency *acceptable =
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900417 &link->acceptable[PCI_FUNC(child->devfn)];
Shaohua Li7d715a62008-02-25 09:46:41 +0800418
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900419 if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
420 child->pcie_type != PCI_EXP_TYPE_LEG_END)
Shaohua Li7d715a62008-02-25 09:46:41 +0800421 continue;
422
Kenji Kaneshigedb9538a2009-11-11 14:33:30 +0900423 pos = pci_pcie_cap(child);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900424 pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, &reg32);
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900425 /* Calculate endpoint L0s acceptable latency */
Kenji Kaneshige5e0eaa72009-05-13 12:21:48 +0900426 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
427 acceptable->l0s = calc_l0s_acceptable(encoding);
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900428 /* Calculate endpoint L1 acceptable latency */
429 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
430 acceptable->l1 = calc_l1_acceptable(encoding);
431
432 pcie_aspm_check_latency(child);
Shaohua Li7d715a62008-02-25 09:46:41 +0800433 }
434}
435
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900436static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
Shaohua Li7d715a62008-02-25 09:46:41 +0800437{
438 u16 reg16;
Kenji Kaneshigedb9538a2009-11-11 14:33:30 +0900439 int pos = pci_pcie_cap(pdev);
Shaohua Li7d715a62008-02-25 09:46:41 +0800440
441 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
442 reg16 &= ~0x3;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900443 reg16 |= val;
Shaohua Li7d715a62008-02-25 09:46:41 +0800444 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
445}
446
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900447static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
Shaohua Li7d715a62008-02-25 09:46:41 +0800448{
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900449 u32 upstream = 0, dwstream = 0;
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900450 struct pci_dev *child, *parent = link->pdev;
451 struct pci_bus *linkbus = parent->subordinate;
Shaohua Li7d715a62008-02-25 09:46:41 +0800452
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900453 /* Nothing to do if the link is already in the requested state */
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900454 state &= (link->aspm_capable & ~link->aspm_disable);
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900455 if (link->aspm_enabled == state)
456 return;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900457 /* Convert ASPM state to upstream/downstream ASPM register state */
458 if (state & ASPM_STATE_L0S_UP)
459 dwstream |= PCIE_LINK_STATE_L0S;
460 if (state & ASPM_STATE_L0S_DW)
461 upstream |= PCIE_LINK_STATE_L0S;
462 if (state & ASPM_STATE_L1) {
463 upstream |= PCIE_LINK_STATE_L1;
464 dwstream |= PCIE_LINK_STATE_L1;
465 }
Shaohua Li7d715a62008-02-25 09:46:41 +0800466 /*
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900467 * Spec 2.0 suggests all functions should be configured the
468 * same setting for ASPM. Enabling ASPM L1 should be done in
469 * upstream component first and then downstream, and vice
470 * versa for disabling ASPM L1. Spec doesn't mention L0S.
Shaohua Li7d715a62008-02-25 09:46:41 +0800471 */
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900472 if (state & ASPM_STATE_L1)
473 pcie_config_aspm_dev(parent, upstream);
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900474 list_for_each_entry(child, &linkbus->devices, bus_list)
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900475 pcie_config_aspm_dev(child, dwstream);
476 if (!(state & ASPM_STATE_L1))
477 pcie_config_aspm_dev(parent, upstream);
Shaohua Li7d715a62008-02-25 09:46:41 +0800478
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900479 link->aspm_enabled = state;
Shaohua Li7d715a62008-02-25 09:46:41 +0800480}
481
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900482static void pcie_config_aspm_path(struct pcie_link_state *link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800483{
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900484 while (link) {
485 pcie_config_aspm_link(link, policy_to_aspm_state(link));
486 link = link->parent;
Shaohua Li46bbdfa2008-12-19 09:27:42 +0800487 }
Shaohua Li7d715a62008-02-25 09:46:41 +0800488}
489
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900490static void free_link_state(struct pcie_link_state *link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800491{
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900492 link->pdev->link_state = NULL;
493 kfree(link);
Shaohua Li7d715a62008-02-25 09:46:41 +0800494}
495
Shaohua Liddc97532008-05-21 16:58:40 +0800496static int pcie_aspm_sanity_check(struct pci_dev *pdev)
497{
Kenji Kaneshige36475842009-05-13 12:23:09 +0900498 struct pci_dev *child;
499 int pos;
Shaohua Li149e1632008-07-23 10:32:31 +0800500 u32 reg32;
Shaohua Liddc97532008-05-21 16:58:40 +0800501 /*
Stefan Assmann45e829e2009-12-03 06:49:24 -0500502 * Some functions in a slot might not all be PCIe functions,
Kenji Kaneshige36475842009-05-13 12:23:09 +0900503 * very strange. Disable ASPM for the whole slot
Shaohua Liddc97532008-05-21 16:58:40 +0800504 */
Kenji Kaneshige36475842009-05-13 12:23:09 +0900505 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
Kenji Kaneshigedb9538a2009-11-11 14:33:30 +0900506 pos = pci_pcie_cap(child);
Kenji Kaneshige36475842009-05-13 12:23:09 +0900507 if (!pos)
Shaohua Liddc97532008-05-21 16:58:40 +0800508 return -EINVAL;
Shaohua Li149e1632008-07-23 10:32:31 +0800509 /*
510 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
511 * RBER bit to determine if a function is 1.1 version device
512 */
Kenji Kaneshige36475842009-05-13 12:23:09 +0900513 pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, &reg32);
Sitsofe Wheelere1f4f592008-09-16 14:27:13 +0100514 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
Kenji Kaneshige36475842009-05-13 12:23:09 +0900515 dev_printk(KERN_INFO, &child->dev, "disabling ASPM"
Vincent Legollf393d9b2008-10-12 12:26:12 +0200516 " on pre-1.1 PCIe device. You can enable it"
517 " with 'pcie_aspm=force'\n");
Shaohua Li149e1632008-07-23 10:32:31 +0800518 return -EINVAL;
519 }
Shaohua Liddc97532008-05-21 16:58:40 +0800520 }
521 return 0;
522}
523
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900524static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900525{
526 struct pcie_link_state *link;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900527
528 link = kzalloc(sizeof(*link), GFP_KERNEL);
529 if (!link)
530 return NULL;
531 INIT_LIST_HEAD(&link->sibling);
532 INIT_LIST_HEAD(&link->children);
533 INIT_LIST_HEAD(&link->link);
534 link->pdev = pdev;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900535 if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) {
536 struct pcie_link_state *parent;
537 parent = pdev->bus->parent->self->link_state;
538 if (!parent) {
539 kfree(link);
540 return NULL;
541 }
542 link->parent = parent;
543 list_add(&link->link, &parent->children);
544 }
Kenji Kaneshige5c92ffb2009-05-13 12:23:57 +0900545 /* Setup a pointer to the root port link */
546 if (!link->parent)
547 link->root = link;
548 else
549 link->root = link->parent->root;
550
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900551 list_add(&link->sibling, &link_list);
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900552 pdev->link_state = link;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900553 return link;
554}
555
Shaohua Li7d715a62008-02-25 09:46:41 +0800556/*
557 * pcie_aspm_init_link_state: Initiate PCI express link state.
558 * It is called after the pcie and its children devices are scaned.
559 * @pdev: the root port or switch downstream port
560 */
561void pcie_aspm_init_link_state(struct pci_dev *pdev)
562{
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900563 struct pcie_link_state *link;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900564 int blacklist = !!pcie_aspm_sanity_check(pdev);
Shaohua Li7d715a62008-02-25 09:46:41 +0800565
Kenji Kaneshige8b064772009-11-11 14:36:52 +0900566 if (aspm_disabled || !pci_is_pcie(pdev) || pdev->link_state)
Shaohua Li7d715a62008-02-25 09:46:41 +0800567 return;
568 if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900569 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
Shaohua Li7d715a62008-02-25 09:46:41 +0800570 return;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900571
Shaohua Li8e822df2009-06-08 09:27:25 +0800572 /* VIA has a strange chipset, root port is under a bridge */
573 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT &&
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900574 pdev->bus->self)
Shaohua Li8e822df2009-06-08 09:27:25 +0800575 return;
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900576
Shaohua Li7d715a62008-02-25 09:46:41 +0800577 down_read(&pci_bus_sem);
578 if (list_empty(&pdev->subordinate->devices))
579 goto out;
580
Shaohua Li7d715a62008-02-25 09:46:41 +0800581 mutex_lock(&aspm_lock);
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900582 link = alloc_pcie_link_state(pdev);
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900583 if (!link)
584 goto unlock;
585 /*
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900586 * Setup initial ASPM state. Note that we need to configure
587 * upstream links also because capable state of them can be
588 * update through pcie_aspm_cap_init().
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900589 */
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900590 pcie_aspm_cap_init(link, blacklist);
591 pcie_config_aspm_path(link);
Shaohua Li7d715a62008-02-25 09:46:41 +0800592
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900593 /* Setup initial Clock PM state */
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900594 pcie_clkpm_cap_init(link, blacklist);
595 pcie_set_clkpm(link, policy_to_clkpm_state(link));
Kenji Kaneshige8d349ac2009-05-13 12:18:22 +0900596unlock:
Shaohua Li7d715a62008-02-25 09:46:41 +0800597 mutex_unlock(&aspm_lock);
598out:
599 up_read(&pci_bus_sem);
600}
601
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900602/* Recheck latencies and update aspm_capable for links under the root */
603static void pcie_update_aspm_capable(struct pcie_link_state *root)
604{
605 struct pcie_link_state *link;
606 BUG_ON(root->parent);
607 list_for_each_entry(link, &link_list, sibling) {
608 if (link->root != root)
609 continue;
610 link->aspm_capable = link->aspm_support;
611 }
612 list_for_each_entry(link, &link_list, sibling) {
613 struct pci_dev *child;
614 struct pci_bus *linkbus = link->pdev->subordinate;
615 if (link->root != root)
616 continue;
617 list_for_each_entry(child, &linkbus->devices, bus_list) {
618 if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT) &&
619 (child->pcie_type != PCI_EXP_TYPE_LEG_END))
620 continue;
621 pcie_aspm_check_latency(child);
622 }
623 }
624}
625
Shaohua Li7d715a62008-02-25 09:46:41 +0800626/* @pdev: the endpoint device */
627void pcie_aspm_exit_link_state(struct pci_dev *pdev)
628{
629 struct pci_dev *parent = pdev->bus->self;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900630 struct pcie_link_state *link, *root, *parent_link;
Shaohua Li7d715a62008-02-25 09:46:41 +0800631
Kenji Kaneshige8b064772009-11-11 14:36:52 +0900632 if (aspm_disabled || !pci_is_pcie(pdev) ||
633 !parent || !parent->link_state)
Shaohua Li7d715a62008-02-25 09:46:41 +0800634 return;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900635 if ((parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
636 (parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
Shaohua Li7d715a62008-02-25 09:46:41 +0800637 return;
Kenji Kaneshigefc87e912009-08-19 10:58:46 +0900638
Shaohua Li7d715a62008-02-25 09:46:41 +0800639 down_read(&pci_bus_sem);
640 mutex_lock(&aspm_lock);
Shaohua Li7d715a62008-02-25 09:46:41 +0800641 /*
642 * All PCIe functions are in one slot, remove one function will remove
Alex Chiang3419c752009-01-28 14:59:18 -0700643 * the whole slot, so just wait until we are the last function left.
Shaohua Li7d715a62008-02-25 09:46:41 +0800644 */
Alex Chiang3419c752009-01-28 14:59:18 -0700645 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
Shaohua Li7d715a62008-02-25 09:46:41 +0800646 goto out;
647
Kenji Kaneshigefc87e912009-08-19 10:58:46 +0900648 link = parent->link_state;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900649 root = link->root;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900650 parent_link = link->parent;
Kenji Kaneshigefc87e912009-08-19 10:58:46 +0900651
Shaohua Li7d715a62008-02-25 09:46:41 +0800652 /* All functions are removed, so just disable ASPM for the link */
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900653 pcie_config_aspm_link(link, 0);
Kenji Kaneshigefc87e912009-08-19 10:58:46 +0900654 list_del(&link->sibling);
655 list_del(&link->link);
Shaohua Li7d715a62008-02-25 09:46:41 +0800656 /* Clock PM is for endpoint device */
Kenji Kaneshigefc87e912009-08-19 10:58:46 +0900657 free_link_state(link);
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900658
659 /* Recheck latencies and configure upstream links */
Kenji Kaneshigeb26a34a2009-11-06 11:25:13 +0900660 if (parent_link) {
661 pcie_update_aspm_capable(root);
662 pcie_config_aspm_path(parent_link);
663 }
Shaohua Li7d715a62008-02-25 09:46:41 +0800664out:
665 mutex_unlock(&aspm_lock);
666 up_read(&pci_bus_sem);
667}
668
669/* @pdev: the root port or switch downstream port */
670void pcie_aspm_pm_state_change(struct pci_dev *pdev)
671{
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900672 struct pcie_link_state *link = pdev->link_state;
Shaohua Li7d715a62008-02-25 09:46:41 +0800673
Kenji Kaneshige8b064772009-11-11 14:36:52 +0900674 if (aspm_disabled || !pci_is_pcie(pdev) || !link)
Shaohua Li7d715a62008-02-25 09:46:41 +0800675 return;
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900676 if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
677 (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
Shaohua Li7d715a62008-02-25 09:46:41 +0800678 return;
679 /*
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900680 * Devices changed PM state, we should recheck if latency
681 * meets all functions' requirement
Shaohua Li7d715a62008-02-25 09:46:41 +0800682 */
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900683 down_read(&pci_bus_sem);
684 mutex_lock(&aspm_lock);
685 pcie_update_aspm_capable(link->root);
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900686 pcie_config_aspm_path(link);
Kenji Kaneshige07d92762009-08-19 11:00:25 +0900687 mutex_unlock(&aspm_lock);
688 up_read(&pci_bus_sem);
Shaohua Li7d715a62008-02-25 09:46:41 +0800689}
690
691/*
692 * pci_disable_link_state - disable pci device's link state, so the link will
693 * never enter specific states
694 */
695void pci_disable_link_state(struct pci_dev *pdev, int state)
696{
697 struct pci_dev *parent = pdev->bus->self;
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900698 struct pcie_link_state *link;
Shaohua Li7d715a62008-02-25 09:46:41 +0800699
Kenji Kaneshige8b064772009-11-11 14:36:52 +0900700 if (aspm_disabled || !pci_is_pcie(pdev))
Shaohua Li7d715a62008-02-25 09:46:41 +0800701 return;
702 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
703 pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
704 parent = pdev;
705 if (!parent || !parent->link_state)
706 return;
707
708 down_read(&pci_bus_sem);
709 mutex_lock(&aspm_lock);
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900710 link = parent->link_state;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900711 if (state & PCIE_LINK_STATE_L0S)
712 link->aspm_disable |= ASPM_STATE_L0S;
713 if (state & PCIE_LINK_STATE_L1)
714 link->aspm_disable |= ASPM_STATE_L1;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900715 pcie_config_aspm_link(link, policy_to_aspm_state(link));
716
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900717 if (state & PCIE_LINK_STATE_CLKPM) {
Kenji Kaneshigef1c0ca22009-08-19 10:59:52 +0900718 link->clkpm_capable = 0;
719 pcie_set_clkpm(link, 0);
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900720 }
Shaohua Li7d715a62008-02-25 09:46:41 +0800721 mutex_unlock(&aspm_lock);
722 up_read(&pci_bus_sem);
723}
724EXPORT_SYMBOL(pci_disable_link_state);
725
726static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
727{
728 int i;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900729 struct pcie_link_state *link;
Shaohua Li7d715a62008-02-25 09:46:41 +0800730
731 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
732 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
733 break;
734 if (i >= ARRAY_SIZE(policy_str))
735 return -EINVAL;
736 if (i == aspm_policy)
737 return 0;
738
739 down_read(&pci_bus_sem);
740 mutex_lock(&aspm_lock);
741 aspm_policy = i;
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900742 list_for_each_entry(link, &link_list, sibling) {
743 pcie_config_aspm_link(link, policy_to_aspm_state(link));
744 pcie_set_clkpm(link, policy_to_clkpm_state(link));
Shaohua Li7d715a62008-02-25 09:46:41 +0800745 }
746 mutex_unlock(&aspm_lock);
747 up_read(&pci_bus_sem);
748 return 0;
749}
750
751static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
752{
753 int i, cnt = 0;
754 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
755 if (i == aspm_policy)
756 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
757 else
758 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
759 return cnt;
760}
761
762module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
763 NULL, 0644);
764
765#ifdef CONFIG_PCIEASPM_DEBUG
766static ssize_t link_state_show(struct device *dev,
767 struct device_attribute *attr,
768 char *buf)
769{
770 struct pci_dev *pci_device = to_pci_dev(dev);
771 struct pcie_link_state *link_state = pci_device->link_state;
772
Kenji Kaneshige80bfdbe2009-05-13 12:12:43 +0900773 return sprintf(buf, "%d\n", link_state->aspm_enabled);
Shaohua Li7d715a62008-02-25 09:46:41 +0800774}
775
776static ssize_t link_state_store(struct device *dev,
777 struct device_attribute *attr,
778 const char *buf,
779 size_t n)
780{
Kenji Kaneshige5aa63582009-05-13 12:17:44 +0900781 struct pci_dev *pdev = to_pci_dev(dev);
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900782 struct pcie_link_state *link, *root = pdev->link_state->root;
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900783 u32 val = buf[0] - '0', state = 0;
Shaohua Li7d715a62008-02-25 09:46:41 +0800784
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900785 if (n < 1 || val > 3)
Shaohua Li7d715a62008-02-25 09:46:41 +0800786 return -EINVAL;
Shaohua Li7d715a62008-02-25 09:46:41 +0800787
Kenji Kaneshigeac180182009-08-19 11:02:13 +0900788 /* Convert requested state to ASPM state */
789 if (val & PCIE_LINK_STATE_L0S)
790 state |= ASPM_STATE_L0S;
791 if (val & PCIE_LINK_STATE_L1)
792 state |= ASPM_STATE_L1;
793
Kenji Kaneshigeb7206cb2009-08-19 11:01:37 +0900794 down_read(&pci_bus_sem);
795 mutex_lock(&aspm_lock);
796 list_for_each_entry(link, &link_list, sibling) {
797 if (link->root != root)
798 continue;
799 pcie_config_aspm_link(link, state);
800 }
801 mutex_unlock(&aspm_lock);
802 up_read(&pci_bus_sem);
803 return n;
Shaohua Li7d715a62008-02-25 09:46:41 +0800804}
805
806static ssize_t clk_ctl_show(struct device *dev,
807 struct device_attribute *attr,
808 char *buf)
809{
810 struct pci_dev *pci_device = to_pci_dev(dev);
811 struct pcie_link_state *link_state = pci_device->link_state;
812
Kenji Kaneshige4d246e42009-05-13 12:15:38 +0900813 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
Shaohua Li7d715a62008-02-25 09:46:41 +0800814}
815
816static ssize_t clk_ctl_store(struct device *dev,
817 struct device_attribute *attr,
818 const char *buf,
819 size_t n)
820{
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900821 struct pci_dev *pdev = to_pci_dev(dev);
Shaohua Li7d715a62008-02-25 09:46:41 +0800822 int state;
823
824 if (n < 1)
825 return -EINVAL;
826 state = buf[0]-'0';
827
828 down_read(&pci_bus_sem);
829 mutex_lock(&aspm_lock);
Kenji Kaneshige430842e2009-05-13 12:20:10 +0900830 pcie_set_clkpm_nocheck(pdev->link_state, !!state);
Shaohua Li7d715a62008-02-25 09:46:41 +0800831 mutex_unlock(&aspm_lock);
832 up_read(&pci_bus_sem);
833
834 return n;
835}
836
837static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
838static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
839
840static char power_group[] = "power";
841void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
842{
843 struct pcie_link_state *link_state = pdev->link_state;
844
Kenji Kaneshige8b064772009-11-11 14:36:52 +0900845 if (!pci_is_pcie(pdev) ||
846 (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
847 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
Shaohua Li7d715a62008-02-25 09:46:41 +0800848 return;
849
Kenji Kaneshige80bfdbe2009-05-13 12:12:43 +0900850 if (link_state->aspm_support)
Shaohua Li7d715a62008-02-25 09:46:41 +0800851 sysfs_add_file_to_group(&pdev->dev.kobj,
852 &dev_attr_link_state.attr, power_group);
Kenji Kaneshige4d246e42009-05-13 12:15:38 +0900853 if (link_state->clkpm_capable)
Shaohua Li7d715a62008-02-25 09:46:41 +0800854 sysfs_add_file_to_group(&pdev->dev.kobj,
855 &dev_attr_clk_ctl.attr, power_group);
856}
857
858void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
859{
860 struct pcie_link_state *link_state = pdev->link_state;
861
Kenji Kaneshige8b064772009-11-11 14:36:52 +0900862 if (!pci_is_pcie(pdev) ||
863 (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
864 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
Shaohua Li7d715a62008-02-25 09:46:41 +0800865 return;
866
Kenji Kaneshige80bfdbe2009-05-13 12:12:43 +0900867 if (link_state->aspm_support)
Shaohua Li7d715a62008-02-25 09:46:41 +0800868 sysfs_remove_file_from_group(&pdev->dev.kobj,
869 &dev_attr_link_state.attr, power_group);
Kenji Kaneshige4d246e42009-05-13 12:15:38 +0900870 if (link_state->clkpm_capable)
Shaohua Li7d715a62008-02-25 09:46:41 +0800871 sysfs_remove_file_from_group(&pdev->dev.kobj,
872 &dev_attr_clk_ctl.attr, power_group);
873}
874#endif
875
876static int __init pcie_aspm_disable(char *str)
877{
Shaohua Lid6d38572008-07-23 10:32:42 +0800878 if (!strcmp(str, "off")) {
879 aspm_disabled = 1;
880 printk(KERN_INFO "PCIe ASPM is disabled\n");
881 } else if (!strcmp(str, "force")) {
882 aspm_force = 1;
883 printk(KERN_INFO "PCIe ASPM is forcedly enabled\n");
884 }
Shaohua Li7d715a62008-02-25 09:46:41 +0800885 return 1;
886}
887
Shaohua Lid6d38572008-07-23 10:32:42 +0800888__setup("pcie_aspm=", pcie_aspm_disable);
Shaohua Li7d715a62008-02-25 09:46:41 +0800889
Shaohua Li5fde2442008-07-23 10:32:24 +0800890void pcie_no_aspm(void)
891{
Shaohua Lid6d38572008-07-23 10:32:42 +0800892 if (!aspm_force)
893 aspm_disabled = 1;
Shaohua Li5fde2442008-07-23 10:32:24 +0800894}
895
Andrew Patterson3e1b1602008-11-10 15:30:55 -0700896/**
897 * pcie_aspm_enabled - is PCIe ASPM enabled?
898 *
899 * Returns true if ASPM has not been disabled by the command-line option
900 * pcie_aspm=off.
901 **/
902int pcie_aspm_enabled(void)
Shaohua Li7d715a62008-02-25 09:46:41 +0800903{
Andrew Patterson3e1b1602008-11-10 15:30:55 -0700904 return !aspm_disabled;
Shaohua Li7d715a62008-02-25 09:46:41 +0800905}
Andrew Patterson3e1b1602008-11-10 15:30:55 -0700906EXPORT_SYMBOL(pcie_aspm_enabled);
Shaohua Li7d715a62008-02-25 09:46:41 +0800907