Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 1 | /* |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 2 | * arch/arm/mach-orion5x/pci.c |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 3 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 4 | * PCI and PCIe functions for Marvell Orion System On Chip |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/pci.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 15 | #include <linux/slab.h> |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 16 | #include <linux/mbus.h> |
Bryan Wu | 158c0c6 | 2011-08-17 17:29:38 +0800 | [diff] [blame] | 17 | #include <video/vga.h> |
Nicolas Pitre | ff89c46 | 2009-01-07 04:52:58 +0100 | [diff] [blame] | 18 | #include <asm/irq.h> |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 19 | #include <asm/mach/pci.h> |
Lennert Buytenhek | 6f088f1 | 2008-08-09 13:44:58 +0200 | [diff] [blame] | 20 | #include <plat/pcie.h> |
Andrew Lunn | 45173d5 | 2011-12-07 21:48:06 +0100 | [diff] [blame] | 21 | #include <plat/addr-map.h> |
Rob Herring | 8a52dd4 | 2012-02-10 18:29:09 -0600 | [diff] [blame] | 22 | #include <mach/orion5x.h> |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 23 | #include "common.h" |
| 24 | |
| 25 | /***************************************************************************** |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 26 | * Orion has one PCIe controller and one PCI controller. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 27 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 28 | * Note1: The local PCIe bus number is '0'. The local PCI bus number |
| 29 | * follows the scanned PCIe bridged busses, if any. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 30 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 31 | * Note2: It is possible for PCI/PCIe agents to access many subsystem's |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 32 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on |
| 33 | * device bus, Orion registers, etc. However this code only enable the |
| 34 | * access to DDR banks. |
| 35 | ****************************************************************************/ |
| 36 | |
| 37 | |
| 38 | /***************************************************************************** |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 39 | * PCIe controller |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 40 | ****************************************************************************/ |
Thomas Petazzoni | 3904a39 | 2012-09-11 14:27:21 +0200 | [diff] [blame] | 41 | #define PCIE_BASE (ORION5X_PCIE_VIRT_BASE) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 42 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 43 | void __init orion5x_pcie_id(u32 *dev, u32 *rev) |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 44 | { |
| 45 | *dev = orion_pcie_dev_id(PCIE_BASE); |
| 46 | *rev = orion_pcie_rev(PCIE_BASE); |
| 47 | } |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 48 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 49 | static int pcie_valid_config(int bus, int dev) |
| 50 | { |
| 51 | /* |
| 52 | * Don't go out when trying to access -- |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 53 | * 1. nonexisting device on local bus |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 54 | * 2. where there's no device connected (no link) |
| 55 | */ |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 56 | if (bus == 0 && dev == 0) |
| 57 | return 1; |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 58 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 59 | if (!orion_pcie_link_up(PCIE_BASE)) |
| 60 | return 0; |
| 61 | |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 62 | if (bus == 0 && dev != 1) |
| 63 | return 0; |
| 64 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 65 | return 1; |
| 66 | } |
| 67 | |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 68 | |
| 69 | /* |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 70 | * PCIe config cycles are done by programming the PCIE_CONF_ADDR register |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 71 | * and then reading the PCIE_CONF_DATA register. Need to make sure these |
| 72 | * transactions are atomic. |
| 73 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 74 | static DEFINE_SPINLOCK(orion5x_pcie_lock); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 75 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 76 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
| 77 | int size, u32 *val) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 78 | { |
| 79 | unsigned long flags; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 80 | int ret; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 81 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 82 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 83 | *val = 0xffffffff; |
| 84 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 85 | } |
| 86 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 87 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 88 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 89 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 90 | |
| 91 | return ret; |
| 92 | } |
| 93 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 94 | static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, |
| 95 | int where, int size, u32 *val) |
| 96 | { |
| 97 | int ret; |
| 98 | |
| 99 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
| 100 | *val = 0xffffffff; |
| 101 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 102 | } |
| 103 | |
| 104 | /* |
| 105 | * We only support access to the non-extended configuration |
| 106 | * space when using the WA access method (or we would have to |
| 107 | * sacrifice 256M of CPU virtual address space.) |
| 108 | */ |
| 109 | if (where >= 0x100) { |
| 110 | *val = 0xffffffff; |
| 111 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 112 | } |
| 113 | |
Thomas Petazzoni | 3904a39 | 2012-09-11 14:27:21 +0200 | [diff] [blame] | 114 | ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 115 | bus, devfn, where, size, val); |
| 116 | |
| 117 | return ret; |
| 118 | } |
| 119 | |
| 120 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
| 121 | int where, int size, u32 val) |
| 122 | { |
| 123 | unsigned long flags; |
| 124 | int ret; |
| 125 | |
| 126 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) |
| 127 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 128 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 129 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 130 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 131 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 132 | |
| 133 | return ret; |
| 134 | } |
| 135 | |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 136 | static struct pci_ops pcie_ops = { |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 137 | .read = pcie_rd_conf, |
| 138 | .write = pcie_wr_conf, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 139 | }; |
| 140 | |
| 141 | |
Lennert Buytenhek | a998427 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 142 | static int __init pcie_setup(struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 143 | { |
| 144 | struct resource *res; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 145 | int dev; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 146 | |
| 147 | /* |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 148 | * Generic PCIe unit setup. |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 149 | */ |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 150 | orion_pcie_setup(PCIE_BASE); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 151 | |
| 152 | /* |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 153 | * Check whether to apply Orion-1/Orion-NAS PCIe config |
| 154 | * read transaction workaround. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 155 | */ |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 156 | dev = orion_pcie_dev_id(PCIE_BASE); |
| 157 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { |
| 158 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " |
| 159 | "read transaction workaround\n"); |
Lennert Buytenhek | 386a048 | 2008-05-10 17:01:18 +0200 | [diff] [blame] | 160 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 161 | ORION5X_PCIE_WA_SIZE); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 162 | pcie_ops.read = pcie_rd_conf_wa; |
| 163 | } |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 164 | |
Rob Herring | 0a4b8c6 | 2012-07-06 10:59:30 -0500 | [diff] [blame] | 165 | pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE); |
| 166 | |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 167 | /* |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 168 | * Request resources. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 169 | */ |
Rob Herring | 0a4b8c6 | 2012-07-06 10:59:30 -0500 | [diff] [blame] | 170 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 171 | if (!res) |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 172 | panic("pcie_setup unable to alloc resources"); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 173 | |
| 174 | /* |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 175 | * IORESOURCE_MEM |
| 176 | */ |
Rob Herring | 0a4b8c6 | 2012-07-06 10:59:30 -0500 | [diff] [blame] | 177 | res->name = "PCIe Memory Space"; |
| 178 | res->flags = IORESOURCE_MEM; |
| 179 | res->start = ORION5X_PCIE_MEM_PHYS_BASE; |
| 180 | res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1; |
| 181 | if (request_resource(&iomem_resource, res)) |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 182 | panic("Request PCIe Memory resource failed\n"); |
Rob Herring | 0a4b8c6 | 2012-07-06 10:59:30 -0500 | [diff] [blame] | 183 | pci_add_resource_offset(&sys->resources, res, sys->mem_offset); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 184 | |
| 185 | return 1; |
| 186 | } |
| 187 | |
| 188 | /***************************************************************************** |
| 189 | * PCI controller |
| 190 | ****************************************************************************/ |
Thomas Petazzoni | 2332656 | 2012-09-11 14:27:17 +0200 | [diff] [blame] | 191 | #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x)) |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 192 | #define PCI_MODE ORION5X_PCI_REG(0xd00) |
| 193 | #define PCI_CMD ORION5X_PCI_REG(0xc00) |
| 194 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) |
| 195 | #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) |
| 196 | #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 197 | |
| 198 | /* |
| 199 | * PCI_MODE bits |
| 200 | */ |
| 201 | #define PCI_MODE_64BIT (1 << 2) |
| 202 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) |
| 203 | |
| 204 | /* |
| 205 | * PCI_CMD bits |
| 206 | */ |
| 207 | #define PCI_CMD_HOST_REORDER (1 << 29) |
| 208 | |
| 209 | /* |
| 210 | * PCI_P2P_CONF bits |
| 211 | */ |
| 212 | #define PCI_P2P_BUS_OFFS 16 |
| 213 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) |
| 214 | #define PCI_P2P_DEV_OFFS 24 |
| 215 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) |
| 216 | |
| 217 | /* |
| 218 | * PCI_CONF_ADDR bits |
| 219 | */ |
| 220 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) |
| 221 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) |
| 222 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) |
| 223 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) |
| 224 | #define PCI_CONF_ADDR_EN (1 << 31) |
| 225 | |
| 226 | /* |
| 227 | * Internal configuration space |
| 228 | */ |
| 229 | #define PCI_CONF_FUNC_STAT_CMD 0 |
| 230 | #define PCI_CONF_REG_STAT_CMD 4 |
| 231 | #define PCIX_STAT 0x64 |
| 232 | #define PCIX_STAT_BUS_OFFS 8 |
| 233 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) |
| 234 | |
| 235 | /* |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 236 | * PCI Address Decode Windows registers |
| 237 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 238 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ |
Lennert Buytenhek | e7068ad | 2008-05-10 16:30:01 +0200 | [diff] [blame] | 239 | ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ |
| 240 | ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ |
| 241 | ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) |
| 242 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ |
| 243 | ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ |
| 244 | ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ |
| 245 | ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 246 | #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) |
| 247 | #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 248 | |
| 249 | /* |
| 250 | * PCI configuration helpers for BAR settings |
| 251 | */ |
| 252 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) |
| 253 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) |
| 254 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) |
| 255 | |
| 256 | /* |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 257 | * PCI config cycles are done by programming the PCI_CONF_ADDR register |
| 258 | * and then reading the PCI_CONF_DATA register. Need to make sure these |
| 259 | * transactions are atomic. |
| 260 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 261 | static DEFINE_SPINLOCK(orion5x_pci_lock); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 262 | |
Lennert Buytenhek | da01bba | 2008-06-26 17:12:50 +0200 | [diff] [blame] | 263 | static int orion5x_pci_cardbus_mode; |
| 264 | |
Lennert Buytenhek | 92b913b | 2008-04-25 16:28:33 -0400 | [diff] [blame] | 265 | static int orion5x_pci_local_bus_nr(void) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 266 | { |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 267 | u32 conf = readl(PCI_P2P_CONF); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 268 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); |
| 269 | } |
| 270 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 271 | static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 272 | u32 where, u32 size, u32 *val) |
| 273 | { |
| 274 | unsigned long flags; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 275 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 276 | |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 277 | writel(PCI_CONF_BUS(bus) | |
| 278 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | |
| 279 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 280 | |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 281 | *val = readl(PCI_CONF_DATA); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 282 | |
| 283 | if (size == 1) |
| 284 | *val = (*val >> (8*(where & 0x3))) & 0xff; |
| 285 | else if (size == 2) |
| 286 | *val = (*val >> (8*(where & 0x3))) & 0xffff; |
| 287 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 288 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 289 | |
| 290 | return PCIBIOS_SUCCESSFUL; |
| 291 | } |
| 292 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 293 | static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 294 | u32 where, u32 size, u32 val) |
| 295 | { |
| 296 | unsigned long flags; |
| 297 | int ret = PCIBIOS_SUCCESSFUL; |
| 298 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 299 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 300 | |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 301 | writel(PCI_CONF_BUS(bus) | |
| 302 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | |
| 303 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 304 | |
| 305 | if (size == 4) { |
| 306 | __raw_writel(val, PCI_CONF_DATA); |
| 307 | } else if (size == 2) { |
| 308 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); |
| 309 | } else if (size == 1) { |
| 310 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); |
| 311 | } else { |
| 312 | ret = PCIBIOS_BAD_REGISTER_NUMBER; |
| 313 | } |
| 314 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 315 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 316 | |
| 317 | return ret; |
| 318 | } |
| 319 | |
Lennert Buytenhek | da01bba | 2008-06-26 17:12:50 +0200 | [diff] [blame] | 320 | static int orion5x_pci_valid_config(int bus, u32 devfn) |
| 321 | { |
| 322 | if (bus == orion5x_pci_local_bus_nr()) { |
| 323 | /* |
| 324 | * Don't go out for local device |
| 325 | */ |
| 326 | if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) |
| 327 | return 0; |
| 328 | |
| 329 | /* |
| 330 | * When the PCI signals are directly connected to a |
| 331 | * Cardbus slot, ignore all but device IDs 0 and 1. |
| 332 | */ |
| 333 | if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) |
| 334 | return 0; |
| 335 | } |
| 336 | |
| 337 | return 1; |
| 338 | } |
| 339 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 340 | static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 341 | int where, int size, u32 *val) |
| 342 | { |
Lennert Buytenhek | da01bba | 2008-06-26 17:12:50 +0200 | [diff] [blame] | 343 | if (!orion5x_pci_valid_config(bus->number, devfn)) { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 344 | *val = 0xffffffff; |
| 345 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 346 | } |
| 347 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 348 | return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 349 | PCI_FUNC(devfn), where, size, val); |
| 350 | } |
| 351 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 352 | static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 353 | int where, int size, u32 val) |
| 354 | { |
Lennert Buytenhek | da01bba | 2008-06-26 17:12:50 +0200 | [diff] [blame] | 355 | if (!orion5x_pci_valid_config(bus->number, devfn)) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 356 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 357 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 358 | return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 359 | PCI_FUNC(devfn), where, size, val); |
| 360 | } |
| 361 | |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 362 | static struct pci_ops pci_ops = { |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 363 | .read = orion5x_pci_rd_conf, |
| 364 | .write = orion5x_pci_wr_conf, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 365 | }; |
| 366 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 367 | static void __init orion5x_pci_set_bus_nr(int nr) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 368 | { |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 369 | u32 p2p = readl(PCI_P2P_CONF); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 370 | |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 371 | if (readl(PCI_MODE) & PCI_MODE_PCIX) { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 372 | /* |
| 373 | * PCI-X mode |
| 374 | */ |
| 375 | u32 pcix_status, bus, dev; |
| 376 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; |
| 377 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 378 | orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 379 | pcix_status &= ~PCIX_STAT_BUS_MASK; |
| 380 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 381 | orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 382 | } else { |
| 383 | /* |
| 384 | * PCI Conventional mode |
| 385 | */ |
| 386 | p2p &= ~PCI_P2P_BUS_MASK; |
| 387 | p2p |= (nr << PCI_P2P_BUS_OFFS); |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 388 | writel(p2p, PCI_P2P_CONF); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 389 | } |
| 390 | } |
| 391 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 392 | static void __init orion5x_pci_master_slave_enable(void) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 393 | { |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 394 | int bus_nr, func, reg; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 395 | u32 val; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 396 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 397 | bus_nr = orion5x_pci_local_bus_nr(); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 398 | func = PCI_CONF_FUNC_STAT_CMD; |
| 399 | reg = PCI_CONF_REG_STAT_CMD; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 400 | orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 401 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 402 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 403 | } |
| 404 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 405 | static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 406 | { |
| 407 | u32 win_enable; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 408 | int bus; |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 409 | int i; |
| 410 | |
| 411 | /* |
| 412 | * First, disable windows. |
| 413 | */ |
| 414 | win_enable = 0xffffffff; |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 415 | writel(win_enable, PCI_BAR_ENABLE); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 416 | |
| 417 | /* |
| 418 | * Setup windows for DDR banks. |
| 419 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 420 | bus = orion5x_pci_local_bus_nr(); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 421 | |
| 422 | for (i = 0; i < dram->num_cs; i++) { |
| 423 | struct mbus_dram_window *cs = dram->cs + i; |
| 424 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); |
| 425 | u32 reg; |
| 426 | u32 val; |
| 427 | |
| 428 | /* |
| 429 | * Write DRAM bank base address register. |
| 430 | */ |
| 431 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 432 | orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 433 | val = (cs->base & 0xfffff000) | (val & 0xfff); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 434 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 435 | |
| 436 | /* |
| 437 | * Write DRAM bank size register. |
| 438 | */ |
| 439 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 440 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 441 | writel((cs->size - 1) & 0xfffff000, |
| 442 | PCI_BAR_SIZE_DDR_CS(cs->cs_index)); |
| 443 | writel(cs->base & 0xfffff000, |
| 444 | PCI_BAR_REMAP_DDR_CS(cs->cs_index)); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 445 | |
| 446 | /* |
| 447 | * Enable decode window for this chip select. |
| 448 | */ |
| 449 | win_enable &= ~(1 << cs->cs_index); |
| 450 | } |
| 451 | |
| 452 | /* |
| 453 | * Re-enable decode windows. |
| 454 | */ |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 455 | writel(win_enable, PCI_BAR_ENABLE); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 456 | |
| 457 | /* |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 458 | * Disable automatic update of address remapping when writing to BARs. |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 459 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 460 | orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 461 | } |
| 462 | |
Lennert Buytenhek | a998427 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 463 | static int __init pci_setup(struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 464 | { |
| 465 | struct resource *res; |
| 466 | |
| 467 | /* |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 468 | * Point PCI unit MBUS decode windows to DRAM space. |
| 469 | */ |
Andrew Lunn | 45173d5 | 2011-12-07 21:48:06 +0100 | [diff] [blame] | 470 | orion5x_setup_pci_wins(&orion_mbus_dram_info); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 471 | |
| 472 | /* |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 473 | * Master + Slave enable |
| 474 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 475 | orion5x_pci_master_slave_enable(); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 476 | |
| 477 | /* |
| 478 | * Force ordering |
| 479 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 480 | orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 481 | |
Rob Herring | 0a4b8c6 | 2012-07-06 10:59:30 -0500 | [diff] [blame] | 482 | pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE); |
| 483 | |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 484 | /* |
| 485 | * Request resources |
| 486 | */ |
Rob Herring | 0a4b8c6 | 2012-07-06 10:59:30 -0500 | [diff] [blame] | 487 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 488 | if (!res) |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 489 | panic("pci_setup unable to alloc resources"); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 490 | |
| 491 | /* |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 492 | * IORESOURCE_MEM |
| 493 | */ |
Rob Herring | 0a4b8c6 | 2012-07-06 10:59:30 -0500 | [diff] [blame] | 494 | res->name = "PCI Memory Space"; |
| 495 | res->flags = IORESOURCE_MEM; |
| 496 | res->start = ORION5X_PCI_MEM_PHYS_BASE; |
| 497 | res->end = res->start + ORION5X_PCI_MEM_SIZE - 1; |
| 498 | if (request_resource(&iomem_resource, res)) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 499 | panic("Request PCI Memory resource failed\n"); |
Rob Herring | 0a4b8c6 | 2012-07-06 10:59:30 -0500 | [diff] [blame] | 500 | pci_add_resource_offset(&sys->resources, res, sys->mem_offset); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 501 | |
| 502 | return 1; |
| 503 | } |
| 504 | |
| 505 | |
| 506 | /***************************************************************************** |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 507 | * General PCIe + PCI |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 508 | ****************************************************************************/ |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 509 | static void __devinit rc_pci_fixup(struct pci_dev *dev) |
| 510 | { |
| 511 | /* |
| 512 | * Prevent enumeration of root complex. |
| 513 | */ |
| 514 | if (dev->bus->parent == NULL && dev->devfn == 0) { |
| 515 | int i; |
| 516 | |
| 517 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
| 518 | dev->resource[i].start = 0; |
| 519 | dev->resource[i].end = 0; |
| 520 | dev->resource[i].flags = 0; |
| 521 | } |
| 522 | } |
| 523 | } |
| 524 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); |
| 525 | |
Per Andersson | 7a6bb26 | 2008-08-11 12:00:52 +0200 | [diff] [blame] | 526 | static int orion5x_pci_disabled __initdata; |
| 527 | |
| 528 | void __init orion5x_pci_disable(void) |
| 529 | { |
| 530 | orion5x_pci_disabled = 1; |
| 531 | } |
| 532 | |
Lennert Buytenhek | da01bba | 2008-06-26 17:12:50 +0200 | [diff] [blame] | 533 | void __init orion5x_pci_set_cardbus_mode(void) |
| 534 | { |
| 535 | orion5x_pci_cardbus_mode = 1; |
| 536 | } |
| 537 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 538 | int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 539 | { |
| 540 | int ret = 0; |
| 541 | |
Rob Herring | cc22b4c | 2011-06-28 21:22:40 -0500 | [diff] [blame] | 542 | vga_base = ORION5X_PCIE_MEM_PHYS_BASE; |
| 543 | |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 544 | if (nr == 0) { |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 545 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); |
| 546 | ret = pcie_setup(sys); |
Per Andersson | 7a6bb26 | 2008-08-11 12:00:52 +0200 | [diff] [blame] | 547 | } else if (nr == 1 && !orion5x_pci_disabled) { |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 548 | orion5x_pci_set_bus_nr(sys->busnr); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 549 | ret = pci_setup(sys); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 550 | } |
| 551 | |
| 552 | return ret; |
| 553 | } |
| 554 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 555 | struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 556 | { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 557 | struct pci_bus *bus; |
| 558 | |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 559 | if (nr == 0) { |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 560 | bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, |
| 561 | &sys->resources); |
Per Andersson | 7a6bb26 | 2008-08-11 12:00:52 +0200 | [diff] [blame] | 562 | } else if (nr == 1 && !orion5x_pci_disabled) { |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 563 | bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, |
| 564 | &sys->resources); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 565 | } else { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 566 | bus = NULL; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 567 | BUG(); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 568 | } |
| 569 | |
| 570 | return bus; |
| 571 | } |
Lennert Buytenhek | 92b913b | 2008-04-25 16:28:33 -0400 | [diff] [blame] | 572 | |
Ralf Baechle | d534194 | 2011-06-10 15:30:21 +0100 | [diff] [blame] | 573 | int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Lennert Buytenhek | 92b913b | 2008-04-25 16:28:33 -0400 | [diff] [blame] | 574 | { |
| 575 | int bus = dev->bus->number; |
| 576 | |
| 577 | /* |
| 578 | * PCIe endpoint? |
| 579 | */ |
Per Andersson | 7a6bb26 | 2008-08-11 12:00:52 +0200 | [diff] [blame] | 580 | if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) |
Lennert Buytenhek | 92b913b | 2008-04-25 16:28:33 -0400 | [diff] [blame] | 581 | return IRQ_ORION5X_PCIE0_INT; |
| 582 | |
| 583 | return -1; |
| 584 | } |