Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Russell King |
| 3 | * Rewritten from the dovefb driver, and Armada510 manuals. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | #include <linux/clk.h> |
| 10 | #include <drm/drmP.h> |
| 11 | #include <drm/drm_crtc_helper.h> |
| 12 | #include "armada_crtc.h" |
| 13 | #include "armada_drm.h" |
| 14 | #include "armada_fb.h" |
| 15 | #include "armada_gem.h" |
| 16 | #include "armada_hw.h" |
| 17 | |
| 18 | struct armada_frame_work { |
| 19 | struct drm_pending_vblank_event *event; |
| 20 | struct armada_regs regs[4]; |
| 21 | struct drm_framebuffer *old_fb; |
| 22 | }; |
| 23 | |
| 24 | enum csc_mode { |
| 25 | CSC_AUTO = 0, |
| 26 | CSC_YUV_CCIR601 = 1, |
| 27 | CSC_YUV_CCIR709 = 2, |
| 28 | CSC_RGB_COMPUTER = 1, |
| 29 | CSC_RGB_STUDIO = 2, |
| 30 | }; |
| 31 | |
| 32 | /* |
| 33 | * A note about interlacing. Let's consider HDMI 1920x1080i. |
| 34 | * The timing parameters we have from X are: |
| 35 | * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot |
| 36 | * 1920 2448 2492 2640 1080 1084 1094 1125 |
| 37 | * Which get translated to: |
| 38 | * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot |
| 39 | * 1920 2448 2492 2640 540 542 547 562 |
| 40 | * |
| 41 | * This is how it is defined by CEA-861-D - line and pixel numbers are |
| 42 | * referenced to the rising edge of VSYNC and HSYNC. Total clocks per |
| 43 | * line: 2640. The odd frame, the first active line is at line 21, and |
| 44 | * the even frame, the first active line is 584. |
| 45 | * |
| 46 | * LN: 560 561 562 563 567 568 569 |
| 47 | * DE: ~~~|____________________________//__________________________ |
| 48 | * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____ |
| 49 | * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________ |
| 50 | * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge). |
| 51 | * |
| 52 | * LN: 1123 1124 1125 1 5 6 7 |
| 53 | * DE: ~~~|____________________________//__________________________ |
| 54 | * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____ |
| 55 | * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________ |
| 56 | * 23 blanking lines |
| 57 | * |
| 58 | * The Armada LCD Controller line and pixel numbers are, like X timings, |
| 59 | * referenced to the top left of the active frame. |
| 60 | * |
| 61 | * So, translating these to our LCD controller: |
| 62 | * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128. |
| 63 | * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448. |
| 64 | * Note: Vsync front porch remains constant! |
| 65 | * |
| 66 | * if (odd_frame) { |
| 67 | * vtotal = mode->crtc_vtotal + 1; |
| 68 | * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1; |
| 69 | * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2 |
| 70 | * } else { |
| 71 | * vtotal = mode->crtc_vtotal; |
| 72 | * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay; |
| 73 | * vhorizpos = mode->crtc_hsync_start; |
| 74 | * } |
| 75 | * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end; |
| 76 | * |
| 77 | * So, we need to reprogram these registers on each vsync event: |
| 78 | * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL |
| 79 | * |
| 80 | * Note: we do not use the frame done interrupts because these appear |
| 81 | * to happen too early, and lead to jitter on the display (presumably |
| 82 | * they occur at the end of the last active line, before the vsync back |
| 83 | * porch, which we're reprogramming.) |
| 84 | */ |
| 85 | |
| 86 | void |
| 87 | armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs) |
| 88 | { |
| 89 | while (regs->offset != ~0) { |
| 90 | void __iomem *reg = dcrtc->base + regs->offset; |
| 91 | uint32_t val; |
| 92 | |
| 93 | val = regs->mask; |
| 94 | if (val != 0) |
| 95 | val &= readl_relaxed(reg); |
| 96 | writel_relaxed(val | regs->val, reg); |
| 97 | ++regs; |
| 98 | } |
| 99 | } |
| 100 | |
| 101 | #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON) |
| 102 | |
| 103 | static void armada_drm_crtc_update(struct armada_crtc *dcrtc) |
| 104 | { |
| 105 | uint32_t dumb_ctrl; |
| 106 | |
| 107 | dumb_ctrl = dcrtc->cfg_dumb_ctrl; |
| 108 | |
| 109 | if (!dpms_blanked(dcrtc->dpms)) |
| 110 | dumb_ctrl |= CFG_DUMB_ENA; |
| 111 | |
| 112 | /* |
| 113 | * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might |
| 114 | * be using SPI or GPIO. If we set this to DUMB_BLANK, we will |
| 115 | * force LCD_D[23:0] to output blank color, overriding the GPIO or |
| 116 | * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode. |
| 117 | */ |
| 118 | if (dpms_blanked(dcrtc->dpms) && |
| 119 | (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) { |
| 120 | dumb_ctrl &= ~DUMB_MASK; |
| 121 | dumb_ctrl |= DUMB_BLANK; |
| 122 | } |
| 123 | |
| 124 | /* |
| 125 | * The documentation doesn't indicate what the normal state of |
| 126 | * the sync signals are. Sebastian Hesselbart kindly probed |
| 127 | * these signals on his board to determine their state. |
| 128 | * |
| 129 | * The non-inverted state of the sync signals is active high. |
| 130 | * Setting these bits makes the appropriate signal active low. |
| 131 | */ |
| 132 | if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC) |
| 133 | dumb_ctrl |= CFG_INV_CSYNC; |
| 134 | if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC) |
| 135 | dumb_ctrl |= CFG_INV_HSYNC; |
| 136 | if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC) |
| 137 | dumb_ctrl |= CFG_INV_VSYNC; |
| 138 | |
| 139 | if (dcrtc->dumb_ctrl != dumb_ctrl) { |
| 140 | dcrtc->dumb_ctrl = dumb_ctrl; |
| 141 | writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL); |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb, |
| 146 | int x, int y, struct armada_regs *regs, bool interlaced) |
| 147 | { |
| 148 | struct armada_gem_object *obj = drm_fb_obj(fb); |
| 149 | unsigned pitch = fb->pitches[0]; |
| 150 | unsigned offset = y * pitch + x * fb->bits_per_pixel / 8; |
| 151 | uint32_t addr_odd, addr_even; |
| 152 | unsigned i = 0; |
| 153 | |
| 154 | DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n", |
| 155 | pitch, x, y, fb->bits_per_pixel); |
| 156 | |
| 157 | addr_odd = addr_even = obj->dev_addr + offset; |
| 158 | |
| 159 | if (interlaced) { |
| 160 | addr_even += pitch; |
| 161 | pitch *= 2; |
| 162 | } |
| 163 | |
| 164 | /* write offset, base, and pitch */ |
| 165 | armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0); |
| 166 | armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1); |
| 167 | armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH); |
| 168 | |
| 169 | return i; |
| 170 | } |
| 171 | |
| 172 | static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc, |
| 173 | struct armada_frame_work *work) |
| 174 | { |
| 175 | struct drm_device *dev = dcrtc->crtc.dev; |
| 176 | unsigned long flags; |
| 177 | int ret; |
| 178 | |
| 179 | ret = drm_vblank_get(dev, dcrtc->num); |
| 180 | if (ret) { |
| 181 | DRM_ERROR("failed to acquire vblank counter\n"); |
| 182 | return ret; |
| 183 | } |
| 184 | |
| 185 | spin_lock_irqsave(&dev->event_lock, flags); |
| 186 | if (!dcrtc->frame_work) |
| 187 | dcrtc->frame_work = work; |
| 188 | else |
| 189 | ret = -EBUSY; |
| 190 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 191 | |
| 192 | if (ret) |
| 193 | drm_vblank_put(dev, dcrtc->num); |
| 194 | |
| 195 | return ret; |
| 196 | } |
| 197 | |
| 198 | static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc) |
| 199 | { |
| 200 | struct drm_device *dev = dcrtc->crtc.dev; |
| 201 | struct armada_frame_work *work = dcrtc->frame_work; |
| 202 | |
| 203 | dcrtc->frame_work = NULL; |
| 204 | |
| 205 | armada_drm_crtc_update_regs(dcrtc, work->regs); |
| 206 | |
| 207 | if (work->event) |
| 208 | drm_send_vblank_event(dev, dcrtc->num, work->event); |
| 209 | |
| 210 | drm_vblank_put(dev, dcrtc->num); |
| 211 | |
| 212 | /* Finally, queue the process-half of the cleanup. */ |
| 213 | __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb); |
| 214 | kfree(work); |
| 215 | } |
| 216 | |
| 217 | static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, |
| 218 | struct drm_framebuffer *fb, bool force) |
| 219 | { |
| 220 | struct armada_frame_work *work; |
| 221 | |
| 222 | if (!fb) |
| 223 | return; |
| 224 | |
| 225 | if (force) { |
| 226 | /* Display is disabled, so just drop the old fb */ |
| 227 | drm_framebuffer_unreference(fb); |
| 228 | return; |
| 229 | } |
| 230 | |
| 231 | work = kmalloc(sizeof(*work), GFP_KERNEL); |
| 232 | if (work) { |
| 233 | int i = 0; |
| 234 | work->event = NULL; |
| 235 | work->old_fb = fb; |
| 236 | armada_reg_queue_end(work->regs, i); |
| 237 | |
| 238 | if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0) |
| 239 | return; |
| 240 | |
| 241 | kfree(work); |
| 242 | } |
| 243 | |
| 244 | /* |
| 245 | * Oops - just drop the reference immediately and hope for |
| 246 | * the best. The worst that will happen is the buffer gets |
| 247 | * reused before it has finished being displayed. |
| 248 | */ |
| 249 | drm_framebuffer_unreference(fb); |
| 250 | } |
| 251 | |
| 252 | static void armada_drm_vblank_off(struct armada_crtc *dcrtc) |
| 253 | { |
| 254 | struct drm_device *dev = dcrtc->crtc.dev; |
| 255 | |
| 256 | /* |
| 257 | * Tell the DRM core that vblank IRQs aren't going to happen for |
| 258 | * a while. This cleans up any pending vblank events for us. |
| 259 | */ |
| 260 | drm_vblank_off(dev, dcrtc->num); |
| 261 | |
| 262 | /* Handle any pending flip event. */ |
| 263 | spin_lock_irq(&dev->event_lock); |
| 264 | if (dcrtc->frame_work) |
| 265 | armada_drm_crtc_complete_frame_work(dcrtc); |
| 266 | spin_unlock_irq(&dev->event_lock); |
| 267 | } |
| 268 | |
| 269 | void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b, |
| 270 | int idx) |
| 271 | { |
| 272 | } |
| 273 | |
| 274 | void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
| 275 | int idx) |
| 276 | { |
| 277 | } |
| 278 | |
| 279 | /* The mode_config.mutex will be held for this call */ |
| 280 | static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms) |
| 281 | { |
| 282 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 283 | |
| 284 | if (dcrtc->dpms != dpms) { |
| 285 | dcrtc->dpms = dpms; |
| 286 | armada_drm_crtc_update(dcrtc); |
| 287 | if (dpms_blanked(dpms)) |
| 288 | armada_drm_vblank_off(dcrtc); |
| 289 | } |
| 290 | } |
| 291 | |
| 292 | /* |
| 293 | * Prepare for a mode set. Turn off overlay to ensure that we don't end |
| 294 | * up with the overlay size being bigger than the active screen size. |
| 295 | * We rely upon X refreshing this state after the mode set has completed. |
| 296 | * |
| 297 | * The mode_config.mutex will be held for this call |
| 298 | */ |
| 299 | static void armada_drm_crtc_prepare(struct drm_crtc *crtc) |
| 300 | { |
| 301 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 302 | struct drm_plane *plane; |
| 303 | |
| 304 | /* |
| 305 | * If we have an overlay plane associated with this CRTC, disable |
| 306 | * it before the modeset to avoid its coordinates being outside |
| 307 | * the new mode parameters. DRM doesn't provide help with this. |
| 308 | */ |
| 309 | plane = dcrtc->plane; |
| 310 | if (plane) { |
| 311 | struct drm_framebuffer *fb = plane->fb; |
| 312 | |
| 313 | plane->funcs->disable_plane(plane); |
| 314 | plane->fb = NULL; |
| 315 | plane->crtc = NULL; |
| 316 | drm_framebuffer_unreference(fb); |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | /* The mode_config.mutex will be held for this call */ |
| 321 | static void armada_drm_crtc_commit(struct drm_crtc *crtc) |
| 322 | { |
| 323 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 324 | |
| 325 | if (dcrtc->dpms != DRM_MODE_DPMS_ON) { |
| 326 | dcrtc->dpms = DRM_MODE_DPMS_ON; |
| 327 | armada_drm_crtc_update(dcrtc); |
| 328 | } |
| 329 | } |
| 330 | |
| 331 | /* The mode_config.mutex will be held for this call */ |
| 332 | static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc, |
| 333 | const struct drm_display_mode *mode, struct drm_display_mode *adj) |
| 334 | { |
| 335 | struct armada_private *priv = crtc->dev->dev_private; |
| 336 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 337 | int ret; |
| 338 | |
| 339 | /* We can't do interlaced modes if we don't have the SPU_ADV_REG */ |
| 340 | if (!priv->variant->has_spu_adv_reg && |
| 341 | adj->flags & DRM_MODE_FLAG_INTERLACE) |
| 342 | return false; |
| 343 | |
| 344 | /* Check whether the display mode is possible */ |
| 345 | ret = priv->variant->crtc_compute_clock(dcrtc, adj, NULL); |
| 346 | if (ret) |
| 347 | return false; |
| 348 | |
| 349 | return true; |
| 350 | } |
| 351 | |
| 352 | void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) |
| 353 | { |
| 354 | struct armada_vbl_event *e, *n; |
| 355 | void __iomem *base = dcrtc->base; |
| 356 | |
| 357 | if (stat & DMA_FF_UNDERFLOW) |
| 358 | DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); |
| 359 | if (stat & GRA_FF_UNDERFLOW) |
| 360 | DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num); |
| 361 | |
| 362 | if (stat & VSYNC_IRQ) |
| 363 | drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num); |
| 364 | |
| 365 | spin_lock(&dcrtc->irq_lock); |
| 366 | |
| 367 | list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) { |
| 368 | list_del_init(&e->node); |
| 369 | drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); |
| 370 | e->fn(dcrtc, e->data); |
| 371 | } |
| 372 | |
| 373 | if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { |
| 374 | int i = stat & GRA_FRAME_IRQ0 ? 0 : 1; |
| 375 | uint32_t val; |
| 376 | |
| 377 | writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); |
| 378 | writel_relaxed(dcrtc->v[i].spu_v_h_total, |
| 379 | base + LCD_SPUT_V_H_TOTAL); |
| 380 | |
| 381 | val = readl_relaxed(base + LCD_SPU_ADV_REG); |
| 382 | val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN); |
| 383 | val |= dcrtc->v[i].spu_adv_reg; |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 384 | writel_relaxed(val, base + LCD_SPU_ADV_REG); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 385 | } |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 386 | |
| 387 | if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) { |
| 388 | writel_relaxed(dcrtc->cursor_hw_pos, |
| 389 | base + LCD_SPU_HWC_OVSA_HPXL_VLN); |
| 390 | writel_relaxed(dcrtc->cursor_hw_sz, |
| 391 | base + LCD_SPU_HWC_HPXL_VLN); |
| 392 | armada_updatel(CFG_HWC_ENA, |
| 393 | CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA, |
| 394 | base + LCD_SPU_DMA_CTRL0); |
| 395 | dcrtc->cursor_update = false; |
| 396 | armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); |
| 397 | } |
| 398 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 399 | spin_unlock(&dcrtc->irq_lock); |
| 400 | |
| 401 | if (stat & GRA_FRAME_IRQ) { |
| 402 | struct drm_device *dev = dcrtc->crtc.dev; |
| 403 | |
| 404 | spin_lock(&dev->event_lock); |
| 405 | if (dcrtc->frame_work) |
| 406 | armada_drm_crtc_complete_frame_work(dcrtc); |
| 407 | spin_unlock(&dev->event_lock); |
| 408 | |
| 409 | wake_up(&dcrtc->frame_wait); |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | /* These are locked by dev->vbl_lock */ |
| 414 | void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask) |
| 415 | { |
| 416 | if (dcrtc->irq_ena & mask) { |
| 417 | dcrtc->irq_ena &= ~mask; |
| 418 | writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); |
| 419 | } |
| 420 | } |
| 421 | |
| 422 | void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask) |
| 423 | { |
| 424 | if ((dcrtc->irq_ena & mask) != mask) { |
| 425 | dcrtc->irq_ena |= mask; |
| 426 | writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); |
| 427 | if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) |
| 428 | writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); |
| 429 | } |
| 430 | } |
| 431 | |
| 432 | static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc) |
| 433 | { |
| 434 | struct drm_display_mode *adj = &dcrtc->crtc.mode; |
| 435 | uint32_t val = 0; |
| 436 | |
| 437 | if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709) |
| 438 | val |= CFG_CSC_YUV_CCIR709; |
| 439 | if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO) |
| 440 | val |= CFG_CSC_RGB_STUDIO; |
| 441 | |
| 442 | /* |
| 443 | * In auto mode, set the colorimetry, based upon the HDMI spec. |
| 444 | * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use |
| 445 | * ITU601. It may be more appropriate to set this depending on |
| 446 | * the source - but what if the graphic frame is YUV and the |
| 447 | * video frame is RGB? |
| 448 | */ |
| 449 | if ((adj->hdisplay == 1280 && adj->vdisplay == 720 && |
| 450 | !(adj->flags & DRM_MODE_FLAG_INTERLACE)) || |
| 451 | (adj->hdisplay == 1920 && adj->vdisplay == 1080)) { |
| 452 | if (dcrtc->csc_yuv_mode == CSC_AUTO) |
| 453 | val |= CFG_CSC_YUV_CCIR709; |
| 454 | } |
| 455 | |
| 456 | /* |
| 457 | * We assume we're connected to a TV-like device, so the YUV->RGB |
| 458 | * conversion should produce a limited range. We should set this |
| 459 | * depending on the connectors attached to this CRTC, and what |
| 460 | * kind of device they report being connected. |
| 461 | */ |
| 462 | if (dcrtc->csc_rgb_mode == CSC_AUTO) |
| 463 | val |= CFG_CSC_RGB_STUDIO; |
| 464 | |
| 465 | return val; |
| 466 | } |
| 467 | |
| 468 | /* The mode_config.mutex will be held for this call */ |
| 469 | static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, |
| 470 | struct drm_display_mode *mode, struct drm_display_mode *adj, |
| 471 | int x, int y, struct drm_framebuffer *old_fb) |
| 472 | { |
| 473 | struct armada_private *priv = crtc->dev->dev_private; |
| 474 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 475 | struct armada_regs regs[17]; |
| 476 | uint32_t lm, rm, tm, bm, val, sclk; |
| 477 | unsigned long flags; |
| 478 | unsigned i; |
| 479 | bool interlaced; |
| 480 | |
| 481 | drm_framebuffer_reference(crtc->fb); |
| 482 | |
| 483 | interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE); |
| 484 | |
| 485 | i = armada_drm_crtc_calc_fb(dcrtc->crtc.fb, x, y, regs, interlaced); |
| 486 | |
| 487 | rm = adj->crtc_hsync_start - adj->crtc_hdisplay; |
| 488 | lm = adj->crtc_htotal - adj->crtc_hsync_end; |
| 489 | bm = adj->crtc_vsync_start - adj->crtc_vdisplay; |
| 490 | tm = adj->crtc_vtotal - adj->crtc_vsync_end; |
| 491 | |
| 492 | DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n", |
| 493 | adj->crtc_hdisplay, |
| 494 | adj->crtc_hsync_start, |
| 495 | adj->crtc_hsync_end, |
| 496 | adj->crtc_htotal, lm, rm); |
| 497 | DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n", |
| 498 | adj->crtc_vdisplay, |
| 499 | adj->crtc_vsync_start, |
| 500 | adj->crtc_vsync_end, |
| 501 | adj->crtc_vtotal, tm, bm); |
| 502 | |
| 503 | /* Wait for pending flips to complete */ |
| 504 | wait_event(dcrtc->frame_wait, !dcrtc->frame_work); |
| 505 | |
| 506 | drm_vblank_pre_modeset(crtc->dev, dcrtc->num); |
| 507 | |
| 508 | crtc->mode = *adj; |
| 509 | |
| 510 | val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA; |
| 511 | if (val != dcrtc->dumb_ctrl) { |
| 512 | dcrtc->dumb_ctrl = val; |
| 513 | writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL); |
| 514 | } |
| 515 | |
| 516 | /* Now compute the divider for real */ |
| 517 | priv->variant->crtc_compute_clock(dcrtc, adj, &sclk); |
| 518 | |
| 519 | /* Ensure graphic fifo is enabled */ |
| 520 | armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1); |
| 521 | armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); |
| 522 | |
| 523 | if (interlaced ^ dcrtc->interlaced) { |
| 524 | if (adj->flags & DRM_MODE_FLAG_INTERLACE) |
| 525 | drm_vblank_get(dcrtc->crtc.dev, dcrtc->num); |
| 526 | else |
| 527 | drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); |
| 528 | dcrtc->interlaced = interlaced; |
| 529 | } |
| 530 | |
| 531 | spin_lock_irqsave(&dcrtc->irq_lock, flags); |
| 532 | |
| 533 | /* Even interlaced/progressive frame */ |
| 534 | dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | |
| 535 | adj->crtc_htotal; |
| 536 | dcrtc->v[1].spu_v_porch = tm << 16 | bm; |
| 537 | val = adj->crtc_hsync_start; |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 538 | dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | |
| 539 | priv->variant->spu_adv_reg; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 540 | |
| 541 | if (interlaced) { |
| 542 | /* Odd interlaced frame */ |
| 543 | dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total + |
| 544 | (1 << 16); |
| 545 | dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1; |
| 546 | val = adj->crtc_hsync_start - adj->crtc_htotal / 2; |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 547 | dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | |
| 548 | priv->variant->spu_adv_reg; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 549 | } else { |
| 550 | dcrtc->v[0] = dcrtc->v[1]; |
| 551 | } |
| 552 | |
| 553 | val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; |
| 554 | |
| 555 | armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); |
| 556 | armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN); |
| 557 | armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN); |
| 558 | armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH); |
| 559 | armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); |
| 560 | armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, |
| 561 | LCD_SPUT_V_H_TOTAL); |
| 562 | |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 563 | if (priv->variant->has_spu_adv_reg) { |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 564 | armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, |
| 565 | ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | |
| 566 | ADV_VSYNCOFFEN, LCD_SPU_ADV_REG); |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 567 | } |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 568 | |
| 569 | val = CFG_GRA_ENA | CFG_GRA_HSMOOTH; |
| 570 | val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.fb)->fmt); |
| 571 | val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.fb)->mod); |
| 572 | |
| 573 | if (drm_fb_to_armada_fb(dcrtc->crtc.fb)->fmt > CFG_420) |
| 574 | val |= CFG_PALETTE_ENA; |
| 575 | |
| 576 | if (interlaced) |
| 577 | val |= CFG_GRA_FTOGGLE; |
| 578 | |
| 579 | armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT | |
| 580 | CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV | |
| 581 | CFG_SWAPYU | CFG_YUV2RGB) | |
| 582 | CFG_PALETTE_ENA | CFG_GRA_FTOGGLE, |
| 583 | LCD_SPU_DMA_CTRL0); |
| 584 | |
| 585 | val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0; |
| 586 | armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1); |
| 587 | |
| 588 | val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc); |
| 589 | armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL); |
| 590 | armada_reg_queue_end(regs, i); |
| 591 | |
| 592 | armada_drm_crtc_update_regs(dcrtc, regs); |
| 593 | spin_unlock_irqrestore(&dcrtc->irq_lock, flags); |
| 594 | |
| 595 | armada_drm_crtc_update(dcrtc); |
| 596 | |
| 597 | drm_vblank_post_modeset(crtc->dev, dcrtc->num); |
| 598 | armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); |
| 599 | |
| 600 | return 0; |
| 601 | } |
| 602 | |
| 603 | /* The mode_config.mutex will be held for this call */ |
| 604 | static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
| 605 | struct drm_framebuffer *old_fb) |
| 606 | { |
| 607 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 608 | struct armada_regs regs[4]; |
| 609 | unsigned i; |
| 610 | |
| 611 | i = armada_drm_crtc_calc_fb(crtc->fb, crtc->x, crtc->y, regs, |
| 612 | dcrtc->interlaced); |
| 613 | armada_reg_queue_end(regs, i); |
| 614 | |
| 615 | /* Wait for pending flips to complete */ |
| 616 | wait_event(dcrtc->frame_wait, !dcrtc->frame_work); |
| 617 | |
| 618 | /* Take a reference to the new fb as we're using it */ |
| 619 | drm_framebuffer_reference(crtc->fb); |
| 620 | |
| 621 | /* Update the base in the CRTC */ |
| 622 | armada_drm_crtc_update_regs(dcrtc, regs); |
| 623 | |
| 624 | /* Drop our previously held reference */ |
| 625 | armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); |
| 626 | |
| 627 | return 0; |
| 628 | } |
| 629 | |
| 630 | static void armada_drm_crtc_load_lut(struct drm_crtc *crtc) |
| 631 | { |
| 632 | } |
| 633 | |
| 634 | /* The mode_config.mutex will be held for this call */ |
| 635 | static void armada_drm_crtc_disable(struct drm_crtc *crtc) |
| 636 | { |
| 637 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 638 | |
| 639 | armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
| 640 | armada_drm_crtc_finish_fb(dcrtc, crtc->fb, true); |
| 641 | |
| 642 | /* Power down most RAMs and FIFOs */ |
| 643 | writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | |
| 644 | CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 | |
| 645 | CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); |
| 646 | } |
| 647 | |
| 648 | static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = { |
| 649 | .dpms = armada_drm_crtc_dpms, |
| 650 | .prepare = armada_drm_crtc_prepare, |
| 651 | .commit = armada_drm_crtc_commit, |
| 652 | .mode_fixup = armada_drm_crtc_mode_fixup, |
| 653 | .mode_set = armada_drm_crtc_mode_set, |
| 654 | .mode_set_base = armada_drm_crtc_mode_set_base, |
| 655 | .load_lut = armada_drm_crtc_load_lut, |
| 656 | .disable = armada_drm_crtc_disable, |
| 657 | }; |
| 658 | |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 659 | static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix, |
| 660 | unsigned stride, unsigned width, unsigned height) |
| 661 | { |
| 662 | uint32_t addr; |
| 663 | unsigned y; |
| 664 | |
| 665 | addr = SRAM_HWC32_RAM1; |
| 666 | for (y = 0; y < height; y++) { |
| 667 | uint32_t *p = &pix[y * stride]; |
| 668 | unsigned x; |
| 669 | |
| 670 | for (x = 0; x < width; x++, p++) { |
| 671 | uint32_t val = *p; |
| 672 | |
| 673 | val = (val & 0xff00ff00) | |
| 674 | (val & 0x000000ff) << 16 | |
| 675 | (val & 0x00ff0000) >> 16; |
| 676 | |
| 677 | writel_relaxed(val, |
| 678 | base + LCD_SPU_SRAM_WRDAT); |
| 679 | writel_relaxed(addr | SRAM_WRITE, |
| 680 | base + LCD_SPU_SRAM_CTRL); |
| 681 | addr += 1; |
| 682 | if ((addr & 0x00ff) == 0) |
| 683 | addr += 0xf00; |
| 684 | if ((addr & 0x30ff) == 0) |
| 685 | addr = SRAM_HWC32_RAM2; |
| 686 | } |
| 687 | } |
| 688 | } |
| 689 | |
| 690 | static void armada_drm_crtc_cursor_tran(void __iomem *base) |
| 691 | { |
| 692 | unsigned addr; |
| 693 | |
| 694 | for (addr = 0; addr < 256; addr++) { |
| 695 | /* write the default value */ |
| 696 | writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT); |
| 697 | writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN, |
| 698 | base + LCD_SPU_SRAM_CTRL); |
| 699 | } |
| 700 | } |
| 701 | |
| 702 | static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload) |
| 703 | { |
| 704 | uint32_t xoff, xscr, w = dcrtc->cursor_w, s; |
| 705 | uint32_t yoff, yscr, h = dcrtc->cursor_h; |
| 706 | uint32_t para1; |
| 707 | |
| 708 | /* |
| 709 | * Calculate the visible width and height of the cursor, |
| 710 | * screen position, and the position in the cursor bitmap. |
| 711 | */ |
| 712 | if (dcrtc->cursor_x < 0) { |
| 713 | xoff = -dcrtc->cursor_x; |
| 714 | xscr = 0; |
| 715 | w -= min(xoff, w); |
| 716 | } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) { |
| 717 | xoff = 0; |
| 718 | xscr = dcrtc->cursor_x; |
| 719 | w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0); |
| 720 | } else { |
| 721 | xoff = 0; |
| 722 | xscr = dcrtc->cursor_x; |
| 723 | } |
| 724 | |
| 725 | if (dcrtc->cursor_y < 0) { |
| 726 | yoff = -dcrtc->cursor_y; |
| 727 | yscr = 0; |
| 728 | h -= min(yoff, h); |
| 729 | } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) { |
| 730 | yoff = 0; |
| 731 | yscr = dcrtc->cursor_y; |
| 732 | h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0); |
| 733 | } else { |
| 734 | yoff = 0; |
| 735 | yscr = dcrtc->cursor_y; |
| 736 | } |
| 737 | |
| 738 | /* On interlaced modes, the vertical cursor size must be halved */ |
| 739 | s = dcrtc->cursor_w; |
| 740 | if (dcrtc->interlaced) { |
| 741 | s *= 2; |
| 742 | yscr /= 2; |
| 743 | h /= 2; |
| 744 | } |
| 745 | |
| 746 | if (!dcrtc->cursor_obj || !h || !w) { |
| 747 | spin_lock_irq(&dcrtc->irq_lock); |
| 748 | armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); |
| 749 | dcrtc->cursor_update = false; |
| 750 | armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); |
| 751 | spin_unlock_irq(&dcrtc->irq_lock); |
| 752 | return 0; |
| 753 | } |
| 754 | |
| 755 | para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); |
| 756 | armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32, |
| 757 | dcrtc->base + LCD_SPU_SRAM_PARA1); |
| 758 | |
| 759 | /* |
| 760 | * Initialize the transparency if the SRAM was powered down. |
| 761 | * We must also reload the cursor data as well. |
| 762 | */ |
| 763 | if (!(para1 & CFG_CSB_256x32)) { |
| 764 | armada_drm_crtc_cursor_tran(dcrtc->base); |
| 765 | reload = true; |
| 766 | } |
| 767 | |
| 768 | if (dcrtc->cursor_hw_sz != (h << 16 | w)) { |
| 769 | spin_lock_irq(&dcrtc->irq_lock); |
| 770 | armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); |
| 771 | dcrtc->cursor_update = false; |
| 772 | armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); |
| 773 | spin_unlock_irq(&dcrtc->irq_lock); |
| 774 | reload = true; |
| 775 | } |
| 776 | if (reload) { |
| 777 | struct armada_gem_object *obj = dcrtc->cursor_obj; |
| 778 | uint32_t *pix; |
| 779 | /* Set the top-left corner of the cursor image */ |
| 780 | pix = obj->addr; |
| 781 | pix += yoff * s + xoff; |
| 782 | armada_load_cursor_argb(dcrtc->base, pix, s, w, h); |
| 783 | } |
| 784 | |
| 785 | /* Reload the cursor position, size and enable in the IRQ handler */ |
| 786 | spin_lock_irq(&dcrtc->irq_lock); |
| 787 | dcrtc->cursor_hw_pos = yscr << 16 | xscr; |
| 788 | dcrtc->cursor_hw_sz = h << 16 | w; |
| 789 | dcrtc->cursor_update = true; |
| 790 | armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); |
| 791 | spin_unlock_irq(&dcrtc->irq_lock); |
| 792 | |
| 793 | return 0; |
| 794 | } |
| 795 | |
| 796 | static void cursor_update(void *data) |
| 797 | { |
| 798 | armada_drm_crtc_cursor_update(data, true); |
| 799 | } |
| 800 | |
| 801 | static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc, |
| 802 | struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h) |
| 803 | { |
| 804 | struct drm_device *dev = crtc->dev; |
| 805 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 806 | struct armada_private *priv = crtc->dev->dev_private; |
| 807 | struct armada_gem_object *obj = NULL; |
| 808 | int ret; |
| 809 | |
| 810 | /* If no cursor support, replicate drm's return value */ |
| 811 | if (!priv->variant->has_spu_adv_reg) |
| 812 | return -ENXIO; |
| 813 | |
| 814 | if (handle && w > 0 && h > 0) { |
| 815 | /* maximum size is 64x32 or 32x64 */ |
| 816 | if (w > 64 || h > 64 || (w > 32 && h > 32)) |
| 817 | return -ENOMEM; |
| 818 | |
| 819 | obj = armada_gem_object_lookup(dev, file, handle); |
| 820 | if (!obj) |
| 821 | return -ENOENT; |
| 822 | |
| 823 | /* Must be a kernel-mapped object */ |
| 824 | if (!obj->addr) { |
| 825 | drm_gem_object_unreference_unlocked(&obj->obj); |
| 826 | return -EINVAL; |
| 827 | } |
| 828 | |
| 829 | if (obj->obj.size < w * h * 4) { |
| 830 | DRM_ERROR("buffer is too small\n"); |
| 831 | drm_gem_object_unreference_unlocked(&obj->obj); |
| 832 | return -ENOMEM; |
| 833 | } |
| 834 | } |
| 835 | |
| 836 | mutex_lock(&dev->struct_mutex); |
| 837 | if (dcrtc->cursor_obj) { |
| 838 | dcrtc->cursor_obj->update = NULL; |
| 839 | dcrtc->cursor_obj->update_data = NULL; |
| 840 | drm_gem_object_unreference(&dcrtc->cursor_obj->obj); |
| 841 | } |
| 842 | dcrtc->cursor_obj = obj; |
| 843 | dcrtc->cursor_w = w; |
| 844 | dcrtc->cursor_h = h; |
| 845 | ret = armada_drm_crtc_cursor_update(dcrtc, true); |
| 846 | if (obj) { |
| 847 | obj->update_data = dcrtc; |
| 848 | obj->update = cursor_update; |
| 849 | } |
| 850 | mutex_unlock(&dev->struct_mutex); |
| 851 | |
| 852 | return ret; |
| 853 | } |
| 854 | |
| 855 | static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 856 | { |
| 857 | struct drm_device *dev = crtc->dev; |
| 858 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 859 | struct armada_private *priv = crtc->dev->dev_private; |
| 860 | int ret; |
| 861 | |
| 862 | /* If no cursor support, replicate drm's return value */ |
| 863 | if (!priv->variant->has_spu_adv_reg) |
| 864 | return -EFAULT; |
| 865 | |
| 866 | mutex_lock(&dev->struct_mutex); |
| 867 | dcrtc->cursor_x = x; |
| 868 | dcrtc->cursor_y = y; |
| 869 | ret = armada_drm_crtc_cursor_update(dcrtc, false); |
| 870 | mutex_unlock(&dev->struct_mutex); |
| 871 | |
| 872 | return ret; |
| 873 | } |
| 874 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 875 | static void armada_drm_crtc_destroy(struct drm_crtc *crtc) |
| 876 | { |
| 877 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 878 | struct armada_private *priv = crtc->dev->dev_private; |
| 879 | |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 880 | if (dcrtc->cursor_obj) |
| 881 | drm_gem_object_unreference(&dcrtc->cursor_obj->obj); |
| 882 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 883 | priv->dcrtc[dcrtc->num] = NULL; |
| 884 | drm_crtc_cleanup(&dcrtc->crtc); |
| 885 | |
| 886 | if (!IS_ERR(dcrtc->clk)) |
| 887 | clk_disable_unprepare(dcrtc->clk); |
| 888 | |
| 889 | kfree(dcrtc); |
| 890 | } |
| 891 | |
| 892 | /* |
| 893 | * The mode_config lock is held here, to prevent races between this |
| 894 | * and a mode_set. |
| 895 | */ |
| 896 | static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, |
Dave Airlie | 5e4e3ba | 2013-10-22 09:38:18 +0100 | [diff] [blame] | 897 | struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags) |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 898 | { |
| 899 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 900 | struct armada_frame_work *work; |
| 901 | struct drm_device *dev = crtc->dev; |
| 902 | unsigned long flags; |
| 903 | unsigned i; |
| 904 | int ret; |
| 905 | |
| 906 | /* We don't support changing the pixel format */ |
| 907 | if (fb->pixel_format != crtc->fb->pixel_format) |
| 908 | return -EINVAL; |
| 909 | |
| 910 | work = kmalloc(sizeof(*work), GFP_KERNEL); |
| 911 | if (!work) |
| 912 | return -ENOMEM; |
| 913 | |
| 914 | work->event = event; |
| 915 | work->old_fb = dcrtc->crtc.fb; |
| 916 | |
| 917 | i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs, |
| 918 | dcrtc->interlaced); |
| 919 | armada_reg_queue_end(work->regs, i); |
| 920 | |
| 921 | /* |
| 922 | * Hold the old framebuffer for the work - DRM appears to drop our |
| 923 | * reference to the old framebuffer in drm_mode_page_flip_ioctl(). |
| 924 | */ |
| 925 | drm_framebuffer_reference(work->old_fb); |
| 926 | |
| 927 | ret = armada_drm_crtc_queue_frame_work(dcrtc, work); |
| 928 | if (ret) { |
| 929 | /* |
| 930 | * Undo our reference above; DRM does not drop the reference |
| 931 | * to this object on error, so that's okay. |
| 932 | */ |
| 933 | drm_framebuffer_unreference(work->old_fb); |
| 934 | kfree(work); |
| 935 | return ret; |
| 936 | } |
| 937 | |
| 938 | /* |
| 939 | * Don't take a reference on the new framebuffer; |
| 940 | * drm_mode_page_flip_ioctl() has already grabbed a reference and |
| 941 | * will _not_ drop that reference on successful return from this |
| 942 | * function. Simply mark this new framebuffer as the current one. |
| 943 | */ |
| 944 | dcrtc->crtc.fb = fb; |
| 945 | |
| 946 | /* |
| 947 | * Finally, if the display is blanked, we won't receive an |
| 948 | * interrupt, so complete it now. |
| 949 | */ |
| 950 | if (dpms_blanked(dcrtc->dpms)) { |
| 951 | spin_lock_irqsave(&dev->event_lock, flags); |
| 952 | if (dcrtc->frame_work) |
| 953 | armada_drm_crtc_complete_frame_work(dcrtc); |
| 954 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 955 | } |
| 956 | |
| 957 | return 0; |
| 958 | } |
| 959 | |
| 960 | static int |
| 961 | armada_drm_crtc_set_property(struct drm_crtc *crtc, |
| 962 | struct drm_property *property, uint64_t val) |
| 963 | { |
| 964 | struct armada_private *priv = crtc->dev->dev_private; |
| 965 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 966 | bool update_csc = false; |
| 967 | |
| 968 | if (property == priv->csc_yuv_prop) { |
| 969 | dcrtc->csc_yuv_mode = val; |
| 970 | update_csc = true; |
| 971 | } else if (property == priv->csc_rgb_prop) { |
| 972 | dcrtc->csc_rgb_mode = val; |
| 973 | update_csc = true; |
| 974 | } |
| 975 | |
| 976 | if (update_csc) { |
| 977 | uint32_t val; |
| 978 | |
| 979 | val = dcrtc->spu_iopad_ctrl | |
| 980 | armada_drm_crtc_calculate_csc(dcrtc); |
| 981 | writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL); |
| 982 | } |
| 983 | |
| 984 | return 0; |
| 985 | } |
| 986 | |
| 987 | static struct drm_crtc_funcs armada_crtc_funcs = { |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 988 | .cursor_set = armada_drm_crtc_cursor_set, |
| 989 | .cursor_move = armada_drm_crtc_cursor_move, |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 990 | .destroy = armada_drm_crtc_destroy, |
| 991 | .set_config = drm_crtc_helper_set_config, |
| 992 | .page_flip = armada_drm_crtc_page_flip, |
| 993 | .set_property = armada_drm_crtc_set_property, |
| 994 | }; |
| 995 | |
| 996 | static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = { |
| 997 | { CSC_AUTO, "Auto" }, |
| 998 | { CSC_YUV_CCIR601, "CCIR601" }, |
| 999 | { CSC_YUV_CCIR709, "CCIR709" }, |
| 1000 | }; |
| 1001 | |
| 1002 | static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = { |
| 1003 | { CSC_AUTO, "Auto" }, |
| 1004 | { CSC_RGB_COMPUTER, "Computer system" }, |
| 1005 | { CSC_RGB_STUDIO, "Studio" }, |
| 1006 | }; |
| 1007 | |
| 1008 | static int armada_drm_crtc_create_properties(struct drm_device *dev) |
| 1009 | { |
| 1010 | struct armada_private *priv = dev->dev_private; |
| 1011 | |
| 1012 | if (priv->csc_yuv_prop) |
| 1013 | return 0; |
| 1014 | |
| 1015 | priv->csc_yuv_prop = drm_property_create_enum(dev, 0, |
| 1016 | "CSC_YUV", armada_drm_csc_yuv_enum_list, |
| 1017 | ARRAY_SIZE(armada_drm_csc_yuv_enum_list)); |
| 1018 | priv->csc_rgb_prop = drm_property_create_enum(dev, 0, |
| 1019 | "CSC_RGB", armada_drm_csc_rgb_enum_list, |
| 1020 | ARRAY_SIZE(armada_drm_csc_rgb_enum_list)); |
| 1021 | |
| 1022 | if (!priv->csc_yuv_prop || !priv->csc_rgb_prop) |
| 1023 | return -ENOMEM; |
| 1024 | |
| 1025 | return 0; |
| 1026 | } |
| 1027 | |
| 1028 | int armada_drm_crtc_create(struct drm_device *dev, unsigned num, |
| 1029 | struct resource *res) |
| 1030 | { |
| 1031 | struct armada_private *priv = dev->dev_private; |
| 1032 | struct armada_crtc *dcrtc; |
| 1033 | void __iomem *base; |
| 1034 | int ret; |
| 1035 | |
| 1036 | ret = armada_drm_crtc_create_properties(dev); |
| 1037 | if (ret) |
| 1038 | return ret; |
| 1039 | |
| 1040 | base = devm_request_and_ioremap(dev->dev, res); |
| 1041 | if (!base) { |
| 1042 | DRM_ERROR("failed to ioremap register\n"); |
| 1043 | return -ENOMEM; |
| 1044 | } |
| 1045 | |
| 1046 | dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL); |
| 1047 | if (!dcrtc) { |
| 1048 | DRM_ERROR("failed to allocate Armada crtc\n"); |
| 1049 | return -ENOMEM; |
| 1050 | } |
| 1051 | |
| 1052 | dcrtc->base = base; |
| 1053 | dcrtc->num = num; |
| 1054 | dcrtc->clk = ERR_PTR(-EINVAL); |
| 1055 | dcrtc->csc_yuv_mode = CSC_AUTO; |
| 1056 | dcrtc->csc_rgb_mode = CSC_AUTO; |
| 1057 | dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0; |
| 1058 | dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; |
| 1059 | spin_lock_init(&dcrtc->irq_lock); |
| 1060 | dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; |
| 1061 | INIT_LIST_HEAD(&dcrtc->vbl_list); |
| 1062 | init_waitqueue_head(&dcrtc->frame_wait); |
| 1063 | |
| 1064 | /* Initialize some registers which we don't otherwise set */ |
| 1065 | writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); |
| 1066 | writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); |
| 1067 | writel_relaxed(dcrtc->spu_iopad_ctrl, |
| 1068 | dcrtc->base + LCD_SPU_IOPAD_CONTROL); |
| 1069 | writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); |
| 1070 | writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | |
| 1071 | CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 | |
| 1072 | CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); |
| 1073 | writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); |
| 1074 | writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN); |
| 1075 | |
| 1076 | if (priv->variant->crtc_init) { |
| 1077 | ret = priv->variant->crtc_init(dcrtc); |
| 1078 | if (ret) { |
| 1079 | kfree(dcrtc); |
| 1080 | return ret; |
| 1081 | } |
| 1082 | } |
| 1083 | |
| 1084 | /* Ensure AXI pipeline is enabled */ |
| 1085 | armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); |
| 1086 | |
| 1087 | priv->dcrtc[dcrtc->num] = dcrtc; |
| 1088 | |
| 1089 | drm_crtc_init(dev, &dcrtc->crtc, &armada_crtc_funcs); |
| 1090 | drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); |
| 1091 | |
| 1092 | drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop, |
| 1093 | dcrtc->csc_yuv_mode); |
| 1094 | drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop, |
| 1095 | dcrtc->csc_rgb_mode); |
| 1096 | |
| 1097 | return armada_overlay_plane_create(dev, 1 << dcrtc->num); |
| 1098 | } |