Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 1999 - 2003 ARM Limited |
| 3 | * Copyright 2000 Deep Blue Solutions Ltd |
| 4 | * Copyright 2008 Cavium Networks |
| 5 | * |
| 6 | * This file is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License, Version 2, as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/clockchips.h> |
| 14 | #include <linux/io.h> |
Rob Herring | 520f7bd | 2012-12-27 13:10:24 -0600 | [diff] [blame] | 15 | #include <linux/irqchip/arm-gic.h> |
Arnd Bergmann | 415f5914 | 2013-03-14 22:27:32 +0100 | [diff] [blame] | 16 | #include <linux/of_platform.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/usb/ehci_pdriver.h> |
| 19 | #include <linux/usb/ohci_pdriver.h> |
| 20 | #include <asm/mach/arch.h> |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 21 | #include <asm/mach/map.h> |
| 22 | #include <asm/mach/time.h> |
| 23 | #include <asm/mach/irq.h> |
Anton Vorontsov | 93e85d8 | 2011-07-06 16:45:09 +0400 | [diff] [blame] | 24 | #include <asm/hardware/cache-l2x0.h> |
Arnd Bergmann | 3f9fb2a | 2013-03-13 13:15:25 +0100 | [diff] [blame] | 25 | #include "cns3xxx.h" |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 26 | #include "core.h" |
Arnd Bergmann | 415f5914 | 2013-03-14 22:27:32 +0100 | [diff] [blame] | 27 | #include "pm.h" |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 28 | |
| 29 | static struct map_desc cns3xxx_io_desc[] __initdata = { |
| 30 | { |
Mac Lin | a3d9052 | 2013-03-25 17:23:33 +0800 | [diff] [blame] | 31 | .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT, |
| 32 | .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE), |
| 33 | .length = SZ_8K, |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 34 | .type = MT_DEVICE, |
| 35 | }, { |
| 36 | .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, |
| 37 | .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE), |
| 38 | .length = SZ_4K, |
| 39 | .type = MT_DEVICE, |
| 40 | }, { |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 41 | .virtual = CNS3XXX_MISC_BASE_VIRT, |
| 42 | .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE), |
| 43 | .length = SZ_4K, |
| 44 | .type = MT_DEVICE, |
| 45 | }, { |
| 46 | .virtual = CNS3XXX_PM_BASE_VIRT, |
| 47 | .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), |
| 48 | .length = SZ_4K, |
| 49 | .type = MT_DEVICE, |
Krzysztof HaĆasa | 64cf9d0 | 2014-03-04 08:37:10 +0100 | [diff] [blame] | 50 | #ifdef CONFIG_PCI |
| 51 | }, { |
| 52 | .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, |
| 53 | .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE), |
| 54 | .length = SZ_4K, |
| 55 | .type = MT_DEVICE, |
| 56 | }, { |
| 57 | .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT, |
| 58 | .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE), |
| 59 | .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ |
| 60 | .type = MT_DEVICE, |
| 61 | }, { |
| 62 | .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT, |
| 63 | .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE), |
| 64 | .length = SZ_16M, |
| 65 | .type = MT_DEVICE, |
| 66 | }, { |
| 67 | .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT, |
| 68 | .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE), |
| 69 | .length = SZ_4K, |
| 70 | .type = MT_DEVICE, |
| 71 | }, { |
| 72 | .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT, |
| 73 | .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE), |
| 74 | .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ |
| 75 | .type = MT_DEVICE, |
| 76 | }, { |
| 77 | .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT, |
| 78 | .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE), |
| 79 | .length = SZ_16M, |
| 80 | .type = MT_DEVICE, |
| 81 | #endif |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 82 | }, |
| 83 | }; |
| 84 | |
| 85 | void __init cns3xxx_map_io(void) |
| 86 | { |
| 87 | iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc)); |
| 88 | } |
| 89 | |
| 90 | /* used by entry-macro.S */ |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 91 | void __init cns3xxx_init_irq(void) |
| 92 | { |
Rob Herring | a2a47ca | 2012-03-09 17:16:40 -0600 | [diff] [blame] | 93 | gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), |
| 94 | IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | void cns3xxx_power_off(void) |
| 98 | { |
Rob Herring | a2a47ca | 2012-03-09 17:16:40 -0600 | [diff] [blame] | 99 | u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT); |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 100 | u32 clkctrl; |
| 101 | |
| 102 | printk(KERN_INFO "powering system down...\n"); |
| 103 | |
| 104 | clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET); |
| 105 | clkctrl &= 0xfffff1ff; |
| 106 | clkctrl |= (0x5 << 9); /* Hibernate */ |
| 107 | writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); |
| 108 | |
| 109 | } |
| 110 | |
| 111 | /* |
| 112 | * Timer |
| 113 | */ |
| 114 | static void __iomem *cns3xxx_tmr1; |
| 115 | |
| 116 | static void cns3xxx_timer_set_mode(enum clock_event_mode mode, |
| 117 | struct clock_event_device *clk) |
| 118 | { |
| 119 | unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
| 120 | int pclk = cns3xxx_cpu_clock() / 8; |
| 121 | int reload; |
| 122 | |
| 123 | switch (mode) { |
| 124 | case CLOCK_EVT_MODE_PERIODIC: |
| 125 | reload = pclk * 20 / (3 * HZ) * 0x25000; |
| 126 | writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); |
| 127 | ctrl |= (1 << 0) | (1 << 2) | (1 << 9); |
| 128 | break; |
| 129 | case CLOCK_EVT_MODE_ONESHOT: |
| 130 | /* period set, and timer enabled in 'next_event' hook */ |
| 131 | ctrl |= (1 << 2) | (1 << 9); |
| 132 | break; |
| 133 | case CLOCK_EVT_MODE_UNUSED: |
| 134 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 135 | default: |
| 136 | ctrl = 0; |
| 137 | } |
| 138 | |
| 139 | writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
| 140 | } |
| 141 | |
| 142 | static int cns3xxx_timer_set_next_event(unsigned long evt, |
| 143 | struct clock_event_device *unused) |
| 144 | { |
| 145 | unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
| 146 | |
| 147 | writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); |
| 148 | writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
| 149 | |
| 150 | return 0; |
| 151 | } |
| 152 | |
| 153 | static struct clock_event_device cns3xxx_tmr1_clockevent = { |
| 154 | .name = "cns3xxx timer1", |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 155 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
| 156 | .set_mode = cns3xxx_timer_set_mode, |
| 157 | .set_next_event = cns3xxx_timer_set_next_event, |
| 158 | .rating = 350, |
| 159 | .cpumask = cpu_all_mask, |
| 160 | }; |
| 161 | |
| 162 | static void __init cns3xxx_clockevents_init(unsigned int timer_irq) |
| 163 | { |
| 164 | cns3xxx_tmr1_clockevent.irq = timer_irq; |
Shawn Guo | 838a2ae | 2013-01-12 11:50:05 +0000 | [diff] [blame] | 165 | clockevents_config_and_register(&cns3xxx_tmr1_clockevent, |
| 166 | (cns3xxx_cpu_clock() >> 3) * 1000000, |
| 167 | 0xf, 0xffffffff); |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | /* |
| 171 | * IRQ handler for the timer |
| 172 | */ |
| 173 | static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id) |
| 174 | { |
| 175 | struct clock_event_device *evt = &cns3xxx_tmr1_clockevent; |
| 176 | u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET; |
| 177 | u32 val; |
| 178 | |
| 179 | /* Clear the interrupt */ |
| 180 | val = readl(stat); |
| 181 | writel(val & ~(1 << 2), stat); |
| 182 | |
| 183 | evt->event_handler(evt); |
| 184 | |
| 185 | return IRQ_HANDLED; |
| 186 | } |
| 187 | |
| 188 | static struct irqaction cns3xxx_timer_irq = { |
| 189 | .name = "timer", |
Michael Opdenacker | 19bd9b2 | 2014-03-04 21:56:10 +0100 | [diff] [blame] | 190 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 191 | .handler = cns3xxx_timer_interrupt, |
| 192 | }; |
| 193 | |
| 194 | /* |
| 195 | * Set up the clock source and clock events devices |
| 196 | */ |
| 197 | static void __init __cns3xxx_timer_init(unsigned int timer_irq) |
| 198 | { |
| 199 | u32 val; |
| 200 | u32 irq_mask; |
| 201 | |
| 202 | /* |
| 203 | * Initialise to a known state (all timers off) |
| 204 | */ |
| 205 | |
| 206 | /* disable timer1 and timer2 */ |
| 207 | writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
| 208 | /* stop free running timer3 */ |
| 209 | writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); |
| 210 | |
| 211 | /* timer1 */ |
| 212 | writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); |
| 213 | writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); |
| 214 | |
| 215 | writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); |
| 216 | writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); |
| 217 | |
| 218 | /* mask irq, non-mask timer1 overflow */ |
| 219 | irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); |
| 220 | irq_mask &= ~(1 << 2); |
| 221 | irq_mask |= 0x03; |
| 222 | writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); |
| 223 | |
| 224 | /* down counter */ |
| 225 | val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
| 226 | val |= (1 << 9); |
| 227 | writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
| 228 | |
| 229 | /* timer2 */ |
| 230 | writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); |
| 231 | writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); |
| 232 | |
| 233 | /* mask irq */ |
| 234 | irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); |
| 235 | irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); |
| 236 | writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); |
| 237 | |
| 238 | /* down counter */ |
| 239 | val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
| 240 | val |= (1 << 10); |
| 241 | writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
| 242 | |
| 243 | /* Make irqs happen for the system timer */ |
| 244 | setup_irq(timer_irq, &cns3xxx_timer_irq); |
| 245 | |
| 246 | cns3xxx_clockevents_init(timer_irq); |
| 247 | } |
| 248 | |
Stephen Warren | 6bb27d7 | 2012-11-08 12:40:59 -0700 | [diff] [blame] | 249 | void __init cns3xxx_timer_init(void) |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 250 | { |
Rob Herring | a2a47ca | 2012-03-09 17:16:40 -0600 | [diff] [blame] | 251 | cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT); |
Anton Vorontsov | d94f944 | 2010-03-25 17:12:41 +0300 | [diff] [blame] | 252 | |
| 253 | __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0); |
| 254 | } |
| 255 | |
Anton Vorontsov | 93e85d8 | 2011-07-06 16:45:09 +0400 | [diff] [blame] | 256 | #ifdef CONFIG_CACHE_L2X0 |
| 257 | |
| 258 | void __init cns3xxx_l2x0_init(void) |
| 259 | { |
| 260 | void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); |
| 261 | u32 val; |
| 262 | |
| 263 | if (WARN_ON(!base)) |
| 264 | return; |
| 265 | |
| 266 | /* |
| 267 | * Tag RAM Control register |
| 268 | * |
| 269 | * bit[10:8] - 1 cycle of write accesses latency |
| 270 | * bit[6:4] - 1 cycle of read accesses latency |
| 271 | * bit[3:0] - 1 cycle of setup latency |
| 272 | * |
| 273 | * 1 cycle of latency for setup, read and write accesses |
| 274 | */ |
Russell King | 1a5a954 | 2014-03-16 20:52:25 +0000 | [diff] [blame] | 275 | val = readl(base + L310_TAG_LATENCY_CTRL); |
Anton Vorontsov | 93e85d8 | 2011-07-06 16:45:09 +0400 | [diff] [blame] | 276 | val &= 0xfffff888; |
Russell King | 1a5a954 | 2014-03-16 20:52:25 +0000 | [diff] [blame] | 277 | writel(val, base + L310_TAG_LATENCY_CTRL); |
Anton Vorontsov | 93e85d8 | 2011-07-06 16:45:09 +0400 | [diff] [blame] | 278 | |
| 279 | /* |
| 280 | * Data RAM Control register |
| 281 | * |
| 282 | * bit[10:8] - 1 cycles of write accesses latency |
| 283 | * bit[6:4] - 1 cycles of read accesses latency |
| 284 | * bit[3:0] - 1 cycle of setup latency |
| 285 | * |
| 286 | * 1 cycle of latency for setup, read and write accesses |
| 287 | */ |
Russell King | 1a5a954 | 2014-03-16 20:52:25 +0000 | [diff] [blame] | 288 | val = readl(base + L310_DATA_LATENCY_CTRL); |
Anton Vorontsov | 93e85d8 | 2011-07-06 16:45:09 +0400 | [diff] [blame] | 289 | val &= 0xfffff888; |
Russell King | 1a5a954 | 2014-03-16 20:52:25 +0000 | [diff] [blame] | 290 | writel(val, base + L310_DATA_LATENCY_CTRL); |
Anton Vorontsov | 93e85d8 | 2011-07-06 16:45:09 +0400 | [diff] [blame] | 291 | |
| 292 | /* 32 KiB, 8-way, parity disable */ |
Russell King | 24cb65f | 2014-03-19 12:06:27 +0000 | [diff] [blame] | 293 | l2x0_init(base, 0x00500000, 0xfe0f0fff); |
Anton Vorontsov | 93e85d8 | 2011-07-06 16:45:09 +0400 | [diff] [blame] | 294 | } |
| 295 | |
| 296 | #endif /* CONFIG_CACHE_L2X0 */ |
Arnd Bergmann | 415f5914 | 2013-03-14 22:27:32 +0100 | [diff] [blame] | 297 | |
| 298 | static int csn3xxx_usb_power_on(struct platform_device *pdev) |
| 299 | { |
| 300 | /* |
| 301 | * EHCI and OHCI share the same clock and power, |
| 302 | * resetting twice would cause the 1st controller been reset. |
| 303 | * Therefore only do power up at the first up device, and |
| 304 | * power down at the last down device. |
| 305 | * |
| 306 | * Set USB AHB INCR length to 16 |
| 307 | */ |
| 308 | if (atomic_inc_return(&usb_pwr_ref) == 1) { |
| 309 | cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); |
| 310 | cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); |
| 311 | cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); |
| 312 | __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), |
| 313 | MISC_CHIP_CONFIG_REG); |
| 314 | } |
| 315 | |
| 316 | return 0; |
| 317 | } |
| 318 | |
| 319 | static void csn3xxx_usb_power_off(struct platform_device *pdev) |
| 320 | { |
| 321 | /* |
| 322 | * EHCI and OHCI share the same clock and power, |
| 323 | * resetting twice would cause the 1st controller been reset. |
| 324 | * Therefore only do power up at the first up device, and |
| 325 | * power down at the last down device. |
| 326 | */ |
| 327 | if (atomic_dec_return(&usb_pwr_ref) == 0) |
| 328 | cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); |
| 329 | } |
| 330 | |
| 331 | static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { |
| 332 | .power_on = csn3xxx_usb_power_on, |
| 333 | .power_off = csn3xxx_usb_power_off, |
| 334 | }; |
| 335 | |
| 336 | static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { |
| 337 | .num_ports = 1, |
| 338 | .power_on = csn3xxx_usb_power_on, |
| 339 | .power_off = csn3xxx_usb_power_off, |
| 340 | }; |
| 341 | |
| 342 | static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { |
| 343 | { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, |
| 344 | { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, |
| 345 | { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, |
| 346 | { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL }, |
| 347 | {}, |
| 348 | }; |
| 349 | |
| 350 | static void __init cns3xxx_init(void) |
| 351 | { |
| 352 | struct device_node *dn; |
| 353 | |
| 354 | cns3xxx_l2x0_init(); |
| 355 | |
| 356 | dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci"); |
| 357 | if (of_device_is_available(dn)) { |
| 358 | u32 tmp; |
| 359 | |
| 360 | tmp = __raw_readl(MISC_SATA_POWER_MODE); |
| 361 | tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ |
| 362 | tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ |
| 363 | __raw_writel(tmp, MISC_SATA_POWER_MODE); |
| 364 | |
| 365 | /* Enable SATA PHY */ |
| 366 | cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); |
| 367 | cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); |
| 368 | |
| 369 | /* Enable SATA Clock */ |
| 370 | cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); |
| 371 | |
| 372 | /* De-Asscer SATA Reset */ |
| 373 | cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); |
| 374 | } |
| 375 | |
| 376 | dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci"); |
| 377 | if (of_device_is_available(dn)) { |
| 378 | u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); |
| 379 | u32 gpioa_pins = __raw_readl(gpioa); |
| 380 | |
| 381 | /* MMC/SD pins share with GPIOA */ |
| 382 | gpioa_pins |= 0x1fff0004; |
| 383 | __raw_writel(gpioa_pins, gpioa); |
| 384 | |
| 385 | cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); |
| 386 | cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); |
| 387 | } |
| 388 | |
| 389 | pm_power_off = cns3xxx_power_off; |
| 390 | |
| 391 | of_platform_populate(NULL, of_default_bus_match_table, |
| 392 | cns3xxx_auxdata, NULL); |
| 393 | } |
| 394 | |
| 395 | static const char *cns3xxx_dt_compat[] __initdata = { |
| 396 | "cavium,cns3410", |
| 397 | "cavium,cns3420", |
| 398 | NULL, |
| 399 | }; |
| 400 | |
| 401 | DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") |
| 402 | .dt_compat = cns3xxx_dt_compat, |
Arnd Bergmann | 415f5914 | 2013-03-14 22:27:32 +0100 | [diff] [blame] | 403 | .map_io = cns3xxx_map_io, |
| 404 | .init_irq = cns3xxx_init_irq, |
| 405 | .init_time = cns3xxx_timer_init, |
| 406 | .init_machine = cns3xxx_init, |
Xia Kaixu | 0a2e912 | 2014-09-03 21:18:12 +0800 | [diff] [blame] | 407 | .init_late = cns3xxx_pcie_init_late, |
Arnd Bergmann | 415f5914 | 2013-03-14 22:27:32 +0100 | [diff] [blame] | 408 | .restart = cns3xxx_restart, |
| 409 | MACHINE_END |