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Saeed Bisharaedabd382009-08-06 15:12:43 +03001/*
2 * arch/arm/mach-dove/irq.c
3 *
4 * Dove IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16#include <asm/mach/arch.h>
17#include <plat/irq.h>
18#include <asm/mach/irq.h>
19#include <mach/pm.h>
20#include <mach/bridge-regs.h>
Rob Herringce915742012-08-29 10:16:55 -050021#include <plat/orion-gpio.h>
Saeed Bisharaedabd382009-08-06 15:12:43 +030022#include "common.h"
23
Lennert Buytenhekaa456a62010-11-29 10:27:47 +010024static void pmu_irq_mask(struct irq_data *d)
Saeed Bisharaedabd382009-08-06 15:12:43 +030025{
Lennert Buytenhekaa456a62010-11-29 10:27:47 +010026 int pin = irq_to_pmu(d->irq);
Saeed Bisharaedabd382009-08-06 15:12:43 +030027 u32 u;
28
29 u = readl(PMU_INTERRUPT_MASK);
30 u &= ~(1 << (pin & 31));
31 writel(u, PMU_INTERRUPT_MASK);
32}
33
Lennert Buytenhekaa456a62010-11-29 10:27:47 +010034static void pmu_irq_unmask(struct irq_data *d)
Saeed Bisharaedabd382009-08-06 15:12:43 +030035{
Lennert Buytenhekaa456a62010-11-29 10:27:47 +010036 int pin = irq_to_pmu(d->irq);
Saeed Bisharaedabd382009-08-06 15:12:43 +030037 u32 u;
38
39 u = readl(PMU_INTERRUPT_MASK);
40 u |= 1 << (pin & 31);
41 writel(u, PMU_INTERRUPT_MASK);
42}
43
Lennert Buytenhekaa456a62010-11-29 10:27:47 +010044static void pmu_irq_ack(struct irq_data *d)
Saeed Bisharaedabd382009-08-06 15:12:43 +030045{
Lennert Buytenhekaa456a62010-11-29 10:27:47 +010046 int pin = irq_to_pmu(d->irq);
Saeed Bisharaedabd382009-08-06 15:12:43 +030047 u32 u;
48
Russell King - ARM Linux5d3df932012-11-18 16:29:44 +000049 /*
50 * The PMU mask register is not RW0C: it is RW. This means that
51 * the bits take whatever value is written to them; if you write
52 * a '1', you will set the interrupt.
53 *
54 * Unfortunately this means there is NO race free way to clear
55 * these interrupts.
56 *
57 * So, let's structure the code so that the window is as small as
58 * possible.
59 */
Saeed Bisharaedabd382009-08-06 15:12:43 +030060 u = ~(1 << (pin & 31));
Russell King - ARM Linux5d3df932012-11-18 16:29:44 +000061 u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
62 writel_relaxed(u, PMU_INTERRUPT_CAUSE);
Saeed Bisharaedabd382009-08-06 15:12:43 +030063}
64
65static struct irq_chip pmu_irq_chip = {
66 .name = "pmu_irq",
Lennert Buytenhekaa456a62010-11-29 10:27:47 +010067 .irq_mask = pmu_irq_mask,
68 .irq_unmask = pmu_irq_unmask,
69 .irq_ack = pmu_irq_ack,
Saeed Bisharaedabd382009-08-06 15:12:43 +030070};
71
72static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
73{
74 unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
75
76 cause &= readl(PMU_INTERRUPT_MASK);
77 if (cause == 0) {
78 do_bad_IRQ(irq, desc);
79 return;
80 }
81
82 for (irq = 0; irq < NR_PMU_IRQS; irq++) {
83 if (!(cause & (1 << irq)))
84 continue;
85 irq = pmu_to_irq(irq);
Thomas Gleixnercf0d6b72011-03-24 12:33:40 +010086 generic_handle_irq(irq);
Saeed Bisharaedabd382009-08-06 15:12:43 +030087 }
88}
89
Andrew Lunn278b45b2012-06-27 13:40:04 +020090static int __initdata gpio0_irqs[4] = {
91 IRQ_DOVE_GPIO_0_7,
92 IRQ_DOVE_GPIO_8_15,
93 IRQ_DOVE_GPIO_16_23,
94 IRQ_DOVE_GPIO_24_31,
95};
96
97static int __initdata gpio1_irqs[4] = {
98 IRQ_DOVE_HIGH_GPIO,
99 0,
100 0,
101 0,
102};
103
104static int __initdata gpio2_irqs[4] = {
105 0,
106 0,
107 0,
108 0,
109};
110
Thomas Petazzonideac3d82014-04-22 23:26:26 +0200111#ifdef CONFIG_MULTI_IRQ_HANDLER
112/*
113 * Compiling with both non-DT and DT support enabled, will
114 * break asm irq handler used by non-DT boards. Therefore,
115 * we provide a C-style irq handler even for non-DT boards,
116 * if MULTI_IRQ_HANDLER is set.
117 */
118
119static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
120
121static asmlinkage void
122__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
123{
124 u32 stat;
125
126 stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
127 stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
128 if (stat) {
129 unsigned int hwirq = __fls(stat);
130 handle_IRQ(hwirq, regs);
131 return;
132 }
133 stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
134 stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
135 if (stat) {
136 unsigned int hwirq = 32 + __fls(stat);
137 handle_IRQ(hwirq, regs);
138 return;
139 }
140}
141#endif
142
Saeed Bisharaedabd382009-08-06 15:12:43 +0300143void __init dove_init_irq(void)
144{
145 int i;
146
Thomas Petazzonic3c5a282012-09-11 14:27:18 +0200147 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
148 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
Saeed Bisharaedabd382009-08-06 15:12:43 +0300149
Thomas Petazzonideac3d82014-04-22 23:26:26 +0200150#ifdef CONFIG_MULTI_IRQ_HANDLER
151 set_handle_irq(dove_legacy_handle_irq);
152#endif
153
Saeed Bisharaedabd382009-08-06 15:12:43 +0300154 /*
Lennert Buytenhek9eac6d02010-12-14 12:54:03 +0100155 * Initialize gpiolib for GPIOs 0-71.
Saeed Bisharaedabd382009-08-06 15:12:43 +0300156 */
Thomas Petazzonic3c5a282012-09-11 14:27:18 +0200157 orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
Andrew Lunn278b45b2012-06-27 13:40:04 +0200158 IRQ_DOVE_GPIO_START, gpio0_irqs);
Lennert Buytenhek9eac6d02010-12-14 12:54:03 +0100159
Thomas Petazzonic3c5a282012-09-11 14:27:18 +0200160 orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
Andrew Lunn278b45b2012-06-27 13:40:04 +0200161 IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
Lennert Buytenhek9eac6d02010-12-14 12:54:03 +0100162
Thomas Petazzonic3c5a282012-09-11 14:27:18 +0200163 orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
Andrew Lunn278b45b2012-06-27 13:40:04 +0200164 IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
Saeed Bisharaedabd382009-08-06 15:12:43 +0300165
166 /*
167 * Mask and clear PMU interrupts
168 */
169 writel(0, PMU_INTERRUPT_MASK);
170 writel(0, PMU_INTERRUPT_CAUSE);
171
Saeed Bisharaedabd382009-08-06 15:12:43 +0300172 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100173 irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
Thomas Gleixnercf0d6b72011-03-24 12:33:40 +0100174 irq_set_status_flags(i, IRQ_LEVEL);
Saeed Bisharaedabd382009-08-06 15:12:43 +0300175 set_irq_flags(i, IRQF_VALID);
176 }
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100177 irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
Saeed Bisharaedabd382009-08-06 15:12:43 +0300178}