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Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -07001/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
19 */
20
21#ifndef __DMAR_H__
22#define __DMAR_H__
23
24#include <linux/acpi.h>
25#include <linux/types.h>
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070026#include <linux/msi.h>
Suresh Siddha1531a6a2009-03-16 17:04:57 -070027#include <linux/irqreturn.h>
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070028
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070029struct intel_iommu;
Suresh Siddha29b61be2009-03-16 17:05:02 -070030#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070031struct dmar_drhd_unit {
32 struct list_head list; /* list of drhd units */
Suresh Siddha1886e8a2008-07-10 11:16:37 -070033 struct acpi_dmar_header *hdr; /* ACPI header */
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070034 u64 reg_base_addr; /* register base address*/
35 struct pci_dev **devices; /* target device array */
36 int devices_cnt; /* target device count */
37 u8 ignored:1; /* ignore drhd */
38 u8 include_all:1;
39 struct intel_iommu *iommu;
40};
41
Suresh Siddha2ae21012008-07-10 11:16:43 -070042extern struct list_head dmar_drhd_units;
43
44#define for_each_drhd_unit(drhd) \
45 list_for_each_entry(drhd, &dmar_drhd_units, list)
46
David Woodhouse8f912ba2009-04-03 15:19:32 +010047#define for_each_active_iommu(i, drhd) \
48 list_for_each_entry(drhd, &dmar_drhd_units, list) \
49 if (i=drhd->iommu, drhd->ignored) {} else
50
51#define for_each_iommu(i, drhd) \
52 list_for_each_entry(drhd, &dmar_drhd_units, list) \
53 if (i=drhd->iommu, 0) {} else
54
Suresh Siddha2ae21012008-07-10 11:16:43 -070055extern int dmar_table_init(void);
Suresh Siddha2ae21012008-07-10 11:16:43 -070056extern int dmar_dev_scope_init(void);
57
58/* Intel IOMMU detection */
59extern void detect_intel_iommu(void);
Suresh Siddha9d783ba2009-03-16 17:04:55 -070060extern int enable_drhd_fault_handling(void);
Suresh Siddha2ae21012008-07-10 11:16:43 -070061
Suresh Siddha2ae21012008-07-10 11:16:43 -070062extern int parse_ioapics_under_ir(void);
63extern int alloc_iommu(struct dmar_drhd_unit *);
64#else
65static inline void detect_intel_iommu(void)
66{
67 return;
68}
69
70static inline int dmar_table_init(void)
71{
72 return -ENODEV;
73}
Suresh Siddha29b61be2009-03-16 17:05:02 -070074static inline int enable_drhd_fault_handling(void)
75{
76 return -1;
77}
Suresh Siddha2ae21012008-07-10 11:16:43 -070078#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
79
Suresh Siddha2ae21012008-07-10 11:16:43 -070080struct irte {
81 union {
82 struct {
83 __u64 present : 1,
84 fpd : 1,
85 dst_mode : 1,
86 redir_hint : 1,
87 trigger_mode : 1,
88 dlvry_mode : 3,
89 avail : 4,
90 __reserved_1 : 4,
91 vector : 8,
92 __reserved_2 : 8,
93 dest_id : 32;
94 };
95 __u64 low;
96 };
97
98 union {
99 struct {
100 __u64 sid : 16,
101 sq : 2,
102 svt : 2,
103 __reserved_3 : 44;
104 };
105 __u64 high;
106 };
107};
Suresh Siddha29b61be2009-03-16 17:05:02 -0700108#ifdef CONFIG_INTR_REMAP
109extern int intr_remapping_enabled;
110extern int enable_intr_remapping(int);
111
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700112extern int get_irte(int irq, struct irte *entry);
113extern int modify_irte(int irq, struct irte *irte_modified);
114extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
115extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
116 u16 sub_handle);
117extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
118extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
119extern int flush_irte(int irq);
120extern int free_irte(int irq);
121
122extern int irq_remapped(int irq);
Suresh Siddha75c46fa2008-07-10 11:16:57 -0700123extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
Suresh Siddha89027d32008-07-10 11:16:56 -0700124extern struct intel_iommu *map_ioapic_to_ir(int apic);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700125#else
Suresh Siddha29b61be2009-03-16 17:05:02 -0700126static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
127{
128 return -1;
129}
130static inline int modify_irte(int irq, struct irte *irte_modified)
131{
132 return -1;
133}
134static inline int free_irte(int irq)
135{
136 return -1;
137}
138static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
139{
140 return -1;
141}
142static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
143 u16 sub_handle)
144{
145 return -1;
146}
147static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
148{
149 return NULL;
150}
151static inline struct intel_iommu *map_ioapic_to_ir(int apic)
152{
153 return NULL;
154}
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700155#define irq_remapped(irq) (0)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700156#define enable_intr_remapping(mode) (-1)
157#define intr_remapping_enabled (0)
158#endif
159
Suresh Siddha2ae21012008-07-10 11:16:43 -0700160/* Can't use the common MSI interrupt functions
161 * since DMAR is not a pci device
162 */
163extern void dmar_msi_unmask(unsigned int irq);
164extern void dmar_msi_mask(unsigned int irq);
165extern void dmar_msi_read(int irq, struct msi_msg *msg);
166extern void dmar_msi_write(int irq, struct msi_msg *msg);
167extern int dmar_set_interrupt(struct intel_iommu *iommu);
Suresh Siddha1531a6a2009-03-16 17:04:57 -0700168extern irqreturn_t dmar_fault(int irq, void *dev_id);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700169extern int arch_setup_dmar_msi(unsigned int irq);
170
Suresh Siddha9d783ba2009-03-16 17:04:55 -0700171#ifdef CONFIG_DMAR
Suresh Siddha2ae21012008-07-10 11:16:43 -0700172extern int iommu_detected, no_iommu;
173extern struct list_head dmar_rmrr_units;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700174struct dmar_rmrr_unit {
175 struct list_head list; /* list of rmrr units */
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700176 struct acpi_dmar_header *hdr; /* ACPI header */
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700177 u64 base_address; /* reserved base address*/
178 u64 end_address; /* reserved end address */
179 struct pci_dev **devices; /* target devices */
180 int devices_cnt; /* target device count */
181};
182
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700183#define for_each_rmrr_units(rmrr) \
184 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700185/* Intel DMAR initialization functions */
186extern int intel_iommu_init(void);
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700187#else
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700188static inline int intel_iommu_init(void)
189{
Suresh Siddha2ae21012008-07-10 11:16:43 -0700190#ifdef CONFIG_INTR_REMAP
191 return dmar_dev_scope_init();
192#else
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700193 return -ENODEV;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700194#endif
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700195}
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700196#endif /* !CONFIG_DMAR */
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700197#endif /* __DMAR_H__ */