blob: 3689eee0453575a3a115f5bb08fef0fca248dbd2 [file] [log] [blame]
James Smartda0436e2009-05-22 14:51:39 -04001/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2009 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21/* Macros to deal with bit fields. Each bit field must have 3 #defines
22 * associated with it (_SHIFT, _MASK, and _WORD).
23 * EG. For a bit field that is in the 7th bit of the "field4" field of a
24 * structure and is 2 bits in size the following #defines must exist:
25 * struct temp {
26 * uint32_t field1;
27 * uint32_t field2;
28 * uint32_t field3;
29 * uint32_t field4;
30 * #define example_bit_field_SHIFT 7
31 * #define example_bit_field_MASK 0x03
32 * #define example_bit_field_WORD field4
33 * uint32_t field5;
34 * };
35 * Then the macros below may be used to get or set the value of that field.
36 * EG. To get the value of the bit field from the above example:
37 * struct temp t1;
38 * value = bf_get(example_bit_field, &t1);
39 * And then to set that bit field:
40 * bf_set(example_bit_field, &t1, 2);
41 * Or clear that bit field:
42 * bf_set(example_bit_field, &t1, 0);
43 */
44#define bf_get(name, ptr) \
45 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
46#define bf_set(name, ptr, value) \
47 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
48 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
49
50struct dma_address {
51 uint32_t addr_lo;
52 uint32_t addr_hi;
53};
54
James Smart8fa38512009-07-19 10:01:03 -040055#define LPFC_SLIREV_CONF_WORD 0x58
56struct lpfc_sli_intf {
57 uint32_t word0;
58#define lpfc_sli_intf_iftype_MASK 0x00000007
59#define lpfc_sli_intf_iftype_SHIFT 0
60#define lpfc_sli_intf_iftype_WORD word0
61#define lpfc_sli_intf_rev_MASK 0x0000000f
62#define lpfc_sli_intf_rev_SHIFT 4
63#define lpfc_sli_intf_rev_WORD word0
64#define LPFC_SLIREV_CONF_SLI4 4
65#define lpfc_sli_intf_family_MASK 0x000000ff
66#define lpfc_sli_intf_family_SHIFT 8
67#define lpfc_sli_intf_family_WORD word0
68#define lpfc_sli_intf_feat1_MASK 0x000000ff
69#define lpfc_sli_intf_feat1_SHIFT 16
70#define lpfc_sli_intf_feat1_WORD word0
71#define lpfc_sli_intf_feat2_MASK 0x0000001f
72#define lpfc_sli_intf_feat2_SHIFT 24
73#define lpfc_sli_intf_feat2_WORD word0
74#define lpfc_sli_intf_valid_MASK 0x00000007
75#define lpfc_sli_intf_valid_SHIFT 29
76#define lpfc_sli_intf_valid_WORD word0
77#define LPFC_SLI_INTF_VALID 6
78};
79
James Smartda0436e2009-05-22 14:51:39 -040080#define LPFC_SLI4_BAR0 1
81#define LPFC_SLI4_BAR1 2
82#define LPFC_SLI4_BAR2 4
83
84#define LPFC_SLI4_MBX_EMBED true
85#define LPFC_SLI4_MBX_NEMBED false
86
87#define LPFC_SLI4_MB_WORD_COUNT 64
88#define LPFC_MAX_MQ_PAGE 8
89#define LPFC_MAX_WQ_PAGE 8
90#define LPFC_MAX_CQ_PAGE 4
91#define LPFC_MAX_EQ_PAGE 8
92
93#define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */
94#define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */
95#define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
96
97/* Define SLI4 Alignment requirements. */
98#define LPFC_ALIGN_16_BYTE 16
99#define LPFC_ALIGN_64_BYTE 64
100
101/* Define SLI4 specific definitions. */
102#define LPFC_MQ_CQE_BYTE_OFFSET 256
103#define LPFC_MBX_CMD_HDR_LENGTH 16
104#define LPFC_MBX_ERROR_RANGE 0x4000
105#define LPFC_BMBX_BIT1_ADDR_HI 0x2
106#define LPFC_BMBX_BIT1_ADDR_LO 0
107#define LPFC_RPI_HDR_COUNT 64
108#define LPFC_HDR_TEMPLATE_SIZE 4096
109#define LPFC_RPI_ALLOC_ERROR 0xFFFF
110#define LPFC_FCF_RECORD_WD_CNT 132
111#define LPFC_ENTIRE_FCF_DATABASE 0
112#define LPFC_DFLT_FCF_INDEX 0
113
114/* Virtual function numbers */
115#define LPFC_VF0 0
116#define LPFC_VF1 1
117#define LPFC_VF2 2
118#define LPFC_VF3 3
119#define LPFC_VF4 4
120#define LPFC_VF5 5
121#define LPFC_VF6 6
122#define LPFC_VF7 7
123#define LPFC_VF8 8
124#define LPFC_VF9 9
125#define LPFC_VF10 10
126#define LPFC_VF11 11
127#define LPFC_VF12 12
128#define LPFC_VF13 13
129#define LPFC_VF14 14
130#define LPFC_VF15 15
131#define LPFC_VF16 16
132#define LPFC_VF17 17
133#define LPFC_VF18 18
134#define LPFC_VF19 19
135#define LPFC_VF20 20
136#define LPFC_VF21 21
137#define LPFC_VF22 22
138#define LPFC_VF23 23
139#define LPFC_VF24 24
140#define LPFC_VF25 25
141#define LPFC_VF26 26
142#define LPFC_VF27 27
143#define LPFC_VF28 28
144#define LPFC_VF29 29
145#define LPFC_VF30 30
146#define LPFC_VF31 31
147
148/* PCI function numbers */
149#define LPFC_PCI_FUNC0 0
150#define LPFC_PCI_FUNC1 1
151#define LPFC_PCI_FUNC2 2
152#define LPFC_PCI_FUNC3 3
153#define LPFC_PCI_FUNC4 4
154
155/* Active interrupt test count */
156#define LPFC_ACT_INTR_CNT 4
157
158/* Delay Multiplier constant */
159#define LPFC_DMULT_CONST 651042
160#define LPFC_MIM_IMAX 636
161#define LPFC_FP_DEF_IMAX 10000
162#define LPFC_SP_DEF_IMAX 10000
163
164struct ulp_bde64 {
165 union ULP_BDE_TUS {
166 uint32_t w;
167 struct {
168#ifdef __BIG_ENDIAN_BITFIELD
169 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
170 VALUE !! */
171 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
172#else /* __LITTLE_ENDIAN_BITFIELD */
173 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
174 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
175 VALUE !! */
176#endif
177#define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
178#define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
179#define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
180#define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
181#define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
182#define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
183#define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
184 } f;
185 } tus;
186 uint32_t addrLow;
187 uint32_t addrHigh;
188};
189
190struct lpfc_sli4_flags {
191 uint32_t word0;
192#define lpfc_fip_flag_SHIFT 0
193#define lpfc_fip_flag_MASK 0x00000001
194#define lpfc_fip_flag_WORD word0
195};
196
197/* event queue entry structure */
198struct lpfc_eqe {
199 uint32_t word0;
200#define lpfc_eqe_resource_id_SHIFT 16
201#define lpfc_eqe_resource_id_MASK 0x000000FF
202#define lpfc_eqe_resource_id_WORD word0
203#define lpfc_eqe_minor_code_SHIFT 4
204#define lpfc_eqe_minor_code_MASK 0x00000FFF
205#define lpfc_eqe_minor_code_WORD word0
206#define lpfc_eqe_major_code_SHIFT 1
207#define lpfc_eqe_major_code_MASK 0x00000007
208#define lpfc_eqe_major_code_WORD word0
209#define lpfc_eqe_valid_SHIFT 0
210#define lpfc_eqe_valid_MASK 0x00000001
211#define lpfc_eqe_valid_WORD word0
212};
213
214/* completion queue entry structure (common fields for all cqe types) */
215struct lpfc_cqe {
216 uint32_t reserved0;
217 uint32_t reserved1;
218 uint32_t reserved2;
219 uint32_t word3;
220#define lpfc_cqe_valid_SHIFT 31
221#define lpfc_cqe_valid_MASK 0x00000001
222#define lpfc_cqe_valid_WORD word3
223#define lpfc_cqe_code_SHIFT 16
224#define lpfc_cqe_code_MASK 0x000000FF
225#define lpfc_cqe_code_WORD word3
226};
227
228/* Completion Queue Entry Status Codes */
229#define CQE_STATUS_SUCCESS 0x0
230#define CQE_STATUS_FCP_RSP_FAILURE 0x1
231#define CQE_STATUS_REMOTE_STOP 0x2
232#define CQE_STATUS_LOCAL_REJECT 0x3
233#define CQE_STATUS_NPORT_RJT 0x4
234#define CQE_STATUS_FABRIC_RJT 0x5
235#define CQE_STATUS_NPORT_BSY 0x6
236#define CQE_STATUS_FABRIC_BSY 0x7
237#define CQE_STATUS_INTERMED_RSP 0x8
238#define CQE_STATUS_LS_RJT 0x9
239#define CQE_STATUS_CMD_REJECT 0xb
240#define CQE_STATUS_FCP_TGT_LENCHECK 0xc
241#define CQE_STATUS_NEED_BUFF_ENTRY 0xf
242
243/* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
244#define CQE_HW_STATUS_NO_ERR 0x0
245#define CQE_HW_STATUS_UNDERRUN 0x1
246#define CQE_HW_STATUS_OVERRUN 0x2
247
248/* Completion Queue Entry Codes */
249#define CQE_CODE_COMPL_WQE 0x1
250#define CQE_CODE_RELEASE_WQE 0x2
251#define CQE_CODE_RECEIVE 0x4
252#define CQE_CODE_XRI_ABORTED 0x5
253
254/* completion queue entry for wqe completions */
255struct lpfc_wcqe_complete {
256 uint32_t word0;
257#define lpfc_wcqe_c_request_tag_SHIFT 16
258#define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
259#define lpfc_wcqe_c_request_tag_WORD word0
260#define lpfc_wcqe_c_status_SHIFT 8
261#define lpfc_wcqe_c_status_MASK 0x000000FF
262#define lpfc_wcqe_c_status_WORD word0
263#define lpfc_wcqe_c_hw_status_SHIFT 0
264#define lpfc_wcqe_c_hw_status_MASK 0x000000FF
265#define lpfc_wcqe_c_hw_status_WORD word0
266 uint32_t total_data_placed;
267 uint32_t parameter;
268 uint32_t word3;
269#define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT
270#define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK
271#define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD
272#define lpfc_wcqe_c_xb_SHIFT 28
273#define lpfc_wcqe_c_xb_MASK 0x00000001
274#define lpfc_wcqe_c_xb_WORD word3
275#define lpfc_wcqe_c_pv_SHIFT 27
276#define lpfc_wcqe_c_pv_MASK 0x00000001
277#define lpfc_wcqe_c_pv_WORD word3
278#define lpfc_wcqe_c_priority_SHIFT 24
279#define lpfc_wcqe_c_priority_MASK 0x00000007
280#define lpfc_wcqe_c_priority_WORD word3
281#define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT
282#define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK
283#define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD
284};
285
286/* completion queue entry for wqe release */
287struct lpfc_wcqe_release {
288 uint32_t reserved0;
289 uint32_t reserved1;
290 uint32_t word2;
291#define lpfc_wcqe_r_wq_id_SHIFT 16
292#define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
293#define lpfc_wcqe_r_wq_id_WORD word2
294#define lpfc_wcqe_r_wqe_index_SHIFT 0
295#define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
296#define lpfc_wcqe_r_wqe_index_WORD word2
297 uint32_t word3;
298#define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT
299#define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK
300#define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD
301#define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT
302#define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK
303#define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD
304};
305
306struct sli4_wcqe_xri_aborted {
307 uint32_t word0;
308#define lpfc_wcqe_xa_status_SHIFT 8
309#define lpfc_wcqe_xa_status_MASK 0x000000FF
310#define lpfc_wcqe_xa_status_WORD word0
311 uint32_t parameter;
312 uint32_t word2;
313#define lpfc_wcqe_xa_remote_xid_SHIFT 16
314#define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
315#define lpfc_wcqe_xa_remote_xid_WORD word2
316#define lpfc_wcqe_xa_xri_SHIFT 0
317#define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
318#define lpfc_wcqe_xa_xri_WORD word2
319 uint32_t word3;
320#define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT
321#define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK
322#define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD
323#define lpfc_wcqe_xa_ia_SHIFT 30
324#define lpfc_wcqe_xa_ia_MASK 0x00000001
325#define lpfc_wcqe_xa_ia_WORD word3
326#define CQE_XRI_ABORTED_IA_REMOTE 0
327#define CQE_XRI_ABORTED_IA_LOCAL 1
328#define lpfc_wcqe_xa_br_SHIFT 29
329#define lpfc_wcqe_xa_br_MASK 0x00000001
330#define lpfc_wcqe_xa_br_WORD word3
331#define CQE_XRI_ABORTED_BR_BA_ACC 0
332#define CQE_XRI_ABORTED_BR_BA_RJT 1
333#define lpfc_wcqe_xa_eo_SHIFT 28
334#define lpfc_wcqe_xa_eo_MASK 0x00000001
335#define lpfc_wcqe_xa_eo_WORD word3
336#define CQE_XRI_ABORTED_EO_REMOTE 0
337#define CQE_XRI_ABORTED_EO_LOCAL 1
338#define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT
339#define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK
340#define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD
341};
342
343/* completion queue entry structure for rqe completion */
344struct lpfc_rcqe {
345 uint32_t word0;
346#define lpfc_rcqe_bindex_SHIFT 16
347#define lpfc_rcqe_bindex_MASK 0x0000FFF
348#define lpfc_rcqe_bindex_WORD word0
349#define lpfc_rcqe_status_SHIFT 8
350#define lpfc_rcqe_status_MASK 0x000000FF
351#define lpfc_rcqe_status_WORD word0
352#define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
353#define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
354#define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
355#define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
356 uint32_t reserved1;
357 uint32_t word2;
358#define lpfc_rcqe_length_SHIFT 16
359#define lpfc_rcqe_length_MASK 0x0000FFFF
360#define lpfc_rcqe_length_WORD word2
361#define lpfc_rcqe_rq_id_SHIFT 6
362#define lpfc_rcqe_rq_id_MASK 0x000003FF
363#define lpfc_rcqe_rq_id_WORD word2
364#define lpfc_rcqe_fcf_id_SHIFT 0
365#define lpfc_rcqe_fcf_id_MASK 0x0000003F
366#define lpfc_rcqe_fcf_id_WORD word2
367 uint32_t word3;
368#define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT
369#define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK
370#define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD
371#define lpfc_rcqe_port_SHIFT 30
372#define lpfc_rcqe_port_MASK 0x00000001
373#define lpfc_rcqe_port_WORD word3
374#define lpfc_rcqe_hdr_length_SHIFT 24
375#define lpfc_rcqe_hdr_length_MASK 0x0000001F
376#define lpfc_rcqe_hdr_length_WORD word3
377#define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT
378#define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK
379#define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD
380#define lpfc_rcqe_eof_SHIFT 8
381#define lpfc_rcqe_eof_MASK 0x000000FF
382#define lpfc_rcqe_eof_WORD word3
383#define FCOE_EOFn 0x41
384#define FCOE_EOFt 0x42
385#define FCOE_EOFni 0x49
386#define FCOE_EOFa 0x50
387#define lpfc_rcqe_sof_SHIFT 0
388#define lpfc_rcqe_sof_MASK 0x000000FF
389#define lpfc_rcqe_sof_WORD word3
390#define FCOE_SOFi2 0x2d
391#define FCOE_SOFi3 0x2e
392#define FCOE_SOFn2 0x35
393#define FCOE_SOFn3 0x36
394};
395
396struct lpfc_wqe_generic{
397 struct ulp_bde64 bde;
398 uint32_t word3;
399 uint32_t word4;
400 uint32_t word5;
401 uint32_t word6;
402#define lpfc_wqe_gen_context_SHIFT 16
403#define lpfc_wqe_gen_context_MASK 0x0000FFFF
404#define lpfc_wqe_gen_context_WORD word6
405#define lpfc_wqe_gen_xri_SHIFT 0
406#define lpfc_wqe_gen_xri_MASK 0x0000FFFF
407#define lpfc_wqe_gen_xri_WORD word6
408 uint32_t word7;
409#define lpfc_wqe_gen_lnk_SHIFT 23
410#define lpfc_wqe_gen_lnk_MASK 0x00000001
411#define lpfc_wqe_gen_lnk_WORD word7
412#define lpfc_wqe_gen_erp_SHIFT 22
413#define lpfc_wqe_gen_erp_MASK 0x00000001
414#define lpfc_wqe_gen_erp_WORD word7
415#define lpfc_wqe_gen_pu_SHIFT 20
416#define lpfc_wqe_gen_pu_MASK 0x00000003
417#define lpfc_wqe_gen_pu_WORD word7
418#define lpfc_wqe_gen_class_SHIFT 16
419#define lpfc_wqe_gen_class_MASK 0x00000007
420#define lpfc_wqe_gen_class_WORD word7
421#define lpfc_wqe_gen_command_SHIFT 8
422#define lpfc_wqe_gen_command_MASK 0x000000FF
423#define lpfc_wqe_gen_command_WORD word7
424#define lpfc_wqe_gen_status_SHIFT 4
425#define lpfc_wqe_gen_status_MASK 0x0000000F
426#define lpfc_wqe_gen_status_WORD word7
427#define lpfc_wqe_gen_ct_SHIFT 2
428#define lpfc_wqe_gen_ct_MASK 0x00000007
429#define lpfc_wqe_gen_ct_WORD word7
430 uint32_t abort_tag;
431 uint32_t word9;
432#define lpfc_wqe_gen_request_tag_SHIFT 0
433#define lpfc_wqe_gen_request_tag_MASK 0x0000FFFF
434#define lpfc_wqe_gen_request_tag_WORD word9
435 uint32_t word10;
436#define lpfc_wqe_gen_ccp_SHIFT 24
437#define lpfc_wqe_gen_ccp_MASK 0x000000FF
438#define lpfc_wqe_gen_ccp_WORD word10
439#define lpfc_wqe_gen_ccpe_SHIFT 23
440#define lpfc_wqe_gen_ccpe_MASK 0x00000001
441#define lpfc_wqe_gen_ccpe_WORD word10
442#define lpfc_wqe_gen_pv_SHIFT 19
443#define lpfc_wqe_gen_pv_MASK 0x00000001
444#define lpfc_wqe_gen_pv_WORD word10
445#define lpfc_wqe_gen_pri_SHIFT 16
446#define lpfc_wqe_gen_pri_MASK 0x00000007
447#define lpfc_wqe_gen_pri_WORD word10
448 uint32_t word11;
449#define lpfc_wqe_gen_cq_id_SHIFT 16
James Smartf1126682009-06-10 17:22:44 -0400450#define lpfc_wqe_gen_cq_id_MASK 0x0000FFFF
James Smartda0436e2009-05-22 14:51:39 -0400451#define lpfc_wqe_gen_cq_id_WORD word11
James Smartf1126682009-06-10 17:22:44 -0400452#define LPFC_WQE_CQ_ID_DEFAULT 0xffff
James Smartda0436e2009-05-22 14:51:39 -0400453#define lpfc_wqe_gen_wqec_SHIFT 7
454#define lpfc_wqe_gen_wqec_MASK 0x00000001
455#define lpfc_wqe_gen_wqec_WORD word11
456#define lpfc_wqe_gen_cmd_type_SHIFT 0
457#define lpfc_wqe_gen_cmd_type_MASK 0x0000000F
458#define lpfc_wqe_gen_cmd_type_WORD word11
459 uint32_t payload[4];
460};
461
462struct lpfc_rqe {
463 uint32_t address_hi;
464 uint32_t address_lo;
465};
466
467/* buffer descriptors */
468struct lpfc_bde4 {
469 uint32_t addr_hi;
470 uint32_t addr_lo;
471 uint32_t word2;
472#define lpfc_bde4_last_SHIFT 31
473#define lpfc_bde4_last_MASK 0x00000001
474#define lpfc_bde4_last_WORD word2
475#define lpfc_bde4_sge_offset_SHIFT 0
476#define lpfc_bde4_sge_offset_MASK 0x000003FF
477#define lpfc_bde4_sge_offset_WORD word2
478 uint32_t word3;
479#define lpfc_bde4_length_SHIFT 0
480#define lpfc_bde4_length_MASK 0x000000FF
481#define lpfc_bde4_length_WORD word3
482};
483
484struct lpfc_register {
485 uint32_t word0;
486};
487
488#define LPFC_UERR_STATUS_HI 0x00A4
489#define LPFC_UERR_STATUS_LO 0x00A0
490#define LPFC_ONLINE0 0x00B0
491#define LPFC_ONLINE1 0x00B4
492#define LPFC_SCRATCHPAD 0x0058
493
494/* BAR0 Registers */
495#define LPFC_HST_STATE 0x00AC
496#define lpfc_hst_state_perr_SHIFT 31
497#define lpfc_hst_state_perr_MASK 0x1
498#define lpfc_hst_state_perr_WORD word0
499#define lpfc_hst_state_sfi_SHIFT 30
500#define lpfc_hst_state_sfi_MASK 0x1
501#define lpfc_hst_state_sfi_WORD word0
502#define lpfc_hst_state_nip_SHIFT 29
503#define lpfc_hst_state_nip_MASK 0x1
504#define lpfc_hst_state_nip_WORD word0
505#define lpfc_hst_state_ipc_SHIFT 28
506#define lpfc_hst_state_ipc_MASK 0x1
507#define lpfc_hst_state_ipc_WORD word0
508#define lpfc_hst_state_xrom_SHIFT 27
509#define lpfc_hst_state_xrom_MASK 0x1
510#define lpfc_hst_state_xrom_WORD word0
511#define lpfc_hst_state_dl_SHIFT 26
512#define lpfc_hst_state_dl_MASK 0x1
513#define lpfc_hst_state_dl_WORD word0
514#define lpfc_hst_state_port_status_SHIFT 0
515#define lpfc_hst_state_port_status_MASK 0xFFFF
516#define lpfc_hst_state_port_status_WORD word0
517
518#define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
519#define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
520#define LPFC_POST_STAGE_HOST_RDY 0x0002
521#define LPFC_POST_STAGE_BE_RESET 0x0003
522#define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
523#define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
524#define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
525#define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
526#define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
527#define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
528#define LPFC_POST_STAGE_DDR_TEST_START 0x0400
529#define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
530#define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
531#define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
532#define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
533#define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
534#define LPFC_POST_STAGE_ARMFW_START 0x0800
535#define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
536#define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
537#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
538#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
539#define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
540#define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
541#define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
542#define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
543#define LPFC_POST_STAGE_PARSE_XML 0x0B04
544#define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
545#define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
546#define LPFC_POST_STAGE_RC_DONE 0x0B07
547#define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
548#define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
549#define LPFC_POST_STAGE_ARMFW_READY 0xC000
550#define LPFC_POST_STAGE_ARMFW_UE 0xF000
551
552#define lpfc_scratchpad_slirev_SHIFT 4
553#define lpfc_scratchpad_slirev_MASK 0xF
554#define lpfc_scratchpad_slirev_WORD word0
555#define lpfc_scratchpad_chiptype_SHIFT 8
556#define lpfc_scratchpad_chiptype_MASK 0xFF
557#define lpfc_scratchpad_chiptype_WORD word0
558#define lpfc_scratchpad_featurelevel1_SHIFT 16
559#define lpfc_scratchpad_featurelevel1_MASK 0xFF
560#define lpfc_scratchpad_featurelevel1_WORD word0
561#define lpfc_scratchpad_featurelevel2_SHIFT 24
562#define lpfc_scratchpad_featurelevel2_MASK 0xFF
563#define lpfc_scratchpad_featurelevel2_WORD word0
564
565/* BAR1 Registers */
566#define LPFC_IMR_MASK_ALL 0xFFFFFFFF
567#define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
568
569#define LPFC_HST_ISR0 0x0C18
570#define LPFC_HST_ISR1 0x0C1C
571#define LPFC_HST_ISR2 0x0C20
572#define LPFC_HST_ISR3 0x0C24
573#define LPFC_HST_ISR4 0x0C28
574
575#define LPFC_HST_IMR0 0x0C48
576#define LPFC_HST_IMR1 0x0C4C
577#define LPFC_HST_IMR2 0x0C50
578#define LPFC_HST_IMR3 0x0C54
579#define LPFC_HST_IMR4 0x0C58
580
581#define LPFC_HST_ISCR0 0x0C78
582#define LPFC_HST_ISCR1 0x0C7C
583#define LPFC_HST_ISCR2 0x0C80
584#define LPFC_HST_ISCR3 0x0C84
585#define LPFC_HST_ISCR4 0x0C88
586
587#define LPFC_SLI4_INTR0 BIT0
588#define LPFC_SLI4_INTR1 BIT1
589#define LPFC_SLI4_INTR2 BIT2
590#define LPFC_SLI4_INTR3 BIT3
591#define LPFC_SLI4_INTR4 BIT4
592#define LPFC_SLI4_INTR5 BIT5
593#define LPFC_SLI4_INTR6 BIT6
594#define LPFC_SLI4_INTR7 BIT7
595#define LPFC_SLI4_INTR8 BIT8
596#define LPFC_SLI4_INTR9 BIT9
597#define LPFC_SLI4_INTR10 BIT10
598#define LPFC_SLI4_INTR11 BIT11
599#define LPFC_SLI4_INTR12 BIT12
600#define LPFC_SLI4_INTR13 BIT13
601#define LPFC_SLI4_INTR14 BIT14
602#define LPFC_SLI4_INTR15 BIT15
603#define LPFC_SLI4_INTR16 BIT16
604#define LPFC_SLI4_INTR17 BIT17
605#define LPFC_SLI4_INTR18 BIT18
606#define LPFC_SLI4_INTR19 BIT19
607#define LPFC_SLI4_INTR20 BIT20
608#define LPFC_SLI4_INTR21 BIT21
609#define LPFC_SLI4_INTR22 BIT22
610#define LPFC_SLI4_INTR23 BIT23
611#define LPFC_SLI4_INTR24 BIT24
612#define LPFC_SLI4_INTR25 BIT25
613#define LPFC_SLI4_INTR26 BIT26
614#define LPFC_SLI4_INTR27 BIT27
615#define LPFC_SLI4_INTR28 BIT28
616#define LPFC_SLI4_INTR29 BIT29
617#define LPFC_SLI4_INTR30 BIT30
618#define LPFC_SLI4_INTR31 BIT31
619
620/* BAR2 Registers */
621#define LPFC_RQ_DOORBELL 0x00A0
622#define lpfc_rq_doorbell_num_posted_SHIFT 16
623#define lpfc_rq_doorbell_num_posted_MASK 0x3FFF
624#define lpfc_rq_doorbell_num_posted_WORD word0
625#define LPFC_RQ_POST_BATCH 8 /* RQEs to post at one time */
626#define lpfc_rq_doorbell_id_SHIFT 0
627#define lpfc_rq_doorbell_id_MASK 0x03FF
628#define lpfc_rq_doorbell_id_WORD word0
629
630#define LPFC_WQ_DOORBELL 0x0040
631#define lpfc_wq_doorbell_num_posted_SHIFT 24
632#define lpfc_wq_doorbell_num_posted_MASK 0x00FF
633#define lpfc_wq_doorbell_num_posted_WORD word0
634#define lpfc_wq_doorbell_index_SHIFT 16
635#define lpfc_wq_doorbell_index_MASK 0x00FF
636#define lpfc_wq_doorbell_index_WORD word0
637#define lpfc_wq_doorbell_id_SHIFT 0
638#define lpfc_wq_doorbell_id_MASK 0xFFFF
639#define lpfc_wq_doorbell_id_WORD word0
640
641#define LPFC_EQCQ_DOORBELL 0x0120
642#define lpfc_eqcq_doorbell_arm_SHIFT 29
643#define lpfc_eqcq_doorbell_arm_MASK 0x0001
644#define lpfc_eqcq_doorbell_arm_WORD word0
645#define lpfc_eqcq_doorbell_num_released_SHIFT 16
646#define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
647#define lpfc_eqcq_doorbell_num_released_WORD word0
648#define lpfc_eqcq_doorbell_qt_SHIFT 10
649#define lpfc_eqcq_doorbell_qt_MASK 0x0001
650#define lpfc_eqcq_doorbell_qt_WORD word0
651#define LPFC_QUEUE_TYPE_COMPLETION 0
652#define LPFC_QUEUE_TYPE_EVENT 1
653#define lpfc_eqcq_doorbell_eqci_SHIFT 9
654#define lpfc_eqcq_doorbell_eqci_MASK 0x0001
655#define lpfc_eqcq_doorbell_eqci_WORD word0
656#define lpfc_eqcq_doorbell_cqid_SHIFT 0
657#define lpfc_eqcq_doorbell_cqid_MASK 0x03FF
658#define lpfc_eqcq_doorbell_cqid_WORD word0
659#define lpfc_eqcq_doorbell_eqid_SHIFT 0
660#define lpfc_eqcq_doorbell_eqid_MASK 0x01FF
661#define lpfc_eqcq_doorbell_eqid_WORD word0
662
663#define LPFC_BMBX 0x0160
664#define lpfc_bmbx_addr_SHIFT 2
665#define lpfc_bmbx_addr_MASK 0x3FFFFFFF
666#define lpfc_bmbx_addr_WORD word0
667#define lpfc_bmbx_hi_SHIFT 1
668#define lpfc_bmbx_hi_MASK 0x0001
669#define lpfc_bmbx_hi_WORD word0
670#define lpfc_bmbx_rdy_SHIFT 0
671#define lpfc_bmbx_rdy_MASK 0x0001
672#define lpfc_bmbx_rdy_WORD word0
673
674#define LPFC_MQ_DOORBELL 0x0140
675#define lpfc_mq_doorbell_num_posted_SHIFT 16
676#define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
677#define lpfc_mq_doorbell_num_posted_WORD word0
678#define lpfc_mq_doorbell_id_SHIFT 0
679#define lpfc_mq_doorbell_id_MASK 0x03FF
680#define lpfc_mq_doorbell_id_WORD word0
681
682struct lpfc_sli4_cfg_mhdr {
683 uint32_t word1;
684#define lpfc_mbox_hdr_emb_SHIFT 0
685#define lpfc_mbox_hdr_emb_MASK 0x00000001
686#define lpfc_mbox_hdr_emb_WORD word1
687#define lpfc_mbox_hdr_sge_cnt_SHIFT 3
688#define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
689#define lpfc_mbox_hdr_sge_cnt_WORD word1
690 uint32_t payload_length;
691 uint32_t tag_lo;
692 uint32_t tag_hi;
693 uint32_t reserved5;
694};
695
696union lpfc_sli4_cfg_shdr {
697 struct {
698 uint32_t word6;
699#define lpfc_mbox_hdr_opcode_SHIFT 0
700#define lpfc_mbox_hdr_opcode_MASK 0x000000FF
701#define lpfc_mbox_hdr_opcode_WORD word6
702#define lpfc_mbox_hdr_subsystem_SHIFT 8
703#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
704#define lpfc_mbox_hdr_subsystem_WORD word6
705#define lpfc_mbox_hdr_port_number_SHIFT 16
706#define lpfc_mbox_hdr_port_number_MASK 0x000000FF
707#define lpfc_mbox_hdr_port_number_WORD word6
708#define lpfc_mbox_hdr_domain_SHIFT 24
709#define lpfc_mbox_hdr_domain_MASK 0x000000FF
710#define lpfc_mbox_hdr_domain_WORD word6
711 uint32_t timeout;
712 uint32_t request_length;
713 uint32_t reserved9;
714 } request;
715 struct {
716 uint32_t word6;
717#define lpfc_mbox_hdr_opcode_SHIFT 0
718#define lpfc_mbox_hdr_opcode_MASK 0x000000FF
719#define lpfc_mbox_hdr_opcode_WORD word6
720#define lpfc_mbox_hdr_subsystem_SHIFT 8
721#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
722#define lpfc_mbox_hdr_subsystem_WORD word6
723#define lpfc_mbox_hdr_domain_SHIFT 24
724#define lpfc_mbox_hdr_domain_MASK 0x000000FF
725#define lpfc_mbox_hdr_domain_WORD word6
726 uint32_t word7;
727#define lpfc_mbox_hdr_status_SHIFT 0
728#define lpfc_mbox_hdr_status_MASK 0x000000FF
729#define lpfc_mbox_hdr_status_WORD word7
730#define lpfc_mbox_hdr_add_status_SHIFT 8
731#define lpfc_mbox_hdr_add_status_MASK 0x000000FF
732#define lpfc_mbox_hdr_add_status_WORD word7
733 uint32_t response_length;
734 uint32_t actual_response_length;
735 } response;
736};
737
738/* Mailbox structures */
739struct mbox_header {
740 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
741 union lpfc_sli4_cfg_shdr cfg_shdr;
742};
743
744/* Subsystem Definitions */
745#define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
746#define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
747
748/* Device Specific Definitions */
749
750/* The HOST ENDIAN defines are in Big Endian format. */
751#define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
752#define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
753
754/* Common Opcodes */
755#define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
756#define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
757#define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
758#define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
759#define LPFC_MBOX_OPCODE_NOP 0x21
760#define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
761#define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
762#define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
763#define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
764
765/* FCoE Opcodes */
766#define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
767#define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
768#define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
769#define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
770#define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
771#define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
772#define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
773#define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
774#define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
775#define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
776
777/* Mailbox command structures */
778struct eq_context {
779 uint32_t word0;
780#define lpfc_eq_context_size_SHIFT 31
781#define lpfc_eq_context_size_MASK 0x00000001
782#define lpfc_eq_context_size_WORD word0
783#define LPFC_EQE_SIZE_4 0x0
784#define LPFC_EQE_SIZE_16 0x1
785#define lpfc_eq_context_valid_SHIFT 29
786#define lpfc_eq_context_valid_MASK 0x00000001
787#define lpfc_eq_context_valid_WORD word0
788 uint32_t word1;
789#define lpfc_eq_context_count_SHIFT 26
790#define lpfc_eq_context_count_MASK 0x00000003
791#define lpfc_eq_context_count_WORD word1
792#define LPFC_EQ_CNT_256 0x0
793#define LPFC_EQ_CNT_512 0x1
794#define LPFC_EQ_CNT_1024 0x2
795#define LPFC_EQ_CNT_2048 0x3
796#define LPFC_EQ_CNT_4096 0x4
797 uint32_t word2;
798#define lpfc_eq_context_delay_multi_SHIFT 13
799#define lpfc_eq_context_delay_multi_MASK 0x000003FF
800#define lpfc_eq_context_delay_multi_WORD word2
801 uint32_t reserved3;
802};
803
804struct sgl_page_pairs {
805 uint32_t sgl_pg0_addr_lo;
806 uint32_t sgl_pg0_addr_hi;
807 uint32_t sgl_pg1_addr_lo;
808 uint32_t sgl_pg1_addr_hi;
809};
810
811struct lpfc_mbx_post_sgl_pages {
812 struct mbox_header header;
813 uint32_t word0;
814#define lpfc_post_sgl_pages_xri_SHIFT 0
815#define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
816#define lpfc_post_sgl_pages_xri_WORD word0
817#define lpfc_post_sgl_pages_xricnt_SHIFT 16
818#define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
819#define lpfc_post_sgl_pages_xricnt_WORD word0
820 struct sgl_page_pairs sgl_pg_pairs[1];
821};
822
823/* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
824struct lpfc_mbx_post_uembed_sgl_page1 {
825 union lpfc_sli4_cfg_shdr cfg_shdr;
826 uint32_t word0;
827 struct sgl_page_pairs sgl_pg_pairs;
828};
829
830struct lpfc_mbx_sge {
831 uint32_t pa_lo;
832 uint32_t pa_hi;
833 uint32_t length;
834};
835
836struct lpfc_mbx_nembed_cmd {
837 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
838#define LPFC_SLI4_MBX_SGE_MAX_PAGES 19
839 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
840};
841
842struct lpfc_mbx_nembed_sge_virt {
843 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
844};
845
846struct lpfc_mbx_eq_create {
847 struct mbox_header header;
848 union {
849 struct {
850 uint32_t word0;
851#define lpfc_mbx_eq_create_num_pages_SHIFT 0
852#define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
853#define lpfc_mbx_eq_create_num_pages_WORD word0
854 struct eq_context context;
855 struct dma_address page[LPFC_MAX_EQ_PAGE];
856 } request;
857 struct {
858 uint32_t word0;
859#define lpfc_mbx_eq_create_q_id_SHIFT 0
860#define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
861#define lpfc_mbx_eq_create_q_id_WORD word0
862 } response;
863 } u;
864};
865
866struct lpfc_mbx_eq_destroy {
867 struct mbox_header header;
868 union {
869 struct {
870 uint32_t word0;
871#define lpfc_mbx_eq_destroy_q_id_SHIFT 0
872#define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
873#define lpfc_mbx_eq_destroy_q_id_WORD word0
874 } request;
875 struct {
876 uint32_t word0;
877 } response;
878 } u;
879};
880
881struct lpfc_mbx_nop {
882 struct mbox_header header;
883 uint32_t context[2];
884};
885
886struct cq_context {
887 uint32_t word0;
888#define lpfc_cq_context_event_SHIFT 31
889#define lpfc_cq_context_event_MASK 0x00000001
890#define lpfc_cq_context_event_WORD word0
891#define lpfc_cq_context_valid_SHIFT 29
892#define lpfc_cq_context_valid_MASK 0x00000001
893#define lpfc_cq_context_valid_WORD word0
894#define lpfc_cq_context_count_SHIFT 27
895#define lpfc_cq_context_count_MASK 0x00000003
896#define lpfc_cq_context_count_WORD word0
897#define LPFC_CQ_CNT_256 0x0
898#define LPFC_CQ_CNT_512 0x1
899#define LPFC_CQ_CNT_1024 0x2
900 uint32_t word1;
901#define lpfc_cq_eq_id_SHIFT 22
902#define lpfc_cq_eq_id_MASK 0x000000FF
903#define lpfc_cq_eq_id_WORD word1
904 uint32_t reserved0;
905 uint32_t reserved1;
906};
907
908struct lpfc_mbx_cq_create {
909 struct mbox_header header;
910 union {
911 struct {
912 uint32_t word0;
913#define lpfc_mbx_cq_create_num_pages_SHIFT 0
914#define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
915#define lpfc_mbx_cq_create_num_pages_WORD word0
916 struct cq_context context;
917 struct dma_address page[LPFC_MAX_CQ_PAGE];
918 } request;
919 struct {
920 uint32_t word0;
921#define lpfc_mbx_cq_create_q_id_SHIFT 0
922#define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
923#define lpfc_mbx_cq_create_q_id_WORD word0
924 } response;
925 } u;
926};
927
928struct lpfc_mbx_cq_destroy {
929 struct mbox_header header;
930 union {
931 struct {
932 uint32_t word0;
933#define lpfc_mbx_cq_destroy_q_id_SHIFT 0
934#define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
935#define lpfc_mbx_cq_destroy_q_id_WORD word0
936 } request;
937 struct {
938 uint32_t word0;
939 } response;
940 } u;
941};
942
943struct wq_context {
944 uint32_t reserved0;
945 uint32_t reserved1;
946 uint32_t reserved2;
947 uint32_t reserved3;
948};
949
950struct lpfc_mbx_wq_create {
951 struct mbox_header header;
952 union {
953 struct {
954 uint32_t word0;
955#define lpfc_mbx_wq_create_num_pages_SHIFT 0
956#define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF
957#define lpfc_mbx_wq_create_num_pages_WORD word0
958#define lpfc_mbx_wq_create_cq_id_SHIFT 16
959#define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
960#define lpfc_mbx_wq_create_cq_id_WORD word0
961 struct dma_address page[LPFC_MAX_WQ_PAGE];
962 } request;
963 struct {
964 uint32_t word0;
965#define lpfc_mbx_wq_create_q_id_SHIFT 0
966#define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
967#define lpfc_mbx_wq_create_q_id_WORD word0
968 } response;
969 } u;
970};
971
972struct lpfc_mbx_wq_destroy {
973 struct mbox_header header;
974 union {
975 struct {
976 uint32_t word0;
977#define lpfc_mbx_wq_destroy_q_id_SHIFT 0
978#define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
979#define lpfc_mbx_wq_destroy_q_id_WORD word0
980 } request;
981 struct {
982 uint32_t word0;
983 } response;
984 } u;
985};
986
987#define LPFC_HDR_BUF_SIZE 128
988#define LPFC_DATA_BUF_SIZE 4096
989struct rq_context {
990 uint32_t word0;
991#define lpfc_rq_context_rq_size_SHIFT 16
992#define lpfc_rq_context_rq_size_MASK 0x0000000F
993#define lpfc_rq_context_rq_size_WORD word0
994#define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */
995#define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */
996#define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */
997#define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */
998 uint32_t reserved1;
999 uint32_t word2;
1000#define lpfc_rq_context_cq_id_SHIFT 16
1001#define lpfc_rq_context_cq_id_MASK 0x000003FF
1002#define lpfc_rq_context_cq_id_WORD word2
1003#define lpfc_rq_context_buf_size_SHIFT 0
1004#define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1005#define lpfc_rq_context_buf_size_WORD word2
1006 uint32_t reserved3;
1007};
1008
1009struct lpfc_mbx_rq_create {
1010 struct mbox_header header;
1011 union {
1012 struct {
1013 uint32_t word0;
1014#define lpfc_mbx_rq_create_num_pages_SHIFT 0
1015#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1016#define lpfc_mbx_rq_create_num_pages_WORD word0
1017 struct rq_context context;
1018 struct dma_address page[LPFC_MAX_WQ_PAGE];
1019 } request;
1020 struct {
1021 uint32_t word0;
1022#define lpfc_mbx_rq_create_q_id_SHIFT 0
1023#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1024#define lpfc_mbx_rq_create_q_id_WORD word0
1025 } response;
1026 } u;
1027};
1028
1029struct lpfc_mbx_rq_destroy {
1030 struct mbox_header header;
1031 union {
1032 struct {
1033 uint32_t word0;
1034#define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1035#define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1036#define lpfc_mbx_rq_destroy_q_id_WORD word0
1037 } request;
1038 struct {
1039 uint32_t word0;
1040 } response;
1041 } u;
1042};
1043
1044struct mq_context {
1045 uint32_t word0;
1046#define lpfc_mq_context_cq_id_SHIFT 22
1047#define lpfc_mq_context_cq_id_MASK 0x000003FF
1048#define lpfc_mq_context_cq_id_WORD word0
1049#define lpfc_mq_context_count_SHIFT 16
1050#define lpfc_mq_context_count_MASK 0x0000000F
1051#define lpfc_mq_context_count_WORD word0
1052#define LPFC_MQ_CNT_16 0x5
1053#define LPFC_MQ_CNT_32 0x6
1054#define LPFC_MQ_CNT_64 0x7
1055#define LPFC_MQ_CNT_128 0x8
1056 uint32_t word1;
1057#define lpfc_mq_context_valid_SHIFT 31
1058#define lpfc_mq_context_valid_MASK 0x00000001
1059#define lpfc_mq_context_valid_WORD word1
1060 uint32_t reserved2;
1061 uint32_t reserved3;
1062};
1063
1064struct lpfc_mbx_mq_create {
1065 struct mbox_header header;
1066 union {
1067 struct {
1068 uint32_t word0;
1069#define lpfc_mbx_mq_create_num_pages_SHIFT 0
1070#define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1071#define lpfc_mbx_mq_create_num_pages_WORD word0
1072 struct mq_context context;
1073 struct dma_address page[LPFC_MAX_MQ_PAGE];
1074 } request;
1075 struct {
1076 uint32_t word0;
1077#define lpfc_mbx_mq_create_q_id_SHIFT 0
1078#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1079#define lpfc_mbx_mq_create_q_id_WORD word0
1080 } response;
1081 } u;
1082};
1083
1084struct lpfc_mbx_mq_destroy {
1085 struct mbox_header header;
1086 union {
1087 struct {
1088 uint32_t word0;
1089#define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1090#define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1091#define lpfc_mbx_mq_destroy_q_id_WORD word0
1092 } request;
1093 struct {
1094 uint32_t word0;
1095 } response;
1096 } u;
1097};
1098
1099struct lpfc_mbx_post_hdr_tmpl {
1100 struct mbox_header header;
1101 uint32_t word10;
1102#define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
1103#define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
1104#define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10
1105#define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16
1106#define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
1107#define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10
1108 uint32_t rpi_paddr_lo;
1109 uint32_t rpi_paddr_hi;
1110};
1111
1112struct sli4_sge { /* SLI-4 */
1113 uint32_t addr_hi;
1114 uint32_t addr_lo;
1115
1116 uint32_t word2;
1117#define lpfc_sli4_sge_offset_SHIFT 0 /* Offset of buffer - Not used*/
1118#define lpfc_sli4_sge_offset_MASK 0x00FFFFFF
1119#define lpfc_sli4_sge_offset_WORD word2
1120#define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets
1121 this flag !! */
1122#define lpfc_sli4_sge_last_MASK 0x00000001
1123#define lpfc_sli4_sge_last_WORD word2
1124 uint32_t word3;
1125#define lpfc_sli4_sge_len_SHIFT 0
1126#define lpfc_sli4_sge_len_MASK 0x0001FFFF
1127#define lpfc_sli4_sge_len_WORD word3
1128};
1129
1130struct fcf_record {
1131 uint32_t max_rcv_size;
1132 uint32_t fka_adv_period;
1133 uint32_t fip_priority;
1134 uint32_t word3;
1135#define lpfc_fcf_record_mac_0_SHIFT 0
1136#define lpfc_fcf_record_mac_0_MASK 0x000000FF
1137#define lpfc_fcf_record_mac_0_WORD word3
1138#define lpfc_fcf_record_mac_1_SHIFT 8
1139#define lpfc_fcf_record_mac_1_MASK 0x000000FF
1140#define lpfc_fcf_record_mac_1_WORD word3
1141#define lpfc_fcf_record_mac_2_SHIFT 16
1142#define lpfc_fcf_record_mac_2_MASK 0x000000FF
1143#define lpfc_fcf_record_mac_2_WORD word3
1144#define lpfc_fcf_record_mac_3_SHIFT 24
1145#define lpfc_fcf_record_mac_3_MASK 0x000000FF
1146#define lpfc_fcf_record_mac_3_WORD word3
1147 uint32_t word4;
1148#define lpfc_fcf_record_mac_4_SHIFT 0
1149#define lpfc_fcf_record_mac_4_MASK 0x000000FF
1150#define lpfc_fcf_record_mac_4_WORD word4
1151#define lpfc_fcf_record_mac_5_SHIFT 8
1152#define lpfc_fcf_record_mac_5_MASK 0x000000FF
1153#define lpfc_fcf_record_mac_5_WORD word4
1154#define lpfc_fcf_record_fcf_avail_SHIFT 16
1155#define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
James Smart0c287582009-06-10 17:22:56 -04001156#define lpfc_fcf_record_fcf_avail_WORD word4
James Smartda0436e2009-05-22 14:51:39 -04001157#define lpfc_fcf_record_mac_addr_prov_SHIFT 24
1158#define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
1159#define lpfc_fcf_record_mac_addr_prov_WORD word4
1160#define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */
1161#define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */
1162 uint32_t word5;
1163#define lpfc_fcf_record_fab_name_0_SHIFT 0
1164#define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
1165#define lpfc_fcf_record_fab_name_0_WORD word5
1166#define lpfc_fcf_record_fab_name_1_SHIFT 8
1167#define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
1168#define lpfc_fcf_record_fab_name_1_WORD word5
1169#define lpfc_fcf_record_fab_name_2_SHIFT 16
1170#define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
1171#define lpfc_fcf_record_fab_name_2_WORD word5
1172#define lpfc_fcf_record_fab_name_3_SHIFT 24
1173#define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
1174#define lpfc_fcf_record_fab_name_3_WORD word5
1175 uint32_t word6;
1176#define lpfc_fcf_record_fab_name_4_SHIFT 0
1177#define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
1178#define lpfc_fcf_record_fab_name_4_WORD word6
1179#define lpfc_fcf_record_fab_name_5_SHIFT 8
1180#define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
1181#define lpfc_fcf_record_fab_name_5_WORD word6
1182#define lpfc_fcf_record_fab_name_6_SHIFT 16
1183#define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
1184#define lpfc_fcf_record_fab_name_6_WORD word6
1185#define lpfc_fcf_record_fab_name_7_SHIFT 24
1186#define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
1187#define lpfc_fcf_record_fab_name_7_WORD word6
1188 uint32_t word7;
1189#define lpfc_fcf_record_fc_map_0_SHIFT 0
1190#define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
1191#define lpfc_fcf_record_fc_map_0_WORD word7
1192#define lpfc_fcf_record_fc_map_1_SHIFT 8
1193#define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
1194#define lpfc_fcf_record_fc_map_1_WORD word7
1195#define lpfc_fcf_record_fc_map_2_SHIFT 16
1196#define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
1197#define lpfc_fcf_record_fc_map_2_WORD word7
1198#define lpfc_fcf_record_fcf_valid_SHIFT 24
1199#define lpfc_fcf_record_fcf_valid_MASK 0x000000FF
1200#define lpfc_fcf_record_fcf_valid_WORD word7
1201 uint32_t word8;
1202#define lpfc_fcf_record_fcf_index_SHIFT 0
1203#define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
1204#define lpfc_fcf_record_fcf_index_WORD word8
1205#define lpfc_fcf_record_fcf_state_SHIFT 16
1206#define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
1207#define lpfc_fcf_record_fcf_state_WORD word8
1208 uint8_t vlan_bitmap[512];
James Smart8fa38512009-07-19 10:01:03 -04001209 uint32_t word137;
1210#define lpfc_fcf_record_switch_name_0_SHIFT 0
1211#define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
1212#define lpfc_fcf_record_switch_name_0_WORD word137
1213#define lpfc_fcf_record_switch_name_1_SHIFT 8
1214#define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
1215#define lpfc_fcf_record_switch_name_1_WORD word137
1216#define lpfc_fcf_record_switch_name_2_SHIFT 16
1217#define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
1218#define lpfc_fcf_record_switch_name_2_WORD word137
1219#define lpfc_fcf_record_switch_name_3_SHIFT 24
1220#define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
1221#define lpfc_fcf_record_switch_name_3_WORD word137
1222 uint32_t word138;
1223#define lpfc_fcf_record_switch_name_4_SHIFT 0
1224#define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
1225#define lpfc_fcf_record_switch_name_4_WORD word138
1226#define lpfc_fcf_record_switch_name_5_SHIFT 8
1227#define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
1228#define lpfc_fcf_record_switch_name_5_WORD word138
1229#define lpfc_fcf_record_switch_name_6_SHIFT 16
1230#define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
1231#define lpfc_fcf_record_switch_name_6_WORD word138
1232#define lpfc_fcf_record_switch_name_7_SHIFT 24
1233#define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
1234#define lpfc_fcf_record_switch_name_7_WORD word138
James Smartda0436e2009-05-22 14:51:39 -04001235};
1236
1237struct lpfc_mbx_read_fcf_tbl {
1238 union lpfc_sli4_cfg_shdr cfg_shdr;
1239 union {
1240 struct {
1241 uint32_t word10;
1242#define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
1243#define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
1244#define lpfc_mbx_read_fcf_tbl_indx_WORD word10
1245 } request;
1246 struct {
1247 uint32_t eventag;
1248 } response;
1249 } u;
1250 uint32_t word11;
1251#define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
1252#define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
1253#define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11
1254};
1255
1256struct lpfc_mbx_add_fcf_tbl_entry {
1257 union lpfc_sli4_cfg_shdr cfg_shdr;
1258 uint32_t word10;
1259#define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
1260#define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
1261#define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10
1262 struct lpfc_mbx_sge fcf_sge;
1263};
1264
1265struct lpfc_mbx_del_fcf_tbl_entry {
1266 struct mbox_header header;
1267 uint32_t word10;
1268#define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
1269#define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
1270#define lpfc_mbx_del_fcf_tbl_count_WORD word10
1271#define lpfc_mbx_del_fcf_tbl_index_SHIFT 16
1272#define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
1273#define lpfc_mbx_del_fcf_tbl_index_WORD word10
1274};
1275
1276/* Status field for embedded SLI_CONFIG mailbox command */
1277#define STATUS_SUCCESS 0x0
1278#define STATUS_FAILED 0x1
1279#define STATUS_ILLEGAL_REQUEST 0x2
1280#define STATUS_ILLEGAL_FIELD 0x3
1281#define STATUS_INSUFFICIENT_BUFFER 0x4
1282#define STATUS_UNAUTHORIZED_REQUEST 0x5
1283#define STATUS_FLASHROM_SAVE_FAILED 0x17
1284#define STATUS_FLASHROM_RESTORE_FAILED 0x18
1285#define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
1286#define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
1287#define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
1288#define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
1289#define STATUS_ASSERT_FAILED 0x1e
1290#define STATUS_INVALID_SESSION 0x1f
1291#define STATUS_INVALID_CONNECTION 0x20
1292#define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
1293#define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
1294#define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
1295#define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
1296#define STATUS_FLASHROM_READ_FAILED 0x27
1297#define STATUS_POLL_IOCTL_TIMEOUT 0x28
1298#define STATUS_ERROR_ACITMAIN 0x2a
1299#define STATUS_REBOOT_REQUIRED 0x2c
1300#define STATUS_FCF_IN_USE 0x3a
1301
1302struct lpfc_mbx_sli4_config {
1303 struct mbox_header header;
1304};
1305
1306struct lpfc_mbx_init_vfi {
1307 uint32_t word1;
1308#define lpfc_init_vfi_vr_SHIFT 31
1309#define lpfc_init_vfi_vr_MASK 0x00000001
1310#define lpfc_init_vfi_vr_WORD word1
1311#define lpfc_init_vfi_vt_SHIFT 30
1312#define lpfc_init_vfi_vt_MASK 0x00000001
1313#define lpfc_init_vfi_vt_WORD word1
1314#define lpfc_init_vfi_vf_SHIFT 29
1315#define lpfc_init_vfi_vf_MASK 0x00000001
1316#define lpfc_init_vfi_vf_WORD word1
1317#define lpfc_init_vfi_vfi_SHIFT 0
1318#define lpfc_init_vfi_vfi_MASK 0x0000FFFF
1319#define lpfc_init_vfi_vfi_WORD word1
1320 uint32_t word2;
1321#define lpfc_init_vfi_fcfi_SHIFT 0
1322#define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
1323#define lpfc_init_vfi_fcfi_WORD word2
1324 uint32_t word3;
1325#define lpfc_init_vfi_pri_SHIFT 13
1326#define lpfc_init_vfi_pri_MASK 0x00000007
1327#define lpfc_init_vfi_pri_WORD word3
1328#define lpfc_init_vfi_vf_id_SHIFT 1
1329#define lpfc_init_vfi_vf_id_MASK 0x00000FFF
1330#define lpfc_init_vfi_vf_id_WORD word3
1331 uint32_t word4;
1332#define lpfc_init_vfi_hop_count_SHIFT 24
1333#define lpfc_init_vfi_hop_count_MASK 0x000000FF
1334#define lpfc_init_vfi_hop_count_WORD word4
1335};
1336
1337struct lpfc_mbx_reg_vfi {
1338 uint32_t word1;
1339#define lpfc_reg_vfi_vp_SHIFT 28
1340#define lpfc_reg_vfi_vp_MASK 0x00000001
1341#define lpfc_reg_vfi_vp_WORD word1
1342#define lpfc_reg_vfi_vfi_SHIFT 0
1343#define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
1344#define lpfc_reg_vfi_vfi_WORD word1
1345 uint32_t word2;
1346#define lpfc_reg_vfi_vpi_SHIFT 16
1347#define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
1348#define lpfc_reg_vfi_vpi_WORD word2
1349#define lpfc_reg_vfi_fcfi_SHIFT 0
1350#define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
1351#define lpfc_reg_vfi_fcfi_WORD word2
1352 uint32_t word3_rsvd;
1353 uint32_t word4_rsvd;
1354 struct ulp_bde64 bde;
1355 uint32_t word8_rsvd;
1356 uint32_t word9_rsvd;
1357 uint32_t word10;
1358#define lpfc_reg_vfi_nport_id_SHIFT 0
1359#define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
1360#define lpfc_reg_vfi_nport_id_WORD word10
1361};
1362
1363struct lpfc_mbx_init_vpi {
1364 uint32_t word1;
1365#define lpfc_init_vpi_vfi_SHIFT 16
1366#define lpfc_init_vpi_vfi_MASK 0x0000FFFF
1367#define lpfc_init_vpi_vfi_WORD word1
1368#define lpfc_init_vpi_vpi_SHIFT 0
1369#define lpfc_init_vpi_vpi_MASK 0x0000FFFF
1370#define lpfc_init_vpi_vpi_WORD word1
1371};
1372
1373struct lpfc_mbx_read_vpi {
1374 uint32_t word1_rsvd;
1375 uint32_t word2;
1376#define lpfc_mbx_read_vpi_vnportid_SHIFT 0
1377#define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
1378#define lpfc_mbx_read_vpi_vnportid_WORD word2
1379 uint32_t word3_rsvd;
1380 uint32_t word4;
1381#define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
1382#define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
1383#define lpfc_mbx_read_vpi_acq_alpa_WORD word4
1384#define lpfc_mbx_read_vpi_pb_SHIFT 15
1385#define lpfc_mbx_read_vpi_pb_MASK 0x00000001
1386#define lpfc_mbx_read_vpi_pb_WORD word4
1387#define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16
1388#define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
1389#define lpfc_mbx_read_vpi_spec_alpa_WORD word4
1390#define lpfc_mbx_read_vpi_ns_SHIFT 30
1391#define lpfc_mbx_read_vpi_ns_MASK 0x00000001
1392#define lpfc_mbx_read_vpi_ns_WORD word4
1393#define lpfc_mbx_read_vpi_hl_SHIFT 31
1394#define lpfc_mbx_read_vpi_hl_MASK 0x00000001
1395#define lpfc_mbx_read_vpi_hl_WORD word4
1396 uint32_t word5_rsvd;
1397 uint32_t word6;
1398#define lpfc_mbx_read_vpi_vpi_SHIFT 0
1399#define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
1400#define lpfc_mbx_read_vpi_vpi_WORD word6
1401 uint32_t word7;
1402#define lpfc_mbx_read_vpi_mac_0_SHIFT 0
1403#define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
1404#define lpfc_mbx_read_vpi_mac_0_WORD word7
1405#define lpfc_mbx_read_vpi_mac_1_SHIFT 8
1406#define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
1407#define lpfc_mbx_read_vpi_mac_1_WORD word7
1408#define lpfc_mbx_read_vpi_mac_2_SHIFT 16
1409#define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
1410#define lpfc_mbx_read_vpi_mac_2_WORD word7
1411#define lpfc_mbx_read_vpi_mac_3_SHIFT 24
1412#define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
1413#define lpfc_mbx_read_vpi_mac_3_WORD word7
1414 uint32_t word8;
1415#define lpfc_mbx_read_vpi_mac_4_SHIFT 0
1416#define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
1417#define lpfc_mbx_read_vpi_mac_4_WORD word8
1418#define lpfc_mbx_read_vpi_mac_5_SHIFT 8
1419#define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
1420#define lpfc_mbx_read_vpi_mac_5_WORD word8
1421#define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16
1422#define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
1423#define lpfc_mbx_read_vpi_vlan_tag_WORD word8
1424#define lpfc_mbx_read_vpi_vv_SHIFT 28
1425#define lpfc_mbx_read_vpi_vv_MASK 0x0000001
1426#define lpfc_mbx_read_vpi_vv_WORD word8
1427};
1428
1429struct lpfc_mbx_unreg_vfi {
1430 uint32_t word1_rsvd;
1431 uint32_t word2;
1432#define lpfc_unreg_vfi_vfi_SHIFT 0
1433#define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
1434#define lpfc_unreg_vfi_vfi_WORD word2
1435};
1436
1437struct lpfc_mbx_resume_rpi {
1438 uint32_t word1;
James Smart8fa38512009-07-19 10:01:03 -04001439#define lpfc_resume_rpi_index_SHIFT 0
1440#define lpfc_resume_rpi_index_MASK 0x0000FFFF
1441#define lpfc_resume_rpi_index_WORD word1
1442#define lpfc_resume_rpi_ii_SHIFT 30
1443#define lpfc_resume_rpi_ii_MASK 0x00000003
1444#define lpfc_resume_rpi_ii_WORD word1
1445#define RESUME_INDEX_RPI 0
1446#define RESUME_INDEX_VPI 1
1447#define RESUME_INDEX_VFI 2
1448#define RESUME_INDEX_FCFI 3
James Smartda0436e2009-05-22 14:51:39 -04001449 uint32_t event_tag;
James Smartda0436e2009-05-22 14:51:39 -04001450};
1451
1452#define REG_FCF_INVALID_QID 0xFFFF
1453struct lpfc_mbx_reg_fcfi {
1454 uint32_t word1;
1455#define lpfc_reg_fcfi_info_index_SHIFT 0
1456#define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
1457#define lpfc_reg_fcfi_info_index_WORD word1
1458#define lpfc_reg_fcfi_fcfi_SHIFT 16
1459#define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
1460#define lpfc_reg_fcfi_fcfi_WORD word1
1461 uint32_t word2;
1462#define lpfc_reg_fcfi_rq_id1_SHIFT 0
1463#define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
1464#define lpfc_reg_fcfi_rq_id1_WORD word2
1465#define lpfc_reg_fcfi_rq_id0_SHIFT 16
1466#define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
1467#define lpfc_reg_fcfi_rq_id0_WORD word2
1468 uint32_t word3;
1469#define lpfc_reg_fcfi_rq_id3_SHIFT 0
1470#define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
1471#define lpfc_reg_fcfi_rq_id3_WORD word3
1472#define lpfc_reg_fcfi_rq_id2_SHIFT 16
1473#define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
1474#define lpfc_reg_fcfi_rq_id2_WORD word3
1475 uint32_t word4;
1476#define lpfc_reg_fcfi_type_match0_SHIFT 24
1477#define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
1478#define lpfc_reg_fcfi_type_match0_WORD word4
1479#define lpfc_reg_fcfi_type_mask0_SHIFT 16
1480#define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
1481#define lpfc_reg_fcfi_type_mask0_WORD word4
1482#define lpfc_reg_fcfi_rctl_match0_SHIFT 8
1483#define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
1484#define lpfc_reg_fcfi_rctl_match0_WORD word4
1485#define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
1486#define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
1487#define lpfc_reg_fcfi_rctl_mask0_WORD word4
1488 uint32_t word5;
1489#define lpfc_reg_fcfi_type_match1_SHIFT 24
1490#define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
1491#define lpfc_reg_fcfi_type_match1_WORD word5
1492#define lpfc_reg_fcfi_type_mask1_SHIFT 16
1493#define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
1494#define lpfc_reg_fcfi_type_mask1_WORD word5
1495#define lpfc_reg_fcfi_rctl_match1_SHIFT 8
1496#define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
1497#define lpfc_reg_fcfi_rctl_match1_WORD word5
1498#define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
1499#define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
1500#define lpfc_reg_fcfi_rctl_mask1_WORD word5
1501 uint32_t word6;
1502#define lpfc_reg_fcfi_type_match2_SHIFT 24
1503#define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
1504#define lpfc_reg_fcfi_type_match2_WORD word6
1505#define lpfc_reg_fcfi_type_mask2_SHIFT 16
1506#define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
1507#define lpfc_reg_fcfi_type_mask2_WORD word6
1508#define lpfc_reg_fcfi_rctl_match2_SHIFT 8
1509#define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
1510#define lpfc_reg_fcfi_rctl_match2_WORD word6
1511#define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
1512#define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
1513#define lpfc_reg_fcfi_rctl_mask2_WORD word6
1514 uint32_t word7;
1515#define lpfc_reg_fcfi_type_match3_SHIFT 24
1516#define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
1517#define lpfc_reg_fcfi_type_match3_WORD word7
1518#define lpfc_reg_fcfi_type_mask3_SHIFT 16
1519#define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
1520#define lpfc_reg_fcfi_type_mask3_WORD word7
1521#define lpfc_reg_fcfi_rctl_match3_SHIFT 8
1522#define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
1523#define lpfc_reg_fcfi_rctl_match3_WORD word7
1524#define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
1525#define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
1526#define lpfc_reg_fcfi_rctl_mask3_WORD word7
1527 uint32_t word8;
1528#define lpfc_reg_fcfi_mam_SHIFT 13
1529#define lpfc_reg_fcfi_mam_MASK 0x00000003
1530#define lpfc_reg_fcfi_mam_WORD word8
1531#define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
1532#define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */
1533#define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */
1534#define lpfc_reg_fcfi_vv_SHIFT 12
1535#define lpfc_reg_fcfi_vv_MASK 0x00000001
1536#define lpfc_reg_fcfi_vv_WORD word8
1537#define lpfc_reg_fcfi_vlan_tag_SHIFT 0
1538#define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
1539#define lpfc_reg_fcfi_vlan_tag_WORD word8
1540};
1541
1542struct lpfc_mbx_unreg_fcfi {
1543 uint32_t word1_rsv;
1544 uint32_t word2;
1545#define lpfc_unreg_fcfi_SHIFT 0
1546#define lpfc_unreg_fcfi_MASK 0x0000FFFF
1547#define lpfc_unreg_fcfi_WORD word2
1548};
1549
1550struct lpfc_mbx_read_rev {
1551 uint32_t word1;
1552#define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16
1553#define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
1554#define lpfc_mbx_rd_rev_sli_lvl_WORD word1
1555#define lpfc_mbx_rd_rev_fcoe_SHIFT 20
1556#define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
1557#define lpfc_mbx_rd_rev_fcoe_WORD word1
1558#define lpfc_mbx_rd_rev_vpd_SHIFT 29
1559#define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
1560#define lpfc_mbx_rd_rev_vpd_WORD word1
1561 uint32_t first_hw_rev;
1562 uint32_t second_hw_rev;
1563 uint32_t word4_rsvd;
1564 uint32_t third_hw_rev;
1565 uint32_t word6;
1566#define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
1567#define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
1568#define lpfc_mbx_rd_rev_fcph_low_WORD word6
1569#define lpfc_mbx_rd_rev_fcph_high_SHIFT 8
1570#define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
1571#define lpfc_mbx_rd_rev_fcph_high_WORD word6
1572#define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16
1573#define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
1574#define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6
1575#define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24
1576#define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
1577#define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6
1578 uint32_t word7_rsvd;
1579 uint32_t fw_id_rev;
1580 uint8_t fw_name[16];
1581 uint32_t ulp_fw_id_rev;
1582 uint8_t ulp_fw_name[16];
1583 uint32_t word18_47_rsvd[30];
1584 uint32_t word48;
1585#define lpfc_mbx_rd_rev_avail_len_SHIFT 0
1586#define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
1587#define lpfc_mbx_rd_rev_avail_len_WORD word48
1588 uint32_t vpd_paddr_low;
1589 uint32_t vpd_paddr_high;
1590 uint32_t avail_vpd_len;
1591 uint32_t rsvd_52_63[12];
1592};
1593
1594struct lpfc_mbx_read_config {
1595 uint32_t word1;
1596#define lpfc_mbx_rd_conf_max_bbc_SHIFT 0
1597#define lpfc_mbx_rd_conf_max_bbc_MASK 0x000000FF
1598#define lpfc_mbx_rd_conf_max_bbc_WORD word1
1599#define lpfc_mbx_rd_conf_init_bbc_SHIFT 8
1600#define lpfc_mbx_rd_conf_init_bbc_MASK 0x000000FF
1601#define lpfc_mbx_rd_conf_init_bbc_WORD word1
1602 uint32_t word2;
1603#define lpfc_mbx_rd_conf_nport_did_SHIFT 0
1604#define lpfc_mbx_rd_conf_nport_did_MASK 0x00FFFFFF
1605#define lpfc_mbx_rd_conf_nport_did_WORD word2
1606#define lpfc_mbx_rd_conf_topology_SHIFT 24
1607#define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
1608#define lpfc_mbx_rd_conf_topology_WORD word2
1609 uint32_t word3;
1610#define lpfc_mbx_rd_conf_ao_SHIFT 0
1611#define lpfc_mbx_rd_conf_ao_MASK 0x00000001
1612#define lpfc_mbx_rd_conf_ao_WORD word3
1613#define lpfc_mbx_rd_conf_bb_scn_SHIFT 8
1614#define lpfc_mbx_rd_conf_bb_scn_MASK 0x0000000F
1615#define lpfc_mbx_rd_conf_bb_scn_WORD word3
1616#define lpfc_mbx_rd_conf_cbb_scn_SHIFT 12
1617#define lpfc_mbx_rd_conf_cbb_scn_MASK 0x0000000F
1618#define lpfc_mbx_rd_conf_cbb_scn_WORD word3
1619#define lpfc_mbx_rd_conf_mc_SHIFT 29
1620#define lpfc_mbx_rd_conf_mc_MASK 0x00000001
1621#define lpfc_mbx_rd_conf_mc_WORD word3
1622 uint32_t word4;
1623#define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
1624#define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
1625#define lpfc_mbx_rd_conf_e_d_tov_WORD word4
1626 uint32_t word5;
1627#define lpfc_mbx_rd_conf_lp_tov_SHIFT 0
1628#define lpfc_mbx_rd_conf_lp_tov_MASK 0x0000FFFF
1629#define lpfc_mbx_rd_conf_lp_tov_WORD word5
1630 uint32_t word6;
1631#define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
1632#define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
1633#define lpfc_mbx_rd_conf_r_a_tov_WORD word6
1634 uint32_t word7;
1635#define lpfc_mbx_rd_conf_r_t_tov_SHIFT 0
1636#define lpfc_mbx_rd_conf_r_t_tov_MASK 0x000000FF
1637#define lpfc_mbx_rd_conf_r_t_tov_WORD word7
1638 uint32_t word8;
1639#define lpfc_mbx_rd_conf_al_tov_SHIFT 0
1640#define lpfc_mbx_rd_conf_al_tov_MASK 0x0000000F
1641#define lpfc_mbx_rd_conf_al_tov_WORD word8
1642 uint32_t word9;
1643#define lpfc_mbx_rd_conf_lmt_SHIFT 0
1644#define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
1645#define lpfc_mbx_rd_conf_lmt_WORD word9
1646 uint32_t word10;
1647#define lpfc_mbx_rd_conf_max_alpa_SHIFT 0
1648#define lpfc_mbx_rd_conf_max_alpa_MASK 0x000000FF
1649#define lpfc_mbx_rd_conf_max_alpa_WORD word10
1650 uint32_t word11_rsvd;
1651 uint32_t word12;
1652#define lpfc_mbx_rd_conf_xri_base_SHIFT 0
1653#define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
1654#define lpfc_mbx_rd_conf_xri_base_WORD word12
1655#define lpfc_mbx_rd_conf_xri_count_SHIFT 16
1656#define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
1657#define lpfc_mbx_rd_conf_xri_count_WORD word12
1658 uint32_t word13;
1659#define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
1660#define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
1661#define lpfc_mbx_rd_conf_rpi_base_WORD word13
1662#define lpfc_mbx_rd_conf_rpi_count_SHIFT 16
1663#define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
1664#define lpfc_mbx_rd_conf_rpi_count_WORD word13
1665 uint32_t word14;
1666#define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
1667#define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
1668#define lpfc_mbx_rd_conf_vpi_base_WORD word14
1669#define lpfc_mbx_rd_conf_vpi_count_SHIFT 16
1670#define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
1671#define lpfc_mbx_rd_conf_vpi_count_WORD word14
1672 uint32_t word15;
1673#define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
1674#define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
1675#define lpfc_mbx_rd_conf_vfi_base_WORD word15
1676#define lpfc_mbx_rd_conf_vfi_count_SHIFT 16
1677#define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
1678#define lpfc_mbx_rd_conf_vfi_count_WORD word15
1679 uint32_t word16;
1680#define lpfc_mbx_rd_conf_fcfi_base_SHIFT 0
1681#define lpfc_mbx_rd_conf_fcfi_base_MASK 0x0000FFFF
1682#define lpfc_mbx_rd_conf_fcfi_base_WORD word16
1683#define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16
1684#define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
1685#define lpfc_mbx_rd_conf_fcfi_count_WORD word16
1686 uint32_t word17;
1687#define lpfc_mbx_rd_conf_rq_count_SHIFT 0
1688#define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
1689#define lpfc_mbx_rd_conf_rq_count_WORD word17
1690#define lpfc_mbx_rd_conf_eq_count_SHIFT 16
1691#define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
1692#define lpfc_mbx_rd_conf_eq_count_WORD word17
1693 uint32_t word18;
1694#define lpfc_mbx_rd_conf_wq_count_SHIFT 0
1695#define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
1696#define lpfc_mbx_rd_conf_wq_count_WORD word18
1697#define lpfc_mbx_rd_conf_cq_count_SHIFT 16
1698#define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
1699#define lpfc_mbx_rd_conf_cq_count_WORD word18
1700};
1701
1702struct lpfc_mbx_request_features {
1703 uint32_t word1;
1704#define lpfc_mbx_rq_ftr_qry_SHIFT 0
1705#define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
1706#define lpfc_mbx_rq_ftr_qry_WORD word1
1707 uint32_t word2;
1708#define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
1709#define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
1710#define lpfc_mbx_rq_ftr_rq_iaab_WORD word2
1711#define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1
1712#define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
1713#define lpfc_mbx_rq_ftr_rq_npiv_WORD word2
1714#define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2
1715#define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
1716#define lpfc_mbx_rq_ftr_rq_dif_WORD word2
1717#define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3
1718#define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
1719#define lpfc_mbx_rq_ftr_rq_vf_WORD word2
1720#define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4
1721#define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
1722#define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2
1723#define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5
1724#define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
1725#define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2
1726#define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6
1727#define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
1728#define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2
1729#define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7
1730#define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
1731#define lpfc_mbx_rq_ftr_rq_ifip_WORD word2
1732 uint32_t word3;
1733#define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
1734#define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
1735#define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3
1736#define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1
1737#define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
1738#define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3
1739#define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2
1740#define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
1741#define lpfc_mbx_rq_ftr_rsp_dif_WORD word3
1742#define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3
1743#define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
1744#define lpfc_mbx_rq_ftr_rsp_vf_WORD word3
1745#define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4
1746#define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
1747#define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3
1748#define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5
1749#define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
1750#define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3
1751#define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6
1752#define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
1753#define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3
1754#define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7
1755#define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
1756#define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3
1757};
1758
1759/* Mailbox Completion Queue Error Messages */
1760#define MB_CQE_STATUS_SUCCESS 0x0
1761#define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
1762#define MB_CQE_STATUS_INVALID_PARAMETER 0x2
1763#define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
1764#define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
1765#define MB_CQE_STATUS_DMA_FAILED 0x5
1766
1767/* mailbox queue entry structure */
1768struct lpfc_mqe {
1769 uint32_t word0;
1770#define lpfc_mqe_status_SHIFT 16
1771#define lpfc_mqe_status_MASK 0x0000FFFF
1772#define lpfc_mqe_status_WORD word0
1773#define lpfc_mqe_command_SHIFT 8
1774#define lpfc_mqe_command_MASK 0x000000FF
1775#define lpfc_mqe_command_WORD word0
1776 union {
1777 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
1778 /* sli4 mailbox commands */
1779 struct lpfc_mbx_sli4_config sli4_config;
1780 struct lpfc_mbx_init_vfi init_vfi;
1781 struct lpfc_mbx_reg_vfi reg_vfi;
1782 struct lpfc_mbx_reg_vfi unreg_vfi;
1783 struct lpfc_mbx_init_vpi init_vpi;
1784 struct lpfc_mbx_resume_rpi resume_rpi;
1785 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
1786 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
1787 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
1788 struct lpfc_mbx_reg_fcfi reg_fcfi;
1789 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
1790 struct lpfc_mbx_mq_create mq_create;
1791 struct lpfc_mbx_eq_create eq_create;
1792 struct lpfc_mbx_cq_create cq_create;
1793 struct lpfc_mbx_wq_create wq_create;
1794 struct lpfc_mbx_rq_create rq_create;
1795 struct lpfc_mbx_mq_destroy mq_destroy;
1796 struct lpfc_mbx_eq_destroy eq_destroy;
1797 struct lpfc_mbx_cq_destroy cq_destroy;
1798 struct lpfc_mbx_wq_destroy wq_destroy;
1799 struct lpfc_mbx_rq_destroy rq_destroy;
1800 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
1801 struct lpfc_mbx_nembed_cmd nembed_cmd;
1802 struct lpfc_mbx_read_rev read_rev;
1803 struct lpfc_mbx_read_vpi read_vpi;
1804 struct lpfc_mbx_read_config rd_config;
1805 struct lpfc_mbx_request_features req_ftrs;
1806 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
1807 struct lpfc_mbx_nop nop;
1808 } un;
1809};
1810
1811struct lpfc_mcqe {
1812 uint32_t word0;
1813#define lpfc_mcqe_status_SHIFT 0
1814#define lpfc_mcqe_status_MASK 0x0000FFFF
1815#define lpfc_mcqe_status_WORD word0
1816#define lpfc_mcqe_ext_status_SHIFT 16
1817#define lpfc_mcqe_ext_status_MASK 0x0000FFFF
1818#define lpfc_mcqe_ext_status_WORD word0
1819 uint32_t mcqe_tag0;
1820 uint32_t mcqe_tag1;
1821 uint32_t trailer;
1822#define lpfc_trailer_valid_SHIFT 31
1823#define lpfc_trailer_valid_MASK 0x00000001
1824#define lpfc_trailer_valid_WORD trailer
1825#define lpfc_trailer_async_SHIFT 30
1826#define lpfc_trailer_async_MASK 0x00000001
1827#define lpfc_trailer_async_WORD trailer
1828#define lpfc_trailer_hpi_SHIFT 29
1829#define lpfc_trailer_hpi_MASK 0x00000001
1830#define lpfc_trailer_hpi_WORD trailer
1831#define lpfc_trailer_completed_SHIFT 28
1832#define lpfc_trailer_completed_MASK 0x00000001
1833#define lpfc_trailer_completed_WORD trailer
1834#define lpfc_trailer_consumed_SHIFT 27
1835#define lpfc_trailer_consumed_MASK 0x00000001
1836#define lpfc_trailer_consumed_WORD trailer
1837#define lpfc_trailer_type_SHIFT 16
1838#define lpfc_trailer_type_MASK 0x000000FF
1839#define lpfc_trailer_type_WORD trailer
1840#define lpfc_trailer_code_SHIFT 8
1841#define lpfc_trailer_code_MASK 0x000000FF
1842#define lpfc_trailer_code_WORD trailer
1843#define LPFC_TRAILER_CODE_LINK 0x1
1844#define LPFC_TRAILER_CODE_FCOE 0x2
1845#define LPFC_TRAILER_CODE_DCBX 0x3
1846};
1847
1848struct lpfc_acqe_link {
1849 uint32_t word0;
1850#define lpfc_acqe_link_speed_SHIFT 24
1851#define lpfc_acqe_link_speed_MASK 0x000000FF
1852#define lpfc_acqe_link_speed_WORD word0
1853#define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
1854#define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
1855#define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
1856#define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
1857#define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
1858#define lpfc_acqe_link_duplex_SHIFT 16
1859#define lpfc_acqe_link_duplex_MASK 0x000000FF
1860#define lpfc_acqe_link_duplex_WORD word0
1861#define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
1862#define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
1863#define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
1864#define lpfc_acqe_link_status_SHIFT 8
1865#define lpfc_acqe_link_status_MASK 0x000000FF
1866#define lpfc_acqe_link_status_WORD word0
1867#define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
1868#define LPFC_ASYNC_LINK_STATUS_UP 0x1
1869#define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
1870#define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
1871#define lpfc_acqe_link_physical_SHIFT 0
1872#define lpfc_acqe_link_physical_MASK 0x000000FF
1873#define lpfc_acqe_link_physical_WORD word0
1874#define LPFC_ASYNC_LINK_PORT_A 0x0
1875#define LPFC_ASYNC_LINK_PORT_B 0x1
1876 uint32_t word1;
1877#define lpfc_acqe_link_fault_SHIFT 0
1878#define lpfc_acqe_link_fault_MASK 0x000000FF
1879#define lpfc_acqe_link_fault_WORD word1
1880#define LPFC_ASYNC_LINK_FAULT_NONE 0x0
1881#define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
1882#define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
1883 uint32_t event_tag;
1884 uint32_t trailer;
1885};
1886
1887struct lpfc_acqe_fcoe {
1888 uint32_t fcf_index;
1889 uint32_t word1;
1890#define lpfc_acqe_fcoe_fcf_count_SHIFT 0
1891#define lpfc_acqe_fcoe_fcf_count_MASK 0x0000FFFF
1892#define lpfc_acqe_fcoe_fcf_count_WORD word1
1893#define lpfc_acqe_fcoe_event_type_SHIFT 16
1894#define lpfc_acqe_fcoe_event_type_MASK 0x0000FFFF
1895#define lpfc_acqe_fcoe_event_type_WORD word1
1896#define LPFC_FCOE_EVENT_TYPE_NEW_FCF 0x1
1897#define LPFC_FCOE_EVENT_TYPE_FCF_TABLE_FULL 0x2
1898#define LPFC_FCOE_EVENT_TYPE_FCF_DEAD 0x3
1899 uint32_t event_tag;
1900 uint32_t trailer;
1901};
1902
1903struct lpfc_acqe_dcbx {
1904 uint32_t tlv_ttl;
1905 uint32_t reserved;
1906 uint32_t event_tag;
1907 uint32_t trailer;
1908};
1909
1910/*
1911 * Define the bootstrap mailbox (bmbx) region used to communicate
1912 * mailbox command between the host and port. The mailbox consists
1913 * of a payload area of 256 bytes and a completion queue of length
1914 * 16 bytes.
1915 */
1916struct lpfc_bmbx_create {
1917 struct lpfc_mqe mqe;
1918 struct lpfc_mcqe mcqe;
1919};
1920
1921#define SGL_ALIGN_SZ 64
1922#define SGL_PAGE_SIZE 4096
1923/* align SGL addr on a size boundary - adjust address up */
1924#define NO_XRI ((uint16_t)-1)
1925struct wqe_common {
1926 uint32_t word6;
1927#define wqe_xri_SHIFT 0
1928#define wqe_xri_MASK 0x0000FFFF
1929#define wqe_xri_WORD word6
1930#define wqe_ctxt_tag_SHIFT 16
1931#define wqe_ctxt_tag_MASK 0x0000FFFF
1932#define wqe_ctxt_tag_WORD word6
1933 uint32_t word7;
1934#define wqe_ct_SHIFT 2
1935#define wqe_ct_MASK 0x00000003
1936#define wqe_ct_WORD word7
1937#define wqe_status_SHIFT 4
1938#define wqe_status_MASK 0x0000000f
1939#define wqe_status_WORD word7
1940#define wqe_cmnd_SHIFT 8
1941#define wqe_cmnd_MASK 0x000000ff
1942#define wqe_cmnd_WORD word7
1943#define wqe_class_SHIFT 16
1944#define wqe_class_MASK 0x00000007
1945#define wqe_class_WORD word7
1946#define wqe_pu_SHIFT 20
1947#define wqe_pu_MASK 0x00000003
1948#define wqe_pu_WORD word7
1949#define wqe_erp_SHIFT 22
1950#define wqe_erp_MASK 0x00000001
1951#define wqe_erp_WORD word7
1952#define wqe_lnk_SHIFT 23
1953#define wqe_lnk_MASK 0x00000001
1954#define wqe_lnk_WORD word7
1955#define wqe_tmo_SHIFT 24
1956#define wqe_tmo_MASK 0x000000ff
1957#define wqe_tmo_WORD word7
1958 uint32_t abort_tag; /* word 8 in WQE */
1959 uint32_t word9;
1960#define wqe_reqtag_SHIFT 0
1961#define wqe_reqtag_MASK 0x0000FFFF
1962#define wqe_reqtag_WORD word9
1963#define wqe_rcvoxid_SHIFT 16
1964#define wqe_rcvoxid_MASK 0x0000FFFF
1965#define wqe_rcvoxid_WORD word9
1966 uint32_t word10;
1967#define wqe_pri_SHIFT 16
1968#define wqe_pri_MASK 0x00000007
1969#define wqe_pri_WORD word10
1970#define wqe_pv_SHIFT 19
1971#define wqe_pv_MASK 0x00000001
1972#define wqe_pv_WORD word10
1973#define wqe_xc_SHIFT 21
1974#define wqe_xc_MASK 0x00000001
1975#define wqe_xc_WORD word10
1976#define wqe_ccpe_SHIFT 23
1977#define wqe_ccpe_MASK 0x00000001
1978#define wqe_ccpe_WORD word10
1979#define wqe_ccp_SHIFT 24
1980#define wqe_ccp_MASK 0x000000ff
1981#define wqe_ccp_WORD word10
1982 uint32_t word11;
1983#define wqe_cmd_type_SHIFT 0
1984#define wqe_cmd_type_MASK 0x0000000f
1985#define wqe_cmd_type_WORD word11
1986#define wqe_wqec_SHIFT 7
1987#define wqe_wqec_MASK 0x00000001
1988#define wqe_wqec_WORD word11
1989#define wqe_cqid_SHIFT 16
1990#define wqe_cqid_MASK 0x000003ff
1991#define wqe_cqid_WORD word11
1992};
1993
1994struct wqe_did {
1995 uint32_t word5;
1996#define wqe_els_did_SHIFT 0
1997#define wqe_els_did_MASK 0x00FFFFFF
1998#define wqe_els_did_WORD word5
1999#define wqe_xmit_bls_ar_SHIFT 30
2000#define wqe_xmit_bls_ar_MASK 0x00000001
2001#define wqe_xmit_bls_ar_WORD word5
2002#define wqe_xmit_bls_xo_SHIFT 31
2003#define wqe_xmit_bls_xo_MASK 0x00000001
2004#define wqe_xmit_bls_xo_WORD word5
2005};
2006
2007struct els_request64_wqe {
2008 struct ulp_bde64 bde;
2009 uint32_t payload_len;
2010 uint32_t word4;
2011#define els_req64_sid_SHIFT 0
2012#define els_req64_sid_MASK 0x00FFFFFF
2013#define els_req64_sid_WORD word4
2014#define els_req64_sp_SHIFT 24
2015#define els_req64_sp_MASK 0x00000001
2016#define els_req64_sp_WORD word4
2017#define els_req64_vf_SHIFT 25
2018#define els_req64_vf_MASK 0x00000001
2019#define els_req64_vf_WORD word4
2020 struct wqe_did wqe_dest;
2021 struct wqe_common wqe_com; /* words 6-11 */
2022 uint32_t word12;
2023#define els_req64_vfid_SHIFT 1
2024#define els_req64_vfid_MASK 0x00000FFF
2025#define els_req64_vfid_WORD word12
2026#define els_req64_pri_SHIFT 13
2027#define els_req64_pri_MASK 0x00000007
2028#define els_req64_pri_WORD word12
2029 uint32_t word13;
2030#define els_req64_hopcnt_SHIFT 24
2031#define els_req64_hopcnt_MASK 0x000000ff
2032#define els_req64_hopcnt_WORD word13
2033 uint32_t reserved[2];
2034};
2035
2036struct xmit_els_rsp64_wqe {
2037 struct ulp_bde64 bde;
2038 uint32_t rsvd3;
2039 uint32_t rsvd4;
2040 struct wqe_did wqe_dest;
2041 struct wqe_common wqe_com; /* words 6-11 */
2042 uint32_t rsvd_12_15[4];
2043};
2044
2045struct xmit_bls_rsp64_wqe {
2046 uint32_t payload0;
2047 uint32_t word1;
2048#define xmit_bls_rsp64_rxid_SHIFT 0
2049#define xmit_bls_rsp64_rxid_MASK 0x0000ffff
2050#define xmit_bls_rsp64_rxid_WORD word1
2051#define xmit_bls_rsp64_oxid_SHIFT 16
2052#define xmit_bls_rsp64_oxid_MASK 0x0000ffff
2053#define xmit_bls_rsp64_oxid_WORD word1
2054 uint32_t word2;
2055#define xmit_bls_rsp64_seqcntlo_SHIFT 0
2056#define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
2057#define xmit_bls_rsp64_seqcntlo_WORD word2
2058#define xmit_bls_rsp64_seqcnthi_SHIFT 16
2059#define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
2060#define xmit_bls_rsp64_seqcnthi_WORD word2
2061 uint32_t rsrvd3;
2062 uint32_t rsrvd4;
2063 struct wqe_did wqe_dest;
2064 struct wqe_common wqe_com; /* words 6-11 */
2065 uint32_t rsvd_12_15[4];
2066};
2067struct wqe_rctl_dfctl {
2068 uint32_t word5;
2069#define wqe_si_SHIFT 2
2070#define wqe_si_MASK 0x000000001
2071#define wqe_si_WORD word5
2072#define wqe_la_SHIFT 3
2073#define wqe_la_MASK 0x000000001
2074#define wqe_la_WORD word5
2075#define wqe_ls_SHIFT 7
2076#define wqe_ls_MASK 0x000000001
2077#define wqe_ls_WORD word5
2078#define wqe_dfctl_SHIFT 8
2079#define wqe_dfctl_MASK 0x0000000ff
2080#define wqe_dfctl_WORD word5
2081#define wqe_type_SHIFT 16
2082#define wqe_type_MASK 0x0000000ff
2083#define wqe_type_WORD word5
2084#define wqe_rctl_SHIFT 24
2085#define wqe_rctl_MASK 0x0000000ff
2086#define wqe_rctl_WORD word5
2087};
2088
2089struct xmit_seq64_wqe {
2090 struct ulp_bde64 bde;
2091 uint32_t paylaod_offset;
2092 uint32_t relative_offset;
2093 struct wqe_rctl_dfctl wge_ctl;
2094 struct wqe_common wqe_com; /* words 6-11 */
2095 /* Note: word10 different REVISIT */
2096 uint32_t xmit_len;
2097 uint32_t rsvd_12_15[3];
2098};
2099struct xmit_bcast64_wqe {
2100 struct ulp_bde64 bde;
2101 uint32_t paylaod_len;
2102 uint32_t rsvd4;
2103 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2104 struct wqe_common wqe_com; /* words 6-11 */
2105 uint32_t rsvd_12_15[4];
2106};
2107
2108struct gen_req64_wqe {
2109 struct ulp_bde64 bde;
2110 uint32_t command_len;
2111 uint32_t payload_len;
2112 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2113 struct wqe_common wqe_com; /* words 6-11 */
2114 uint32_t rsvd_12_15[4];
2115};
2116
2117struct create_xri_wqe {
2118 uint32_t rsrvd[5]; /* words 0-4 */
2119 struct wqe_did wqe_dest; /* word 5 */
2120 struct wqe_common wqe_com; /* words 6-11 */
2121 uint32_t rsvd_12_15[4]; /* word 12-15 */
2122};
2123
2124#define T_REQUEST_TAG 3
2125#define T_XRI_TAG 1
2126
2127struct abort_cmd_wqe {
2128 uint32_t rsrvd[3];
2129 uint32_t word3;
2130#define abort_cmd_ia_SHIFT 0
2131#define abort_cmd_ia_MASK 0x000000001
2132#define abort_cmd_ia_WORD word3
2133#define abort_cmd_criteria_SHIFT 8
2134#define abort_cmd_criteria_MASK 0x0000000ff
2135#define abort_cmd_criteria_WORD word3
2136 uint32_t rsrvd4;
2137 uint32_t rsrvd5;
2138 struct wqe_common wqe_com; /* words 6-11 */
2139 uint32_t rsvd_12_15[4]; /* word 12-15 */
2140};
2141
2142struct fcp_iwrite64_wqe {
2143 struct ulp_bde64 bde;
2144 uint32_t payload_len;
2145 uint32_t total_xfer_len;
2146 uint32_t initial_xfer_len;
2147 struct wqe_common wqe_com; /* words 6-11 */
2148 uint32_t rsvd_12_15[4]; /* word 12-15 */
2149};
2150
2151struct fcp_iread64_wqe {
2152 struct ulp_bde64 bde;
2153 uint32_t payload_len; /* word 3 */
2154 uint32_t total_xfer_len; /* word 4 */
2155 uint32_t rsrvd5; /* word 5 */
2156 struct wqe_common wqe_com; /* words 6-11 */
2157 uint32_t rsvd_12_15[4]; /* word 12-15 */
2158};
2159
2160struct fcp_icmnd64_wqe {
2161 struct ulp_bde64 bde; /* words 0-2 */
2162 uint32_t rsrvd[3]; /* words 3-5 */
2163 struct wqe_common wqe_com; /* words 6-11 */
2164 uint32_t rsvd_12_15[4]; /* word 12-15 */
2165};
2166
2167
2168union lpfc_wqe {
2169 uint32_t words[16];
2170 struct lpfc_wqe_generic generic;
2171 struct fcp_icmnd64_wqe fcp_icmd;
2172 struct fcp_iread64_wqe fcp_iread;
2173 struct fcp_iwrite64_wqe fcp_iwrite;
2174 struct abort_cmd_wqe abort_cmd;
2175 struct create_xri_wqe create_xri;
2176 struct xmit_bcast64_wqe xmit_bcast64;
2177 struct xmit_seq64_wqe xmit_sequence;
2178 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
2179 struct xmit_els_rsp64_wqe xmit_els_rsp;
2180 struct els_request64_wqe els_req;
2181 struct gen_req64_wqe gen_req;
2182};
2183
2184#define FCP_COMMAND 0x0
2185#define FCP_COMMAND_DATA_OUT 0x1
2186#define ELS_COMMAND_NON_FIP 0xC
2187#define ELS_COMMAND_FIP 0xD
2188#define OTHER_COMMAND 0x8
2189