blob: 895a07264210680934435a1b29389970bc791f4b [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
Shawn Guoce4c6f92012-05-04 14:32:35 +080017 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +080023 saif0 = &saif0;
24 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -030025 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
Shawn Guoce4c6f92012-05-04 14:32:35 +080030 };
31
Dong Aishengbc3a59c2012-03-31 21:26:57 +080032 cpus {
33 cpu@0 {
34 compatible = "arm,arm926ejs";
35 };
36 };
37
38 apb@80000000 {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x80000000 0x80000>;
43 ranges;
44
45 apbh@80000000 {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <0x80000000 0x3c900>;
50 ranges;
51
52 icoll: interrupt-controller@80000000 {
53 compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
54 interrupt-controller;
55 #interrupt-cells = <1>;
56 reg = <0x80000000 0x2000>;
57 };
58
59 hsadc@80002000 {
60 reg = <0x80002000 2000>;
61 interrupts = <13 87>;
62 status = "disabled";
63 };
64
65 dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +080066 compatible = "fsl,imx28-dma-apbh";
Dong Aishengbc3a59c2012-03-31 21:26:57 +080067 reg = <0x80004000 2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080068 };
69
70 perfmon@80006000 {
71 reg = <0x80006000 800>;
72 interrupts = <27>;
73 status = "disabled";
74 };
75
Huang Shijie7a8e5142012-05-25 17:25:35 +080076 gpmi-nand@8000c000 {
77 compatible = "fsl,imx28-gpmi-nand";
78 #address-cells = <1>;
79 #size-cells = <1>;
80 reg = <0x8000c000 2000>, <0x8000a000 2000>;
81 reg-names = "gpmi-nand", "bch";
82 interrupts = <88>, <41>;
83 interrupt-names = "gpmi-dma", "bch";
84 fsl,gpmi-dma-channel = <4>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080085 status = "disabled";
86 };
87
88 ssp0: ssp@80010000 {
89 reg = <0x80010000 2000>;
90 interrupts = <96 82>;
Shawn Guo35d23042012-05-06 16:33:34 +080091 fsl,ssp-dma-channel = <0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080092 status = "disabled";
93 };
94
95 ssp1: ssp@80012000 {
96 reg = <0x80012000 2000>;
97 interrupts = <97 83>;
Shawn Guo35d23042012-05-06 16:33:34 +080098 fsl,ssp-dma-channel = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +080099 status = "disabled";
100 };
101
102 ssp2: ssp@80014000 {
103 reg = <0x80014000 2000>;
104 interrupts = <98 84>;
Shawn Guo35d23042012-05-06 16:33:34 +0800105 fsl,ssp-dma-channel = <2>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800106 status = "disabled";
107 };
108
109 ssp3: ssp@80016000 {
110 reg = <0x80016000 2000>;
111 interrupts = <99 85>;
Shawn Guo35d23042012-05-06 16:33:34 +0800112 fsl,ssp-dma-channel = <3>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800113 status = "disabled";
114 };
115
116 pinctrl@80018000 {
117 #address-cells = <1>;
118 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800119 compatible = "fsl,imx28-pinctrl", "simple-bus";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800120 reg = <0x80018000 2000>;
121
Shawn Guoce4c6f92012-05-04 14:32:35 +0800122 gpio0: gpio@0 {
123 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
124 interrupts = <127>;
125 gpio-controller;
126 #gpio-cells = <2>;
127 interrupt-controller;
128 #interrupt-cells = <2>;
129 };
130
131 gpio1: gpio@1 {
132 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
133 interrupts = <126>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
138 };
139
140 gpio2: gpio@2 {
141 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
142 interrupts = <125>;
143 gpio-controller;
144 #gpio-cells = <2>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
147 };
148
149 gpio3: gpio@3 {
150 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
151 interrupts = <124>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 interrupt-controller;
155 #interrupt-cells = <2>;
156 };
157
158 gpio4: gpio@4 {
159 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
160 interrupts = <123>;
161 gpio-controller;
162 #gpio-cells = <2>;
163 interrupt-controller;
164 #interrupt-cells = <2>;
165 };
166
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800167 duart_pins_a: duart@0 {
168 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800169 fsl,pinmux-ids = <
170 0x3102 /* MX28_PAD_PWM0__DUART_RX */
171 0x3112 /* MX28_PAD_PWM1__DUART_TX */
172 >;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800173 fsl,drive-strength = <0>;
174 fsl,voltage = <1>;
175 fsl,pull-up = <0>;
176 };
177
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200178 duart_pins_b: duart@1 {
179 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800180 fsl,pinmux-ids = <
181 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
182 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
183 >;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200184 fsl,drive-strength = <0>;
185 fsl,voltage = <1>;
186 fsl,pull-up = <0>;
187 };
188
Huang Shijie7a8e5142012-05-25 17:25:35 +0800189 gpmi_pins_a: gpmi-nand@0 {
190 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800191 fsl,pinmux-ids = <
192 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
193 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
194 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
195 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
196 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
197 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
198 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
199 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
200 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
Shawn Guof14da762012-06-28 11:44:57 +0800201 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
Shawn Guof14da762012-06-28 11:44:57 +0800202 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
203 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
204 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
205 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
206 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
207 >;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800208 fsl,drive-strength = <0>;
209 fsl,voltage = <1>;
210 fsl,pull-up = <0>;
211 };
212
213 gpmi_status_cfg: gpmi-status-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800214 fsl,pinmux-ids = <
215 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
216 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
217 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
218 >;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800219 fsl,drive-strength = <2>;
220 };
221
Fabio Estevam80d969e2012-06-15 12:35:56 -0300222 auart0_pins_a: auart0@0 {
223 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800224 fsl,pinmux-ids = <
225 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
226 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
227 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
228 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
229 >;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300230 fsl,drive-strength = <0>;
231 fsl,voltage = <1>;
232 fsl,pull-up = <0>;
233 };
234
Marek Vasut8fa62e12012-07-07 21:21:38 +0800235 auart0_2pins_a: auart0-2pins@0 {
236 reg = <0>;
237 fsl,pinmux-ids = <
238 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
239 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
240 >;
241 fsl,drive-strength = <0>;
242 fsl,voltage = <1>;
243 fsl,pull-up = <0>;
244 };
245
Fabio Estevam80d969e2012-06-15 12:35:56 -0300246 auart3_pins_a: auart3@0 {
247 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800248 fsl,pinmux-ids = <
249 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
250 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
251 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
252 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
253 >;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300254 fsl,drive-strength = <0>;
255 fsl,voltage = <1>;
256 fsl,pull-up = <0>;
257 };
258
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800259 mac0_pins_a: mac0@0 {
260 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800261 fsl,pinmux-ids = <
262 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
263 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
264 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
265 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
266 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
267 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
268 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
269 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
270 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
271 >;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800272 fsl,drive-strength = <1>;
273 fsl,voltage = <1>;
274 fsl,pull-up = <1>;
275 };
276
277 mac1_pins_a: mac1@0 {
278 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800279 fsl,pinmux-ids = <
280 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
281 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
282 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
283 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
284 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
285 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
286 >;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800287 fsl,drive-strength = <1>;
288 fsl,voltage = <1>;
289 fsl,pull-up = <1>;
290 };
Shawn Guo35d23042012-05-06 16:33:34 +0800291
292 mmc0_8bit_pins_a: mmc0-8bit@0 {
293 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800294 fsl,pinmux-ids = <
295 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
296 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
297 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
298 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
299 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
300 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
301 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
302 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
303 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
304 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
305 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
306 >;
Shawn Guo35d23042012-05-06 16:33:34 +0800307 fsl,drive-strength = <1>;
308 fsl,voltage = <1>;
309 fsl,pull-up = <1>;
310 };
311
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200312 mmc0_4bit_pins_a: mmc0-4bit@0 {
313 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800314 fsl,pinmux-ids = <
315 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
316 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
317 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
318 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
319 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
320 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
321 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
322 >;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200323 fsl,drive-strength = <1>;
324 fsl,voltage = <1>;
325 fsl,pull-up = <1>;
326 };
327
Shawn Guo35d23042012-05-06 16:33:34 +0800328 mmc0_cd_cfg: mmc0-cd-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800329 fsl,pinmux-ids = <
330 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
331 >;
Shawn Guo35d23042012-05-06 16:33:34 +0800332 fsl,pull-up = <0>;
333 };
334
335 mmc0_sck_cfg: mmc0-sck-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800336 fsl,pinmux-ids = <
337 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
338 >;
Shawn Guo35d23042012-05-06 16:33:34 +0800339 fsl,drive-strength = <2>;
340 fsl,pull-up = <0>;
341 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800342
343 i2c0_pins_a: i2c0@0 {
344 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800345 fsl,pinmux-ids = <
346 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
347 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
348 >;
Shawn Guo2a96e392012-05-10 15:02:10 +0800349 fsl,drive-strength = <1>;
350 fsl,voltage = <1>;
351 fsl,pull-up = <1>;
352 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800353
354 saif0_pins_a: saif0@0 {
355 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800356 fsl,pinmux-ids = <
357 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
358 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
359 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
360 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
361 >;
Shawn Guo530f1d42012-05-10 15:03:16 +0800362 fsl,drive-strength = <2>;
363 fsl,voltage = <1>;
364 fsl,pull-up = <1>;
365 };
366
367 saif1_pins_a: saif1@0 {
368 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800369 fsl,pinmux-ids = <
370 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
371 >;
Shawn Guo530f1d42012-05-10 15:03:16 +0800372 fsl,drive-strength = <2>;
373 fsl,voltage = <1>;
374 fsl,pull-up = <1>;
375 };
Shawn Guo52f71762012-06-28 11:45:06 +0800376
377 pwm2_pins_a: pwm2@0 {
378 reg = <0>;
379 fsl,pinmux-ids = <
380 0x3120 /* MX28_PAD_PWM2__PWM_2 */
381 >;
382 fsl,drive-strength = <0>;
383 fsl,voltage = <1>;
384 fsl,pull-up = <0>;
385 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800386
387 lcdif_24bit_pins_a: lcdif-24bit@0 {
388 reg = <0>;
389 fsl,pinmux-ids = <
390 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
391 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
392 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
393 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
394 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
395 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
396 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
397 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
398 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
399 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
400 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
401 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
402 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
403 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
404 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
405 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
406 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
407 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
408 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
409 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
410 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
411 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
412 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
413 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
Shawn Guoa915ee42012-06-28 11:45:07 +0800414 >;
415 fsl,drive-strength = <0>;
416 fsl,voltage = <1>;
417 fsl,pull-up = <0>;
418 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800419
420 can0_pins_a: can0@0 {
421 reg = <0>;
422 fsl,pinmux-ids = <
423 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
424 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
425 >;
426 fsl,drive-strength = <0>;
427 fsl,voltage = <1>;
428 fsl,pull-up = <0>;
429 };
430
431 can1_pins_a: can1@0 {
432 reg = <0>;
433 fsl,pinmux-ids = <
434 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
435 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
436 >;
437 fsl,drive-strength = <0>;
438 fsl,voltage = <1>;
439 fsl,pull-up = <0>;
440 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800441 };
442
443 digctl@8001c000 {
444 reg = <0x8001c000 2000>;
445 interrupts = <89>;
446 status = "disabled";
447 };
448
449 etm@80022000 {
450 reg = <0x80022000 2000>;
451 status = "disabled";
452 };
453
454 dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800455 compatible = "fsl,imx28-dma-apbx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800456 reg = <0x80024000 2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800457 };
458
459 dcp@80028000 {
460 reg = <0x80028000 2000>;
461 interrupts = <52 53 54>;
462 status = "disabled";
463 };
464
465 pxp@8002a000 {
466 reg = <0x8002a000 2000>;
467 interrupts = <39>;
468 status = "disabled";
469 };
470
471 ocotp@8002c000 {
472 reg = <0x8002c000 2000>;
473 status = "disabled";
474 };
475
476 axi-ahb@8002e000 {
477 reg = <0x8002e000 2000>;
478 status = "disabled";
479 };
480
481 lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800482 compatible = "fsl,imx28-lcdif";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800483 reg = <0x80030000 2000>;
484 interrupts = <38 86>;
485 status = "disabled";
486 };
487
488 can0: can@80032000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800489 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800490 reg = <0x80032000 2000>;
491 interrupts = <8>;
492 status = "disabled";
493 };
494
495 can1: can@80034000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800496 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800497 reg = <0x80034000 2000>;
498 interrupts = <9>;
499 status = "disabled";
500 };
501
502 simdbg@8003c000 {
503 reg = <0x8003c000 200>;
504 status = "disabled";
505 };
506
507 simgpmisel@8003c200 {
508 reg = <0x8003c200 100>;
509 status = "disabled";
510 };
511
512 simsspsel@8003c300 {
513 reg = <0x8003c300 100>;
514 status = "disabled";
515 };
516
517 simmemsel@8003c400 {
518 reg = <0x8003c400 100>;
519 status = "disabled";
520 };
521
522 gpiomon@8003c500 {
523 reg = <0x8003c500 100>;
524 status = "disabled";
525 };
526
527 simenet@8003c700 {
528 reg = <0x8003c700 100>;
529 status = "disabled";
530 };
531
532 armjtag@8003c800 {
533 reg = <0x8003c800 100>;
534 status = "disabled";
535 };
536 };
537
538 apbx@80040000 {
539 compatible = "simple-bus";
540 #address-cells = <1>;
541 #size-cells = <1>;
542 reg = <0x80040000 0x40000>;
543 ranges;
544
545 clkctl@80040000 {
546 reg = <0x80040000 2000>;
547 status = "disabled";
548 };
549
550 saif0: saif@80042000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800551 compatible = "fsl,imx28-saif";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800552 reg = <0x80042000 2000>;
553 interrupts = <59 80>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800554 fsl,saif-dma-channel = <4>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800555 status = "disabled";
556 };
557
558 power@80044000 {
559 reg = <0x80044000 2000>;
560 status = "disabled";
561 };
562
563 saif1: saif@80046000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800564 compatible = "fsl,imx28-saif";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800565 reg = <0x80046000 2000>;
566 interrupts = <58 81>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800567 fsl,saif-dma-channel = <5>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800568 status = "disabled";
569 };
570
571 lradc@80050000 {
572 reg = <0x80050000 2000>;
573 status = "disabled";
574 };
575
576 spdif@80054000 {
577 reg = <0x80054000 2000>;
578 interrupts = <45 66>;
579 status = "disabled";
580 };
581
582 rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800583 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800584 reg = <0x80056000 2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800585 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800586 };
587
588 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800589 #address-cells = <1>;
590 #size-cells = <0>;
591 compatible = "fsl,imx28-i2c";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800592 reg = <0x80058000 2000>;
593 interrupts = <111 68>;
594 status = "disabled";
595 };
596
597 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800598 #address-cells = <1>;
599 #size-cells = <0>;
600 compatible = "fsl,imx28-i2c";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800601 reg = <0x8005a000 2000>;
602 interrupts = <110 69>;
603 status = "disabled";
604 };
605
Shawn Guo52f71762012-06-28 11:45:06 +0800606 pwm: pwm@80064000 {
607 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800608 reg = <0x80064000 2000>;
Shawn Guo52f71762012-06-28 11:45:06 +0800609 #pwm-cells = <2>;
610 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800611 status = "disabled";
612 };
613
614 timrot@80068000 {
615 reg = <0x80068000 2000>;
616 status = "disabled";
617 };
618
619 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300620 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800621 reg = <0x8006a000 0x2000>;
622 interrupts = <112 70 71>;
623 status = "disabled";
624 };
625
626 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300627 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800628 reg = <0x8006c000 0x2000>;
629 interrupts = <113 72 73>;
630 status = "disabled";
631 };
632
633 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300634 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800635 reg = <0x8006e000 0x2000>;
636 interrupts = <114 74 75>;
637 status = "disabled";
638 };
639
640 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300641 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800642 reg = <0x80070000 0x2000>;
643 interrupts = <115 76 77>;
644 status = "disabled";
645 };
646
647 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300648 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800649 reg = <0x80072000 0x2000>;
650 interrupts = <116 78 79>;
651 status = "disabled";
652 };
653
654 duart: serial@80074000 {
655 compatible = "arm,pl011", "arm,primecell";
656 reg = <0x80074000 0x1000>;
657 interrupts = <47>;
658 status = "disabled";
659 };
660
661 usbphy0: usbphy@8007c000 {
662 reg = <0x8007c000 0x2000>;
663 status = "disabled";
664 };
665
666 usbphy1: usbphy@8007e000 {
667 reg = <0x8007e000 0x2000>;
668 status = "disabled";
669 };
670 };
671 };
672
673 ahb@80080000 {
674 compatible = "simple-bus";
675 #address-cells = <1>;
676 #size-cells = <1>;
677 reg = <0x80080000 0x80000>;
678 ranges;
679
680 usbctrl0: usbctrl@80080000 {
681 reg = <0x80080000 0x10000>;
682 status = "disabled";
683 };
684
685 usbctrl1: usbctrl@80090000 {
686 reg = <0x80090000 0x10000>;
687 status = "disabled";
688 };
689
690 dflpt@800c0000 {
691 reg = <0x800c0000 0x10000>;
692 status = "disabled";
693 };
694
695 mac0: ethernet@800f0000 {
696 compatible = "fsl,imx28-fec";
697 reg = <0x800f0000 0x4000>;
698 interrupts = <101>;
699 status = "disabled";
700 };
701
702 mac1: ethernet@800f4000 {
703 compatible = "fsl,imx28-fec";
704 reg = <0x800f4000 0x4000>;
705 interrupts = <102>;
706 status = "disabled";
707 };
708
709 switch@800f8000 {
710 reg = <0x800f8000 0x8000>;
711 status = "disabled";
712 };
713
714 };
715};